JP6090329B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Description
実施例1にかかる半導体装置の構造について説明する。図1は、この発明の実施例1にかかる半導体装置の構成を示す断面図である。図1(a)は要部断面図であり、図1(b)は図1(a)のD部拡大図である。図1(b)には、各n型バッファ層5,6,7の深さを示す。図1の実施例1にかかる半導体装置については、PiNダイオード100を例に挙げた。ここで挙げたPiNダイオード100の耐圧は1200Vクラスである。なお、下記のキャリア濃度は広がり抵抗(SR)から算出される値である。
プロトン注入後の熱処理温度を380℃で行った図2に示す比較例(点線)について説明する。比較例では、3つのn型バッファ層を形成するためのプロトン注入の各飛程は、基板裏面からそれぞれ50μm程度、25μm程度、10μm程度である。また、n型シリコン基板1自体の不純物濃度(キャリア濃度)は実施例1より低い。
つぎに、実施例2として、図1の半導体装置を製造する方法について説明する。図4〜図7は、この発明の実施例2にかかる半導体装置の製造途中の状態を示す断面図である。まず、図4に示すように、例えば500μm程度の厚さのn型シリコン基板1の一方の主面の表面層に、p型アノード層3と高耐圧接合終端構造11のp型層12とを選択的に形成する。つぎに、n型シリコン基板1の、p型アノード層3とp型層12とに挟まれた領域の表面上およびp型層12間に挟まれた領域の表面上に、酸化膜である絶縁膜14を形成する。つぎに、p型アノード層3上にアノード電極8を形成し、p型層12上に終端電極13を形成する。つぎに、n型シリコン基板1の他方の面(n型シリコン基板1の裏面1b)を研削・研磨してn型シリコン基板1の厚さを120μm程度まで薄くする。
次に、本発明の実施例3にかかる半導体装置の構成について、絶縁ゲート型バイポーラトランジスタ(IGBT)を例に説明する。図12は、この発明の実施例3にかかる半導体装置の構成を示す説明図である。図12(a)は、実施例3にかかる半導体装置の要部断面図である。図12(b)は、図12(a)の切断線A−A’におけるネットドーピング濃度分布である。
1a n型シリコン基板の裏面
2 n型ドリフト層
3 p型アノード層
4 n型カソード層
5,35 複数のn型バッファ層のうち、n型シリコン基板の裏面から最も深い位置に配置されたn型バッファ層
5a 複数のn型バッファ層のうち、n型シリコン基板の裏面から最も深い位置に配置されたn型バッファ層5のキャリアピーク濃度の位置
6,36 複数のn型バッファ層のうち、他のn型バッファ層の中間の位置に配置されたn型バッファ層
6a 複数のn型バッファ層のうち、他のn型バッファ層の中間の位置に配置されたn型バッファ層6のキャリアピーク濃度の位置
7,37 複数のn型バッファ層のうち、n型シリコン基板の裏面から最も浅い位置に配置されたn型バッファ層
7a 複数のn型バッファ層のうち、n型シリコン基板の裏面から最も浅い位置に配置されたn型バッファ層7のキャリアピーク濃度の位置
8 アノード電極
9 カソード電極
11 高耐圧接合終端構造
12 p型層
13 終端電極
14 絶縁膜
15,16,45,46 n型バッファ層間に挟まれた領域(キャリア溜め込み領域)
17 複数のn型バッファ層のうち、n型シリコン基板の裏面から最も浅い位置に配置されたn型バッファ層7とn型カソード層4とに挟まれた領域
18 アニール炉
20 n型層
22 n型バッファ層を形成するために注入されるプロトン
23 p型アノード層とn型ドリフト層とのpn接合
31 エミッタ電極
32 コレクタ電極
33 p型ベース層
34 n+型エミッタ層
38 n型フィールドストップ層
39 p型コレクタ層
42 ゲート電極
43 ゲート絶縁膜
47 n型バッファ層とn型フィールドストップ層とに挟まれた領域(キャリア溜め込み領域)
100 PiNダイオード
E1,E2,E3 加速エネルギー
P1,P2,P3 n型バッファ層を形成するために注入されるプロトンの飛程
Q1,Q2,Q3 n型バッファ層の基板裏面からの深さ
T n型カソード層4の拡散深さ
Claims (27)
- n型半導体基板の内部に設けられたn型ドリフト層と、
前記n型半導体基板の第1の主面の表面層に、前記n型ドリフト層に接して設けられたp型層と、
前記n型半導体基板の第2の主面側に、前記n型ドリフト層に接して設けられたn型層と、
を備え、
前記n型層は、前記n型半導体基板に導入された水素がドナー化されてなる、前記n型半導体基板の第2の主面からの深さが異なる複数のn型バッファ層で構成されており、
複数の前記n型バッファ層のうち、前記p型層に最も近い位置に配置された最近接バッファ層のキャリアピーク濃度の位置は、前記n型半導体基板の第2の主面から15μmの位置よりも深く、
深さ方向に隣り合う前記n型バッファ層間に挟まれた領域のキャリア濃度は、前記n型バッファ層のキャリアピーク濃度よりも低く、かつ前記n型半導体基板のキャリア濃度以上であり、
深さ方向に隣り合う前記n型バッファ層間に挟まれた領域のキャリア濃度分布において、
深さ方向に隣り合う前記n型バッファ層のキャリア濃度がそれぞれピークとなる位置の間の距離をLABとし、
前記LABの間で、長さがaLABとなる領域を領域Mとし、
前記aは0.3〜0.7の範囲の値とし、
前記領域Mのキャリア濃度を前記領域Mで積分して前記aLABで割った値を前記領域Mの平均キャリア濃度とし、
前記領域Mには、深さ方向に隣り合う前記n型バッファ層の間でキャリア濃度が最小となる位置が含まれ、
前記領域Mにおける前記キャリア濃度の分布が、前記平均キャリア濃度の80%〜120%の範囲内である平坦部を有することを特徴とする半導体装置。 - 前記n型バッファ層、深さ方向に隣り合う前記n型バッファ層間に挟まれた領域、および前記n型半導体基板のキャリア濃度は、広がり抵抗から算出される値であることを特徴とする請求項1に記載の半導体装置。
- 深さ方向に隣り合う前記n型バッファ層間に挟まれた領域のキャリア濃度は、前記n型半導体基板のキャリア濃度の1倍以上5倍以下であることを特徴とする請求項1に記載の半導体装置。
- 深さ方向に隣り合う前記n型バッファ層間に挟まれた複数の領域のうち、前記第2の主面に最も近い領域のキャリア濃度は、前記n型半導体基板のキャリア濃度の1倍以上5倍以下であることを特徴とする請求項1に記載の半導体装置。
- 前記n型バッファ層のキャリア濃度分布において、キャリアピーク濃度の位置から前記p型層側への幅は、キャリアピーク濃度の位置から前記n型半導体基板の第2の主面側への幅より広いことを特徴とする請求項1に記載の半導体装置。
- 深さ方向に隣り合う前記n型バッファ層間に挟まれた領域のキャリア濃度は、前記p型層側へ向かって小さくなることを特徴とする請求項1に記載の半導体装置。
- 前記n型半導体基板の第1の主面から第2の主面までの厚さをW0とし、
前記n型半導体基板の第1の主面からの前記p型層の深さをxjとし、
前記p型層と前記n型ドリフト層との界面から前記最近接バッファ層までの距離をZとし、
前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さをYとしたときに、
前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さYは、Y=W0−(Z+xj)であり、
前記p型層と前記n型ドリフト層との界面から前記最近接バッファ層までの距離ZをZ=αW0としたときの係数αは0.4以上0.8以下であることを特徴とする請求項1に記載の半導体装置。 - 前記係数αは0.45以上0.7以下であることを特徴とする請求項7に記載の半導体装置。
- 前記係数αは0.5以上0.6以下であることを特徴とする請求項8に記載の半導体装置。
- シリコンの誘電率をεS、定格電圧をVrate、定格電流密度をJrate、電荷素量をq、キャリアの飽和速度をvsat、前記n型ドリフト層のドーピング濃度をNd、前記n型半導体基板の第1の主面からの前記p型層の深さをxj、前記p型層と前記n型ドリフト層との界面から前記最近接バッファ層までの距離をZ、前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さをYとし、
距離指標x0を、
前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さYは、Y=W0−(Z+xj)であり、
前記p型層と前記n型ドリフト層との界面から前記最近接バッファ層までの距離ZをZ=βx0としたときの係数βは0.6以上1.4以下であることを特徴とする請求項1に記載の半導体装置。 - 前記係数βは0.7以上1.2以下であることを特徴とする請求項10に記載の半導体装置。
- 前記係数βは0.8以上1.0以下であることを特徴とする請求項11に記載の半導体装置。
- 前記p型層をp型アノード層とし、前記n型層を前記n型バッファ層およびn型カソード層とするダイオード、または、前記p型層をp型ウェル層とし、p型ウェル層の内部に選択的に設けられたn型エミッタ層と、前記n型層の、前記n型ドリフト層側に対して反対側の表面層に設けられたp型コレクタ層と、を有する絶縁ゲート型バイポーラトランジスタであることを特徴とする請求項1〜12のいずれか一つに記載の半導体装置。
- n型半導体基板の第1の主面の表面層に、p型層および当該p型層に接する主電極を形成する第1工程と、
前記n型半導体基板の第2の主面から異なる加速エネルギーで複数回のプロトン注入を行う第2工程と、
前記プロトン注入により注入されたプロトンを熱処理によってドナー化し、前記n型半導体基板の第2の主面からの深さが異なる複数のn型バッファ層を形成する第3工程と、
を含み、
前記第2工程では、前記第3工程により形成される複数の前記n型バッファ層のうち、前記p型層に最も近い位置に形成される最近接バッファ層のキャリアピーク濃度の位置が前記n型半導体基板の第2の主面から15μmの位置よりも離れるように前記プロトン注入を行うことを特徴とする半導体装置の製造方法。 - 前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは、1.0MeV以上8MeV以下であることを特徴とする請求項14に記載の半導体装置の製造方法。
- シリコンの誘電率をεS、定格電圧をVrate、定格電流密度をJrate、電荷素量をq、キャリアの飽和速度をvsat、前記n型半導体基板からなるn型ドリフト層のドーピング濃度をNd、前記n型半導体基板の第1の主面からの前記p型層の深さをxj、前記p型層とn型ドリフト層との界面から前記最近接バッファ層までの距離をZ、前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さをYとし、
距離指標x0を、
前記n型半導体基板の第2の主面から前記最近接バッファ層のキャリアピーク濃度の位置までの深さYは、Y=W0−(Z+xj)であり、
前記p型層とn型ドリフト層との界面から前記最近接バッファ層までの距離ZをZ=βx0とし、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーを、係数βの値に対応して設定することを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は600Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは1.1MeV以上1.8MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は1200Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは1.6MeV以上2.8MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は1700Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは1.9MeV以上3.4MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は3300Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは3.0MeV以上5.1MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は4500Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは3.7MeV以上6.1MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 定格電圧は6500Vであり、
前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーは4.7MeV以上7.6MeV以下であることを特徴とする請求項15に記載の半導体装置の製造方法。 - 前記第3工程では、400℃以上500℃以下の温度で、1時間以上10時間以下の前記熱処理を行うことを特徴とする請求項14に記載の半導体装置の製造方法。
- 前記第3工程では、420℃以上450℃以下の温度で、1時間以上3時間以下の前記熱処理を行うことを特徴とする請求項23に記載の半導体装置の製造方法。
- 前記最近接バッファ層を形成するための前記プロトン注入の加速エネルギーEの常用対数値log(E)をyとし、
前記最近接バッファ層を形成するための前記プロトン注入の、前記n型半導体基板の第2の主面からの飛程Rpの常用対数値log(Rp)をxとしたときに、
y=−0.0047x4+0.0528x3−0.2211x2+0.9923x+5.0474を満たすことを特徴とする請求項14〜24のいずれか一つに記載の半導体装置の製造方法。 - 深さ方向に隣り合う前記n型バッファ層間に挟まれた複数の領域のキャリア濃度は、全て、前記n型半導体基板のキャリア濃度の1倍以上5倍以下であることを特徴とする請求項1に記載の半導体装置。
- 深さ方向に隣り合う前記n型バッファ層間に挟まれた領域のキャリア濃度は、前記n型ドリフト層のキャリア濃度よりも高いことを特徴とする請求項1に記載の半導体装置。
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