CN103765595A - 包含垂直晶体管装置的半导体装置结构、垂直晶体管装置阵列及制作方法 - Google Patents

包含垂直晶体管装置的半导体装置结构、垂直晶体管装置阵列及制作方法 Download PDF

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CN103765595A
CN103765595A CN201280041260.2A CN201280041260A CN103765595A CN 103765595 A CN103765595 A CN 103765595A CN 201280041260 A CN201280041260 A CN 201280041260A CN 103765595 A CN103765595 A CN 103765595A
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grid
table top
metal seed
insulator
conductor
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CN103765595B (zh
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古尔特杰·S·桑胡
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Micron Technology Inc
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明揭示一种半导体装置结构。所述半导体装置结构包含在衬底上面延伸的台面。所述台面具有在所述台面的第一侧与第二侧之间的沟道区。第一栅极在所述台面的第一侧上，所述第一栅极包括第一栅极绝缘体及第一栅极导体，所述第一栅极导体包括上覆于所述第一栅极绝缘体上的石墨烯。所述栅极导体可包括呈一个或一个以上单层的石墨烯。本发明还揭示一种用于制作所述半导体装置结构的方法；一种包含具有所述所揭示结构的半导体装置的垂直晶体管装置阵列；及一种用于制作所述垂直晶体管装置阵列的方法。

Description

包含垂直晶体管装置的半导体装置结构、垂直晶体管装置阵列及制作方法
优先权主张
本申请案主张2011年8月23日申请的题为“包含垂直晶体管装置的半导体装置结构、垂直晶体管装置阵列及制作方法(Semiconductor Device Structures Including VerticalTransistor Devices，Arrays of Vertical Transistor Devices，and Methods of Fabrication)”的第13／215,968号美国专利申请案的申请日期的权益。
技术领域
在各种实施例中，本发明一股来说涉及集成电路设计及制作的领域。更特定来说，本发明涉及垂直定向晶体管及用于制作所述晶体管的方法。
背景技术
在衬底上制作例如晶体管等半导体装置必定导致衬底的某一表面积被所述装置的占用面积占据。通常，给定衬底的可用表面积受限，且最大化对衬底的使用需要最大化在衬底上制作的装置的密度。最小化例如晶体管等装置的组件的尺寸适应最小化装置的总体占用面积及最大化装置密度。此适应在给定衬底上形成较大数目的装置。
晶体管通常构造于衬底的主要表面上。主要表面通常为衬底的最上部外部表面。将衬底的主要表面视为界定水平平面及方向。
包含一对源极／漏极区之间的沟道区及经配置以通过所述沟道区将所述源极／漏极区彼此电连接的栅极的场效应晶体管(“FET”)结构可基于沟道区相对于衬底的主要表面的定向而在两个广泛的类别当中划分。具有主要平行于衬底的主要表面的沟道区的晶体管结构称为平面FET结构，且具有大体垂直于衬底的主要表面的沟道区的晶体管结构称为垂直FET(“VFET”)晶体管结构。由于晶体管装置的源极与漏极区之间的电流流动穿过沟道区而发生，因此可基于电流流动的方向以及沟道区的大体定向两者而将平面FET装置与VFET装置区分开。VFET装置为其中装置的源极与漏极区之间的电流流动主要实质上正交于衬底的主要表面的装置。平面FET装置为其中源极与漏极区之间的电流流动主要平行于衬底的主要表面的装置。
VFET装置包含从下伏衬底向上延伸的垂直的所谓的“台面”，在此项技术中也称为所谓的“鳍片”。此台面形成晶体管主体的部分。一股来说，源极区及漏极区位于台面的端处，而一个或一个以上栅极位于台面或鳍片的一个或一个以上表面上。在激活后，电流即刻在台面内流动穿过沟道区。
VFET在宽度上(即，在平行于由衬底的主要表面界定的水平平面的平面中的尺寸上)通常比平面FET薄。因此，垂直晶体管有助于适应增加的装置堆填密度且有助于包含在交叉点存储器阵列内。以此方式，多个VFET以堆叠行及列来定序。然而，甚至在此布置的情况下，堆填密度也至少部分地受垂直晶体管的组件(包含栅极及沟道组件)的最小尺寸限制。
按比例缩放或以其它方式减小晶体管组件的尺寸至少部分地取决于常规半导体制作技术的限制、在制作中所使用的材料的物理限制及制作操作装置所需的最低性质。举例来说，为了形成具有实现必要水平的低电阻的性质的典型栅极金属，通常需要大于5纳米的栅极厚度。在具有环绕栅极的VFET装置中使用5nm厚度的栅极金属，装置的总宽度必须考虑到栅极材料的宽度的两倍。因此，典型的VFET环绕栅极将使至少10纳米的VFET装置宽度被栅极导体耗用。
发明内容
本发明揭示一种包含垂直晶体管装置的半导体装置结构，其包括在衬底上面延伸的台面及在所述台面的第一侧上的第一栅极。所述台面包括在所述台面的第一侧与第二侧之间的沟道区。所述第一栅极包括第一栅极绝缘体及第一栅极导体，所述第一栅极导体包括上覆于所述第一栅极绝缘体上的石墨烯。
还揭示一种用于制作半导体装置结构的方法。所述方法包括：在衬底上形成多个金属籽晶；在所述多个金属籽晶中的每一者上形成导体材料以形成多个栅极导体；在所述多个栅极导体中的每一者上形成绝缘体材料以形成多个栅极绝缘体；及用沟道材料填充所述第一沟槽以形成沟道区。所述多个栅极绝缘体中的第一栅极绝缘体通过第一沟槽与所述多个栅极绝缘体中的第二栅极绝缘体分离。
揭示一种垂直晶体管装置阵列。所述阵列包括：第一多个台面，其在衬底上面延伸；第一多个绝缘体材料分段；第一栅极绝缘体，其沿着所述第一多个台面中的所述台面的所述第一侧；及第一栅极导体，其沿着所述第一栅极绝缘体，所述第一栅极导体包括石墨烯。所述第一多个台面中的每一台面具有第一侧及与所述第一侧相对的第二侧，所述第一侧彼此相对且所述第二侧彼此相对。每一绝缘体材料分段将所述台面中的一者与所述第一多个台面内的另一台面分离。
还揭示一种用于制作垂直晶体管装置阵列的方法。所述方法包括：在衬底上形成多个金属籽晶；在所述多个金属籽晶中的每一者上形成导体材料以形成多个栅极导体；在所述多个栅极导体中的每一者上形成第一绝缘体材料以形成多个栅极绝缘体；用第二绝缘体材料填充所述第一沟槽；移除所述第二绝缘体材料的分段以暴露所述衬底的下伏区段且界定多个腔；及用沟道材料填充所述多个腔以形成在第一侧上由所述第一栅极绝缘体接界且在第二侧上由所述第二栅极绝缘体接界的沟道区。所述多个栅极绝缘体中的第一栅极绝缘体通过第一沟槽与所述多个栅极绝缘体中的第二栅极绝缘体分离。
附图说明
图1是本发明的实施例的垂直场效应晶体管的横截面俯视及前视透视示意图；
图2到11是根据本发明的实施例在各种处理阶段期间的半导体装置结构的横截面俯视及前视透视示意图；且
图12到21是根据本发明的另一实施例在各种处理阶段期间的半导体装置结构的横截面俯视及前视透视示意图。
具体实施方式
本发明揭示半导体装置结构、垂直晶体管装置阵列及用于制作此些结构或装置的方法。所述垂直晶体管装置及VFET阵列均包含薄栅极导体，从而使得本发明VFET结构及方法有助于高装置密度集成电路设计，包含交叉点存储器阵列。
如本文中所使用，术语“衬底”意指及包含在其上形成例如垂直场效应晶体管等材料的基底材料或构造。衬底可为半导体衬底、在支撑结构上的基底半导体层、金属电极或其上形成有一个或一个以上层、结构或区的半导体衬底。衬底可为常规硅衬底或包括半导电材料层的其它块体衬底。如本文中所使用，术语“块体衬底”不仅意指及包含硅晶片，而且意指及包含绝缘体上硅(“SOI”)衬底(例如，蓝宝石上硅(“SOS”)衬底或玻璃上硅(“SOG”)衬底)、位于基底半导体基础上的外延硅层，或其它半导体或光电子材料(例如，硅-锗(Si1-xGex)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP))。此外，当在以下描述中提及“晶片”或“衬底”时，可能已利用先前工艺步骤在基底半导体结构或基础中形成了区或结。
如本文中所使用，术语“石墨烯”意指及包含具有通过共价键彼此连接的多个碳原子的多环芳香族分子。所述多个碳原子可形成充当标准重复单位的多个六元环且可进一步包含五元环及／或七元环。石墨烯可为六元环的一个原子厚的材料，其中所述碳原子共价地键合且具有sp2杂交。石墨烯可包含石墨烯单层。或者，石墨烯可包含彼此上下堆叠的多个石墨烯单层。就这一点来说，石墨烯可具有约5纳米的最大厚度。如果使用多个石墨烯单层，那么可使用石墨烯作为半导体装置结构中的栅极。如果使用一个原子厚的材料，那么可使用石墨烯作为可切换材料。
如本文中所使用，尽管术语“第一”、“第二”、“第三”等可描述各种元件、组件、区、层及／或区段，但其中的任一者均不受这些术语的限制。这些术语仅用于将一个元件、组件、区、材料、层或区段与另一元件、组件、区、材料、层或区段区分开。因此，在不背离本文中的教示的情况下，下文所论述的“第一元件”、“第一组件”、“第一区”、“第一材料”、“第一层”或“第一区段”可称为第二元件、第二组件、第二区、第二材料、第二层或第二区段。
如本文中所使用，为便于描述可使用例如“在…下方”、“在…下面”、“下部”、“底部”、“在…上面”、“上部”、“顶部”、“前面”、“后面”、“左面”、“右面”等空间相对术语来描述如图中所图解说明的一个元件或特征与另一(些)元件或特征的关系。除非另有规定，否则所述空间相对术语打算除图中所描绘的定向以外还囊括装置在使用或操作中的不同定向。举例来说，如果翻转图中的装置，那么描述为“在其它元件或特征下面”或“在其它元件或特征下方”或“在其它元件或特征底下”或“在其它元件或特征的底部上”的元件则将被定向为“在其它元件或特征上面”或“在其它元件或特征的顶部上”。因此，术语“在…下面”可囊括在…上面及在…下面的定向两者，此取决于使用所述术语的背景，此将为所属领域的一股技术人员所明了。可以其它方式定向装置(旋转90度或处于其它定向)且相应地解释本文中所使用的空间相对描述语。
如本文中所使用，将元件指代为“在另一元件上”意指及包含所述元件直接在另一元件的顶部上、邻近于另一元件、在另一元件下方或与另一元件直接接触。其还包含所述元件间接在另一元件的顶部上、邻近于另一元件、在另一元件下方或接近另一元件，其中其之间具有其它元件。相比之下，当称元件“直接在另一元件上”时，不存在介入元件。
如本文中所使用，术语“包括(comprise)”、“包括(comprising)”、“包含(include)”及／或“包含(including)”规定所陈述特征、区、整数、步骤、操作、元件及／或组件的存在，但并不排除一个或一个以上其它特征、区、整数、步骤、操作、元件、组件及／或其群组的存在或添加。
如本文中所使用，“及／或”包含相关联所列举项目中的一者或一者以上的任何及所有组合。
如本文中所使用，单数形式“一(a)”、“一(an)”及“所述(the)”打算也包含复数形式，除非上下文另有明确指示。
本文中所呈现的图解说明并非意在作为任何特定组件、结构、装置或系统的实际视图，而仅仅是用于描述本发明的实施例的理想化表示。
本文中参考示意性图解说明理想化实施例的横截面图解说明来描述实例性实施例。如此，将预期由于(举例来说)制造技术及／或公差所致的与图解说明的形状的变化。因此，本文中所描述的实施例不应理解为限于如所图解说明的特定形状或区，而是将包含由(举例来说)制造产生的形状偏差。举例来说，图解说明或描述为箱形状的区通常可具有粗糙及／或非线性特征。此外，所图解说明的锐角可经修圆。因此，图中所图解说明的区本质上是示意性的，且其形状并非打算图解说明区的精确形状且并非打算限制本权利要求书的范围。
以下描述提供特定细节(例如材料类型、材料厚度及处理条件)以便提供对所揭示装置及方法的实施例的透彻描述。然而，所属领域的一股技术人员应理解，可在不采用这些特定细节的情况下实践所述装置及方法的实施例。而是，所述装置及方法的实施例可结合工业中所采用的常规半导体制作技术来实践。
本文中所描述的制作工艺并不形成用于处理半导体装置结构的完整工艺流。所述工艺流的剩余部分是所属领域的一股技术人员已知的。因此，本文中仅描述理解本发明装置及方法的实施例所必需的方法及半导体装置结构。
除非上下文另有指示，否则本文中所描述的材料可通过任何适合技术来形成，包含(但不限于)旋涂、毯覆式涂覆、化学气相沉积(“CVD”)、原子层沉积(“ALD”)、等离子增强ALD及物理气相沉积(“PVD”)。或者，可原位生长所述材料。取决于将形成的特定材料，用于沉积或生长材料的技术可由所属领域的一股技术人员选择。
除非上下文另有指示，否则本文中所描述的材料的移除可通过任何适合技术来实现，包含(但不限于)蚀刻、磨料平面化或其它已知材料移除方法。
现在将参考图式，其中在通篇中相似编号指代相似组件。所述图式未必按比例绘制。
图1是具有本发明的结构的VFET100半导体装置的示意图的横截面前视及俯视透视图。VFET100包含台面120，台面120在衬底50上面延伸使得台面120的底部侧125安放于衬底50的水平平面上部表面上。台面120沿垂直于衬底50的方向在衬底50上面延伸。台面120具有第一侧121及与第一侧121相对且实质上平行的第二侧122。沟道区130在第一侧121与第二侧122之间通过台面120。在使用及操作中，沟道区130经配置以允许电流在源极区(未展示)与漏极区(未展示)之间流动。台面120的顶部侧126可与电极(未展示)或互连件(未展示)操作连通。
第一栅极140提供于台面120的第一侧121上。第一栅极140操作以控制沟道区130中的电流流动。第二栅极140也可提供于台面120的第二侧122上，第二栅极140操作以结合第一栅极140来控制台面120的沟道区130中的电流流动。
每一栅极140包含栅极绝缘体160及上覆栅极导体150。栅极绝缘体160可直接提供于台面120的第一侧121及／或第二侧122上。栅极导体150可直接提供于栅极绝缘体160上且可环绕台面120的垂直侧，即，可环绕台面120的第一侧121、第二侧122、第三侧123及第四侧124。在此些实施例中，第三侧123及第四侧124可彼此相对且平行并垂直于第一侧121及第二侧122而布置。
在本发明VFET100结构的其它实施例中，栅极140仅提供于台面120的第一侧121上。在又一些实施例中，栅极140仅提供于台面120的第一侧121及第二侧122上而不提供于第三侧123或第四侧124上。
根据图1中所描绘的本发明VFET100结构的实施例，侧壁栅极结构140的栅极导体150实质上上覆于栅极绝缘体160的整个外部表面(即，与台面120接近的栅极绝缘体160的表面相对且实质上平行的栅极绝缘体160的表面)上。在VFET100结构的其它实施例中，栅极140的栅极导体150仅上覆于栅极绝缘体160的外部表面的一部分上。在一些此类实施例中，栅极导体150被结构化为环形栅极导体。
本发明VFET100的栅极导体150是界定小于或等于约5纳米的栅极导体厚度G(即，当栅极导体150被构造为具有三维箱形状时此栅极导体150的最短侧的尺寸)的栅极导体。因此，根据具有一对栅极140的所描绘VFET100，栅极导体150的厚度向一个所形成VFET单元(图11及图21)的总体宽度C贡献栅极导体150的厚度G的两倍。栅极导体150的厚度G可小于栅极绝缘体160的厚度I，当栅极绝缘体160被构造为具有三维箱形状时，厚度I由此栅极绝缘体160的最短侧的尺寸界定。
栅极导体150可由石墨烯形成，或栅极导体150的至少一部分可包含石墨烯。石墨烯展现高导电率且具有单原子主体厚度。因此，石墨烯拥有高速电子的大电位。一股来说，石墨烯为密集堆填成蜂巢晶格的sp2键合碳原子的一个原子厚的平面薄片，使得石墨烯薄片的碳原子彼此连接成延伸的六边形环阵列。可堆叠个别石墨烯薄片。因此，栅极导体150可包含多个石墨烯层。如果使用多个石墨烯单层，那么可使用石墨烯作为栅极导体150。如果使用一个原子厚的材料，那么可使用石墨烯作为半导体装置中的可切换材料。
图2到11描绘根据用于制作半导体装置(例如VFET100装置)以及用于制作垂直晶体管装置100的阵列300(图10)的本发明方法的实施例处理多个垂直晶体管的各种阶段。特别参考图2，本发明方法包含在衬底50上形成多个金属籽晶110。金属籽晶110彼此间隔开且平行布置。金属籽晶110可以间距形成。每一金属籽晶110包含第一侧111、第二侧112、底部侧115及顶部侧116。根据图2中的描绘，金属籽晶110经定位使得每一金属籽晶110的底部侧115邻近于衬底50，且每一金属籽晶110的顶部侧116与底部侧115相对且从衬底50向上引导。一个金属籽晶110的第一侧111与相邻金属籽晶110的第二侧112相对且平行地定位。金属籽晶110可彼此均匀地间隔开、平行布置，使得每一金属籽晶110通过具有等于第一距离的宽度M的沟槽与每一邻近及平行金属籽晶110分离。在其它实施例中，金属籽晶110可彼此不均匀地间隔开使得一个金属籽晶110与第一相邻金属籽晶110的间隔比其与第二相邻金属籽晶110的间隔更远。在又一些实施例中，金属籽晶110可不均匀地间隔开使得一个金属籽晶110在第一端处与相邻金属籽晶110的间隔比其在第二端处与相邻金属籽晶110的间隔更远。
金属籽晶110的材料可为有助于在其上形成栅极导体150的任何金属，例如石墨烯的栅极导体。举例来说(而不限于)，可使用铜、镍、铱、钌、其组合及含有这些金属中的任一者或全部的固体混合物作为金属籽晶110的材料。作为更特定实例，金属籽晶110可由铜形成，例如多晶铜。
参考图3，用于制作半导体装置(例如VFET装置100或VFET阵列300)的方法进一步包含在多个金属籽晶110中的每一者上形成导体材料以形成栅极导体150，其包含将金属籽晶110的第一侧111及第二侧112中的每一者对准的栅极导体侧壁。所述导体材料可保形地形成于金属籽晶110的第一侧111、第二侧112及顶部侧116上方。可通过任何适合技术来形成栅极导体150的导体材料，包含(但不限于)CVD、ALD、等离子增强ALD或其它已知方法。如果有，那么所述导体材料的上覆于衬底50的上部表面上的部分可通过常规技术来移除，从而暴露衬底50。
栅极导体150的导体材料可由石墨烯形成。已知形成石墨烯的各种方法。以下文献描述形成石墨烯的各种方法：在2006年7月4日颁予江(Jang)等人的美国专利7,071，258；在2006年3月21日颁予德惠(DeHeer)等人的美国专利7,015，142；在2005年3月22日颁予岸(Kishi)等人的美国专利6,869,581；在2011年5月26日公开的真宗(Shin)等人的第2011／0123776号美国专利申请公开案；及在2006年5月11日公开的德惠等人的第2006／0099750号美国专利申请公开案。可使用任何此类适合技术由石墨烯在金属籽晶110上形成栅极导体150。举例来说(而不限于)，在一些实施例中，可使用ALD、CVD或其它已知方法来形成石墨烯。
在此些实施例中，石墨烯可直接形成于金属籽晶110的外部表面上。根据图3的描绘，导体材料可至少上覆于多个金属籽晶110中的每一金属籽晶110的第一侧111、顶部侧116及第二侧112上，但可不上覆于衬底50的上部表面上。不管如何形成，由石墨烯形成的栅极导体150可具有仅一个原子的厚度。或者，由石墨烯形成的栅极导体150可包含双层、三层或其它多层石墨烯。
在所揭示方法的其它实施例中，所述导体材料可经形成以便形成所描绘的栅极导体150侧壁及顶部壁且上覆于衬底50的上部表面上。此后，半导体装置可经适合地处理以移除上覆于衬底50上的导体材料(例如使用光刻、蚀刻或其它已知方法)以至少产生上覆于金属籽晶110中的每一者的第一侧111及第二侧112上但不在衬底50的定位于金属籽晶110之间的上部表面上的栅极导体150侧壁。
参考图4，本发明方法进一步包含在多个栅极导体150侧壁中的每一者上形成绝缘体材料以形成多个栅极绝缘体160侧壁。所述方法可进一步包含在金属籽晶110的栅极导体150顶部壁或顶部侧116上形成绝缘体材料。所述方法可进一步包含在定位于金属籽晶110之间的栅极导体150底部壁上或在定位于金属籽晶110之间的经暴露衬底50表面上形成绝缘体材料。所述绝缘体材料可保形地形成于栅极导体150侧壁及顶部壁以及剩余经暴露衬底50表面上方。因此，根据图4中的描绘，所述绝缘体材料形成于栅极导体150侧壁及顶部壁以及剩余经暴露衬底50表面中的每一者上。在栅极导体150侧壁上形成绝缘体材料可包含在于栅极导体150侧壁上形成绝缘体材料之前直接在栅极导体150侧壁上形成籽晶材料。如此，所形成栅极绝缘体160侧壁可包含籽晶材料及绝缘体材料两者。在形成时，多个栅极绝缘体160侧壁中的第一栅极绝缘体160侧壁通过第一沟槽170与第二栅极绝缘体160侧壁分离。由于金属籽晶110可彼此均匀地平行间隔开，因此所形成栅极绝缘体160侧壁可彼此均匀地间隔开，使得每一第一沟槽170界定第一沟槽宽度T。第一沟槽宽度T小于分离金属籽晶110的宽度M(图2)的第一距离。第一沟槽宽度T等于宽度M减小第一栅极绝缘体160的绝缘体材料的厚度的两倍及第一栅极导体150的导体材料的厚度的两倍。
可通过任何适合技术来形成栅极绝缘体160侧壁、顶部壁或底部壁，包含(但不限于)CVD、ALD、等离子增强ALD、PVD或其它已知方法。在一个实施例中，通过ALD形成栅极绝缘体160。栅极绝缘体160的绝缘体材料可为任何适合绝缘材料。举例来说(而不限于)，栅极绝缘体160可由氧化物形成。
参考图5，本发明方法可进一步包含用第二绝缘体材料180填充第一沟槽170。第二绝缘体材料180可不仅填充第一沟槽170而且可覆盖栅极绝缘体160顶部壁。可通过任何适合方法来实现用第二绝缘体材料180填充第一沟槽170，包含(而不限于)通过旋涂、毯覆式涂覆、CVD或其它已知方法。第二绝缘体材料180可由任何适合绝缘材料形成。举例来说(而不限于)，第二栅极绝缘体160可由常规层间电介质(“ILD”)材料形成，例如氧化硅或氮化硅。
在所揭示方法的其它实施例中，用第二绝缘体材料180填充沟槽170可包含用第二绝缘体材料180仅填充沟槽170而不将第二绝缘体材料180上覆于金属籽晶110的顶部侧116、栅极导体150材料的顶部壁或栅极绝缘体160材料的顶部壁上。
参考图6，如果必要，那么所述方法可进一步包含移除第二绝缘体材料180的部分、栅极绝缘体160材料的部分及栅极导体150材料的部分以暴露金属籽晶110的顶部侧116。此可通过任何适合方法来实现，包含(而不限于)平面化方法，例如磨料平面化、化学机械抛光或平面化(“CMP”)或蚀刻工艺。
所述方法可进一步包含移除金属籽晶110及用具有大于形成金属籽晶110的材料的金属温度的熔化温度的材料填充曾由金属籽晶110占据的空间。如此，经重新填充材料可经配置以在无实质变形的情况下耐受金属籽晶110可耐受的制作温度高的制作温度。
参考图7到9，所述方法可进一步包含选择性地移除第二绝缘体材料180的分段以暴露衬底50的下伏区段。第二绝缘体材料180的经移除分段可为间隔开的分段。经移除分段在第二绝缘体材料180中界定多个腔200。第二绝缘体材料180的分段的移除可通过沿正交于衬底50的方向进行图案化来实现，例如通过使用使第二绝缘体材料180的有序分段的顶部表面暴露的光掩模190。可使用蚀刻或任何其它适合方法根据如图8中所描绘的光掩模190图案来移除第二绝缘体材料180的分段，此后可移除光掩模190(图9)。
根据所描绘方法，每一腔200形成为三维箱形状使得所述腔的第一侧201与第二侧202平行且相对，所述侧中的每一者由栅极绝缘体160侧壁接界及界定。每一腔200的第三侧203及第四侧204也彼此平行且相对，由剩余第二绝缘体材料180接界及界定。
在于形成栅极绝缘体160材料时所述方法产生形成于衬底50上的栅极绝缘体160底部壁的情况下，每一腔200的底部侧205可由栅极绝缘体160材料接界及界定，如图8中所展示。在一些实施例中，可接着移除栅极绝缘体160材料，如通过蚀刻或其它已知材料移除方法，且在栅极导体150材料上重新形成栅极绝缘体160材料。移除及重新形成栅极绝缘体160材料的此中间过程可适应在所得的垂直晶体管装置阵列300中形成最优电质量的栅极绝缘体160材料。
在移除光掩模190之前，可进一步利用光掩模190来移除栅极绝缘体160材料的上覆于衬底50上的区段以便暴露衬底50的曾被覆盖的那些区段，如图9中所描绘。此后，每一腔200的底部侧205由衬底50的经暴露上部表面接界及界定。每一腔200的顶部侧206保持敞开。
参考图10，用于形成半导体装置(例如VFET装置100或VFET300的阵列)的本发明方法进一步包含用沟道材料填充腔200。如图1中所展示，所述沟道材料形成在第一侧121上由第一栅极绝缘体160侧壁接界、在第二侧122上由第二栅极绝缘体160侧壁接界且在第三侧123及第四侧124上由剩余第二绝缘体材料180接界的台面120。一列VFET装置的台面120可通过第二绝缘体材料180间隔开。
可借助任何适合技术来实现用沟道材料填充腔200以形成台面120，包含(而不限于)旋涂、毯覆式涂覆、CVD、ALD、等离子增强ALD、PVD、原位生长或其它已知方法。台面120的沟道材料可为(而不限于)非晶硅、多晶硅、外延硅、氧化铟镓锌(InGaZnOx)(“IGZO”)以及其它。在一个实施例中，所述沟道材料为IGZO。
如图10中所描绘，在用沟道材料填充腔200以形成台面120之后，每一栅极导体150侧壁保持由栅极绝缘体160侧壁及金属籽晶110中的一者接界。因此，本发明的半导体装置结构可包含提供于第一栅极导体150侧壁上的第一金属籽晶110及提供于第二栅极导体150侧壁上的第二金属籽晶110。
如图11中所描绘，本发明方法可进一步包含移除金属籽晶110。可借助任何适合技术来实现移除金属籽晶110，例如蚀刻。移除金属籽晶110产生定位于一对相对安置的栅极导体150侧壁之间的第二沟槽210。因此，形成VFET100的阵列300，每一VFET装置100具有至少一个栅极导体150。
进一步关于图11，所揭示垂直晶体管装置阵列300包含安置于衬底50上的第一多个台面120。第一多个台面120可包含一列所形成VFET装置100的台面120。第一多个台面120中的台面120中的每一者具有第一侧121及与第一侧121相对的第二侧122。第一多个台面120内的台面120的第一侧121彼此对准，且第一多个台面内的台面120的第二侧122彼此对准。
阵列300进一步包含第一多个绝缘体材料分段，例如剩余第二绝缘体材料180的分段，绝缘体材料180的分段中的每一者将台面120中的一者与第一多个台面120内的另一台面120分离。
阵列300进一步包含沿着第一多个台面120中的台面120的第一侧121提供的栅极绝缘体160侧壁。栅极导体150侧壁沿着栅极绝缘体160侧壁提供。栅极导体150可包含呈一个或一个以上层的石墨烯。根据图11中所描绘的垂直晶体管装置100的阵列300，单个栅极绝缘体160侧壁及单个栅极导体150侧壁为沿着VFET装置100的一列台面120的整体在台面120的第一侧121上延伸的单个栅极140的组件。或者，一系列分离的栅极140可沿着VFET装置100的一列台面120中的台面120的第一侧121延伸。
如图11中所描绘，阵列300可进一步包含沿着第一多个半导体台面120中的台面120的第二侧122提供的第二栅极绝缘体160侧壁。阵列300可进一步包含沿着第二栅极绝缘体160侧壁提供的第二栅极导体150侧壁。第二栅极导体150可包含呈一个或一个以上层的石墨烯。根据图11中所描绘的垂直晶体管装置100的阵列300，单个栅极绝缘体160侧壁及单个栅极导体150侧壁为沿着VFET装置100的一列台面120的整体在台面120的第二侧122上延伸的单个栅极140的组件。或者，一系列分离的栅极140可沿着VFET装置100的一列台面120中的台面120的第二侧122延伸。
阵列300的VFET装置100内的台面120可界定在台面120的第一侧121与第二侧122之间通过的沟道区130(图1)。沟道区130可与源极区(未展示)及漏极区(未展示)连通。可通过此项技术中已知的任何适合技术形成所述源极区及漏极区。
垂直晶体管装置100的阵列300可进一步包含具有与第一多个台面120相同的阵列300的一个或一个以上额外的多个台面120。多个台面120可通过第二沟槽210彼此均匀且平行地间隔开。
阵列300的每一列具有由一对栅极导体150侧壁的外部表面界定的宽度，所述宽度C可为每一个别VFET装置100的宽度。每一VFET装置100的宽度C等于或约等于分离最初形成的金属籽晶110的沟槽的宽度M(图2)。因此，VFET装置100的最终宽度C可通过调整所形成金属籽晶110的宽度M而按比例缩放。另外，金属籽晶110以间距形成，其中在业内已知“间距”指代相邻特征中的相同点之间的距离。显著地，金属籽晶110的间距等于或基本上等于所形成VFET装置100的所得间距。
应理解，此后，所形成VFET装置100及阵列300可经受额外处理以形成顶部触点、金属互连件、VFET100阵列300的额外堆叠层等，其结果可为交叉点存储器阵列的形成。可通过本文中未详细描述的常规技术来进行额外处理。
返回参考图10，还揭示垂直晶体管装置100的阵列，其中沿着金属籽晶线110的垂直侧进一步提供栅极导体150侧壁。举例来说(而不限于)，VFET装置100的阵列300的栅极导体150侧壁可沿着金属籽晶110的第一侧111及／或第二侧112提供。
图12到21描绘根据用于制作半导体装置(例如VFET100装置)以及用于制作垂直晶体管装置100的阵列300的本发明方法的另一实施例处理多个垂直晶体管的各种阶段。图12及13分别描绘与图2及3中所描绘的处理阶段相同的处理阶段。图12的描述等效于图2的描述，且图13的描述等效于图3的描述。
参考图14，用于形成半导体装置的方法的本发明实施例包含：在于金属籽晶110上形成导体材料以便形成栅极导体150之后，在多个栅极导体150侧壁中的每一者上形成绝缘体材料以形成多个栅极绝缘体160侧壁。本发明实施例的方法进一步包含在金属籽晶110的栅极导体150顶部壁或顶部侧116上形成绝缘体材料。可保形地形成所述绝缘体材料。由于金属籽晶110可彼此均匀地平行间隔开，因此所形成栅极绝缘体160侧壁可彼此均匀地间隔开，使得在相对栅极绝缘体160侧壁之间界定的每一第一沟槽170界定宽度T(图14)。
本发明实施例的方法包含使衬底50的位于第一沟槽170内的部分暴露。使衬底50的在第一沟槽170内的部分暴露可通过仅在金属籽晶110的第一侧111、第二侧112及／或顶部侧116上而不在第一沟槽170内的衬底50上形成绝缘体材料来实现。使衬底50的在第一沟槽170内的部分暴露可替代地通过在金属籽晶110的第一侧111、第二侧112及顶部侧116上且也在第一沟槽170内的衬底50上形成绝缘体材料、后续接着移除栅极绝缘体160底部壁(即，覆盖第一沟槽170内的衬底50的绝缘体材料)来实现。可通过任何适合技术来实现绝缘体材料的移除，包含蚀刻。
可通过任何适合技术来形成栅极绝缘体160侧壁的绝缘体材料，包含(但不限于)ALD、等离子增强ALD、PVD或其它已知方法。栅极绝缘体160的绝缘体材料可包括任何适合绝缘材料。举例来说(而不限于)，栅极绝缘体160的材料可为氧化物。
参考图15，所述方法的本发明实施例可进一步包含用第二绝缘体材料180填充第一沟槽170。第二绝缘体材料180可不仅填充第一沟槽170从而覆盖经暴露衬底50，而且可覆盖栅极绝缘体160顶部壁。可通过任何适合方法来实现用第二绝缘体材料180填充第一沟槽170，包含(而不限于)通过旋涂、毯覆式涂覆、CVD、PVD、原位生长或其它已知方法。第二绝缘体材料180可为任何适合绝缘材料。举例来说(而不限于)，第二绝缘体材料180可为常规ILD材料，例如氮化硅。
参考图16，所述方法的本发明实施例可进一步包含：如果必要，那么移除第二绝缘体材料180的部分、栅极绝缘体160材料的部分及栅极导体150材料的部分以暴露金属籽晶110的顶部侧116。此可通过任何适合方法来实现，包含(而不限于)磨料平面化方法，例如化学机械抛光或平面化(“CMP”)或蚀刻工艺。
参考图17到19，所述方法的本发明实施例可进一步包含选择性地移除第二绝缘体材料180的分段以暴露衬底50的下伏于第二绝缘体材料180的被移除的分段下的区段。此可如上文参考图7到9所描述来实现。
根据所述方法的本发明实施例，每一腔200的底部侧205由衬底50的经暴露上部表面接界及界定。每一腔200的顶部侧206保持敞开。
图20及21分别描绘与图10及11中所描绘的处理阶段相同的处理阶段。图20的描述等效于图10的描述，且图21的描述等效于图11的描述。
应理解，此后，图21中所描绘的所形成VFET装置100及阵列300可经受额外处理以形成顶部触点、金属互连件、VFET装置100的阵列300的额外堆叠层等，其结果可为交叉点存储器阵列的形成。可通过本文中未详细描述的常规技术来进行额外处理。
VFET装置100及阵列300可用于包含电耦合到VFET装置100的存储器单元(未展示)的存储器存取装置(未展示)中。所述存储器单元包含顶部电极(未展示)及底部电极(未展示)，其耦合到用于漏极的触点(未展示)。源极耦合到另一触点。在偏置源极触点、栅极140及顶部电极后，VFET装置100即刻接“通”且电流流动穿过沟道区130及存储器单元。
尽管所揭示装置结构及方法易于在其实施方案上做出各种修改及替代形式，但已在图式中以实例的方式展示且已在本文中详细地描述特定实施例。然而，应理解，本发明并不打算限制于所揭示的特定形式。而是，本发明涵盖归属于由所附权利要求书及其合法等效内容界定的本发明范围内的所有修改、组合、等效内容、变化及替代方案。

Claims (20)

1.一种半导体装置结构，其包括：
台面，其在衬底上面延伸，所述台面包括：
沟道区，其在所述台面的第一侧与第二侧之间；
第一栅极，其在所述台面的所述第一侧上，所述第一栅极包括：
第一栅极绝缘体；及
第一栅极导体，其包括上覆于所述第一栅极绝缘体上的石墨烯。
2.根据权利要求1所述的半导体装置，其进一步包括：
第二栅极，其在所述台面的所述第二侧上，所述第二栅极包括：
第二栅极绝缘体；及
第二栅极导体，其包括上覆于所述第二栅极绝缘体上的石墨烯。
3.根据权利要求2所述的半导体装置，其进一步包括：
第一金属籽晶，其在所述第一栅极导体上，及
第二金属籽晶，其在所述第二栅极导体上。
4.根据权利要求2所述的半导体装置，其中所述第二栅极操作以结合所述第一栅极来控制所述沟道区中的电流流动。
5.根据权利要求1所述的半导体装置，其中所述第一栅极导体包括至少一个石墨烯层。
6.根据权利要求1所述的半导体装置，其中所述第一栅极导体的厚度小于所述第一栅极绝缘体的厚度。
7.根据权利要求1所述的半导体装置结构，其中所述半导体装置结构安置于垂直晶体管装置阵列内，所述垂直晶体管装置阵列包括：
第一多个所述台面，其在所述衬底上面延伸，所述第一多个台面中的每一台面包括：
所述第一侧及所述第二侧，所述第二侧与所述第一侧相对，所述第一多个所述
台面中的所述台面的所述第一侧彼此对准，且所述第一多个台面中的所述台面的所
述第二侧彼此对准；
所述第一栅极绝缘体，其沿着所述台面的所述第一侧；及
所述第一栅极导体，其沿着所述第一栅极绝缘体；及
第一多个绝缘体材料分段，所述第一多个分段中的每一绝缘体材料分段将所述第一多个所述台面中的所述台面中的一者与所述第一多个台面内的另一台面分离。
8.根据权利要求7所述的半导体装置结构，其中所述第一多个台面中的每一台面进一步包括：
第二栅极绝缘体，其沿着所述第一多个台面中的所述每一台面的所述第二侧；及
第二栅极导体，其沿着所述第二栅极绝缘体，所述第二栅极导体包括石墨烯。
9.根据权利要求7所述的半导体装置结构，其中所述第一栅极导体沿着金属籽晶的垂直侧定位。
10.根据权利要求7所述的半导体装置结构，其中所述垂直晶体管装置阵列进一步包括：
栅极绝缘体侧壁，其包括沿着所述第一多个台面中的所述台面的所述第一侧的所述第一栅极绝缘体；及
栅极导体侧壁，其包括沿着所述第一多个台面中的所述台面的所述第一栅极绝缘体的所述第一栅极导体。
11.一种用于制作半导体装置结构的方法，其包括：
在衬底上形成多个金属籽晶；
在所述多个金属籽晶中的每一者上形成导体材料以形成多个栅极导体；
在所述多个栅极导体中的每一者上形成绝缘体材料以形成多个栅极绝缘体，所述多个栅极绝缘体中的第一栅极绝缘体通过第一沟槽与所述多个栅极绝缘体中的第二栅极绝缘体分离；及
用沟道材料填充所述第一沟槽以形成沟道区。
12.根据权利要求11所述的方法，其中形成多个金属籽晶包括：形成所述多个金属籽晶使得所述金属籽晶彼此间隔开第一距离且平行布置。
13.根据权利要求12所述的方法，其中在所述多个栅极导体中的每一者上形成所述绝缘体材料以形成所述多个栅极绝缘体包括：形成所述绝缘体材料使得所述第一沟槽具有小于所述第一距离的宽度。
14.根据权利要求11所述的方法，其中在所述多个金属籽晶中的每一者上形成导体材料包括：在所述多个金属籽晶中的每一者上形成至少一个石墨烯层。
15.根据权利要求11所述的方法，其中用沟道材料填充所述第一沟槽包括：
用第二绝缘体材料填充所述第一沟槽；
移除所述第二绝缘体材料的分段以暴露所述衬底的下伏区段且界定腔；及
用所述沟道材料填充所述腔以形成在第一侧上由所述第一栅极绝缘体接界且在第二侧上由所述第二栅极绝缘体接界的所述沟道区。
16.根据权利要求15所述的方法，其中在所述多个金属籽晶材料中的每一者上形成导体材料包括：在所述多个金属籽晶材料的每一垂直侧上形成至少一个石墨烯单层。
17.根据权利要求15所述的方法，其中在所述多个栅极导体中的每一者上形成绝缘体材料包括：将氧化物材料上覆于所述多个栅极导体的每一垂直侧上。
18.根据权利要求15所述的方法，其中用第二绝缘体材料填充所述第一沟槽包括：用氧化硅或氮化硅填充所述第一沟槽。
19.根据权利要求15所述的方法，其进一步包括：在用所述沟道材料填充所述腔之后，移除所述多个金属籽晶。
20.根据权利要求15所述的方法，其进一步包括：在用所述沟道材料填充所述腔之前，移除所述第二绝缘体材料的其它分段以暴露所述衬底的其它下伏区段且界定包括所述腔的多个腔，所述多个腔彼此相等地间隔开。
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