CN103329250A - 通过高密度等离子体化学气相沉积（hdp-cvd）形成的多晶硅薄膜 - Google Patents

通过高密度等离子体化学气相沉积（hdp-cvd）形成的多晶硅薄膜 Download PDF

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CN103329250A
CN103329250A CN2011800657605A CN201180065760A CN103329250A CN 103329250 A CN103329250 A CN 103329250A CN 2011800657605 A CN2011800657605 A CN 2011800657605A CN 201180065760 A CN201180065760 A CN 201180065760A CN 103329250 A CN103329250 A CN 103329250A
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A·王
X·陈
Y·S·李
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Abstract

描述形成多晶硅层的方法。所述方法包括在含有沉积基板的基板处理区域中从硅前驱物形成高密度等离子体。所描述的方法在相对于现有技术降低的基板温度（例如，＜500℃）下产生多结晶膜。偏压等离子体功率调整的可行性更使得所形成的多晶硅层的共形性的调整成为可能。当掺杂剂被包括在高密度等离子体中时，掺杂剂能够以掺杂剂不需要单独的激发步骤的方式被并入到多晶硅层内。

Description

通过高密度等离子体化学气相沉积(HDP-CVD)形成的多晶硅薄膜
相关申请的交互引用
本申请是2011年4月19日提交且发明名称为“通过高密度等离子体化学气相沉积形成的多晶硅薄膜（POLYSILICONFILES BY HDP-CVD）”的美国专利申请号13/089,966的PCT申请，并且本申请涉及和要求2011年1月24日提交且发明名称为“通过高密度等离子体化学气相沉积的多晶硅薄膜的沉积（DEPOSITION OF POLYSILICON FILM BY HDP-CVD）”的美国临时专利申请号61/435,487的优先权，这些专利申请为了所有目的通过引用整体地被并入到本文。
发明背景
自从半导体组件在数十年前引进以来，半导体组件几何形状在尺寸上已经显著地减小。现代半导体制造设备常规地生产具有45nm、32nm与28nm特征尺寸的组件，并且新设备正在被开发且被实现用来制造具有甚至更小的几何形状的组件。减小的特征尺寸在组件上造成具有减小的空间尺寸的构造特征。组件上的间隙与沟槽的宽度狭窄到间隙深度与间隙宽度的深宽比（aspect ratio）变得高到足以使得利用材料来填充间隙是富有挑战性的。
多结晶硅（常常简化成多晶硅）是在生产微电路与太阳能电池中具有多次使用的材料。最普遍地藉由热化学气相沉积（例如，LP-CVD）来沉积多晶硅。还已经使用等离子体增强CVD（即，PE-CVD）来沉积以及通过非晶硅的再结晶来形成多晶硅。在许多应用中，多晶硅被掺杂且被用作栅极或电极。在其它应用中，多晶硅被用作晶体管本身的部分，在所述情况下晶体管可被掺杂或是本征的。应用的多样性需要灵活的方法，以共形地以及非共形地沉积多晶硅。
需要新的沉积方法，这些新的沉积方法可提供改变多晶硅层的沉积的共形性的灵活性。这些新方法还应使得在降低的基板温度下的沉积成为可能，以为了维持在渐增的严格的热预算内。
发明内容
描述形成多晶硅层的方法。所述方法包括在含有沉积基板的基板处理区域中从硅前驱物形成高密度等离子体。所描述的方法在相对于现有技术降低的基板温度（例如，＜500℃）下产生多结晶膜。偏压等离子体功率调整的可行性更使得所形成的多晶硅层的共形性的调整成为可能。当掺杂剂被包括在高密度等离子体中时，掺杂剂能够以掺杂剂不需要单独的激发步骤的方式被并入到多晶硅层内。
本发明的实施例包括将多晶硅层沉积在图案化基板的沟槽中的方法，所述图案化基板位于基板处理腔室的基板处理区域中。所述方法包含将所述图案化基板传送到所述基板处理区域内。所述方法更包含藉由在所述基板处理区域中从包含硅源的沉积工艺气体形成高密度等离子体以在所述图案化基板上生长所述多晶硅层，同时将所述基板处理区域内的平均压力维持在约20mTorr或更小且将平均图案化基板温度维持在500℃或更小。所述方法更包含从所述基板处理区域移除所述图案化基板。
额外的实施例与特征部分地在以下的具体实施方式中阐述，并且部分地对于本领域技术人员在参阅本说明书后将变得显而易见或可藉由实施本发明而了解。可藉由本说明书中所描述的设施、组合与方法来实现且获得本发明的特征与优点。
附图说明
图1是指示根据本发明的实施例的在生长填隙多晶硅膜中的经选择的步骤的流程图。
图2是指示根据本发明的实施例的在生长共形多晶硅膜中的经选择的步骤的流程图。
图3A是根据本发明的实施例的高密度等离子体化学气相沉积系统的一个实施例的简化示意图。
图3B是可结合图3A的示范性处理系统使用的气体环的简化剖视图。
具体实施方式
描述形成多晶硅层的方法。这些方法包括在含有沉积基板的基板处理区域中从硅前驱物形成高密度等离子体。所描述的方法在相对于现有技术降低的基板温度（例如，＜500℃）下产生多结晶膜。偏压等离子体功率调整的可行性更使得所形成的多晶硅层的共形性的调整成为可能。当掺杂剂被包括在高密度等离子体中时，掺杂剂能够以掺杂剂不需要单独的激发步骤的方式被并入到多晶硅层内。
已经确定在具有或没有所施加的偏压功率的情况下有可能使用高密度等离子体技术在图案化基板上沉积多晶硅。已经发现，通常与高密度等离子体膜相关联的应力特别适应于在图案化基板上具有暴露的氧化硅的系统中。共形与底部向上的填隙沉积领域（gapfill deposition regime）都已经被确定且主要取决于偏压功率的存在与多晶硅膜生长速率。在共形与底部向上的填隙领域中，已经发现，在沉积多晶硅之前的图案化基板的氢等离子体处理能促进多晶硅层的生长。高密度等离子体化学气相沉积（HDP-CVD）技术可被用来提升填隙以及容许在降低的基板温度下的沉积。
已经发现，使用HDP-CVD的多晶硅的共形沉积发生在较低温度（例如，＜350℃）。还已经发现，在本发明的实施例中，低沉积速率（例如，
Figure BDA00003551917500031
）和/或高压（例如，10-30mTorr）能产生共形的多晶硅膜，所述共形的多晶硅膜具有在彼此的约50%内的侧壁的（水平的）与顶部的（垂直的）生长速率。HDP-CVD还可使得底部向上的多晶硅沉积可用于填充图案化基板上的间隙与沟槽。已经发现，暴露的图案化基板的氢预处理能有助于产生具有柱状和/或颗粒状构造两者的致密的多晶硅膜。这可能源自以氢来清洁暴露的基板和/或化学地终止暴露的表面。
如在此所使用的，高密度等离子体工艺是利用等离子体的一种等离子体CVD工艺，所述等离子体具有1011离子/cm3或更大的数量级的离子密度。高密度等离子体还可具有10-4或更大的数量级的离子化比率（离子/中性粒子比例）。通常，HDP-CVD工艺包括同时的沉积与溅射部分。本发明中所体现的一些HDP-CVD工艺不同于传统的HDP-CVD工艺，本发明中所体现的一些HDP-CVD工艺通常为了填隙而被优化。在一些步骤与实施例中，共形的多晶硅膜是以实质上降低（＜总等离子体功率的10%）的基板偏压功率来达成且因此产生比利用显著偏压功率的HDP-CVD工艺更少的溅射。尽管这与传统的HDP工艺参数有偏差，但涉及溅射与沉积速率的尺度表征是有用的且被定义在下文中。
高密度等离子体的组合的沉积与溅射特征的相对水平可取决于诸如用以提供气体混合物的气体流速、被施加以维持等离子体的源功率水平、被施加到基板的偏压功率等因素。可藉由“沉积与溅射的比例（deposition-to-sputter ratio）”将这些因素的组合方便地予以表征，所述“沉积与溅射的比例”被定义成
Figure BDA00003551917500041
沉积与溅射的比例随着增加的沉积而增加，并且随着增加的溅射而减少。如在沉积与溅射的比例的定义中所使用的，“净沉积速率”指当沉积与溅射同时地发生时所测量的沉积速率。“毯覆式溅射速率”是当在没有沉积气体下（例如，留下氮与流体）运行工艺制法（process recipe）时所测量的溅射速率。残余气体的流速增加，从而维持这些残余气体之间的固定比例，以在正常处理期间达到存在于工艺腔室中的压力。
可使用本领域技术人员所知道的其它功能等效的措施来将HDP工艺的相对沉积与溅射贡献予以量化。普遍的替代比例是“蚀刻与沉积的比例”
Figure BDA00003551917500051
“蚀刻与沉积的比例”随着增加的溅射而增加，并且随着增加的沉积而减少。如在蚀刻与沉积的比例的定义中所使用的，“净沉积速率”再次地指当沉积与溅射同时地发生时所测量的沉积速率。然而，“只有源（source-only）的沉积速率”指在没有溅射下运行工艺制法时所测量的沉积速率。本发明的实施例在此在沉积与溅射的比例方面进行描述。尽管沉积与溅射和蚀刻与沉积的比例不是恰好为倒数，但沉积与溅射和蚀刻与沉积的比例呈反比关系且本领域技术人员可了解沉积与溅射和蚀刻与沉积的比例之间的转换。
典型的HDP-CVD工艺朝着沟槽几何形状的填隙而调适（gear）。在填隙工艺中，基板偏压RF功率用以将离子朝向基板加速，所述离子产生窄范围的接近轨迹。所述窄化与溅射组合的活动的组合在生长的通孔（via）的顶部角落接合在一起而形成且维持孔隙之前容许间隙被填满。在这些填隙应用中的沉积与溅射的比例（D:S）的范围可以是例如从约3:1至约10:1，其中一些特殊应用具有高达例如约25:1的沉积与溅射的比例。可藉由HDP-CVD工艺使用几乎没有或没有基板偏压功率来产生根据本发明的实施例而生长的氧化硅膜。在这些状况下的毯覆式溅射速率可以是低的，并且可大致上期望沉积与溅射的比例在不同实施例中为高于约50:1至约100:1。
为了更好地了解且明了本发明，现在参照图1，图1是指示根据本发明的实施例的在生长填隙多晶硅膜中的经选择的步骤的流程图。当将具有沟槽的图案化基板传送到基板处理区域内（操作101）时，填隙多晶硅形成工艺开始。将氢（H2）引进到基板处理区域内且形成高密度等离子体（操作102），以在多晶硅被沉积之前将图案化基板的表面予以预处理。接着，使硅烷流到基板处理区域且形成高密度等离子体（操作106），以将多晶硅沉积在图案化基板上。
在操作108中，在高密度等离子体与基板之间施加等离子体偏压，以将离子朝向基板加速。因此，填隙多晶硅以底部向上的方式在沟槽中形成。可在多晶硅填隙层的生长期间调整基板偏压功率，以控制沉积与溅射的比例。在沉积期间，示范性沉积与溅射的比例的范围可以是从约2:1至约6:1。容许显著溅射在沉积期间发生减少了在被沉积的块体填隙层中显著孔隙形成的机会。
图2是指示根据本发明的实施例的在生长共形多晶硅膜中的经选择的步骤的流程图。当将基板（图案化基板或未图案化的基板）传送到基板处理区域内（操作202）时，共形多晶硅形成工艺开始。将氢（H2）引进到基板处理区域内且形成高密度等离子体（操作204），以在多晶硅被沉积之前将图案化基板的表面予以预处理。接着，使硅烷流到基板处理区域且形成未偏压（或轻度偏压）的高密度等离子体（操作206），以将多晶硅沉积在图案化基板上。几乎没有或没有等离子体偏压被施加在高密度等离子体与基板之间以将离子朝向基板加速。因此，共形多晶硅被形成在基板上。
根据在此的方法形成填隙或共形的多晶硅使得工艺在相对较低的基板温度下运行成为可能。虽然典型的热多晶硅沉积工艺可在650℃或更大的基板温度下实施，但是在本发明的实施例中，在HDP多晶硅的形成期间所使用的基板温度可低于或约为500℃、低于或约为450℃、或者低于或约为400℃。可以各种方式来控制基板的温度。在图1-2中，可使用氢等离子体将基板加热到沉积温度。在等离子体会将基板温度升高到这些范围以上的情况中，可藉由背侧氦流动将基板的背侧予以冷却。已经发现，在低于约300℃下生长多晶硅能生长多晶硅与非晶硅的混合物。
使用高密度等离子体而形成的多晶硅层可拥有可压缩应力。下方的二氧化硅材料（在实施例中存在于下方的基板的部分上）可吸收与填隙多晶硅层相关联的一些应力。
硅烷不是可用于形成多晶硅的唯一硅源。二硅烷与更高价的硅烷还可形成这些膜，在相邻的硅原子之间具有一个或多个双键的硅烷如此。在本发明的实施例中，用以形成多晶硅的硅烷缺乏卤素，以避免卤素在形成膜时被并入。大致上，这些硅源可单独地被使用或者可以任何组合彼此组合，并且共同地被称为沉积工艺气体。一些或全部的氢（H2）的取代物也是可用的。已经发现，氨（NH3）是对于预沉积处理操作有用的氢（H）源。还期望将联胺（N2H4）以及其它含氮与氢的化合物作为预处理等离子体的输入而起作用。大致上，这些氢源可单独地被使用或者可以任何组合彼此组合，并且共同地被称为预处理工艺气体。
在此所引用的任何工艺气体可与惰性气体组合，所述惰性气体可有助于稳定高密度等离子体或改善遍布基板的多晶硅沉积的均匀性。氩、氖和/或氦在本发明的实施例中被添加到这些气体且被称为流体气体（fluent gas）。可在步骤的一个或多个期间将流体气体引进，以改变（例如，增加）等离子体密度。增加等离子体密度可有助于增加等离子体内的离子化与解离的可能性。
在本发明的实施例中，掺杂剂源还可被包括在沉积工艺气体中，以为了将掺杂剂并入到一些多晶硅膜中。高密度等离子体的本质容许掺杂剂更紧密地键结在多晶硅膜内，这在实施例中可避免对单独的热掺杂剂激发步骤的需要。含硼前驱物（例如，TEB、TMB、BH3、B2H6、更高价的硼烷…）可被添加到沉积工艺气体，以为了将激发的硼（B）掺杂中心放置在形成的多晶硅层中。或者，在实施例中，可藉由将含磷前驱物（例如，PH3…）添加到沉积工艺气体而将激发的磷（P）掺杂中心包括在多晶硅层中。
在本发明的实施例中，掺杂剂源还可引进诸如碳之类的掺杂剂，这些掺杂剂和主要的原子成分（硅）是等价电子的。可藉由将碳氢化合物包括在掺杂剂源中以引进碳。适当的碳氢化合物包括CH4、C2H6、C2H4、C2H2、C3H8、C3H6等。碳掺杂的多晶硅膜中的碳浓度可以是高的，在本发明的实施例中超过10%或20%。
示范性基板处理系统
发明人已经藉由美国加利福尼亚州圣克拉拉市的应用材料公司所制造的ULTIMATM系统实施本发明的实施例，实施的概述被提供在由Fred C.Redeker、Farhad Moghadam、HirogiHanawa、Tetsuya Ishikawa、Dan Maydan、Shijian Li、Brian Lue、Robert Steger、Yaxin Wang、Manus Wong与Ashok Sinha在1996年7月15日提交的“对称调谐、感应耦合的HDP-CVD反应器（SYMMETRIC TUNABLE INDUCTIVELY COUPLEDHDP-CVD REACTOR）”的共同受让的美国专利号6,170,428中，所述专利的全部内容通过引用被并入到本文。所述系统的概观在下文结合图3A和图3B来提供。图3A示意地图示在一个实施例中的此类HDP-CVD系统310的构造。系统310包括腔室313、真空系统370、源等离子体系统380A、基板偏压等离子体系统380B、气体输送系统333、以及远程等离子体清洁系统350。
腔室313的上部包括拱顶（dome）314，所述拱顶314由陶瓷介电材料（诸如氧化铝或氮化铝）制成。拱顶314定义等离子体处理区域316的上边界。等离子体处理区域316的底部由基板317的上表面与基板支撑构件318来界定。
加热板323与冷却板324位于顶上且热耦接到拱顶314。加热板323与冷却板324容许将拱顶温度控制在约100℃至200℃范围的约+10℃内。这容许优化拱顶温度以用于各种工艺。例如，可期望将拱顶维持在较高的温度，以为了供清洁或蚀刻工艺所用而不是为了供沉积工艺所用。拱顶温度的精确控制还可减少腔室中的剥片或粒子数并可改善经沉积的层与基板之间的黏附性。
腔室313的下部包括主体构件322，所述主体构件322将腔室接合到真空系统。基板支撑构件318的基底部分321被装设在主体构件322上且连同主体构件322形成连续的内表面。藉由机械人叶片（未图示）将基板经由位于腔室313的侧中的插入口/移除口（未图示）传送到腔室313内与从腔室313传送出。举升销（未图示）在马达（也未图示）的控制下被升高且接着被降低，以将基板从上装载位置357处的机械人叶片移动到下处理位置356，基板在下处理位置356处被放置在基板支撑构件318的基板接收部分319上。基板接收部分319包括静电夹盘320，所述静电夹盘320在基板处理期间将基板固持到基板支撑构件318。在较佳的实施例中，基板支撑构件318由氧化铝或铝陶瓷材料制成。
真空系统370包括节流主体325，所述节流主体325容纳双叶片节流阀326且接附到闸阀327和涡轮分子泵328。应注意，节流主体325对气体流提供最小的阻碍且容许对称的泵送。闸阀327可将泵328与节流主体325分隔，并且还可在节流阀326完全开启时藉由限制排放流量来控制腔室压力。节流阀、闸阀与涡轮分子泵的配置容许对高达约1mTorr至约2Torr的腔室压力的精确与稳定控制。
源等离子体系统380A包括被装设在拱顶314上的顶线圈329与侧线圈330。对称的接地屏蔽（未图示）减少这些线圈之间的电气耦接。顶线圈329由顶源RF（SRF）产生器331A提供功率，而侧线圈330由侧SRF产生器331B提供功率，从而容许了每一线圈有独立的功率水平与操作频率。所述双线圈系统容许对腔室313中的径向离子密度的控制，藉此改善等离子体均匀性。侧线圈330与顶线圈329通常感应地被驱动，这不需要补充电极（complimentary electrode）。在特定的实施例中，顶源RF产生器331A在名义上以2MHz提供高达5000瓦的RF功率，且侧源RF产生器331B在名义上以2MHz提供高达7500瓦的RF功率。顶与侧RF产生器的操作频率可偏离名义上的操作频率（例如，分别达1.7-1.9MHz与1.9-2.1MHz），以改善等离子体产生效率。
基板偏压等离子体系统380B包括偏压RF（“BRF”）产生器331C与偏压匹配网络332C。偏压等离子体系统380B将基板部分317感应地耦合到主体构件322，作为补充电极。偏压等离子体系统380B用以提升由源等离子体系统380A所产生的等离子体物质（例如，离子）到基板表面的传送。在特定的实施例中，基板偏压RF产生器以约13.56MHz的频率提供高达10000瓦的RF功率。
RF产生器331A与331B包括数字受控的合成器。每一产生器包括RF控制电路（未图标），所述RF控制电路测量从腔室和线圈被反射且返回到产生器的功率并调整操作频率以获得最低的反射功率，如本领域技术人员所能了解的。RF产生器通常被设计以运作成具有50ohms的特征阻抗的负载。RF功率可从负载被反射，这些负载具有与产生产器不同的特征阻抗。这可减少被传送到负载的功率。此外，从负载被反射回到产生器的功率可能超载且损坏产生器。由于等离子体的阻抗的范围可从小于5ohms到超过900ohms（取决于等离子体离子密度以及其它因素），且由于反射功率可以是频率的函数，因此根据反射功率而调整产生器频率可增加从RF产生器被传送到等离子体的功率且保护产生器。另一种减少反射功率且改善效率的方式是藉由匹配网络。
匹配网络332A与332B藉由各自的线圈329与330而匹配产生器331A与331B的输出阻抗。藉由在负载改变时改变匹配网络内的电容器的值以使产生器匹配负载，RF控制电路可调谐所述两个匹配网络。当从负载被反射回到产生器的功率超过特定限值时，RF控制电路可调谐匹配网络。一种提供恒定匹配且有效地使RF控制电路失去调谐匹配网络的能力的方式将反射功率限值设定在高于任何预期的反射功率值。这可藉由在匹配网络的最近状况下将匹配网络保持恒定而有助于在一些状况下将等离子体予以稳定。
其它措施还可有助于将等离子体予以稳定。例如，在一层的沉积期间，RF控制电路可用以决定被输送到负载（等离子体）的功率且可增加或减少产生器的输出功率，以维持输送功率为实质上恒定。
气体输送系统333藉由气体输送线338（仅图示一些气体输送线）的方式将来自一些源334A-334E的气体提供到腔室，以用于处理基板。如本领域技术人员所能了解的，用于源334A-334E的实际源以及输送线338到腔室313的实际连接取决于在腔室313内执行的沉积与清洁工艺而改变。气体经由气体环337和/或顶喷嘴345被引进到腔室313内。图3B是腔室313的简化部分剖视图，所述图图示气体环337的额外细节。
在一个实施例中，第一与第二气体源334A与334B以及第一与第二气体流量控制器335A’与335B’藉由气体输送线338（仅图示一些气体输送线）的方式将气体提供到气体环337中的环容室336。气体环337具有多个源气体喷嘴339（为了说明起见仅图示一个源气体喷嘴），所述源气体喷嘴339在基板上方提供均匀的气体流。可改变喷嘴长度与喷嘴角度，以容许对于各个腔室内的特定工艺的均匀性轮廓与气体利用效率的订制（tailoring）。在较佳的实施例中，气体环337具有由氧化铝陶瓷制成的12个源气体喷嘴。
气体环337还具有多个氧化剂气体喷嘴340（仅图示一个氧化剂气体喷嘴），所述氧化剂气体喷嘴340在一个实施例中与源气体喷嘴339共平面且比源气体喷嘴339更短，并且在一个实施例中接收来自主体容室341的气体。在一些实施例中，期望在将气体注射到腔室313之前不要混合源气体与氧化剂气体。在其它实施例中，可在将气体注射到腔室313内之前藉由在主体容室341与气体环容室336之间提供穿孔（未图示）而混合氧化剂气体与源气体。在一个实施例中，第三、第四与第五气体源334C、334D与334D’以及第三与第四气体流量控制器335C与335D’藉由气体输送线338的方式将气体提供到主体容室。诸如343B（其它阀未图示）之类的额外的阀可切断来自流量控制器到腔室的气体。在实施本发明的特定实施例中，源334A包含硅烷（SiH4）源，源334B包含分子氮（N2）源，源334C包含TSA源，源334D包含氩（Ar）源，且源334D’包含二硅烷（Si2H6）源。
在使用可燃、有毒或腐蚀性气体的实施例中，可期望在沉积之后去除残余在气体输送线中的气体。这可使用三向阀（诸如阀343B）以例如将腔室313与输送线338A分隔且将输送线338A排空到真空前线344来达成。如图3A所示，其它类似的阀（诸如343A与343C）可被并入到其它气体输送线。此类三向阀可被设置成实际上靠近腔室313，以将未被排空的气体输送线的体积（介于三向阀与腔室之间）减到最小。此外，二向（开关）阀（未图示）可被设置在质流控制器（“MFC”）与腔室之间、或者在气体源与MFC之间。
再参照图3A，腔室313还具有顶喷嘴345与顶排放口346。顶喷嘴345与顶排放口346容许对顶与侧气体流的独立控制，这可改善膜均匀性且容许对膜沉积和掺杂参数的细微调整。顶排放口346是环绕顶喷嘴345的环状开口。在一个实施例中，第一气体源334A供应源气体喷嘴339与顶喷嘴345。源喷嘴MFC335A’控制被输送到源气体喷嘴339的气体的量，并且顶喷嘴MFC335A控制被输送到顶气体喷嘴345的气体的量。类似地，可使用两个MFC335B与335B’来控制氧从单一氧源（诸如源334B）到顶排放口346与氧化剂气体喷嘴340两者的流动。在一些实施例中，氧不从任何侧喷嘴供应到腔室。可在使气体流动到腔室313内之前将被供应到顶喷嘴345与顶排放口346的气体保持分离，或者可在使气体流动到腔室313内之前将气体在顶容室348中混合。可使用相同气体的分离源来供应腔室的各个部分。
提供远程微波产生等离子体清洁系统350，以定期地从腔室部件清洁沉积残余物。清洁系统包括远程微波产生器351，所述远程微波产生器351从清洁气体源334E（例如，分子氟、三氟化氮、其它氟碳化合物或等效物）在反应器腔体353中产生等离子体。源自所述等离子体的反应性物质藉由施用管（applicator tube）355的方式经由清洁气体馈送端口354被输送到腔室313。用以容纳清洁等离子体的材料（例如，腔体353与施用管355）必须可以抵抗等离子体的攻击。反应器腔体353与馈送端口354之间的距离应该被保持与实际一样短，因为期望的等离子体物质的浓度会随着远离反应器腔体353的距离而减少。在远程腔体中产生清洁等离子体容许有效率的微波产生器的使用且不会使腔室部件遭受原位地被形成的等离子体中可能存在的温度、辐射或辉光放电的轰击。所以，相对敏感的部件（诸如静电夹盘320）不需要被覆盖有伪晶圆（dummy wafer）或者以其它方式被保护，但这对于原位等离子体清洁工艺是需要的。在图3A中，等离子体清洁系统350被示为设置在腔室313上方，尽管可替代地使用其它位置。
挡板361可被提供在靠近顶喷嘴处，以引导经由顶喷嘴被供应的源气体流到腔室内且引导远程产生的等离子体的流动。经由顶喷嘴345被提供的源气体被引导经由中央通道362到腔室内，而经由清洁气体馈送端口354被提供的远程产生的等离子体物质藉由挡板361被引导到腔室的侧。
已经发现，对基板处理区域的内部的调质（seasoning）能改善许多高密度等离子体沉积工艺。多晶硅的形成也不例外。调质涉及在沉积基板被引进到基板处理区域内之前氧化硅在腔室内部上的沉积。在实施例中，将基板处理区域的内部予以调质包含在基板处理区域中从含有氧源与硅源的调质工艺气体形成高密度等离子体。氧源可以是二原子氧（O2）且硅源可以是硅烷（SiH4），尽管其它前驱物也是可以的。
执行对照测试，以测量被沉积在具有和不具有二氧化硅衬里层的间隙中的多晶硅膜中的应力的量。块体填隙多晶硅层被沉积在间隙中，其中所述间隙被形成在300mm直径的基板晶圆上，且所述300mm直径的基板晶圆被放置在由美国加利福尼亚州圣克拉拉市的应用材料公司所制造的Ultima HDP处理腔室中。基板在HDP-CVD沉积期间被维持在350℃下，并且所施加的总源等离子体RF功率可以是10.6瓦/cm2（7500瓦）（不包括偏压功率）。以约5.0瓦/cm2（3500瓦）的基板偏压功率来生长衬里层。在3.5-10.0瓦/cm2范围中的偏压功率（在300mm直径的晶圆上方为2500-7000瓦）在块体填隙层的多晶硅的生长期间被施加到基板。衬里层的厚度可以分别是
Figure BDA00003551917500141
与
Figure BDA00003551917500142
块体填隙层的厚度可以是约2.0μm。
本领域技术人员可了解处理参数可根据不同的处理腔室和不同的处理状况而改变且可在不悖离本发明的精神下使用不同的前驱物。适当的含硅前驱物可包括除了硅烷以外的三甲硅烷基胺（TSA、(SiH3)3N）与二硅烷（Si2H6）。其它变形对于本领域技术人员也是明显的。这些等效物与替代物旨在被包括在本发明的范围内。所以，本发明的范围不应该被局限在所描述的实施例，而是应该由随附的权利要求来界定。
本文使用术语“沟槽”没有暗示被蚀刻的几何形状具有大的水平深宽比。由表面上方观察，沟槽可呈现成圆形、椭圆形、多边形、矩形、或者各种其它形状。术语“通孔”被使用来指可被填充有或可不被填充有金属以形成垂直电连接的低深宽比沟槽。如在此所使用，共形层指位于表面上而具有与所述表面（即，所述层的表面）相同形状的大致上均匀的材料层，并且被覆盖的表面是大致上平行的。本领域技术人员可了解被沉积的材料可能无法是100%共形的，并且因此术语“大致上”容许可接受的容限。
已经描述了一些实施例，本领域技术人员可了解可在不悖离本发明的精神下使用各种变化、替代构造与等效物。此外，为了避免不必要地模糊本发明，没有描述许多已知的工艺与元件。因此，上述说明不应该被解读成会对本发明的范围构成限制。
当提供值的范围时，应了解还详细揭露介于所述范围的上下限值之间的每一中间值至下限值单位的十分之一，除非上下文另外清楚地指明。涵盖了所陈述范围中的任何陈述值或中间值与所陈述范围中任何其它陈述值或中间值之间的每一个较小范围。受制于所陈述范围中的任何特别排除的限值，这些较小范围的上限值与下限值可独立被包含在所述范围中或被排除在所述范围外，且每一范围（其中限值中的任一个、限值中的两个、或者没有限值被包括在所述较小范围中）还被涵盖在本发明内。当所陈述的范围包括限值中的一个或两个时，还包括排除那些所包括的限值的一个或两个的范围。
如在此所使用且如在随附的权利要求中所使用的，单数形式“一”、“一个”与“所述”包括复数形式，除非上下文另外清楚地指明。因此，举例而言，对“工艺”的引用包括多个此类工艺，并且对“前驱物”的引用包括本领域技术人员所知道的一个或多个前驱物以及所述一个或多个前驱物的等效物。
同样，本说明书与随附的权利要求中使用的词语“包含”、“含有”、“具有”与“包括”旨在指定所陈述的特征、整合件、部件或步骤的存在，但是所述词语并不排除一个或多个其它特征、整合件、部件、步骤、动作或群组的存在或增加。

Claims (17)

1.一种将多晶硅层沉积在图案化基板的沟槽中的方法，所述图案化基板位于基板处理腔室的基板处理区域中，所述方法包含：
将所述图案化基板传送到所述基板处理区域内；
藉由在所述基板处理区域中从包含硅源的沉积工艺气体形成高密度等离子体以在所述图案化基板上生长所述多晶硅层，同时将所述基板处理区域内的平均压力维持在约20mTorr或更小且将平均图案化基板温度维持在500℃或更小；
从所述基板处理区域移除所述图案化基板。
2.如权利要求1的方法，更包含：
在所述图案化基板上生长所述多晶硅层之前，根据包含氢源的预处理工艺气体在所述基板处理区域中的高密度等离子体中预处理所述图案化基板。
3.如权利要求1的方法，其中在生长所述多晶硅层时，基本上没有偏压被施加在所述图案化基板与所述高密度等离子体之间，以致所述多晶硅层是基本上共形的。
4.如权利要求3的方法，其中所述多晶硅层的生长速率小于约
Figure FDA00003551917400011
/分钟。
5.如权利要求3的方法，其中在所述沟槽的壁上所测量到的所述多晶硅层的水平生长速率介于环绕所述沟槽的所述开口的表面上的垂直生长速率的约50%与100%之间。
6.如权利要求1的方法，其中在生长所述多晶硅层时，等离子体偏压功率被施加在所述图案化基板与所述高密度等离子体之间，以致所述沟槽被填充有多晶硅。
7.如权利要求1的方法，其中所述硅源是硅烷。
8.如权利要求1的方法，其中所述工艺气体更包含流体气体，所述流体气体选自氩、氖与氦，所述流体气体在所述两层的至少一个的生长期间以第四流速而流动。
9.如权利要求1的方法，其中所述平均图案化基板温度小于或约为400℃。
10.如权利要求1的方法，其中所述工艺气体更包含掺杂源，所述掺杂源在生长期间将掺杂剂提供到所述多晶硅层，其中在形成所述多晶硅层之后所述掺杂剂已经被激发且不需要单独的掺杂剂激发操作。
11.如权利要求1的方法，其中所述工艺气体更包含磷或硼的源。
12.如权利要求1的方法，其中所述工艺气体包含以第四气体流速而流动的PH3。
13.如权利要求1的方法，其中在所述多晶硅层的生长期间，沉积与溅射的比例介于约2:1与6:1之间。
14.如权利要求1的方法，其中在将所述图案化基板传送到所述基板处理区域内的操作之前，以氧化硅将所述基板处理区域的内部予以调质。
15.如权利要求14的方法，其中将所述基板处理区域的内部予以调质包含：
在所述基板处理区域中从包含氧源与硅源的调质工艺气体形成高密度等离子体。
16.如权利要求15的方法，其中所述氧源是二原子氧（O2）且所述硅源是硅烷（SiH4）。
17.如权利要求1的方法，其中所述工艺气体更包含碳源，并且所述多晶硅层是碳掺杂的多晶硅层。
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