CN102903682A - 半导体器件、通过垂直层叠半导体器件配置的半导体模块结构及其制造方法 - Google Patents

半导体器件、通过垂直层叠半导体器件配置的半导体模块结构及其制造方法 Download PDF

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Publication number
CN102903682A
CN102903682A CN2012102653304A CN201210265330A CN102903682A CN 102903682 A CN102903682 A CN 102903682A CN 2012102653304 A CN2012102653304 A CN 2012102653304A CN 201210265330 A CN201210265330 A CN 201210265330A CN 102903682 A CN102903682 A CN 102903682A
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China
Prior art keywords
semiconductor device
semiconductor
organic substrate
wiring layer
film wiring
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山方修武
胜又章夫
井上广司
泽地茂典
板仓悟
山地泰弘
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Amkor Technology Japan Inc
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J Devices Corp
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Abstract

本发明涉及半导体器件、通过垂直层叠半导体器件配置的半导体模块结构及其制造方法。一种半导体器件包括：有机基板1；通孔4，沿基板的厚度方向贯穿有机基板；内部和外部电极5a，5b，在有机基板1的前和后面上并与通孔4电连接；半导体元件，经接合层3安装在有机基板1的一主表面上，其元件电路表面面向上；绝缘材料层6，密封半导体元件及其周边；金属薄膜布线层7，在绝缘材料层中提供，其一部分在外表面上暴露；金属过孔10，在绝缘材料层中并与布线层7电连接；以及，外部电极9，在布线层7上形成，其中布线层7被构造为电连接在半导体元件2的元件电路表面上的电极、电极5a、金属过孔10以及在布线层上形成的外部电极9。

Description

半导体器件、通过垂直层叠半导体器件配置的半导体模块结构及其制造方法
技术领域
本发明涉及半导体器件通过层叠半导体器件配置的半导体模块结构及其制造方法。 
更具体地，本发明涉及面板级扇出封装结构（Panel scale fan-out package structure），其中以面板级进行所述薄膜布线工艺和组装工艺，并且更具体地，本发明可以应用于具有其中多个封装被垂直层叠的结构的半导体层叠模块。 
背景技术
根据最近对功能更高和更轻、更薄以及更小的电子装备的要求，电子部件的高密度集成和更高密度装配被发展并且还发展了在前述电子装备中使用的比以前更进一步缩小尺寸的半导体器件。 
作为制造半导体器件（例如LSI单元或者IC模块）的方法，存在这样的方法，包括最初以预定的设置将在电学性能测试中被检测为无缺陷的多个半导体元件设置并附接在保持板上，其中元件电路表面面向下，之后整体树脂密封多个半导体元件（例如，通过在其上布置树脂片并且通过加热和加压使其成型），随后剥离保持板，将树脂封装体切割并且处理成预定形状（例如，圆形）随后，在嵌入树脂密封体中的半导体元件的元件电路表面上形成绝缘材料层，在绝缘材料层中形成开口以便与半导体元件的电极衬垫对齐，之后，在绝缘材料层上形成布线层，在开口中形成导电部（过孔部）用于与半导体元件的电极衬垫连接，随后形成阻焊剂层，形成焊料球作为外电极端子，并且之后单独切割半导体元件以完成半导体器件（例如，参考日本专利申请公开No.2003-197662）。 
然而，如上获得的传统半导体器件，一但整体树脂密封多个半导体元件，因为树脂的硬化和收缩，并且收缩量未必是所设计的，所以存在树脂固化后位置依赖于半导体元件的设置而从设计位置偏离的情况，并且，伴随半导体元件具有这样的位置偏离，在绝缘材料层的开口中形成的过孔部和半导体元件的电极衬垫之间形成位置偏离，并且存在连接可靠性下降的问题。 
在日本专利申请公开No.2010-219489中描述了解决前述问题的半导体器件。 
在图14中示出了该半导体器件的基本结构。 
半导体器件30包括从硬化树脂体或金属配置的平板31，在其一个主表面上布置半导体元件32，其中元件电路表面面向上，并且与元件电路表面相对的面（背面）通过粘接剂33固定到平板31。另外，在平板31的整个主表面上形成一个绝缘材料层34以便覆盖半导体元件32的元件电路表面。在前述单个绝缘材料层34上形成由如铜的导电金属构成的布线层35，并且其一部分被引出到半导体元件32的周边区域。另外，在半导体元件32的元件电路表面上形成的绝缘材料层34中形成过孔部36用于电连接电极衬垫（未示出）和半导体元件32的布线层35。与布线层35共同并且集成地形成过孔部36。另外，在布线层35的预定位置上形成作为外电极的多个焊料球37。另外，在绝缘材料层34上和除与焊料球37接合的部分之外的布线层35上形成如阻焊剂层38的保护层。 
在日本专利申请No.2010-219489中描述的半导体器件，在基于前述配置的半导体元件的电极和布线层之间具有高的连接可靠性，并且使得能够廉价且高成品率地制造与电极的小型化兼容的半导体器件产品。 
然而，在日本专利申请公开No.2010-219489中描述的半导体器件，难以提供贯穿封装的前和后表面的过孔，并且因此，存在其中器件不能满足应用于三维结构的层叠模块（其中其它半导体封装或者电路板层叠在半导体封装上）的要求的问题，并且该问题最近几年发展迅速。 
如最近的趋势，要求缩小半导体封装尺寸和增加要安装的半导体元件 数目。为了符合这些要求，提出并发展了以下方面；即，具有POP（层叠封装（Package-on-Package））结构的半导体器件，其中其它半导体封装或者电路板层叠在半导体封装上（日本专利申请公开No.2008-218505）和具有TSV（硅通孔）结构的半导体器件（日本专利申请公开No.2010-278334）. 
现在基于图15解释常规POP结构半导体器件。POP（层叠封装）是一种封装模式，其中多个不同的LST被装配为为独立的封装，测试并且其后附加地层叠封装。 
通过在半导体封装41上层叠另一个半导体封装42配置半导体器件40。在下半导体封装41的基板43上装配半导体元件44，并且在半导体元件44的周边形成的电极衬垫（未示出）和在基板上的电极衬垫45通过线46电连接。半导体元件44的整个表面用封装构件47密封。另外，基于回流，半导体封装41和半导体封装42通过在半导体封装42的下表面上形成的外部连接端子48（焊料球）互相电连接。 
POP是有利的，因为作为如上所述层叠多个封装的结果，可以在装配器件时增加装配面积，并且因此每个封装可以单独测试，可以减少成品率损失。然而，使用POP，因为独立封装被独立的组装并且层叠完成的封装，难以基于半导体元件尺寸的减小（缩小）减少组装的成本，并且存在层叠模块的组装成本很昂贵的问题。 
现在参考图16解释常规TSV结构半导体器件。如在图16中所示，半导体器件50具有这样的结构，其中具有相同的功能和结构并且使用相同的制造掩模分别制造的多个半导体元件51和一个插入基板52通过树脂层53层叠。每个半导体元件51都是使用硅基板的半导体元件，并且通过贯穿硅基板的多个贯通电极（TSV：硅通孔）54与上和下邻接半导体元件电连接并且用封装树脂55密封。同时，插入基板52是由树脂构成的电路板并且在其背面上形成有多个外部连接端子（焊料球）56。 
常规TSV（硅通孔）层叠模块结构，因为向每个独立半导体元件提供通孔，半导体元件有被破坏的可能性，并且还需要增加几个复杂的并且昂 贵的在通孔中形成过孔电极的晶片处理。因此，这导致整个垂直层叠模块的显著成本增加。另外，对于常规结构，难以层叠并安装不同尺寸的芯片，并且归因于如在存储器件中的在相同的芯片上层合所必需的“为每个层提供不同重布线层”，与普通的存储模块比较，制造成本显著增加，并且存在不可能基于大规模制造降低成本的问题。 
发明内容
提供本发明，目的是解决前述问题并且本发明的一个目标是提供具有包括贯穿前和后面的电极的结构的半导体器件，其可以采取包括POP型结构的垂直层叠结构并且其中不同尺寸的LSI芯片可以容易地垂直层叠。 
作为获得前述目标的大量研究的结果，发明人通过发现可以通过下述配置获得前述目标而完成了本发明；使用有机基板作为用于安装半导体元件支撑，提供在厚度方向上贯穿有机基板的通孔，向有机基板的前和后面提供外部电极和内部电极并且与通孔电连接，并且通过在绝缘材料层中提供的金属薄膜布线层来电连接在半导体元件的元件电路表面上设置的电极、内部电极、在绝缘材料层中的金属过孔和在金属薄膜布线层上形成的外部电极。 
换句话说，本发明如下所述。 
（1）一种半导体器件，包括： 
有机基板； 
通孔，在基板的厚度方向上贯穿所述有机基板； 
外部电极和内部电极，被提供到所述有机基板的前面和后面并且电连接到所述通孔； 
半导体元件，通过接合层安装在所述有机基板的一个主表面上，所述半导体元件的元件电路表面面向上； 
绝缘材料层，用于密封所述半导体元件及其周边； 
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露； 
金属过孔，被提供在所述绝缘材料层中并且电连接到所述金属薄膜布线层；以及， 
在所述金属薄膜布线层上形成的外部电极， 
其中所述金属薄膜布线层被构造为电连接设置在所述半导体元件的所述元件电路表面上的电极、所述内部电极、所述金属过孔以及在所述金属薄膜布线层上形成的所述外部电极。 
（2）根据上述（1）的半导体器件，其中由分别地不同绝缘材料构成的多种绝缘材料层形成所述绝缘材料层。 
（3）根据上述（1）或（2）的半导体器件，其中以多个层的形式提供所述金属薄膜布线层和与其连接的所述金属过孔。 
（4）根据上述（1）到（3）的任意一个的半导体器件，其中未电连接到所述绝缘材料层中的所述金属薄膜布线层的通孔被设置在所述有机基板的面向所述半导体元件的区域中。 
（5）根据上述（1）到（4）的任意一个的半导体器件，其中在所述有机基板上提供多个半导体元件。 
（6）一种模块结构，其中多个根据上述（1）到（5）中的任一项的所述半导体器件通过连接在所述半导体器件中的一个上的所述金属薄膜布线层上形成的所述外部电极和在其它半导体器件的所述有机基板上暴露的外部电极而在垂直于所述半导体器件的主平面的方向上被层叠。 
（7）根据上述（6）的模块结构， 
其中所述半导体器件是根据上述（4）的所述半导体器件。 
（8）一种制造半导体器件的方法，所述方法包括如下步骤： 
在有机基板中形成通孔，所述通孔在厚度方向上贯穿所述有机基板； 
形成外部电极和内部电极，所述外部电极和内部电极被提供到所述有机基板的前面和后面并且电连接到所述通孔； 
在所述有机基板的一个主表面上定位并设置多个半导体元件，所述半导体元件的元件电路表面面向上，并且然后将这些半导体元件的与所述元件电路表面相对的面固定到所述有机基板上； 
在所述半导体元件及其周边上形成绝缘材料层； 
在所述绝缘材料层中形成开口； 
在所述绝缘材料层上形成金属薄膜布线层，所述金属薄膜布线层的一部分延伸到所述半导体元件的周边区域，并且在所述绝缘材料层中的所述开口中形成作为导电部的金属过孔，所述金属过孔被连接到在所述半导体元件的所述元件电路表面上设置的电极； 
在所述金属薄膜布线层上形成外部电极；以及 
通过在预定位置处切割所述有机基板和所述绝缘材料层，分离包括一个或多个半导体芯片的所述半导体器件。 
（9）一种制造半导体层叠模块的方法，其中根据上述（1）到（5）的任意一个的多个所述半导体器件通过以在所述半导体器件中的一个的所述金属薄膜布线层上形成的所述外部电极被连接到在另一半导体器件的所述有机基板上暴露的所述外部电极的方式而在垂直于所述半导体器件的主平面的方向上被层叠。 
本发明的半导体器件产生以下效果。 
能够形成处于POP-型结构等等的垂直层叠结构。没有穿通电极的LSI芯片可以容易地被垂直层叠。通过大面板级组装实现了基于半导体元件尺寸的减小的可观的成本下降。因为不再要求为每层提供不同的布线层（这是在存储器件等等中在相同的芯片上层合（lamination）时所必需的），所以大大降低了制造成本。可以防止使用TSV工艺时对器件的破坏。促进了薄芯片的处理。通过热过孔可以提高热性能。 
附图说明
图1示出了根据本发明的半导体器件的实施例1的截面图。 
图2A到2E示出了实施例1的半导体器件的制造方法，以及是示出了其部分工艺的截面图。 
图3F到3I示出了实施例1的半导体器件的制造方法，以及是示出了其部分工艺的截面图。 
图4J和4K示出了实施例1的半导体器件的制造方法，以及是示出了其部分工艺的截面图。 
图5是示出了根据本发明的半导体器件的实施例2的截面图。 
图6是示出了根据本发明的半导体器件的实施例3的截面图。 
图7是示出了根据本发明的半导体器件的实施例4的截面图。 
图8是示出了根据本发明的半导体器件的实施例5的截面图。 
图9是示出了根据本发明的半导体器件的实施例6的截面图。 
图10是示出了根据本发明的半导体器件的实施例7的截面图。 
图11是示出了根据本发明的半导体器件的实施例8的截面图。 
图12是示出了根据本发明的半导体器件的实施例9的截面图。 
图13是示出了根据本发明的半导体器件的实施例10的截面图。 
图14是示出了常规半导体器件的结构的截面图。 
图15是示出了常规POP结构半导体器件的结构的示意图。 
图16是示出常规TSV结构半导体器件的结构的示意图。 
具体实施方式
现在解释用于实施本发明的实施例。注意，虽然下面参考附图解释了实施例，但是提供其附图仅用于图解，并且本发明不以任何方式限制到附图。 
实施例1 
图1示出了实施例1的垂直截面图，实施例1表示根据本发明的半导体器件的基本配置。 
半导体器件20包括由硬化树脂体构成的有机基板1，半导体元件2被布置在基板1的一个主表面上，其中具有电极（未示出）的元件电路表面面向上以及与元件电路表面相对的面（背面）通过粘接剂3固定到有机基板1。向有机基板1提供在厚度方向上贯穿有机基板的通孔4，并且向有机基板1的前和后面提供与通孔4电连接的内部电极5a和外部电极5b。因为在有机基板1中形成用于提供通孔4的通孔，所以具有高处理强度的材 料被用作有机基板材料。例如，其中在玻璃布（glass cloth）中浸入树脂的复合材料可以用作此类有机基板1。另外，有机基板的两个面都被铜箔覆盖。 
另外，在有机基板1的整个主表面上形成绝缘材料层6以覆盖半导体元件2的元件电路表面。在绝缘材料层6上形成金属薄膜布线层（此后也称为“布线层”）7，该层7构成由诸如铜的导体金属制造的金属布线，并且其一部分延伸到所述半导体元件2的周边区域。在半导体元件2的电极表面上提供过孔部8，并且由此布线层7和半导体元件2的电极电连接。在布线层7上的预定位置形成如焊料球的多个外部电极9。在绝缘材料层6中提供用于电连接布线层7和与通孔4电连接的内部电极5a的金属过孔10。在绝缘材料层6上和除了与外部电极9接合的部分之外的布线层7上形成布线保护膜11。可以由与绝缘材料层的绝缘材料相同或者不同的材料形成布线保护膜11. 
对于上述半导体器件20，在半导体元件2上的电极被通过金属薄膜布线层7电连接到金属过孔10，并且金属过孔10被电连接到有机基板1上的内部电极5a和外部电极9。因为如上所述地构造半导体器件20，半导体元件2的端子（电极）变为与在半导体器件的前和背面两者上的外部电极（5b，9）电连接，并且相同结构的封装可以被层叠和装配。 
下面解释制造这样的实施例1的半导体器件20的方法。 
对于下面解释的制造方法，使有机基板1显著大于本发明的半导体元件2的尺寸，多个半导体元件2被分别间隔地安装在有机基板1上，通过预定处理工艺同时制造多个半导体器件，并且最终将获得的多个半导体器件分隔成独立的半导体器件以获得多个半导体器件。 
因此，通过同时制造多个半导体器件，有可能明显抑制制造成本。 
另外，虽然此实施例解释了在有机基板上具有一个半导体元件的实施例，但是在有机基板上提供多个半导体元件的情况同样是本发明的实施例。 
现在参考图2到4解释半导体器件的制造工艺。 
图2A是示出了在形成通孔前的有机基板1的示意图。作为有机基板1， 可以使用基板12，其中玻璃布用作基础材料，诸如环氧树脂的热固化树脂被浸入其中并且被硬化。铜箔13被附接并固定到基板12的前和后面。 
图2B是示出了在有机基板1中形成的用于形成通孔的通孔4’的状态。通过使用微孔钻形成通孔4’。在附图中，虽然用钻共同处理铜箔13和基板12，还可能通过事先用化学方式等等消除通孔上的铜箔13而用激光形成通孔。 
图2C是示出了通过使用电镀敷等等在通孔4’的侧壁上形成镀敷层14而形成通孔的状态的示意图。这里，在侧壁上的镀敷层14处于与铜箔13导电的状态。 
图2D是示出了在通孔4中填充导电材料15的状态的图。可以在形成镀敷层14后通过镀敷或者通过填充导电糊形成导电材料15。当镀敷层14具有充分的厚度并且仅用镀敷层获得良好电连接时，可以省略填充导电材料的工艺。另外，可以填充填孔材料以替代填充导电材料，从而改善通孔的刚性并且促进金属电极的形成。 
图2E是示出了用于连接到布线层的内部电极5a和外部电极5b的状态的示意图，通过将铜箔13处理成任意形状形成半导体器件的连接部分。可以通过使用化学的蚀刻处理等等进行铜箔的处理。 
另外，在有机基板1中形成通孔4后，为了保护布线还可以在基板的两面或者一面上形成诸如阻焊剂的布线保护膜。当提供布线保护膜时，向通孔4和布线部分提供用于连接到外部电极的开口。 
图3F是示出了在电性能测试中被检测为无缺陷的半导体元件2被通过粘接剂3固定在由前述工艺获得的有机基板上的示意图，元件2的元件电路表面面向上。向半导体元件2的表面施加光敏树脂膜16，并且归因于在光敏树脂膜16中形成的开口17，暴露半导体元件2的电极（用于外部连接的金属电极端子）。存在以下情况，在没有施加光敏树脂膜的状态下，半导体元件2被固定到基板上。这里，因为基板显著大于半导体尺寸，所以可以安装大量的半导体元件。 
图3G是示出了向固定在基板上的半导体元件2的周边供给绝缘树脂 并且由此形成绝缘树脂层6的状态的示意图。热固树脂用作绝缘树脂，并且施加这样的绝缘树脂以尽可能避免与半导体元件2乃至光敏树脂膜16之间的任意不平坦。可以通过使用旋涂机的施加方法或者使用刮刷的印刷方法施加绝缘树脂。 
光敏树脂还可以用作绝缘树脂。另外，在没有预先向半导体元件2的电路形成面供给光敏树脂膜16的情况下，还可能向半导体元件2的周边和电路形成面供给光敏树脂作为绝缘树脂。 
这里，半导体元件2的电路形成面的电极部通过在曝光和显影的分离工艺中打开的开口而暴露电极表面。 
这里还可以同时形成用于树脂部的金属过孔的开口（参考图3H的18）。 
图3H是示出了在绝缘材料层6中形成用于形成金属过孔的开口18的状态的示意图。用激光等等处理开口18并且开口18贯穿到有机基板的内部电极5a。开口18有时用微孔钻处理并形成，并且当绝缘材料层6由光敏树脂构成时有时通过曝光和显影来打开。 
图3I是示出了在其中形成开口18的绝缘材料层6上以及半导体元件2的表面上形成金属薄膜布线层7的状态的示意图。通过气相沉积方法（溅射）、无电镀敷等等在绝缘材料层6的整个上表面上形成底层（种子层）并且之后进行电解镀敷。这里，如附图所示，还通过镀敷在绝缘材料层6的开口18的侧壁上形成导电金属层，并且由此形成金属过孔19。随后，通过光刻构图在整个表面上形成的导电金属层，并形成金属薄膜布线层7。通过在导电金属层上形成光致抗蚀剂层，使用预定图形的掩模进行曝光和显影以及之后蚀刻导电金属层的预定部分进行通过光刻的构图。通过此类通过光刻的构图和电解镀敷，可以共同形成电连接到半导体元件2的电极的金属过孔19、布线层7以及金属薄膜布线层7的其中在随后的工艺中要形成由焊料球等等构成的外部电极9的预定部分。另外，在形成金属薄膜布线层7后，通过蚀刻除去前述底层（种子层）。 
图4J是示出了在金属薄膜布线层7上形成诸如阻焊剂的布线保护膜 11的示意图。 
当阻焊剂是液体形式时，用辊涂机提供阻焊剂，并且当阻焊剂具有薄膜形状时用层合（lamination）或者压着（bonding press）提供。在形成布线保护膜11后，形成用于向布线保护膜提供外部金属电极的开口。 
图4K是示出了在金属薄膜布线层7的外部金属电极端子部分上形成的由导电材料制成的外部金属电极9的状态的示意图。作为导电材料，使用诸如焊料球、导电糊，焊料糊等等的导电材料。 
在形成外部电极9后，通过将如上述获得的产品沿切割线A-A分隔为独立的片，可以获得本发明的实施例1的半导体器件。 
实施例2 
图5是示出了本发明的实施例2的截面图。 
实施例2具有这样的结构，其中，在实施例1中，仅在通孔的壁表面上形成金属导体，并且诸如树脂的填孔材料21填充在剩余中空部分。 
作为填充填孔材料21的结果，可以提高通孔的刚性，并且有助于在通孔的上或者下面上的金属电极（导电膜）的形成。 
实施例3 
图6是示出了本发明的实施例3的截面图。 
实施例3在布线层的下侧和上侧上使用不同类型的树脂作为围绕实施例1中的半导体元件的绝缘材料层6。例如，热固树脂或者光敏树脂被用作树脂6a，并且能够在外部电极之间绝缘的诸如阻焊剂的绝缘树脂材料被用作树脂6b。由树脂6b制造的层构成布线保护层11。 
作为采用前述配置的结果，分别期望通过使用热固树脂作为树脂6a增强半导体元件的密封可靠性的效果，通过使用光敏树脂作为树脂6a增强构图特性的效果以及通过使用阻焊剂作为树脂6b增强外部电极之间的短路抑制效应。 
另外，在示出的实例中，用如在实施例2中的填孔材料填充有机基板的通孔。 
实施例4 
图7是示出了本发明的实施例4的截面图。 
实施例4通过以下方式改善通过半导体元件2产生的热的散热特性，通过在有机基板1的面向在实施例3中的半导体元件2的表面部分上保留铜箔以形成铜电极衬垫23，在铜电极衬垫23之下的有机基板1中设置没有与在绝缘材料层6中的金属薄膜布线层7电连接的虚设通孔22并且使通孔成为热过孔。 
作为在层叠模块中使用具有前述结构的半导体器件的结果，热在垂直方向上有效地流动而有助于散热。 
实施例5 
图8是示出了本发明的实施例5的截面图。 
实施例5将实施例3中的有机基板的下面连接到布线24。作为采用前述结构的结果，使得能够进行从在有机基板中的过孔向不同的衬垫位置的重布线。另外，作为增加构图区域的结果，基于面内温度分布的均匀性可以改善散热性能。 
实施例6 
图9是示出了本发明的实施例6的截面图。 
实施例6是实施例4的修改实例，留下在有机基板1面向半导体元件2的表面部分上的铜箔区域作为大区域并且用作接地层。 
此配置使得改善了散热特性并且基于接地层的加强而改善了电特性。 
图10是示出了本发明的实施例7的截面图。 
实施例7是这样的配置，其中作为围绕实施例5中的半导体元件的绝缘材料层6，使用热固树脂层6c作为最下层，光敏树脂层6d用作在其上的层并且阻焊剂层6e用作最上层。作为采用前述结构的结果，分别期望通过热固树脂6c增强半导体元件的封装可靠性的效果，通过使用光敏树脂层6d增强构图特性的效果以及通过使用阻焊剂层6e改善外部电极之间的短路抑制效果。 
实施例8 
图11是示出了本发明的实施例8的截面图。 
实施例8提供在多个层中金属薄膜布线层7和其要连接的金属过孔10（两层的每一个都在示出的实例中）。 
提供多个金属薄膜布线层7和其要连接的金属过孔10增加了布线与半导体元件和外部金属电极或者金属过孔的电连接的自由度，并且因此当与相同外部尺寸的半导体器件比较时，增加了可安装的半导体元件尺寸的自由度，或者增加半导体元件表面的可装配的电极端子的数目的自由度。 
实施例9 
图12是示出了本发明的实施例9的截面图。 
实施例9是半导体层叠模块26，通过连接在半导体器件的金属薄膜布线层上形成的外部电极和另一个半导体器件的有机基板上暴露的外部电极，在垂直于半导体器件的主表面的方向上层叠半导体器件的单元（U1到U4）获得。 
作为使用本发明的半导体器件作为层叠模块单元的结果，可以实现任意数目的叠层的层叠模块而不必像在TSV结构中一样向半导体元件提供穿通电极，并且即使独立的半导体元件的尺寸不同是也能实现。 
实施例10 
图13是示出了本发明的实施例10的截面图。 
实施例10是半导体层叠模块28，通过在图12中示出的实施例9的半导体层叠模块26的最上层上设置具有图14中示出的结构的半导体器件U5获得。 
关于图14中示出的半导体器件U5，高导热金属板27被用作平板31，并且由此可以实现具有更高散热性能的层叠模块，其中高功率消耗半导体元件可以安装在最上层上。 

Claims (9)

1.一种半导体器件，包括：
有机基板；
通孔，在基板的厚度方向上贯穿所述有机基板；
外部电极和内部电极，被提供到所述有机基板的前面和后面并且电连接到所述通孔；
半导体元件，通过接合层安装在所述有机基板的一个主表面上，所述半导体元件的元件电路表面面向上；
绝缘材料层，用于密封所述半导体元件及其周边；
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露；
金属过孔，被提供在所述绝缘材料层中并且电连接到所述金属薄膜布线层；以及，
在所述金属薄膜布线层上形成的外部电极，
其中所述金属薄膜布线层被构造为电连接设置在所述半导体元件的所述元件电路表面上的电极、所述内部电极、所述金属过孔以及在所述金属薄膜布线层上形成的所述外部电极。
2.根据权利要求1的半导体器件，其中由分别地不同绝缘材料构成的多种绝缘材料层形成所述绝缘材料层。
3.根据权利要求1或2的半导体器件，其中以多个层的形式提供所述金属薄膜布线层和与其连接的所述金属过孔。
4.根据权利要求1到3中的任一项的半导体器件，其中未电连接到所述绝缘材料层中的所述金属薄膜布线层的通孔被设置在所述有机基板的面向所述半导体元件的区域中。
5.根据权利要求1到4中的任一项的半导体器件，其中在所述有机基板上提供多个半导体元件。
6.一种模块结构，其中多个根据权利要求1到5中的任一项的所述半导体器件通过连接在所述半导体器件中的一个上的所述金属薄膜布线层上形成的所述外部电极和在其它半导体器件的所述有机基板上暴露的所述外部电极而在垂直于所述半导体器件的主平面的方向上被层叠。
7.根据权利要求6的模块结构，
其中所述半导体器件是根据权利要求4的所述半导体器件。
8.一种制造半导体器件的方法，所述方法包括如下步骤：
在有机基板中形成通孔，所述通孔在厚度方向上贯穿所述有机基板；
形成外部电极和内部电极，所述外部电极和内部电极被提供到所述有机基板的前面和后面并且电连接到所述通孔；
在所述有机基板的一个主表面上定位并设置多个半导体元件，所述半导体元件的元件电路表面面向上，并且然后将这些半导体元件的与所述元件电路表面相对的面固定到所述有机基板上；
在所述半导体元件及其周边上形成绝缘材料层；
在所述绝缘材料层中形成开口；
在所述绝缘材料层上形成金属薄膜布线层，所述金属薄膜布线层的一部分延伸到所述半导体元件的周边区域，并且在所述绝缘材料层中的所述开口中形成作为导电部的金属过孔，所述金属过孔被连接到在所述半导体元件的所述元件电路表面上设置的电极；
在所述金属薄膜布线层上形成外部电极；以及
通过在预定位置处切割所述有机基板和所述绝缘材料层，分离包括一个或多个半导体芯片的所述半导体器件。
9.一种制造半导体层叠模块的方法，其中根据权利要求1到5中的任一项的多个半导体器件通过以在所述半导体器件中的一个的所述金属薄膜布线层上形成的所述外部电极被连接到在另一半导体器件的所述有机基板上暴露的所述外部电极的方式而在垂直于所述半导体器件的主平面的方向上被层叠。
CN2012102653304A 2011-07-28 2012-07-27 半导体器件、通过垂直层叠半导体器件配置的半导体模块结构及其制造方法 Pending CN102903682A (zh)

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Publication number Priority date Publication date Assignee Title
CN104465642A (zh) * 2014-12-10 2015-03-25 华进半导体封装先导技术研发中心有限公司 基于有机基板的多层芯片的扇出型封装结构及封装方法
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CN106165086A (zh) * 2014-03-31 2016-11-23 信越化学工业株式会社 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
CN106249542A (zh) * 2015-06-08 2016-12-21 信越化学工业株式会社 半导体装置、积层型半导体装置、密封后积层型半导体装置、以及这些装置的制造方法
CN106415823A (zh) * 2014-03-31 2017-02-15 信越化学工业株式会社 半导体装置、积层型半导体装置、密封后积层型半导体装置以及这些装置的制造方法
CN109378308A (zh) * 2014-12-10 2019-02-22 上海兆芯集成电路有限公司 线路基板和封装结构
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014002923A1 (ja) * 2012-06-26 2014-01-03 株式会社村田製作所 実装基板および発光装置
JP2014082245A (ja) 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
JP6377894B2 (ja) * 2013-09-03 2018-08-22 信越化学工業株式会社 半導体装置の製造方法、積層型半導体装置の製造方法、及び封止後積層型半導体装置の製造方法
EP3057993B1 (en) 2013-10-17 2020-08-12 Omeros Corporation Methods for treating conditions associated with masp-2 dependent complement activation
TWI544555B (zh) * 2014-02-11 2016-08-01 東琳精密股份有限公司 半導體封裝結構及其製造方法
JP6415365B2 (ja) * 2014-03-28 2018-10-31 株式会社ジェイデバイス 半導体パッケージ
TWI555105B (zh) * 2014-03-31 2016-10-21 英凡薩斯公司 具延伸通過密封連接器所耦接之堆疊端子的微電子組件的製造
US9214454B2 (en) * 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
JP2016139752A (ja) * 2015-01-29 2016-08-04 日立化成株式会社 半導体装置の製造方法
JP6620989B2 (ja) * 2015-05-25 2019-12-18 パナソニックＩｐマネジメント株式会社 電子部品パッケージ
US9613942B2 (en) * 2015-06-08 2017-04-04 Qualcomm Incorporated Interposer for a package-on-package structure
JP6291094B2 (ja) * 2017-01-24 2018-03-14 信越化学工業株式会社 積層型半導体装置、及び封止後積層型半導体装置
WO2018193531A1 (ja) 2017-04-19 2018-10-25 オリンパス株式会社 内視鏡、撮像モジュール、および撮像モジュールの製造方法
WO2018198189A1 (ja) 2017-04-25 2018-11-01 オリンパス株式会社 内視鏡、および、撮像モジュール
WO2018216092A1 (ja) 2017-05-23 2018-11-29 オリンパス株式会社 撮像モジュールおよび内視鏡
WO2019138440A1 (ja) 2018-01-09 2019-07-18 オリンパス株式会社 撮像装置、内視鏡、および、撮像装置の製造方法
WO2019138442A1 (ja) 2018-01-09 2019-07-18 オリンパス株式会社 撮像装置、内視鏡、および、撮像装置の製造方法
KR102542573B1 (ko) 2018-09-13 2023-06-13 삼성전자주식회사 재배선 기판, 이의 제조 방법, 및 이를 포함하는 반도체 패키지
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
DE102019202718B4 (de) * 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
JP7371882B2 (ja) * 2019-04-12 2023-10-31 株式会社ライジングテクノロジーズ 電子回路装置および電子回路装置の製造方法
WO2020250795A1 (ja) 2019-06-10 2020-12-17 株式会社ライジングテクノロジーズ 電子回路装置
WO2021152658A1 (ja) 2020-01-27 2021-08-05 オリンパス株式会社 撮像装置、および、内視鏡
US11211310B1 (en) * 2020-09-03 2021-12-28 Delta Electronics, Inc. Package structures
CN112234026A (zh) * 2020-10-14 2021-01-15 天津津航计算技术研究所 一种3d芯片封装
JP2023071301A (ja) * 2021-11-11 2023-05-23 新光電気工業株式会社 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP2003197662A (ja) 2001-12-25 2003-07-11 Sony Corp 電子部品、電子部品の製造方法および装置
US7208825B2 (en) * 2003-01-22 2007-04-24 Siliconware Precision Industries Co., Ltd. Stacked semiconductor packages
JP4303563B2 (ja) * 2003-11-12 2009-07-29 大日本印刷株式会社 電子装置および電子装置の製造方法
JP2006041438A (ja) * 2004-07-30 2006-02-09 Shinko Electric Ind Co Ltd 半導体チップ内蔵基板及びその製造方法
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
JP2008210912A (ja) * 2007-02-26 2008-09-11 Cmk Corp 半導体装置及びその製造方法
JP5135828B2 (ja) 2007-02-28 2013-02-06 ソニー株式会社 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法
US20080258293A1 (en) * 2007-04-17 2008-10-23 Advanced Chip Engineering Technology Inc. Semiconductor device package to improve functions of heat sink and ground shield
JP5496445B2 (ja) * 2007-06-08 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008288607A (ja) * 2008-07-04 2008-11-27 Shinko Electric Ind Co Ltd 電子部品実装構造の製造方法
JP2010219489A (ja) 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法
JPWO2010101163A1 (ja) * 2009-03-04 2012-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
JP2010238994A (ja) * 2009-03-31 2010-10-21 Sanyo Electric Co Ltd 半導体モジュールおよびその製造方法
JP2010278334A (ja) 2009-05-29 2010-12-09 Elpida Memory Inc 半導体装置
US8643164B2 (en) * 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10141272B2 (en) 2014-03-31 2018-11-27 Shin-Etsu Chemical Co., Ltd. Semiconductor apparatus, stacked semiconductor apparatus and encapsulated stacked-semiconductor apparatus each having photo-curable resin layer
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US10319653B2 (en) 2014-03-31 2019-06-11 Shin-Etsu Chemical Co., Ltd. Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same
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