WO2021142599A1 - 一种芯片封装结构及封装方法 - Google Patents

一种芯片封装结构及封装方法 Download PDF

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Publication number
WO2021142599A1
WO2021142599A1 PCT/CN2020/071890 CN2020071890W WO2021142599A1 WO 2021142599 A1 WO2021142599 A1 WO 2021142599A1 CN 2020071890 W CN2020071890 W CN 2020071890W WO 2021142599 A1 WO2021142599 A1 WO 2021142599A1
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Prior art keywords
substrate
chip
protective layer
hole
connecting portion
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PCT/CN2020/071890
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English (en)
French (fr)
Inventor
张鼎
王腾飞
许美蓉
李文浩
Original Assignee
深圳市大疆创新科技有限公司
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Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to CN202080004145.2A priority Critical patent/CN112640098A/zh
Priority to PCT/CN2020/071890 priority patent/WO2021142599A1/zh
Publication of WO2021142599A1 publication Critical patent/WO2021142599A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

Definitions

  • This application relates to the field of packaging technology, and in particular to a chip packaging structure and packaging method.
  • the electronic equipment at the end of the load of the pan/tilt and the core motherboard of the fuselage need to be connected through multiple soft signal wires.
  • the soft signal line has better characteristic impedance continuity and less high-frequency component loss. It is a better connection method on the gimbal side under the condition of insensitive cost.
  • the existing pan/tilt products connected by soft signal lines still have certain defects when they are used. For example, when the signal line propagates signals, sometimes it will cause a certain degree of signal amplitude, upper and lower edges and other key indicators. As a result, the SI (Signal Integrity) performance of the signal is poor, resulting in poor signal quality received by the electronic device at the end of the pan/tilt load.
  • SI Signal Integrity
  • this application is proposed in order to provide a chip packaging structure and packaging method that solves the above-mentioned problems.
  • a chip packaging structure including:
  • a substrate the substrate has a first connection portion and a second connection portion, the first connection portion and the second connection portion are electrically connected through the internal circuit of the substrate; wherein, the second connection portion is a through In the through hole of the substrate, an electroplating layer with connection holes is arranged in the through hole;
  • a chip the chip is disposed on the substrate and is electrically connected to the first connection portion, so that a signal path is formed between the second connection portion and the chip through the internal circuit of the substrate;
  • a protective layer, the protective layer is disposed on the substrate, and the chip and the second connecting portion are wrapped in the protective layer, and a position on the protective layer corresponding to the second connecting portion has A wire-passing hole, so that the signal line passes through the wire-passing hole to be electrically connected to the second connecting portion.
  • the first connection part is a welding part
  • a columnar solder ball is provided on the chip, and the chip is soldered to the first connecting portion through the columnar solder ball.
  • first connecting portions which are located in the middle of the substrate, and each of the first connecting portions is connected to one of the second connecting portions respectively.
  • second connecting portions which are symmetrically distributed on both sides of the symmetry axis in the width direction of the substrate;
  • first connecting portions which are symmetrically distributed on both sides of the symmetry axis in the width direction of the substrate;
  • the second connecting portions located on the same side of the symmetry axis are connected to the first connecting portions in a one-to-one correspondence.
  • a pad is further provided on the side of the substrate facing away from the chip;
  • the pad is electrically connected to the second connection part.
  • the substrate is a two-layer structure substrate.
  • the protective layer is made of epoxy resin material
  • the protective layer is injected onto the substrate through an injection molding process.
  • a chip packaging method including:
  • the chip is arranged on the substrate so that the chip is electrically connected to the first connection part on the substrate; wherein the substrate has a first connection part and a second connection part, and the first connection part is connected to the first connection part on the substrate.
  • the second connecting portion is electrically connected through the internal circuit of the substrate; wherein the second connecting portion is a through hole penetrating the substrate, and an electroplating layer with a connecting hole is provided in the through hole;
  • a via hole is provided on the protective layer at a position corresponding to the second connecting portion, so that the signal line passes through the via hole and is electrically connected to the second connecting portion.
  • the first connection part is a welding part
  • a columnar solder ball is arranged on the chip
  • the arranging the chip on the substrate includes:
  • the arranging the chip on the substrate further includes: making the substrate, including:
  • a double-layer structure substrate as the main body of the substrate, wherein the main body has internal circuits;
  • a connection hole is provided on the electroplating layer.
  • disposing an electroplating layer on the inner wall of the through hole further includes:
  • a pad is provided on the side of the substrate facing away from the chip, and the pad is electrically connected to the second connecting portion.
  • using a double-layer structure substrate as the main body of the substrate further includes: providing a positioning mark for positioning the position of the second connecting portion on the side of the substrate facing the protective layer.
  • the disposing a protective layer on the substrate includes:
  • a filler is provided at a position corresponding to the positioning mark
  • the filler and the injection mold are removed to form the protective layer with the via hole.
  • the disposing a protective layer on the substrate includes:
  • the via hole is formed on the protective layer through a laser drilling process or a mechanical drilling process.
  • the method further includes:
  • the position of the wire via is accurate.
  • forming the protective layer by injection molding by the injection mold includes: forming the protective layer by an epoxy resin material.
  • the technical solution provided by the embodiments of the present application can reduce the parasitic capacitance on the signal path, effectively improve the signal quality of the receiving end, improve the reliability of the signal line connection, and reduce the volume and cost.
  • FIG. 1 is a schematic diagram of the state when a signal is transmitted through a signal line in the prior art
  • FIG. 2 is a schematic diagram of the state of signal transmission when a relay board is set between the signal sending side and the signal receiving side in the prior art
  • FIG. 3 is a schematic structural diagram of a cross-section of the chip packaging structure in this application.
  • FIG. 4 is a schematic structural diagram of the top of the chip packaging structure in this application, in which the chip is in a perspective state;
  • Fig. 5 is a schematic diagram of the structure of the injection mold and the filling part in the application.
  • FIG. 6 is a schematic structural diagram of the bottom of the chip packaging structure in this application.
  • FIG. 7 is a schematic diagram of the comparison of the signal SI performance when the chip packaging structure in this application is used and the signal SI performance when the chip packaging structure in this application is not used;
  • FIG. 8 is a schematic flow chart of the packaging method in this application.
  • first and second are only used to facilitate the description of different components, and cannot be understood as indicating or implying the order relationship, relative importance, or implicitly indicating what is indicated.
  • pan-tilt products connected by soft signal lines have certain defects when they are used. For example, when the signal lines are propagating signals, they sometimes interfere with the signals. Amplitude, upper and lower edges and other key indicators will cause a certain degree of impact, making the SI (signal integrity) performance of the signal poor, resulting in poor signal quality received by the electronic device at the end of the pan/tilt load.
  • the inventor believes that the above-mentioned defects are caused by the following reasons.
  • One reason is that, referring to Figure 1, due to the mechanical structure of the pan/tilt, especially when the size of the pan/tilt is large, the signal line needs to be wound. Pass the pan/tilt arm, so the length of the signal line is usually longer, for example, the length of the signal line is generally longer than 20cm.
  • the relay board needs to have two signal line connectors, driver chips, PCB boards and other components to increase the relay capacity.
  • the relay board is not only additional.
  • additional consideration should be given to the signal interference caused by the introduction of this relay board and the issues affecting the overall design of the PTZ.
  • the components on the relay board will bring new parasitic capacitance, which will affect the SI performance of the signal.
  • the relay board is used as a carrier to connect the signal line and the driver, and its volume is relatively small. Large, high cost, affects the overall design of the PTZ.
  • the present application provides a chip packaging structure and packaging method, which can omit the relay board, so as to obtain better SI performance, reduce the use cost, and be more beneficial to the overall pan/tilt. Structural design.
  • FIG. 3 is a schematic structural diagram of a cross-section of the chip packaging structure in this application.
  • FIG. 4 is a schematic structural diagram of the top of the chip packaging structure in this application, in which the chip 20 is in a perspective state. As shown in Figure 3 and Figure 4.
  • a chip packaging structure which includes a substrate 10, a chip 20, and a protective layer 30.
  • the substrate 10 has a first connection portion and a second connection portion 11, and the first connection portion and the second connection portion 11 are electrically connected through the internal circuit 13 of the substrate 10.
  • the second connecting portion 11 is a through hole penetrating the substrate 10, and an electroplated layer with a connecting hole is provided in the through hole.
  • the chip 20 is disposed on the substrate 10 and is electrically connected to the first connection portion, so that a signal path is formed between the second connection portion 11 and the chip 20 through the internal circuit 13 of the substrate 10.
  • the protective layer 30 is disposed on the substrate 10, and wraps the chip 20 and the second connecting portion 11 in the protective layer 30.
  • the protective layer 30 has a via 31 at a position corresponding to the second connecting portion 11 for the signal line 40 to pass through.
  • the via hole 31 is electrically connected to the second connecting portion 11.
  • the chip 20 can be connected to the signal line 40 through the internal circuit 13 of the substrate 10, and the relay board and the electronic devices provided on the relay board can be omitted, which can effectively reduce the cost and greatly improve the cost advantage.
  • the quality of signal propagation can still reach the performance index, or even better.
  • the chip packaging structure becomes smaller. When applied to the pan/tilt, it is more conducive to the overall mechanical structure design of the pan/tilt.
  • the first connecting portion is used to connect to the chip 20, it is inconvenient to show in the figure, so it is not shown in Figs. 3 and 4, and the wiring mode of the internal circuit 13 shown in Figs. 3 and 4 is only It is an exemplary structure, and it does not mean that the wiring method of the internal circuit 13 of the substrate 10 in the present application is only shown in the figure, and the wiring method of the internal circuit 13 can be adjusted according to actual needs, and will not be repeated here.
  • the substrate 10 is a substrate 10 with a double-layer structure.
  • the substrate 10 includes, but is not limited to, an RT (radio frequency) board with a double-layer structure.
  • the substrate 10 can also be made of other material plates that can achieve precise circuit etching.
  • the use of the double-layer structure of the substrate 10 can achieve strict inter-layer alignment, so that the layout of the internal circuit 13 is more accurate, and the realization is relatively simple.
  • the double-layer structure of the substrate 10 has a thinner structure, which can meet a better solder penetration rate, and bring higher reliability for subsequent connection of the chip 20 and the signal line 40.
  • the connection manner between the first connection portion and the substrate 10 includes, but is not limited to, welding.
  • the first connecting part is a welding part.
  • the chip 20 is provided with a columnar solder ball 21, and the chip 20 is soldered to the first connecting portion through the columnar solder ball 21.
  • the soldering part on the substrate 10 may be a soldering spot reserved during the etching process of the substrate 10.
  • the chip 20 includes, but is not limited to, a driver chip 20, and the columnar solder balls 21 on the chip 20 may be contact points grown through a chemical process during the production of the chip 20.
  • the second connecting portion 11 on the substrate 10 is a through hole penetrating the substrate 10, and the substrate 10 can be punched through by a laser drilling process or a mechanical drilling process. At this time, the through hole is only connected to the internal circuit 13 at the edge. The signal transmission effect is poor after being connected to the signal line 40. In order to improve the connection effect between the through hole and the internal circuit 13, after the drilling is completed, metal is plated on the inner wall of the through hole as a plating layer, and the entire through hole has electrical conductivity through the plating layer.
  • a hole is drilled inside the electroplated layer, so that the signal line 40 can complete the coaxial wire welding.
  • the through hole can be used to guide the signal line 40 to be inserted from the surface of the substrate 10 into the hole of the plating layer of the substrate 10.
  • the through hole with the plating layer is used as the main space for solder fixing and signal transmission after the signal line 40 is inserted.
  • the aperture of the through hole can be approximately 10 mils, that is, the aperture of the through hole can be 10 mils, or slightly larger than 10 mils, or slightly smaller than 10 mils.
  • the aperture of the through hole is about 10 mils, which facilitates the insertion of the signal line 40 and repeated solder penetration.
  • the thickness of the electroplating layer is about 1 mil to ensure good electrical conductivity.
  • the substrate 10 can be used as a hardware supporting bottom plate of the entire chip packaging structure, and the signal connection between the chip 20 and the corresponding through hole is completed through the internal circuit 13 of the substrate 10.
  • the position of the second connection portion 11 of the substrate 10 can be pre-marked according to different design requirements, and then the substrate 10 is punched through the substrate 10 through a laser drilling process or a mechanical drilling process according to the marked position to form a through hole.
  • One way of marking is to provide a positioning mark for positioning the position of the second connecting portion 11 on the side of the substrate 10 facing the protective layer 30 during the etching process of the substrate 10.
  • the positioning marks include, but are not limited to, reserved metal optical template marks.
  • the metal optical template marks not only serve as markings until the second connecting portion 11 is provided, but also, when the via hole 31 is subsequently provided on the protective layer 30, It also provides an accurate reference position for the positioning of the wire via 31.
  • the metal optical template mark is the positioning of the via hole 31, which is described in the following content, and will not be described in detail here.
  • the number of second connecting portions 11 can be set to different according to different chip 20 specifications and different signal transmission requirements.
  • the number of second connecting portions 11 can be set to at least two, and the number of first connecting portions is greater than the number of second connecting portions.
  • the number of 11 corresponds, therefore, there are at least two first connecting parts.
  • One way of positioning the second connecting portion 11 and the first connecting portion is that at least two second connecting portions 11 are respectively located at opposite ends of the substrate 10, the first connecting portion is located in the middle of the substrate 10, and each first connecting portion is The parts are respectively connected to a second connecting part 11 respectively.
  • the number of the columnar solder balls 21 on the chip 20 corresponds to the number of the first connection parts.
  • FIG. 3 and FIG. 4 there are four second connecting portions 11, which are symmetrically distributed on both sides of the symmetry axis in the width direction of the substrate 10.
  • the dotted line A-A shown in FIG. 4 is the axis of symmetry in the width direction of the substrate 10.
  • the second connecting portions 11 located on the same side of the symmetry axis are connected to the first connecting portions in a one-to-one correspondence.
  • This arrangement makes the distance between the second connecting portion 11 and the chip 20 on both sides of the width symmetry axis approximately equal, thereby ensuring equal signal transmission distances, reducing parasitic capacitance, and ensuring signal quality. Further, on the basis that the second connecting portions 11 are symmetrically distributed on both sides of the axis of symmetry in the width direction of the substrate 10, the second connecting portions 11 are symmetrically distributed on both sides of the axis of symmetry in the length direction of the substrate 10, as shown in FIG.
  • the BB dotted line shown is the longitudinal axis of symmetry of the substrate 10, and the longitudinal axis of symmetry is perpendicular to the width direction of symmetry, so as to further ensure that the distance between the second connecting portion 11 and the chip 20 on both sides of the width symmetry axis is approximately equal.
  • a protective layer 30 is provided on the substrate 10, and the protective layer 30 can be used to fix and protect the entire chip packaging structure.
  • the embodiment of the present application includes but is not limited to the protective layer 30 being made of epoxy material.
  • the protective layer 30 can be injection molded onto the substrate 10 through an injection molding process.
  • the wire via 31 on the protective layer 30 can be completed by the following setting methods:
  • the protective layer 30 is made by the injection mold 50 and the filler 51 in cooperation with the injection molding process, and the specific way is as follows:
  • the substrate 10 with the chip 20 is placed in an injection mold 50.
  • the substrate 10 has been fabricated.
  • four second connecting portions 11 are provided on the substrate 10, and the chip 20 is provided in the middle of the substrate 10.
  • the substrate 10 is provided with a positioning mark for positioning the position of the second connecting portion 11, and the positioning mark can be realized by the metal optical template mark described in the above content.
  • the metal optical template mark is used to provide an accurate reference position for the positioning of the via 31 when the via 31 is provided on the protective layer 30.
  • a filler 51 is set at a position corresponding to the positioning mark.
  • the filler 51 can be made of a material with greater rigidity, for example, the filler 51 can be made of a metal material.
  • the shape of the filler 51 matches the second connecting portion 11.
  • the filler 51 has a cylindrical structure, and the diameter of the cylindrical structure is approximately the same as the diameter of the second connecting portion 11. The diameter of the structure is equal to the diameter of the second connecting portion 11, or may be slightly larger or slightly smaller.
  • the filler 51 and the injection mold 50 are removed to form a protective layer 30 with a wire hole 31.
  • the protective layer 30 is made of epoxy resin. After the epoxy resin is solidified, the injection mold 50 and the filler 51 are removed to obtain the protective layer 30 with the via 31.
  • the protective layer 30 is made by an injection mold 50 in conjunction with the injection molding process.
  • this method does not provide a filler 51.
  • the protective layer 30 is perforated to form via holes 31, so as to obtain the protective layer 30 having the via holes 31.
  • the specific method is as follows:
  • the substrate 10 with the chip 20 is placed in an injection mold 50.
  • the protective layer 30 is formed by injection molding through an injection mold 50.
  • a via 31 is formed on the protective layer 30 by a laser drilling process or a mechanical drilling process.
  • the position of the metal optical template mark on the substrate 10 can be accurately confirmed by X-ray perspective, and then the via hole 31 is formed on the protective layer 30 through a laser perforating process or a mechanical perforating process.
  • the position of the metal optical template mark on the substrate 10 can be accurately confirmed by X-ray perspective, so as to mark the reference zero position for the punching device, and the surface of the protective layer 30 can be printed by silk screen.
  • Laser engraving is used to accurately point out the position of the reference zero point, and at the same time identify and confirm the coordinate position of the via hole 31, and accurately engrave the via hole 31 on the surface of the protective layer 30.
  • the protective layer 30 with the via hole 31 can be obtained in the above two methods. If the obtained position of the via hole 31 corresponds to the position of the second connecting portion 11, this indicates that the chip package structure is qualified. If the position of the via 31 is deviated from the position of the second connection portion 11, it means that the chip package structure is unqualified and cannot be used. Even if it can be used, the connection between the signal line 40 and the second connection portion 11 may be unstable. . Therefore, in the embodiment of the present application, after the protective layer 30 with the via hole 31 is obtained, a detection step is further provided to detect the chip package in which the position of the via hole 31 and the position of the second connection portion 11 have a deviation structure.
  • An achievable detection method is to first obtain the coordinates of the center point of the threaded hole 31 by using the positioning mark as the zero point coordinate position.
  • the chip packaging structure is placed on the machine by a robotic arm, the metal optical template mark is placed at the zero position of the machine, and the substrate 10 is vacuumed and positioned and fixed.
  • the coordinates of the center point of the threaded hole 31 are compared with the preset coordinates to obtain the coordinate error.
  • the pre-programmed opening coordinates ie, preset coordinates
  • the coordinates of the center point of the via hole 31 laser-engraved on the surface of the protective layer 30 are compared with the coordinate error.
  • the error threshold can be preset according to different design requirements, and the embodiment of the present application does not specifically limit it here.
  • the length of the connection section according to the thickness of the chip packaging structure (thickness of the substrate 10 + thickness of the protective layer 30), for example, select the length of 1.5mm, and peel off the length of about 1.5mm.
  • the outer skin 42 exposes the core wire 41.
  • the back surface of the substrate 10 refers to the side of the substrate 10 facing away from the protective layer 30.
  • the signal line 40 is fixed, which can be fixed along the extension direction of the substrate 10, and fast-curing non-conductive glue is applied to the position of the via hole 31 of the protective layer 30 to realize high-speed assembly and ensure the signal line 40 and the protective layer 30 Reliable fixation between.
  • a heat-proof sticker is wrapped around the entire signal line 40 outside the chip packaging structure to avoid damage to the signal line 40 caused by external heat sources.
  • wave soldering is performed under the through holes to make the solder fully penetrate the through holes of the substrate 10, so that the core wires 41 in the through holes of the substrate 10 are completely connected to the electroplating layer.
  • the signal wire 40 can also be completely connected to the core wire 41 and the electroplating layer by brushing solder paste + heating with an air gun.
  • a pad 13 is further provided on the side of the substrate 10 facing away from the chip 20.
  • the pad 13 is electrically connected to the second connection portion 11.
  • the pad 13 may be reserved when the substrate 10 is made, and the pad 13 may be a copper pad.
  • the chip package structure can be directly welded to other circuit boards through the pad 13, and the reserved copper pad is used as the contact surface for the chip 20 to be directly welded and fixed on the circuit board, forming an LGA package form (LGA is the Land Grid Array, Grid array package).
  • Line A solid line
  • Figure 2 for the connection mode
  • Line B dotted line
  • FIG. 7 shows the SI performance of signal propagation when the chip packaging structure provided by the embodiment of the present application is used between the signal sending end and the signal receiving end.
  • the signal propagation path is simplified, and after only one through hole, the signal can be directly transmitted into the chip 20 through the cylindrical solder ball 21, and the SI performance is better.
  • the comparison performance of the transmission coefficient S21 at 1 GHz shows that the SI performance of the solution of the embodiment of the present application is 69.3 mdB better than the solution of the embodiment of the present application. The signal transmission quality is guaranteed.
  • the relay board is removed, that is, various electronic devices on the relay board are omitted, so the production cost can be reduced, and a significant cost reduction advantage is achieved.
  • the relay board is omitted, which makes the chip packaging structure smaller and saves the space occupied by the intermediate board, which is more conducive to the mechanical structure design of the pan/tilt arm.
  • the connection method of the signal line 40 and the chip package structure is through-hole filling plug-in welding and fixing.
  • the connection method of the signal line 40 is integrated into the chip package structure, and the product characteristic index is improved from various dimensions. Compared with the traditional technology of connector connection, it has better firmness and reliability.
  • the signal line 40 is directly soldered to the side of the substrate 10 in the embodiment of the present application, the parasitic capacitance caused by the connector is avoided, a better SI effect can be achieved, and the signal quality of the receiving end can be effectively improved.
  • the application range of the chip packaging structure is expanded according to the set pad 13 and the practicability is improved.
  • a method for packaging the chip 20 is also provided.
  • the method in the second embodiment can produce the chip packaging structure described in the first embodiment.
  • the specific plan is as follows:
  • a method for packaging a chip 20 including:
  • Step S101 The chip 20 is arranged on the substrate 10 so that the chip 20 is electrically connected to the first connection portion on the substrate 10; wherein the substrate 10 has a first connection portion and a second connection portion 11, and the first connection portion is connected to the first connection portion 11
  • the two connecting portions 11 are electrically connected by the internal circuit 13 of the substrate 10; wherein, the second connecting portion 11 is a through hole penetrating the substrate 10, and an electroplating layer with connecting holes is provided in the through hole;
  • Step S102 a protective layer 30 is provided on the substrate 10, and the protective layer 30 wraps the chip 20 and the second connection portion 11 in the protective layer 30;
  • Step S103 a wire via 31 is provided on the protective layer 30 at a position corresponding to the second connection portion 11, so that the signal wire 40 passes through the wire via 31 and is electrically connected to the second connection portion 11.
  • the technical solution provided by the embodiments of the present application can realize the connection of the chip 20 to the signal line 40 through the internal circuit 13 of the substrate 10 through the chip packaging structure, and can omit the relay board and the electronic devices provided on the relay board, which can effectively reduce the cost , Greatly enhance the cost advantage.
  • the relay board is omitted, the quality of signal propagation can still reach the performance index, or even better.
  • the chip packaging structure becomes smaller. When applied to the pan/tilt, it is more conducive to the overall mechanical structure design of the pan/tilt. It can avoid the parasitic capacitance caused by the electronic devices on the relay board, and can achieve better SI effects.
  • the connection manner between the first connecting portion and the substrate 10 includes, but is not limited to, welding.
  • the first connecting part is a welding part.
  • the chip 20 is provided with a columnar solder ball 21, and the chip 20 is soldered to the first connecting portion through the columnar solder ball 21.
  • the soldering part on the substrate 10 may be a soldering spot reserved during the etching process of the substrate 10.
  • the chip 20 includes, but is not limited to, a driver chip 20, and the columnar solder balls 21 on the chip 20 may be contact points grown through a chemical process during the production of the chip 20.
  • Arranging the chip 20 on the substrate 10 includes fixing the chip 20 on the substrate 10 and heating the cylindrical solder ball 21 and/or the soldering part to weld the cylindrical solder ball 21 and/or the soldering part.
  • the column-shaped solder ball 21 is connected to the soldering part through a wire bonding process.
  • disposing the chip 20 on the substrate 10 also includes: manufacturing the substrate 10 including: using the double-layer structure substrate 10 as the main body of the substrate 10, wherein the main body has an internal circuit 13.
  • a first connecting portion is provided at the first preset position of the main body.
  • a through hole penetrating the substrate 10 is provided at the second preset position of the main body to serve as the second connecting portion 11.
  • An electroplating layer is provided on the inner wall of the through hole; a connecting hole is provided on the electroplating layer.
  • the substrate 10 is a substrate 10 with a double-layer structure.
  • the substrate 10 includes, but is not limited to, an RT (radio frequency) board with a double-layer structure.
  • the substrate 10 can also be made of other material plates that can achieve precise circuit etching.
  • the use of the double-layer structure of the substrate 10 can achieve strict inter-layer alignment, so that the layout of the internal circuit 13 is more accurate, and the realization is relatively simple.
  • the double-layer structure of the substrate 10 has a thinner structure, which can meet a better solder penetration rate, and bring higher reliability for subsequent connection of the chip 20 and the signal line 40.
  • the second connecting portion 11 on the substrate 10 is a through hole penetrating the substrate 10, and the substrate 10 can be punched through by a laser drilling process or a mechanical drilling process. At this time, the through hole is only connected to the internal circuit 13 at the edge. The signal transmission effect is poor after being connected to the signal line 40. In order to improve the connection effect between the through hole and the internal circuit 13, after the drilling is completed, metal is plated on the inner wall of the through hole as a plating layer, and the entire through hole has electrical conductivity through the plating layer.
  • a hole is drilled inside the electroplated layer, so that the signal line 40 can complete the coaxial wire welding.
  • the through hole can be used to guide the signal line 40 to be inserted from the surface of the substrate 10 into the hole of the plating layer of the substrate 10.
  • the through hole with the plating layer is used as the main space for solder fixing and signal transmission after the signal line 40 is inserted.
  • the aperture of the through hole can be approximately 10 mils, that is, the aperture of the through hole can be 10 mils, or slightly larger than 10 mils, or slightly smaller than 10 mils.
  • the aperture of the through hole is about 10 mils, which can facilitate the insertion of the signal line 40 and repeated solder penetration.
  • the thickness of the electroplating layer is about 1 mil to ensure good electrical conductivity.
  • the substrate 10 can be used as a hardware supporting bottom plate of the entire chip packaging structure, and the signal connection between the chip 20 and the corresponding through hole is completed through the internal circuit 13 of the substrate 10.
  • using the double-layer structure substrate 10 as the main body of the substrate 10 further includes: providing a positioning mark for positioning the position of the second connecting portion 11 on the side of the substrate 10 facing the protective layer 30.
  • the position of the second connecting portion 11 of the substrate 10 can be pre-marked according to different design requirements, and then the substrate 10 is punched through the substrate 10 through a laser drilling process or a mechanical drilling process according to the marked position to form a through hole.
  • One way of marking is to provide a positioning mark for positioning the position of the second connecting portion 11 on the side of the substrate 10 facing the protective layer 30 during the etching process of the substrate 10.
  • the positioning marks include, but are not limited to, reserved metal optical template marks.
  • the metal optical template marks not only serve as markings until the second connecting portion 11 is provided, but also, when the via hole 31 is subsequently provided on the protective layer 30, It also provides an accurate reference position for the positioning of the wire via 31.
  • the number of second connecting portions 11 can be set to different according to different chip 20 specifications and different signal transmission requirements.
  • the number of second connecting portions 11 can be set to at least two, and the number of first connecting portions is greater than the number of second connecting portions.
  • the number of 11 corresponds, therefore, there are at least two first connecting parts.
  • One way of positioning the second connecting portion 11 and the first connecting portion is that at least two second connecting portions 11 are respectively located at opposite ends of the substrate 10, the first connecting portion is located in the middle of the substrate 10, and each first connecting portion is The parts are respectively connected to a second connecting part 11 respectively.
  • the number of the columnar solder balls 21 on the chip 20 corresponds to the number of the first connection parts.
  • FIG. 3 and FIG. 4 there are four second connecting portions 11, which are symmetrically distributed on both sides of the symmetry axis in the width direction of the substrate 10.
  • the dotted line A-A shown in FIG. 4 is the axis of symmetry in the width direction of the substrate 10.
  • the second connecting portions 11 located on the same side of the symmetry axis are connected to the first connecting portions in a one-to-one correspondence.
  • This arrangement makes the distance between the second connecting portion 11 and the chip 20 on both sides of the width symmetry axis approximately equal, thereby ensuring equal signal transmission distances, reducing parasitic capacitance, and ensuring signal quality. Further, on the basis that the second connecting portions 11 are symmetrically distributed on both sides of the axis of symmetry in the width direction of the substrate 10, the second connecting portions 11 are symmetrically distributed on both sides of the axis of symmetry in the length direction of the substrate 10, as shown in FIG.
  • the BB dotted line shown is the longitudinal axis of symmetry of the substrate 10, and the longitudinal axis of symmetry is perpendicular to the width direction of symmetry, so as to further ensure that the distance between the second connecting portion 11 and the chip 20 on both sides of the width symmetry axis is approximately equal.
  • a protective layer 30 is provided on the substrate 10, and the protective layer 30 can be used to fix and protect the entire chip packaging structure.
  • the embodiment of the present application includes but is not limited to the protective layer 30 being made of epoxy material.
  • the protective layer 30 can be injection molded onto the substrate 10 through an injection molding process.
  • the wire via 31 on the protective layer 30 can be completed by the following setting methods:
  • the protective layer 30 is made by the injection mold 50 and the filler 51 in cooperation with the injection molding process, and the specific way is as follows:
  • a protective layer 30 is provided on the substrate 10, including:
  • Step S201 Put the substrate 10 with the chip 20 into the injection mold 50.
  • the substrate 10 has been fabricated.
  • four second connecting portions 11 are provided on the substrate 10, and the chip 20 is provided in the middle of the substrate 10.
  • the substrate 10 is provided with a positioning mark for positioning the position of the second connecting portion 11, and the positioning mark can be realized by the metal optical template mark described in the above content.
  • the metal optical template mark is used to provide an accurate reference position for the positioning of the via 31 when the via 31 is provided on the protective layer 30.
  • Step S202 In the injection mold 50, a filler 51 is set at a position corresponding to the positioning mark. Among them, there are four fillers 51, and the positions of the fillers 51 correspond to the positioning marks. In order to ensure that the filler 51 will not be deformed during the injection molding process, thereby causing the position of the via hole 31 to shift, the filler 51 can be made of a material with greater rigidity, for example, the filler 51 can be made of a metal material.
  • the shape of the filler 51 matches the second connecting portion 11.
  • the filler 51 has a cylindrical structure, and the diameter of the cylindrical structure is approximately the same as the diameter of the second connecting portion 11. The diameter of the structure is equal to the diameter of the second connecting portion 11, or may be slightly larger or slightly smaller.
  • Step S203 After injection by the injection mold 50, the filler 51 and the injection mold 50 are removed to form a protective layer 30 with a wire hole 31.
  • the protective layer 30 is made of epoxy resin. After the epoxy resin is solidified, the injection mold 50 and the filler 51 are removed to obtain the protective layer 30 with the via 31.
  • the protective layer 30 is made by an injection mold 50 in conjunction with the injection molding process.
  • this method does not provide a filler 51.
  • the protective layer 30 is perforated to form via holes 31, so as to obtain the protective layer 30 having the via holes 31.
  • the specific method is as follows:
  • a protective layer 30 is provided on the substrate 10, including:
  • Step S301 Put the substrate 10 with the chip 20 into the injection mold 50;
  • Step S302 forming the protective layer 30 by injection molding through the injection mold 50;
  • Step S303 According to the positioning mark, a via 31 is formed on the protective layer 30 through a laser drilling process or a mechanical drilling process.
  • the position of the metal optical template mark on the substrate 10 can be accurately confirmed by X-ray perspective, and then the via hole 31 is formed on the protective layer 30 through a laser perforating process or a mechanical perforating process.
  • the position of the metal optical template mark on the substrate 10 can be accurately confirmed by X-ray perspective, so as to mark the reference zero position for the punching device, and the surface of the protective layer 30 can be printed by silk screen.
  • Laser engraving is used to accurately point out the position of the reference zero point, and at the same time identify and confirm the coordinate position of the via hole 31, and accurately engrave the via hole 31 on the surface of the protective layer 30.
  • the protective layer 30 with the via hole 31 can be obtained in the above two methods. If the obtained position of the via hole 31 corresponds to the position of the second connecting portion 11, this indicates that the chip package structure is qualified. If the position of the via 31 is deviated from the position of the second connection portion 11, it means that the chip package structure is unqualified and cannot be used. Even if it can be used, the connection between the signal line 40 and the second connection portion 11 may be unstable. . Therefore, in the embodiment of the present application, after the protective layer 30 with the via hole 31 is obtained, a detection step is further provided to detect the chip package in which the position of the via hole 31 and the position of the second connection portion 11 have a deviation structure.
  • An achievable detection method is that after the connecting hole is formed, it also includes:
  • Step S501 Take the positioning mark as the zero coordinate position, and obtain the coordinate of the center point of the threaded hole 31.
  • the chip packaging structure is placed on the machine by a robotic arm, the metal optical template mark is placed at the zero position of the machine, and the substrate 10 is vacuumed and positioned and fixed.
  • Step S501 Compare the coordinates of the center point of the threaded hole 31 with preset coordinates to obtain coordinate errors.
  • the pre-programmed opening coordinates ie, preset coordinates
  • the coordinates of the center point of the via hole 31 laser-engraved on the surface of the protective layer 30 are compared with the coordinates of the center point of the via hole 31 laser-engraved on the surface of the protective layer 30 to obtain the coordinate error.
  • Step S501 If the coordinate error is less than the error threshold, the position of the wire via 31 is accurate. If the coordinate error is greater than or equal to the error threshold, the chip package structure with excessive error is eliminated.
  • the error threshold can be preset according to different design requirements, and the embodiment of the present application does not specifically limit it here.
  • an electroplating layer is provided on the inner wall of the through hole. 13 is electrically connected to the second connecting portion 11.
  • the pad 13 may be reserved when the substrate 10 is made, and the pad 13 may be a copper pad.
  • the chip package structure can be directly welded to other circuit boards through the pad 13, and the reserved copper pad is used as the contact surface for the chip 20 to be directly welded and fixed on the circuit board, forming an LGA package form (LGA is the Land Grid Array, Grid array package).
  • Embodiment 2 and the technical solutions described in Embodiment 1 can be referred to each other for reference, and will not be repeated here.
  • the relay board is removed, that is, various electronic devices on the relay board are omitted, so the production cost can be reduced, and a significant cost reduction advantage is achieved.
  • the relay board is omitted, which makes the chip packaging structure smaller and saves the space occupied by the intermediate board, which is more conducive to the mechanical structure design of the pan/tilt arm.
  • connection method of the signal line and the chip package structure is through-hole filling plug-in welding and fixing, and the connection method of the signal line is integrated into the chip package structure, which improves the product characteristic indicators from all dimensions, compared with traditional technology
  • the connector connection has better firmness and reliability, so it is more suitable for the use of frequently moving PTZ structural parts.
  • the signal line is directly soldered to the side of the substrate, thereby avoiding the parasitic capacitance caused by the connector, which can achieve a better SI effect, and effectively improve the signal quality of the receiving end.
  • the applicable scope of the chip packaging structure is expanded and the practicability is improved.
  • the embodiments of this application are applicable to but not limited to the following technical fields: hardware design, SI (Signal Integrity, signal integrity) performance optimization and other fields.
  • the embodiments of the present application are suitable for, but not limited to, the following application modes: applied to the connection signal line between the system board and the load board.
  • the embodiments of this application are applicable to, but not limited to, the following product forms: product forms with pan/tilt winding and suitable for soft signal cable extension signals; for example, handheld pan/tilt, drone pan/tilt, camera pan/tilt, and various shooting equipment Yuntai etc.

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Abstract

本申请实施例提供一种芯片封装结构及封装方法，其中，芯片封装结构包括：基板，基板上具有第一连接部及第二连接部，第一连接部与第二连接部通过基板的内部线路电连接；其中，第二连接部为贯穿基板的通孔，通孔内设置有带有连接孔的电镀层；芯片，芯片设置于基板之上，并与第一连接部电连接，以便第二连接部与芯片之间通过基板的内部线路形成信号通路；保护层，保护层设置于基板上，并将芯片及第二连接部包裹于保护层内，保护层上与第二连接部对应的位置具有过线孔，以便信号线穿过过线孔与第二连接部电连接。本申请实施例提供的技术方案，可减少信号通路上的寄生电容，有效提高接收端的信号质量，提高信号线连接可靠性，且减小体积，降低成本。

Description

一种芯片封装结构及封装方法 技术领域
本申请涉及封装技术领域，尤其涉及一种芯片封装结构及封装方法。
背景技术
目前，在云台产品形态上，由于云台的机械结构的关系，云台负载末端的电子设备与机身核心主板之间，需要通过多根软信号线连接。软信号线相对FPC(Flexible Printed Circuit，柔性电路板)具有较好的特征阻抗连续性、更少的高频分量损失，是一种在成本不敏感条件下较优的云台侧连接方式。
但是，现有的通过软信号线连接的云台产品在使用时，还具有一定的缺陷，例如，信号线在传播信号时，有时候对信号的幅度、上下沿等关键指标都会造成一定程度的影响，使得信号的SI(信号完整性)性能不佳，导致云台负载末端的电子设备端接收的信号质量不佳。
申请内容
鉴于上述问题，提出了本申请，以便提供一种解决上述问题的一种芯片封装结构及封装方法。
在本申请的一个实施例中，提供了一种芯片封装结构，包括：
基板，所述基板上具有第一连接部及第二连接部，所述第一连接部与所述第二连接部通过所述基板的内部线路电连接；其中，所述第二连接部为贯穿所述基板的通孔，所述通孔内设置有带有连接孔的电镀层；
芯片，所述芯片设置于所述基板之上，并与所述第一连接部电连接，以便所述第二连接部与所述芯片之间通过所述基板的内部线路形成信号通路；
保护层，所述保护层设置于所述基板上，并将所述芯片及所述第二连接部包裹于所述保护层内，所述保护层上与所述第二连接部对应的位置具有过线孔，以便信号线穿过所述过线孔与所述第二连接部电连接。
可选地，所述第一连接部为焊接部；
所述芯片上设置有柱形焊接球，所述芯片通过所述柱形焊接球与所述第一连接部焊接。
可选地，所述第二连接部至少为两个，分别位于所述基板的相对两端；
所述第一连接部至少为两个，位于所述基板的中部，每个所述第一连接部分别对应连接一个所述第二连接部。
可选地，所述第二连接部为四个，对称分布在所述基板的宽度方向的对称轴的两侧；
所述第一连接部为四个，对称分布在所述基板的宽度方向的对称轴的两侧；
位于对称轴同侧的所述第二连接部与所述第一连接部一一对应连接。
可选地，在所述基板背向所述芯片的一侧上还设置有焊盘；
所述焊盘与所述第二连接部电连接。
可选地，所述基板为双层结构基板。
可选地，所述保护层通过环氧树脂材料制成；
所述保护层通过注塑工艺，注塑与所述基板上。
在本申请的一个实施例中，还提供了一种芯片的封装方法，包括：
将芯片设置在基板上，使得所述芯片与所述基板上的第一连接部电连接；其中，所述基板上具有第一连接部及第二连接部，所述第一连接部与所述第二连接部通过所述基板的内部线路电连接；其中，所述第二连接部为贯穿所述基板的通孔，所述通孔内设置有带有连接孔的电镀层；
在所述基板上设置保护层，所述保护层将所述芯片及所述第二连接部包裹于所述保护层内；
在所述保护层上与所述第二连接部对应的位置设置过线孔，以便信号线穿过所述过线孔与所述第二连接部电连接。
可选地，所述第一连接部为焊接部；
所述芯片上设置有柱形焊接球；
所述将芯片设置在基板上，包括：
将所述芯片固定于所述基板上；
加热所述柱形焊接球和/或所述焊接部，以将所述柱形焊接球和/或所述焊接 部熔接；或者通过引线键合工艺，将所述柱形焊接球与所述焊接部连接。
可选地，所述将芯片设置在基板上，之前还包括：制作所述基板，包括：
通过双层结构基板作为所述基板的主体，其中，所述主体具有内部线路；
在所述主体的第一预设位置上设置所述第一连接部；
在所述主体的第二预设位置上设置贯穿所述基板的所述通孔，以作为所述第二连接部；
在所述通孔内壁设置电镀层；
在所述电镀层上设置连接孔。
可选地，在所述通孔内壁设置电镀层，还包括：
在所述基板背向所述芯片的一侧设置焊盘，所述焊盘与所述第二连接部电连接。
可选地，通过双层结构基板作为所述基板的主体，还包括：在所述基板的朝向所述保护层的一侧上设置用于定位所述第二连接部位置的定位标识。
可选地，所述在所述基板上设置保护层，包括：
将带有所述芯片的所述基板放入注塑模具内；
在所述注塑模具内，在与所述定位标识相应的位置上设置填充件；
通过所述注塑模具注塑后，移除所述填充件及所述注塑模具，形成带有所述过线孔的所述保护层。
可选地，所述在所述基板上设置保护层，包括：
将带有所述芯片的所述基板放入注塑模具内；
通过所述注塑模具注塑形成所述保护层；
根据所述定位标识，通过激光打孔工艺或机械打孔工艺在所述保护层上形成所述过线孔。
可选地，形成所述连接孔之后，还包括：
以所述定位标识作为零点坐标位置，获取所述过线孔的中心点的坐标；
对比所述过线孔的中心点的坐标与预设坐标，获取坐标误差；
若所述坐标误差小于误差阈值，则所述过线孔位置准确。
另外，可选地，通过所述注塑模具注塑形成所述保护层，包括：通过环氧树脂材料制成所述保护层。
本申请实施例提供的技术方案，可减少信号通路上的寄生电容，有效提高接收端的信号质量，提高信号线连接可靠性，且减小体积，降低成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中，通过信号线传输信号时的状态示意图；
图2为现有技术中，信号发出侧及信号接收侧之间设置中继板时，信号传输时的状态示意图；
图3为本申请中芯片封装结构的剖面的结构示意图；
图4为本申请中芯片封装结构的顶部的结构示意图，其中，芯片为透视状态；
图5为本申请中注塑模具及填充件的结构示意图；
图6为本申请中芯片封装结构的底部的结构示意图；
图7为使用本申请中的芯片封装结构时的信号SI性能与未使用本申请中的芯片封装结构时的信号SI性能的对比示意图；
图8为本申请中封装方法的流程示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，在本申请的描述中，术语“第一”、“第二”仅用于方便描述不同的部件，而不能理解为指示或暗示顺序关系、相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
在实践本申请实施例时，发明人发现，现有技术中，通过软信号线连接的云台产品在使用时，还具有一定的缺陷，例如，信号线在传播信号时，有时候对信号的幅度、上下沿等关键指标都会造成一定程度的影响，使得信号的SI(信号完整性)性能不佳，导致云台负载末端的电子设备端接收的信号质量不佳。
经过多次实践，发明人认为是如下原因造成的上述缺陷，一种原因是，参见图1，由于云台的机械结构的关系，尤其是当云台尺寸较大的情况下，信号线需要绕过云台臂，因此信号线的长度通常会较长，例如，信号线的长度一般长于20cm。信号线在传播信号时，尤其当信号线长度较长的情况下，信号线带来的损耗、所需要驱动的整段PCB走线和信号线的寄生电容+接收端器件引脚电容，对信号的幅度(被降低)、上下沿(被变缓)等关键指标都造成了一定程度的影响。
另一种原因是，参见图2，为解决上一种原因带来的影响，现有技术中，会在信号发出端及信号接收端之间设置驱动器，驱动器能够通过隔断整个信号通路的寄生电容，使信号源驱动的寄生电容范围被截断至驱动器，而不是整个信号链路，优化、减少对信号源驱动力的要求，在相同驱动力的情况下，使得接收端收到信号的质量更佳。但是，当引入驱动器以优化信号质量的情况下，需要额外设计引入一块中继板来承载驱动器。其中，中继板必须要将一段信号线分为两段信号线，因此中继板上需要有两个信号线接插件、驱动器芯片、PCB板等器件增加中继能力，中继板不仅额外附加的成本较高，同时，在云台结构设计中需要额外考虑此中继板引入带来的对信号的干涉问题及影响云台整体设计的问题。举例来说，引入中继板后，中继板上的器件会带来新的寄生电容，寄生电容大，影响信号的SI性能，且中继板作为连接信 号线及驱动器的载体，其体积较大，成本高，影响云台整体设计。
针对上述现有技术中的存在的问题，本申请提供一种芯片封装结构及封装方法，可省略掉中继板，从而够获得更好的SI性能的同时，降低使用成本，更利于云台整体结构设计。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例1
图3为本申请中芯片封装结构的剖面的结构示意图。图4为本申请中芯片封装结构的顶部的结构示意图，其中，芯片20为透视状态。结合图3及图4中所示。
在本申请的一个实施例中，提供了一种芯片封装结构，包括：基板10、芯片20及保护层30。其中，基板10上具有第一连接部及第二连接部11，第一连接部与第二连接部11通过基板10的内部线路13电连接。其中，第二连接部11为贯穿基板10的通孔，通孔内设置有带有连接孔的电镀层。芯片20设置于基板10之上，并与第一连接部电连接，以便第二连接部11与芯片20之间通过基板10的内部线路13形成信号通路。保护层30设置于基板10上，并将芯片20及第二连接部11包裹于保护层30内，保护层30上与第二连接部11对应的位置具有过线孔31，以便信号线40穿过过线孔31与第二连接部11电连接。
本申请实施例提供的技术方案，与现有技术相比，具有以下有益效果：
1、通过芯片封装结构可实现芯片20通过基板10的内部线路13与信号线40的连接，可省略中继板以及中继板上设置的电子器件，可有效降低成本，大大提升成本优势。
2、虽然省去了中继板，但信号传播的质量依然能够达到性能指标，甚至更好。
3、由于省去了中继板，因此，芯片封装结构体积变小，应用于云台时，更利于整体云台机械结构设计。
4、可避免中继板上电子器件带来的寄生电容，能够取得更好的SI效果。
需要说明的是，由于第一连接部用于与芯片20连接，图中不便示出，因此图3及图4中未示出，图3及图4中所示的内部线路13的布线方式仅为示例性结构，并不代表本申请中基板10的内部线路13的布线方式仅为图中所示，内部线路13的布线方式可根据实际的需求进行调整，此处不一一赘述。
在本申请实施例中，为更好地实现基板10的内部线路13的精准设计，基板10为双层结构的基板10，例如基板10包括但不限于为双层结构的RT(射频)板，当然基板10也可以通过其他可实现精准线路蚀刻的材料板制成。采用双层结构的基板10，可实现严格的层间对位，以使得内部线路13的布置更加精准，且实现起来也比较简单。同时，双层结构的基板10自身结构较薄，能够满足更好的焊锡渗透率，为后续连接芯片20及信号线40带来更高的可靠性。
进一步地，本申请实施例中，第一连接部与基板10的连接方式包括但不限于为焊接。一种可实现的方式是，继续参见图3，第一连接部为焊接部。芯片20上设置有柱形焊接球21，芯片20通过柱形焊接球21与第一连接部焊接。基板10上的焊接部可在基板10进行蚀刻过程中预留下的焊接点。芯片20包括但不限于为驱动器芯片20，芯片20上的柱形焊接球21可在生产芯片20的过程中通过化学工艺生长出的接触点。连接时，先将芯片20上的柱形焊接球21与第一连接部对位并固定，然后再通过加锡、加热等方式完成柱形焊接球21将芯片20与第一连接部的焊接，从而实现芯片20与基板10的内部线路13导通信号。或者通过引线键合工艺，将柱形焊接球21与焊接部连接。
基板10上的第二连接部11为贯穿基板10的通孔，可采用激光打孔工艺或者机械打孔工艺等方式将基板10打穿，此时的通孔仅边缘处与内部线路13连接，与信号线40连接后信号传输效果不佳。为提高通孔与内部线路13的连接效果，在打孔完成后，在通孔的内壁上电镀金属，作为电镀层，通过电镀层使得整个通孔具有电器传导能力。
通孔电镀完成后，在电镀层内侧钻孔，以便信号线40完成同轴线焊接。通孔可用于引导信号线40从基板10的表面插入基板10的电镀层的钻孔内，具有电镀层的通孔作为信号线40插入后焊锡固定、信号传输的主要空间。通孔的孔径可大致在10mil左右，即通孔的孔径可为10mil，或者稍大于10mil，或者稍小于10mil均可。通孔的孔径在10mil左右，可便于信号线40插入且重复渗透 焊锡。电镀层的厚度为1mil左右，保证良好的导电性能。基板10可作为整个芯片封装结构的硬体承载底板，通过基板10的内部线路13完成芯片20与对应的通孔之间的信号连接。
进一步地，基板10的第二连接部11的位置可根据不同的设计需求进行预先标记，然后根据标记的位置通过激光打孔工艺或者机械打孔工艺等方式将基板10打穿，以形成通孔。一种标记方式是，在基板10进行蚀刻过程中，在基板10的朝向保护层30的一侧上设置用于定位第二连接部11位置的定位标识。定位标记包括但不限于为预留的金属光学样板标志，金属光学样板标志不仅在至设置第二连接部11是起到标记作用，同时，在后续在保护层30上设置过线孔31时，同样为过线孔31的定位提供精确参考位置。金属光学样板标志为过线孔31定位在下述内容中记载，此处不做详述。
第二连接部11根据不同的芯片20规格及不同的信号传输需求可设置为不同的数量，例如，第二连接部11可设置为至少为两个，第一连接部的数量与第二连接部11的数量对应，因此，第一连接部至少为两个。第二连接部11及第一连接部的一种位置设置方式是，至少两个第二连接部11分别位于基板10的相对两端，第一连接部位于基板10的中部，每个第一连接部分别对应连接一个第二连接部11。相应地，芯片20上的柱形焊接球21的数量与第一连接部的数量对应。
举例来说，参见图3及图4，第二连接部11为四个，对称分布在基板10的宽度方向的对称轴的两侧。图4中所示的A-A虚线即为基板10的宽度方向的对称轴。第二连接部11为四个，对称分布在基板10的宽度方向的对称轴的两侧，即对称轴的两侧分别设置有两个第二连接部11。位于对称轴同侧的第二连接部11与第一连接部一一对应连接。这样的设置方式使得宽度对称轴的两侧的第二连接部11到芯片20的距离大致相等，从而保证信号的传输距离相等，减少寄生电容，保证信号质量。进一步地，在第二连接部11对称分布在基板10的宽度方向的对称轴的两侧的基础上，第二连接部11对称分布在基板10的长度方向的对称轴的两侧，图4中所示的B-B虚线即为基板10的长度方向的对称轴，长度方向的对称轴与宽度方向的对称轴垂直，从而进一步保证宽度对称轴的两侧的第二连接部11到芯片20的距离大致相等。
为保护芯片20，在基板10上层设置保护层30，保护层30可用于固定、保 护整个芯片封装结构。为防止后续保护层30设置过线孔31的步骤导致的保护层30崩裂，提高良率，本申请实施例中，包括但不限于保护层30通过环氧树脂材料制成。保护层30可通过注塑工艺，注塑与基板10上。保护层30上的过线孔31可通过以下设置方式完成：
一种可实现的方式是，参见图5，保护层30通过注塑模具50及填充件51，配合注塑工艺制成，具体方式如下：
首先，将带有芯片20的基板10放入注塑模具50内。其中，基板10已经制作完成，如，参见图4，基板10上设置有四个第二连接部11，芯片20设在基板10的中部。基板10上设置有用于定位第二连接部11位置的定位标识，定位标识可通过上述内容所记载的金属光学样板标志实现。定位标识也为四个。金属光学样板标志用于在保护层30上设置过线孔31时，为过线孔31的定位提供精确参考位置。
然后，在注塑模具50内，在与定位标识相应的位置上设置填充件51。其中，填充件51也为四个，且填充件51的位置与定位标识对应。为保证在注塑过程中，填充件51不会发生形变，从而导致过线孔31位置偏移，填充件51可通过刚性较大的材料制成，如，填充件51可通过金属材料制成。填充件51的形状与第二连接部11相匹配，如填充件51为柱形结构，柱形结构的直径与第二连接部11的直径大致相等，其中，大致相等的意思可指，柱形结构的直径与第二连接部11的直径相等，或者略大或者略小均可。
之后，通过注塑模具50注塑后，移除填充件51及注塑模具50，形成带有过线孔31的保护层30。其中，通过环氧树脂材料制成保护层30，待环氧树脂凝固后，移除注塑模具50及填充件51，便可得到具有过线孔31的保护层30。
另一种可实现的方式是，参见图5，保护层30通过注塑模具50，配合注塑工艺制成，与上述方式不同的是，此种方式不设置填充件51，在完成注塑后，在保护层30上打孔形成过线孔31，从而得到具有过线孔31的保护层30。具体方式如下：
首先，将带有芯片20的基板10放入注塑模具50内。
然后，通过注塑模具50注塑形成保护层30。
之后，根据定位标识，通过激光打孔工艺或机械打孔工艺在保护层30上形成过线孔31。其中，在打孔时，可通过X射线透视的方式，精确确认基板10 上的金属光学样板标志位置，然后通过激光打孔工艺或机械打孔工艺在保护层30上形成过线孔31。例如，通过激光打孔时，在打孔时，可通过X射线透视的方式，精确确认基板10上的金属光学样板标志位置，以便为打孔设备标记基准零点位置，通过丝印在保护层30表面使用激光雕刻精确点出基准零点位置，并同时识别确认过线孔31的坐标位置，在保护层30的表面精确雕刻出过线孔31。
上述两种方式均可得到具有过线孔31的保护层30，若获得的过线孔31的位置与第二连接部11的位置对应，这说明芯片封装结构合格。若过线孔31的位置与第二连接部11的位置具有偏差，则说明芯片封装结构不合格，不能使用，即便是可以使用也可能造成信号线40与第二连接部11连接不稳定的情况。因此，在本申请实施例中，在获得具有过线孔31的保护层30之后，还提供了检测步骤，以检测出过线孔31的位置与第二连接部11的位置具有偏差的芯片封装结构。
一种可实现的检测方式是，首先，以定位标识作为零点坐标位置，获取过线孔31的中心点的坐标。如，通过机械手臂将芯片封装结构放置在机台上，将金属光学样板标志置于机台零点位置，并在基板10下方抽真空定位固定。
然后，对比过线孔31的中心点的坐标与预设坐标，获取坐标误差。例如，将预先编程的开孔坐标(即预设坐标)与保护层30表面激光雕刻出来的过线孔31的中心点坐标进行误差对比，获取坐标误差。
之后，根据对比结果判断芯片封装结构是否合格。若坐标误差小于误差阈值，则过线孔31位置准确。若坐标误差大于等于误差阈值，则剔除误差过大的芯片封装结构。其中，误差阈值可根据不同的设计需求进行预先设定，本申请实施例在此处不做具体限定。
下面以图3及图4中所示的芯片封装结构为例，对本申请实施例提供的芯片封装结构如何使用进行介绍，一种使用方式，如下：
首先，在信号线40材的头端，根据芯片封装结构的厚度(基板10的厚度+保护层30的厚度)，选取连接段的长度，如，选取1.5mm长度，剥开约1.5mm长度的外皮42，露出芯线41。
然后，将芯线41插入保护层30的过线孔31内，且确保芯线41完全穿过保护层30的过线孔31及基板10的通孔(第二连接部11)，在基板10的背面能够看到芯线41露出。其中，基板10的背面是指基板10背向保护层30的一 面。
之后，将信号线40固定，可沿着基板10的延伸方向固定，并在保护层30的过线孔31位置打迅速固化的非导电胶，实现高速组装，保证信号线40与保护层30之间可靠的固定。
再然后，在整个信号线40的位于芯片封装结构外的部位包裹防热贴纸，以避免外部热源对信号线40造成损坏。
最后，在基板10的背面，通孔的下方通过波峰焊，使焊锡充分渗透整个基板10的通孔，使基板10的通孔内的芯线41与电镀层完全连接。或者，信号线40还可以通过刷锡膏+风枪加热的方式也可完成芯线41与电镀层完全连接。
进一步地，为扩展芯片封装结构的适用范围，参见图6，本申请实施例中，在基板10背向芯片20的一侧上还设置有焊盘13。焊盘13与第二连接部11电连接。可在基板10制作时预留焊盘13，焊盘13可为铜皮焊盘。通过焊盘13可直接将芯片封装结构焊接在其他电路板上，预留的铜皮焊盘作为芯片20直接在电路板上焊接固定的接触面，构成LGA封装形式(LGA全称是Land Grid Array，栅格阵列封装)。
下面通过具体检测数据介绍本申请实施例提供的芯片封装结构的使用效果，参见图7，图中A线(实线)所示为信号发送端与信号接收端之间具有中继板时，信号传播时的SI性能，如图2中所示的连接方式。图中B线(虚线)所示为信号发送端与信号接收端之间使用本申请实施例提供的芯片封装结构时，信号传播的SI性能。
参见图7所示，具有中继板时，信号传至驱动器内部时，必须经过连接器、至少2个过孔和PCB走线，会产生影响信号传输的寄生电容，对信号质量有影响，SI性能(Signal Integrity，信号完整性)较差。
本申请实施例中，信号传播路径精简，只经过一个通孔后，信号便可经由柱形焊接球21直接传入芯片20内，SI性能更好。参见图7，具有中继板的方案与本申请实施例的方案相比，在1GHz下的传输系数S21对比表现可知，本申请实施例的方案SI性能优于具有中继板的方案69.3mdB，信号传输质量得到保证。
需要说明的是，图7中所示的对比数据仅为示例性结构，并不代表本申请中的芯片封装结构的使用效果仅为图中所示，这并不构成本申请实施例的不当 限定。
综上，在本申请实施例中，去掉了中继板，即省去了中继板上的各类电子器件，所以能够降低生产成本，达到了重大的降成本优势。同时，省去了中继板，使得芯片封装结构的体积变小，省去了中间板所占的空间，因此更利于云台臂的机械结构设计。并且，使用信号线40连接时，信号线40与芯片封装结构的连接方式为过孔填塞插入式焊接固定，将信号线40的连接方式融入芯片封装结构中，从各维度提升产品特性指标，相比传统技术的接插件连接，具有更好的牢固性、可靠性，因此，更适合经常移动的云台结构件使用。由于本申请实施例中，直接将信号线40焊接于基板10侧，因此避免了接插件带来的寄生电容，能够取得更好的SI效果，有效提高接收端的信号质量。另外，本申请实施例中根据设置的焊盘13，扩展了芯片封装结构的适用范围，提高了实用性。
实施例2
相应地，在本申请的一个实施例中，还提供了一种芯片20的封装方法，实施例2中的方法可制作实施例1中所述的芯片封装结构。具体方案如下：
参见图8，结合图3及图4，在本申请的一个实施例中，还提供了一种芯片20的封装方法，包括：
步骤S101：将芯片20设置在基板10上，使得芯片20与基板10上的第一连接部电连接；其中，基板10上具有第一连接部及第二连接部11，第一连接部与第二连接部11通过基板10的内部线路13电连接；其中，第二连接部11为贯穿基板10的通孔，通孔内设置有带有连接孔的电镀层；
步骤S102：在基板10上设置保护层30，保护层30将芯片20及第二连接部11包裹于保护层30内；
步骤S103：在保护层30上与第二连接部11对应的位置设置过线孔31，以便信号线40穿过过线孔31与第二连接部11电连接。
本申请实施例提供的技术方案，通过芯片封装结构可实现芯片20通过基板10的内部线路13与信号线40的连接，可省略中继板以及中继板上设置的电子器件，可有效降低成本，大大提升成本优势。虽然省去了中继板，但信号传播的质量依然能够达到性能指标，甚至更好。由于省去了中继板，因此，芯片封装结构体积变小，应用于云台时，更利于整体云台机械结构设计。可 避免中继板上电子器件带来的寄生电容，能够取得更好的SI效果。
进一步地，本申请实施例中，对于步骤S101来说，本申请实施例中，第一连接部与基板10的连接方式包括但不限于为焊接。一种可实现的方式是，继续参见图3，第一连接部为焊接部。芯片20上设置有柱形焊接球21，芯片20通过柱形焊接球21与第一连接部焊接。基板10上的焊接部可在基板10进行蚀刻过程中预留下的焊接点。芯片20包括但不限于为驱动器芯片20，芯片20上的柱形焊接球21可在生产芯片20的过程中通过化学工艺生长出的接触点。将芯片20设置在基板10上，包括：将芯片20固定于基板10上，加热柱形焊接球21和/或焊接部，以将柱形焊接球21和/或焊接部熔接。或者通过引线键合工艺，将柱形焊接球21与焊接部连接。
在本申请实施例中，将芯片20设置在基板10上，之前还包括：制作基板10，包括：通过双层结构基板10作为基板10的主体，其中，主体具有内部线路13。在主体的第一预设位置上设置第一连接部。在主体的第二预设位置上设置贯穿基板10的通孔，以作为第二连接部11。在通孔内壁设置电镀层；在电镀层上设置连接孔。
在本申请实施例中，为更好地实现基板10的内部线路13的精准设计，基板10为双层结构的基板10，例如基板10包括但不限于为双层结构的RT(射频)板，当然基板10也可以通过其他可实现精准线路蚀刻的材料板制成。采用双层结构的基板10，可实现严格的层间对位，以使得内部线路13的布置更加精准，且实现起来也比较简单。同时，双层结构的基板10自身结构较薄，能够满足更好的焊锡渗透率，为后续连接芯片20及信号线40带来更高的可靠性。
基板10上的第二连接部11为贯穿基板10的通孔，可采用激光打孔工艺或者机械打孔工艺等方式将基板10打穿，此时的通孔仅边缘处与内部线路13连接，与信号线40连接后信号传输效果不佳。为提高通孔与内部线路13的连接效果，在打孔完成后，在通孔的内壁上电镀金属，作为电镀层，通过电镀层使得整个通孔具有电器传导能力。
通孔电镀完成后，在电镀层内侧钻孔，以便信号线40完成同轴线焊接。通孔可用于引导信号线40从基板10的表面插入基板10的电镀层的钻孔内，具有电镀层的通孔作为信号线40插入后焊锡固定、信号传输的主要空间。通孔的孔径可大致在10mil左右，即通孔的孔径可为10mil，或者稍大于10mil，或者稍 小于10mil均可。通孔的孔径在10mil左右，可便于信号线40插入且重复渗透焊锡。电镀层的厚度为1mil左右，保证良好的导电性能。基板10可作为整个芯片封装结构的硬体承载底板，通过基板10的内部线路13完成芯片20与对应的通孔之间的信号连接。
进一步地，可选地，通过双层结构基板10作为基板10的主体，还包括：在基板10的朝向保护层30的一侧上设置用于定位第二连接部11位置的定位标识。基板10的第二连接部11的位置可根据不同的设计需求进行预先标记，然后根据标记的位置通过激光打孔工艺或者机械打孔工艺等方式将基板10打穿，以形成通孔。一种标记方式是，在基板10进行蚀刻过程中，在基板10的朝向保护层30的一侧上设置用于定位第二连接部11位置的定位标识。定位标记包括但不限于为预留的金属光学样板标志，金属光学样板标志不仅在至设置第二连接部11是起到标记作用，同时，在后续在保护层30上设置过线孔31时，同样为过线孔31的定位提供精确参考位置。
第二连接部11根据不同的芯片20规格及不同的信号传输需求可设置为不同的数量，例如，第二连接部11可设置为至少为两个，第一连接部的数量与第二连接部11的数量对应，因此，第一连接部至少为两个。第二连接部11及第一连接部的一种位置设置方式是，至少两个第二连接部11分别位于基板10的相对两端，第一连接部位于基板10的中部，每个第一连接部分别对应连接一个第二连接部11。相应地，芯片20上的柱形焊接球21的数量与第一连接部的数量对应。
举例来说，参见图3及图4，第二连接部11为四个，对称分布在基板10的宽度方向的对称轴的两侧。图4中所示的A-A虚线即为基板10的宽度方向的对称轴。第二连接部11为四个，对称分布在基板10的宽度方向的对称轴的两侧，即对称轴的两侧分别设置有两个第二连接部11。位于对称轴同侧的第二连接部11与第一连接部一一对应连接。这样的设置方式使得宽度对称轴的两侧的第二连接部11到芯片20的距离大致相等，从而保证信号的传输距离相等，减少寄生电容，保证信号质量。进一步地，在第二连接部11对称分布在基板10的宽度方向的对称轴的两侧的基础上，第二连接部11对称分布在基板10的长度方向的对称轴的两侧，图4中所示的B-B虚线即为基板10的长度方向的对称轴，长度方向的对称轴与宽度方向的对称轴垂直，从而进一步保证宽度对称轴的两侧的第二连接部11到芯片20的距离大致相等。
为保护芯片20，在基板10上层设置保护层30，保护层30可用于固定、保护整个芯片封装结构。为防止后续保护层30设置过线孔31的步骤导致的保护层30崩裂，提高良率，本申请实施例中，包括但不限于保护层30通过环氧树脂材料制成。保护层30可通过注塑工艺，注塑与基板10上。保护层30上的过线孔31可通过以下设置方式完成：
一种可实现的方式是，参见图5，保护层30通过注塑模具50及填充件51，配合注塑工艺制成，具体方式如下：
在基板10上设置保护层30，包括：
步骤S201：将带有芯片20的基板10放入注塑模具50内。其中，基板10已经制作完成，如，参见图4，基板10上设置有四个第二连接部11，芯片20设在基板10的中部。基板10上设置有用于定位第二连接部11位置的定位标识，定位标识可通过上述内容所记载的金属光学样板标志实现。定位标识也为四个。金属光学样板标志用于在保护层30上设置过线孔31时，为过线孔31的定位提供精确参考位置。
步骤S202：在注塑模具50内，在与定位标识相应的位置上设置填充件51。其中，填充件51也为四个，且填充件51的位置与定位标识对应。为保证在注塑过程中，填充件51不会发生形变，从而导致过线孔31位置偏移，填充件51可通过刚性较大的材料制成，如，填充件51可通过金属材料制成。填充件51的形状与第二连接部11相匹配，如填充件51为柱形结构，柱形结构的直径与第二连接部11的直径大致相等，其中，大致相等的意思可指，柱形结构的直径与第二连接部11的直径相等，或者略大或者略小均可。
步骤S203：通过注塑模具50注塑后，移除填充件51及注塑模具50，形成带有过线孔31的保护层30。其中，通过环氧树脂材料制成保护层30，待环氧树脂凝固后，移除注塑模具50及填充件51，便可得到具有过线孔31的保护层30。
另一种可实现的方式是，参见图5，保护层30通过注塑模具50，配合注塑工艺制成，与上述方式不同的是，此种方式不设置填充件51，在完成注塑后，在保护层30上打孔形成过线孔31，从而得到具有过线孔31的保护层30。具体方式如下：
在基板10上设置保护层30，包括：
步骤S301：将带有芯片20的基板10放入注塑模具50内；
步骤S302：通过注塑模具50注塑形成保护层30；
步骤S303：根据定位标识，通过激光打孔工艺或机械打孔工艺在保护层30上形成过线孔31。其中，在打孔时，可通过X射线透视的方式，精确确认基板10上的金属光学样板标志位置，然后通过激光打孔工艺或机械打孔工艺在保护层30上形成过线孔31。例如，通过激光打孔时，在打孔时，可通过X射线透视的方式，精确确认基板10上的金属光学样板标志位置，以便为打孔设备标记基准零点位置，通过丝印在保护层30表面使用激光雕刻精确点出基准零点位置，并同时识别确认过线孔31的坐标位置，在保护层30的表面精确雕刻出过线孔31。
上述两种方式均可得到具有过线孔31的保护层30，若获得的过线孔31的位置与第二连接部11的位置对应，这说明芯片封装结构合格。若过线孔31的位置与第二连接部11的位置具有偏差，则说明芯片封装结构不合格，不能使用，即便是可以使用也可能造成信号线40与第二连接部11连接不稳定的情况。因此，在本申请实施例中，在获得具有过线孔31的保护层30之后，还提供了检测步骤，以检测出过线孔31的位置与第二连接部11的位置具有偏差的芯片封装结构。
一种可实现的检测方式是，形成连接孔之后，还包括：
步骤S501：以定位标识作为零点坐标位置，获取过线孔31的中心点的坐标。如，通过机械手臂将芯片封装结构放置在机台上，将金属光学样板标志置于机台零点位置，并在基板10下方抽真空定位固定。
步骤S501：对比过线孔31的中心点的坐标与预设坐标，获取坐标误差。例如，将预先编程的开孔坐标(即预设坐标)与保护层30表面激光雕刻出来的过线孔31的中心点坐标进行误差对比，获取坐标误差。
步骤S501：若坐标误差小于误差阈值，则过线孔31位置准确。若坐标误差大于等于误差阈值，则剔除误差过大的芯片封装结构。其中，误差阈值可根据不同的设计需求进行预先设定，本申请实施例在此处不做具体限定。
进一步地，为扩展芯片封装结构的适用范围，参见图6，本申请实施例中，在通孔内壁设置电镀层，还包括：在基板10背向芯片20的一侧设置焊盘13，焊盘13与第二连接部11电连接。可在基板10制作时预留焊盘13，焊盘13可 为铜皮焊盘。通过焊盘13可直接将芯片封装结构焊接在其他电路板上，预留的铜皮焊盘作为芯片20直接在电路板上焊接固定的接触面，构成LGA封装形式(LGA全称是Land Grid Array，栅格阵列封装)。
需要说明的是，实施例2中所记载的相关技术方案与实施例1中所记载的技术方案可相互参考、借鉴，此处不再一一赘述。
综上所示，在本申请实施例中，去掉了中继板，即省去了中继板上的各类电子器件，所以能够降低生产成本，达到了重大的降成本优势。同时，省去了中继板，使得芯片封装结构的体积变小，省去了中间板所占的空间，因此更利于云台臂的机械结构设计。并且，使用信号线连接时，信号线与芯片封装结构的连接方式为过孔填塞插入式焊接固定，将信号线的连接方式融入芯片封装结构中，从各维度提升产品特性指标，相比传统技术的接插件连接，具有更好的牢固性、可靠性，因此，更适合经常移动的云台结构件使用。由于本申请实施例中，直接将信号线焊接于基板侧，因此避免了接插件带来的寄生电容，能够取得更好的SI效果，有效提高接收端的信号质量。另外，本申请实施例中根据设置的焊盘，扩展了芯片封装结构的适用范围，提高了实用性。
本申请实施例适用于但不限于以下技术领域：硬件设计、SI(Signal Integrity，信号完整性)性能优化等领域。本申请实施例适用于但不限于以下应用方式：应用在系统板与负载板之间的连接信号线中。本申请实施例适用于但不限于以下产品形态：具有云台绕线、适用于软信号线延长信号的产品形态；如，手持云台、无人机云台、相机云台及各种拍摄设备云台等。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种芯片封装结构，其特征在于，包括：
    基板，所述基板上具有第一连接部及第二连接部，所述第一连接部与所述第二连接部通过所述基板的内部线路电连接；其中，所述第二连接部为贯穿所述基板的通孔，所述通孔内设置有带有连接孔的电镀层；
    芯片，所述芯片设置于所述基板之上，并与所述第一连接部电连接，以便所述第二连接部与所述芯片之间通过所述基板的内部线路形成信号通路；
    保护层，所述保护层设置于所述基板上，并将所述芯片及所述第二连接部包裹于所述保护层内，所述保护层上与所述第二连接部对应的位置具有过线孔，以便信号线穿过所述过线孔与所述第二连接部电连接。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述第一连接部为焊接部；
    所述芯片上设置有柱形焊接球，所述芯片通过所述柱形焊接球与所述第一连接部焊接。
  3. 根据权利要求1所述的芯片封装结构，其特征在于，所述第二连接部至少为两个，分别位于所述基板的相对两端；
    所述第一连接部至少为两个，位于所述基板的中部，每个所述第一连接部分别对应连接一个所述第二连接部。
  4. 根据权利要求3所述的芯片封装结构，其特征在于，所述第二连接部为四个，对称分布在所述基板的宽度方向的对称轴的两侧；
    所述第一连接部为四个，对称分布在所述基板的宽度方向的对称轴的两侧；
    位于对称轴同侧的所述第二连接部与所述第一连接部一一对应连接。
  5. 根据权利要求1所述的芯片封装结构，其特征在于，在所述基板背向所述芯片的一侧上还设置有焊盘；
    所述焊盘与所述第二连接部电连接。
  6. 根据权利要求1至5中任一项所述的芯片封装结构，其特征在于，所述基板为双层结构基板。
  7. 根据权利要求1至5中任一项所述的芯片封装结构，其特征在于，所述保护层通过环氧树脂材料制成；
    所述保护层通过注塑工艺，注塑与所述基板上。
  8. 一种芯片的封装方法，其特征在于，包括：
    将芯片设置在基板上，使得所述芯片与所述基板上的第一连接部电连接；其中，所述基板上具有第一连接部及第二连接部，所述第一连接部与所述第二连接部通过所述基板的内部线路电连接；其中，所述第二连接部为贯穿所述基板的通孔，所述通孔内设置有带有连接孔的电镀层；
    在所述基板上设置保护层，所述保护层将所述芯片及所述第二连接部包裹于所述保护层内；
    在所述保护层上与所述第二连接部对应的位置设置过线孔，以便信号线穿过所述过线孔与所述第二连接部电连接。
  9. 根据权利要求8所述的封装方法，其特征在于，所述第一连接部为焊接部；
    所述芯片上设置有柱形焊接球；
    所述将芯片设置在基板上，包括：
    将所述芯片固定于所述基板上；
    加热所述柱形焊接球和/或所述焊接部，以将所述柱形焊接球和/或所述焊接部熔接；或者通过引线键合工艺，将所述柱形焊接球与所述焊接部连接。
  10. 根据权利要求8所述的封装方法，其特征在于，所述将芯片设置在基板上，之前还包括：制作所述基板，包括：
    通过双层结构基板作为所述基板的主体，其中，所述主体具有内部线路；
    在所述主体的第一预设位置上设置所述第一连接部；
    在所述主体的第二预设位置上设置贯穿所述基板的所述通孔，以作为所述第二连接部；
    在所述通孔内壁设置电镀层；
    在所述电镀层上设置连接孔。
  11. 根据权利要求10所述的封装方法，其特征在于，在所述通孔内壁设置 电镀层，还包括：
    在所述基板背向所述芯片的一侧设置焊盘，所述焊盘与所述第二连接部电连接。
  12. 根据权利要求10所述的封装方法，其特征在于，通过双层结构基板作为所述基板的主体，还包括：在所述基板的朝向所述保护层的一侧上设置用于定位所述第二连接部位置的定位标识。
  13. 根据权利要求12所述的封装方法，其特征在于，所述在所述基板上设置保护层，包括：
    将带有所述芯片的所述基板放入注塑模具内；
    在所述注塑模具内，在与所述定位标识相应的位置上设置填充件；
    通过所述注塑模具注塑后，移除所述填充件及所述注塑模具，形成带有所述过线孔的所述保护层。
  14. 根据权利要求12所述的封装方法，其特征在于，所述在所述基板上设置保护层，包括：
    将带有所述芯片的所述基板放入注塑模具内；
    通过所述注塑模具注塑形成所述保护层；
    根据所述定位标识，通过激光打孔工艺或机械打孔工艺在所述保护层上形成所述过线孔。
  15. 根据权利要求13或14所述的封装方法，其特征在于，形成所述连接孔之后，还包括：
    以所述定位标识作为零点坐标位置，获取所述过线孔的中心点的坐标；
    对比所述过线孔的中心点的坐标与预设坐标，获取坐标误差；
    若所述坐标误差小于误差阈值，则所述过线孔位置准确。
  16. 根据权利要求13或14所述的封装方法，其特征在于，通过所述注塑模具注塑形成所述保护层，包括：通过环氧树脂材料制成所述保护层。
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