CN102246306A - 具有增大的击穿电压特性的基于沟槽的功率半导体器件 - Google Patents
具有增大的击穿电压特性的基于沟槽的功率半导体器件 Download PDFInfo
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- CN102246306A CN102246306A CN2009801491991A CN200980149199A CN102246306A CN 102246306 A CN102246306 A CN 102246306A CN 2009801491991 A CN2009801491991 A CN 2009801491991A CN 200980149199 A CN200980149199 A CN 200980149199A CN 102246306 A CN102246306 A CN 102246306A
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Abstract
本发明公开了具有提供增大的击穿电压和其它益处的特征的示例性功率半导体器件。
Description
相关申请的引用
本申请要求于2008年12月8日提交的美国临时专利申请No.61/120818的权益,将其全部内容结合于此供参考。
背景技术
示例性功率半导体器件包括平面栅MOSFET晶体管、竖直栅MOSFET晶体管、绝缘栅双极晶体管(IGBT)、整流管和同步整流管。这些器件的槽栅多样性的典型实施包括在半导体芯片(裸芯片,die)顶面上形成的沟槽阵列,其中每个沟槽用屏蔽电极(shield electrode)和/或栅电极填充,这取决于功率器件的类型。沟槽限定平台(mesa)的对应阵列,每个平台设置在相邻沟槽之间。取决于在芯片上实现的器件,各种电极和/或掺杂区设置在平台的顶部。每个平台和它的相邻沟槽实现该器件的小实例,并且这些小实例并联耦接在一起从而提供整个功率半导体器件。整个器件具有其中期望电流流过该器件的ON状态(连通状态)、其中电流在器件中基本被阻断的OFF状态(断开状态),以及其中由于在器件的导电电极之间施加过大断开电压导致的不期望电流流动的击穿状态。引发击穿的电压称为击穿电压(breakdown voltage)。每个平台和它的相邻沟槽被构造成提供一组期望的ON状态特性和击穿电压。在平台和沟槽的设计中,在实现良好ON状态特性、高击穿电压和改善的开关特性之间存在各种权衡(tradeoff)。
典型的功率半导体芯片具有其中设置有实现器件的平台和沟槽阵列的有源区、围绕该有源区的场终止区(field termination area),以及其中可以提供互连和沟道截止(channel stop)的无源区(inactive area)。场终止区使有源区周围的电场最小化,并且不用于传导电流。理想地,人们希望器件的击穿电压由与有源区相关的击穿过程确定。然而,存在在显著较低电压下能够在场终止区和无源区中发生的各种击穿过程。这些击穿过程可称为被动击穿过程。
现有技术中为了设计具有比有源区更高的击穿电压的场终止区已经做出了许多努力。然而,这样的现有技术设计常常没有达到该目的,经常需要增加总芯片面积和芯片成本的折衷。
发明内容
本发明的发明人发现了基于沟槽的功率器件中寄生击穿条件可能首先发生的若干位置。本申请提供了对抗这些击穿条件并增大击穿电压的新颖和创造性特征。
本文中描述的本发明示例性实施方式的各个方面可以单独使用或以任意组合使用。
附图说明
图1示出了包括根据本发明的若干特征的一种示例性半导体芯片的顶视图。
图2示出了根据本发明的图1的示例性半导体芯片的左上角的放大视图。
图3示出了根据本发明的图1的示例性半导体芯片的左侧的一部分的放大视图。
图4和图5示出了根据本发明的图1的示例性半导体芯片的一部分的第一剖面图和其在图5中的放大图。
图6示出了根据本发明的图1的示例性半导体芯片的变形的一部分的放大剖面图。
图7-14示出了根据本发明的图1的示例性半导体芯片及其可能的变形的各种放大剖面图。
图15示出了包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图16-19示出了根据本发明的图15的示例性半导体芯片及其可能的变形的各种放大剖面图。
图20示出了包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图21-29示出了根据本发明的图20的示例性半导体芯片及其可能的变形的各种放大剖面图。
图30示出包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图31示出了根据本发明的图30的示例性半导体芯片的放大剖面图。
图32示出了根据本发明的包括数个特征的另一示例性半导体芯片的俯视图。
图33-36示出了本发明的图32的示例性半导体芯片的各种放大剖面图及其可能变型。
图37-39示出了根据本发明的包括数个特征的另一示例性半导体的各种放大剖面图及其可能变型。
具体实施方式
在下文中将参考其中示出了本发明的示例性实施方式的附图更充分地描述根据本发明的技术。然而,本发明可以以不同形式具体体现,并且不应该解释为限于本文中例举的这些实施方式。相反,提供这些实施方式以使本申请公开内容充分完整,并向本领域技术人员充分传达本发明的范围。在附图中,为了清楚,可能夸大了层和区域的厚度。使用相同的标号来指代整个说明书中的相同元件。这些元件对于不同的实施方式可以具有不同的相互关系和不同的位置。
还应理解,当一个层称为在另一个层或衬底“上”时,它能够直接在其它层或衬底上,或也可以存在插入层。还应理解,当一个元件例如层、区域或衬底称为在另一元件“上”,“连接至”、“电连接至”、“耦接至(coupledto)”或“电耦接至(electrically coupled to)”另一元件时,它能够直接在其它元件上、连接或耦接至其它元件,或可以存在一个或更多插入元件。相反,当一个元件称为“直接在另一元件上”、“直接连接至”或“直接耦接至”另一元件或层时,没有插入元件或层存在。可以理解,本申请的权利要求可以修改为引述本说明书中描述的或附图中示出的示例性关系,其支持由原始申请提供。本文中使用的术语“和/或”包括相关例举项目中的一个或多个的任意和全部组合。
本文中使用的术语仅用于本发明的举例说明目的,而不应解释为限制本发明的含义或范围。如在本说明书中使用的,除非根据上下文明确表示特定情形,单数形式可以包括复数形式。同样,在本说明书中使用的表达“包含”和/或“包括”既不限定提及的形状、数量、步骤、行为、操作、构件、元件和/或这些的组,也不排除存在或添加一个或多个其他不同的形状、数量、步骤、行为、操作、构件、元件和/或这些的组,或添加这些。空间相关术语,例如“在上方”、“高于”、“较高”、“在下方”、“在下面”、“低于”、“较低”等等,可以在本文中使用,用于方便描述以描述如图中所示的一个元件或特征相对于一个元件或特征的关系。应当理解,这些空间相关术语用于涵盖除了图中示出的定向之外,在使用或操作中器件的不同取向。例如,如果图中器件翻转,那么描述为“低于”其它元件或特征或“在其它元件或特征下面”或“在其它元件或特征下方”的元件将会定向为“在其它元件或特征上面”或“高于”其它元件或特征。因此,示例性术语“高于”可能涵盖高于和低于两种定向。
如本文使用的,术语例如“第一”、“第二”等用来描述各种构件、组件、区域、层和/或部分。然而,很明显,构件、组件、区域、层和/或部分不应由这些术语限定。这些术语仅用于区分一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分。因此,将要描述的第一构件、组件、区域、层或部分也可指第二构件、组件、区域、层或部分,而不背离本发明的范畴。
图1示出了包括根据本发明的若干特征的示例性半导体器件100的顶视图。器件100包括位于在芯片中部的有源器件区(装置区,device region)120。不失一般性,器件区120可实现一个竖直的、沟槽屏蔽的功率MOSFET器件。如下面更详细描述和示出的,该示例性MOSFET器件包括与平台(mesa)阵列交错(interleave)的沟槽阵列、设置在沟槽底部中的绝缘屏蔽电极(shield electrode)、设置在屏蔽电极上方的沟槽中的绝缘栅电极(gate electrode)、设置在平台中的源极区(source region)、设置在源极区上的源电极(source electrode)、以及设置在半导体器件背侧处的漏电极(drain electrode)。器件100进一步包括设置在器件区120上方并电耦接至源电极的源极金属层110(也称为导电层110)、以及设置在导电层110上方并与其电耦接且又电耦接至该功率MOSFET器件的源极区的源极焊盘(源极垫,source pad)111。源极焊盘111适合接收外部连接,例如提供源极电位的焊线(wire bond)或焊料凸点(solder bump),并在每侧上可以具有150微米的尺寸。
在器件区120左右侧的每侧上,器件100进一步包括与设置在沟槽中的栅电极和屏蔽电极形成电接触的连接区(connection region)150。在每个连接区中,一条导电材料,称为栅极流道(gate runner),平行于器件区120的侧面设置并与其隔开。栅极流道与沟槽中栅电极电接触,但从在沟槽之间交错的平台电绝缘。每个栅极流道电耦接至位于在芯片底部的栅极焊盘(栅极垫,gate pad)112。栅极焊盘112适合接收外部连接,例如提供栅极电位的焊线或焊料凸点。同样在每个连接区150中,另一条导电材料,称为屏蔽流道(shield runner),平行于栅极流道设置并与其隔开。屏蔽流道与沟槽中的屏蔽电极形成电接触,但与它覆盖的平台的部分电隔离。屏蔽流道通过在芯片顶部处的源极导电层的延伸而电耦接至源极导电层,或电耦接至屏蔽焊盘并使用外部链接。
沟道截断环(channel stopper)设置在芯片周边处或附近,并通过间隙与屏蔽流道和器件区120的顶部部分隔开。沟道截断环是常规的,并且可以包括遮盖且接触一条掺杂半导体区的金属的隔离环(isolated ring),其围绕芯片周边形成一个环。必需注意,芯片100不包括在这种间隙中通常出现的常规场终止结构(field termination structure)。
图2示出了芯片100左上角的放大图,而图3示出了沿该芯片左侧的一部分的放大图。以上特征在这些图中更清晰地看到。图2和图3为接下来将要讨论的芯片100的许多剖面提供参考点。
图4是包括有源器件区120和第一场终止区的芯片100的一部分的剖面图。芯片100包括N+掺杂半导体衬底102、设置在半导体衬底102上的一个或多个外延生长半导体n型层104(“外延半导体层”)、设置在无源(inactive)和第一场终止区中的外延半导体层104上方的氧化物层106、设置在氧化物层106上方的介电层107、设置在无源区左边部分的介电层107上方的栅极流道、以及设置在第一场终止区中的介电层107上方的导电层110(源极金属层110)。如在现有技术中已知的,半导体区可以用p型掺杂剂掺杂为p导电型(或“p型”)区,或用n型掺杂剂掺杂为n导电型(或“n型”)区。在器件区120中,器件100进一步包括设置在外延半导体层中的多个沟槽122,以及交错在沟槽122之间的半导体材料的多个平台130。介电层107的部分覆盖沟槽122的顶部,并且源极金属层110在有源器件区120上方延伸并与平台130形成接触。沟槽122和平台130的结构参考图5在下面进行描述。在第一终止区中,器件100进一步包括第一末端沟槽(first end trench)222、设置在第一末端沟槽222和器件区120的最左边沟槽122之间的第一末端平台(first end mesa)230、以及设置在第一末端沟槽222左边的第二末端平台238。
图5是图4中示出的第一场终止区和器件区120的放大剖面图。每个沟槽122都具有衬有介电层123的相对侧壁、设置在沟槽底部附近的侧壁之间的屏蔽电极124、设置在屏蔽电极124上方的介电层125、以及设置在该介电层上方且在沟槽侧壁之间的栅电极126。每个平台130包括设置在与层104顶面相邻的外延半导体层104中的p型阱134、设置在与两个相邻沟槽122和外延半导体层104顶面相邻的p型阱134中的一对源极(n+型)区136、以及设置在p型阱134下方的N漂移区(drift region)132。(本文中描述的p型阱、p型区和p掺杂区可以称为“第一导电型阱区”或“第二导电型阱区”,取决于讨论的上下文或权利要求的上下文内容)。在平台130的中心形成小沟槽,以允许源极金属层110与源极区136形成电接触,以及与在增强p+掺杂的小区域135处的p阱134形成电接触。电子电流竖直传导通过器件,从源极区136,通过与栅极氧化物123相邻的p型阱134的反转区(inverted region),进一步通过漂移区132,并向下直到N+衬底102和漏极接触,其中在正常操作条件下电流量通过沟槽122中的栅电极126上的电位进行调制。屏蔽电极124电耦接至源极金属层110和源极区136的电位,并屏蔽p型阱免于高电场。
当设定栅电极126上的电位以将器件置于断开状态(例如,通常大约为零伏的电位)时,在其中漏极电位相对源极电位非常高的击穿条件期间,大量电流仍可流动。在该击穿条件中,在每个平台130的区域中形成高电场,并且这种高电场产生雪崩载流子(avalanche carrier)(空穴和电子二者)。出现这种击穿条件的电压称为击穿电压。可以通过选择屏蔽氧化物厚度、平台宽度和N漂移区132的掺杂以使N漂移区132正常地耗尽电子而升高平台的击穿电压。这引起在断开状态条件期间的电场沿平台的中线更均匀地分布(例如,正方形电场轮廓),由此减小峰值电场(并由此增大能够产生雪崩载流子的电压)。N漂移区132耗尽电子的条件称为“电荷平衡条件(charge-balanced condition)”。当平台宽度和N漂移区132的掺杂的乘积(product)在1×1011cm-2到1×1013cm-2范围内时,通常能够实现电荷平衡条件。
理想地,人们希望通过与平台130相关的击穿过程来确定击穿电压。然而,各种寄生击穿机制在较低电压下在器件的各种场终止区中发生,并由此将器件的总体击穿电压的值设置为低于由平台130中的击穿过程引起的值。一种这样的电位寄生机制能够在设计有现有技术的终止区的器件区120的最外沟槽中的介电层123的薄部分处出现。没有紧接它的平台130,这个薄介电层将会暴露于耦接至漏极电位的n型外延层的电位,并且大电场能够横跨该薄介电层形成,这能够在相对低电压下引起发生击穿。
根据本发明的一个特征通过在器件区120的有源沟槽122的阵列的任一侧上设置末端沟槽222解决这种寄生击穿机制。沟槽222具有衬有介电层223的相对侧壁、设置在沟槽底部附近的侧壁之间的屏蔽电极124、设置在屏蔽电极124上方的介电层125、以及设置在介电层上方且在沟槽侧壁之间的栅电极226。然而,不同于沟槽122的介电层123,如沿着栅电极226的深度测量时,介电层223沿着面对n型外延层的侧壁的厚度比沿着面对器件区120的沟槽122的侧壁的厚度更厚。在图中通过标号227表示较厚区。较厚的电介质减小介电层中的电场,并由此增大它的击穿电压。沟槽222可以具有与每个沟槽122相同的宽度,并且栅电极226可以具有小于栅电极126的宽度。
以上沟槽222、122与平台238、230和130在用于图4的剖面线指示附近的图3的顶视图中指示。沟槽和平台的类似设置在器件区120的相反侧上存在,如通过图2的顶视图中的这些标号指示的。尽管沟槽222对结合沟槽122和平台130的阵列(在该阵列的任一侧上)(例如,阵列的顶部和底部),但它们不环绕该阵列或具有结合该阵列右侧和左侧的部分。即,在沟槽122和平台130的末端处没有竖直终止沟槽。(应当注意,沟槽122和平台130连续以在栅极流道下方伸展)。有关于此,器件100不具有设置在沟槽122末端处的p掺杂区。这些特征中的每一个都减小场终止区的尺寸,并使有源区能够被增大和/或使芯片尺寸能够被减小。尽管以上构造用于提供MOSFET器件的器件区120,但它也能够应用于其它器件类型,例如IGBT器件和整流管,特别是其中存在上述电荷平衡条件的那些器件。
再次参考图5,作为本发明的另一特征,到末端沟槽222左边的宽平台238可以可选地具有设置在它表面的p型区239,其紧接介电层223。p型区239可以与任何电位直接去耦接,并以浮置状态保持,或者可以电耦接至源极金属层110和源极电位(例如,它可以接地)。在任一情况下,区239减小宽平台238右上角周围的电场,从而消除作为寄生击穿机制的来源的这个区域。当电耦接至源极电位时,p型区239进一步屏蔽电介质223免于区域227中的漏极电位。p型区239可以在制造p型阱134的相同工艺期间进行制造。
作为本发明的另一特征,到末端沟槽222右边的平台230可以构造为p-n二极管而不是MOSFET晶体管。为此,它可以包括p型阱134和增强的p+掺杂区135,但没有源极区136。在器件区120的MOSFET晶体管的正常操作期间,该p-n二极管偏置于断开状态。平台230在宽平台238和用来从第一有源平台130缓冲宽平台238中的电位的第一有源平台130之间提供另外的间距。这使第一平台130的电特性能够与内平台130基本相同。
图6示出了根据本发明的图1的示例性半导体芯片的一种变形的一部分的放大剖面图。图6中的放大剖面中的特征与图5的放大剖面中示出的那些特征相同,其中增加了周边沟槽220、介质层221和屏蔽电极124。沟槽220具有衬有介电层221的相对侧壁、以及设置在侧壁之间(优选从外延半导体层顶部到沟槽底部附近)的屏蔽电极224。屏蔽电极224电耦接至源极金属层110。屏蔽电极224对末端沟槽(end trench)222和栅电极226提供漏极电位的另外屏蔽。平台230′限定在沟槽220和222之间。P掺杂区239可以包括在沟槽220和222之间的平台230′中,或省略。而且,可以使用设置在平台230′中并从沟槽222延伸到沟槽220的p掺杂区234中。连同区域234,P掺杂区239′可以包括在沟槽220的左侧上。一对沟槽220在阵列的任一侧(例如,阵列的顶部和底部)上结合沟槽122、222以及平台130、230、230′的阵列,但它们不环绕该阵列或不具有结合该阵列右侧和左侧的部分。这个特征减小场终止区的尺寸,并且使有源区能够被增大和/或芯片尺寸能够被减小。尽管以上构造用于提供MOSFET器件的器件区120,但它也能够应用于其它器件类型,例如IGBT器件和整流管,特别是其中存在上面描述的电荷平衡条件的那些器件。
图7示出了沿图3中限定的切割线7-7,紧邻器件区120的连接区150中的上文提及的沟槽和平台的剖面图。薄量的氧化物层106设置在平台130和230的每一个上方,并且介电层107设置在栅电极126和226、以及下面的氧化物层106上方。可选的周边沟槽220、屏蔽电极221以及介电层221以虚轮廓示出。关于在图4和图5中示出的剖面,对于p掺杂区239关于其毗邻元件的构造没有变化。
图8示出了沿图3中限定的切割线8-8,在栅极流道下方的连接区150中的上文提及的沟槽和平台的剖面图。薄量的氧化物层106设置在平台130和230的每一个上方。栅电极126和226的顶部通过导电上升部(conductive riser)126R电耦接在一起。导电上升部126R通过氧化物106的薄部分与平台130、230电隔离。在典型的实施方式中,上升部126R和栅电极126、226由相同材料例如多晶硅形成。在在先剖面中,上升部126R被移除。金属栅极流道在通过电介质107的岛分隔开的栅电极126和226上的位置处与上升部126R形成接触。可省去这些岛。栅电极126和226在该点处在沟槽中终止。可选的周边沟槽220、屏蔽电极221和介电层221以虚线轮廓示出。关于图4和图5中示出的剖面,对于p掺杂区239关于其毗邻元件的构造没有变化。
图9示出了沿图3中限定的切割线9-9,在栅极流道和屏蔽流道之间的连接区150中的上文提及的沟槽和平台的剖面图。仅屏蔽电极124和224存在于沟槽122和222中,其中氧化物层106覆盖它们以及平台130和230。
图10示出了沿图3中限定的切割线10-10,在连接区150中的沟槽122的剖面图,其中切割线10-10竖直于切割线4-4、7-7、8-8和9-9。栅电极126和屏蔽电极124设置在沟槽中,其中栅电极126具有与栅极流道形成电接触的上升部126R,并且其中屏蔽电极124具有与屏蔽流道形成电接触的上升部部分124R。介电层125在屏蔽电极124和栅电极126之间沿它们面对的水平维度设置,介电层125S在电极124和126之间沿它们面对的侧边维度设置,以及电介质的角贴片(corner patch)125C设置在栅电极126的外侧角和屏蔽电极124的内侧角之间。屏蔽电极124具有邻近介电材料的贴片123C设置的外侧角,以及邻近介电材料的侧面层123S设置的竖直侧。
曲率半径效应(radius of curvature effect)显著增加邻接屏蔽电极和栅电极126外侧角的区域中的电场。介电贴片123的厚度通常足以防止介电材料的击穿。然而,介电贴片125C和栅电极126周围的介电侧面层125S相对较薄,并且能够是用于末端沟槽222(在图8中示出)的击穿源。包括可选的屏蔽电极224和沟槽220屏蔽介电贴片125C和介电侧面层125S免于耦接至半导体层104的漏极电位,并由此减小介电贴片125C和介电侧面层125S中的电场。由于曲率半径效应引起的击穿的另一可能区域,特别是对于高电压器件,在屏蔽上升部部分124R末端处的介电侧面层123S中存在,如图10中通过点“A”指示的。通过在介电侧面层123S上方并以距离L1超过沟槽122的末端延伸顶侧屏蔽流道金属(其为导电迹线),能够显著减轻这种电位击穿。距离L1可以等于或大于沟槽122的深度。对于较浅的电压器件应用,在点“A”处的击穿可能性非常小,并且顶侧屏蔽流道金属不在介电侧面层123S上方或超过沟槽122的末端延伸,如图中通过边缘“B”指示的。这种构造导致产生更薄的屏蔽流道和更小的芯片。
图11示出了沿图3中限定的切割线11-11,在连接区150中的平台130的剖面图,其中切割线11-11竖直于切割线4-4、7-7、8-8和9-9。p掺杂阱134和用于栅电极126的上升部126R在图右边示出。典型地,p掺杂阱134电耦接至源极和屏蔽的电位,但对于其中区域用于场终止区中的一些情况下可以处于浮置状态。p掺杂阱134具有在栅极上升部126R(其是导电迹线)处或在其下方终止的的末端。供参考,栅电极126和屏蔽电极124的轮廓以短划线示出。存在由于曲率半径效应导致的在p掺杂阱134末端处发生击穿的可能性。然而,设置在p掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗邻近阱134末端的n掺杂平台130的部分,由此显著减小阱134末端周围的电位和电场。然而,减小量的电场仍在阱134的末端周围存在,并且能够以径向方式(即,曲率半径效应)在阱134的末端处集中。然而,利用图11中示出的构造,阱134的末端基本上由栅极上升部126R屏蔽,并且基本上减小了在该区域末端的曲率半径效应。具体地,导电上升部126R引导在阱134末端处的平台130中存在的电场远离阱134的末端并朝向它自身,由此减小电场的径向集中。如果阱134的末端延伸到导电上升部126R下部的左侧,那么将会丧失这种屏蔽。如果阱134的末端与导电上升部126R下部的最远端侧(即,左侧)间隔开等于或大于阱134深度的距离L2,那么获得最佳的这种屏蔽效果。在优选的实施中,L2等于或大于阱134深度加上在阱134和导电上升部126R之间的分隔距离,其中该分隔距离等于用于在图中示出的构造的氧化物层106的薄部分。
如上面提及的,设置在p掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗邻近阱134末端的n掺杂平台130的部分,由此显著减小阱134末端周围的电位和电场。为实现这个益处,p掺杂区的末端应与屏蔽电极124的末端、或沟槽122的末端间隔开至少距离L3,如图12中示出的。距离L3可以等于沟槽122的深度,或者可以等于沟槽122的深度和阱134的深度之间的差。阱134可以延伸超过栅极上升部126R,如图13中示出的,并且阱134的末端进一步可以设置在屏蔽流道(和场板(fieldplate))下面。如果屏蔽流道设置在阱134末端附近或上方,则它能够以如之前参考图11描述的栅极上升部126R提供屏蔽的方式提供屏蔽,从而减轻在阱134末端处的曲率半径效应。然而,对于低和中等电压施加,屏蔽流道不需要设置在p掺杂阱134的末端上方。尽管优选没有其它p掺杂区设置在阱134的末端和相邻沟槽的末端之间,但更轻度的p掺杂区可以设置在阱134的末端和相邻沟槽的末端之间。如横跨平台宽度的剖面测量的,更轻度的p掺杂区具有比阱134更低的掺杂剂量。换句话说,如横跨平台宽度的剖面测量的,更轻度的p掺杂区具有由于掺杂剂导致的比阱134更低的整体改变。利用以上的构造,如在现有技术构造中完成的,不需要竖直于沟槽122末端伸展的终止沟槽。p掺杂阱134末端的全部以上构造可以应用于沟槽屏蔽的肖特基势垒二极管器件,其中以上的间隔距离施加至肖特基金属的末端,或者如果类似于图6中示出的区域239′的p掺杂区在肖特基金属的周边周围使用。
再次参考图10,可以看到,屏蔽流道金属在处于或低于外延层104顶部表面的水平处与屏蔽电极124的上升部部分124R的顶部表面形成电接触。这个特征也在图14中示出,其为竖直于图10的剖面。如图14中看到的,通过穿过介电层107和氧化物层106形成的接触开口形成从屏蔽流道金属到上升部部分124R的接触。这种构造具有减小的电接触电阻以及简化制造工艺的优点。在常规制造工艺中,多晶硅蚀刻掩模和蚀刻步骤用来限定在屏蔽流道金属和屏蔽电极124、224之间的多晶硅总线结构。然而,能够通过调整工艺中使用的早期掩模,例如用来限定图5中示出的从源极金属到增强的掺杂区135和源极区136的掩模而限定以上简化的接触结构。因此,可以消除传统用来限定上述多晶硅总线结构的掩模和蚀刻步骤。
当制作高电流容量器件时,可以使用器件区120的若干实例而不是一个大的器件区120。器件区120的这些实例并联电耦接,并且与其中使用器件区120的一个大实例的情况相比,这种构造向屏蔽电极124的中心和栅电极126的中心提供低电阻路径。图15示出了设置在半导体芯片上的半导体器件200的顶部示意平面图。器件200包括设置在底部器件区120B上方的顶部器件区120A、设置在顶部器件区120A上方的顶部连接区150(如先前描述的)、设置在器件区120B下面的底部连接区150、设置在器件区120A和120B之间的中间连接区250。器件区120A和120B是先前描述的器件区120的实例。存在在每个连接区150中的栅极流道和屏蔽流道,以及在中间连接区250中的两个栅极流道和一个屏蔽流道。栅极流道通过栅极馈送(gate feed)而电耦接至栅极焊盘212。源极金属层110设置在器件区120A和120B上方,电耦接至屏蔽流道和两个源极焊盘111。多个交错沟槽122′和平台130′设置在半导体外延层中,并且在器件区120A、120B和连接区150、250内,如通过在图右侧处的短划线示出的。为在在图中视觉上清晰,仅示出了前几个沟槽和平台,但在阵列左边的箭头符号示意地表示交错沟槽和平台的阵列延伸到器件区120A、120B和连接区150、250的左侧。沟槽122′与沟槽122基本相同,除了它们连续伸展通过器件区120A、120B和连接区150、250之外。平台130′与平台130基本相同,除了它们连续伸展通过器件区120A、120B和连接区150、250之外。沟道截断环结构在芯片周边处围绕区域120A、120B、150和250,并通过间隙与区域120A、120B、150和250分隔开。这种间隙与在图11中示出的间隙相同。
图16示出了沿图15中示出的切割线16-16,连接区250的剖面图。该剖面沿沟槽122′截取。组件与参考图10在上面描述的组件相同,只是在该图左侧出现的栅电极126、栅极上升部126R和栅极流道的镜像组(mirror set),不存在介电贴片123C和介电侧123S,并且沟槽122′、介电层123′、屏蔽电极124′和屏蔽上升部124R′镜像到左侧并沿剖面从左到右伸展。栅极流道与栅电极126的栅极上升部126R形成电接触,但与屏蔽金属流道以及屏蔽上升部124R′和屏蔽电极124′电绝缘。屏蔽流道金属与屏蔽上升部124R′和屏蔽电极124′形成电接触,但与栅极流道、栅极上升部124R和栅电极124电绝缘。以上沟槽构造消除了在紧接连接区150中的沟槽中断的器件100的平台区中发生的电场和电位不平衡,并因此消除相应的局部化电荷不平衡。这种构造背离了在连接区205的中部包括复杂场终止结构的现有技术构造。
图17示出了沿图15中示出的切割线17-17,连接区250的剖面图。该剖面沿平台130′截取。组件与参考图10在上面描述的组件相同,除了在图左侧出现的p掺杂阱134、栅电极126、栅极上升部126R和栅极流道的镜像组之外。屏蔽电极124′和栅电极125的位置的轮廓用短划线示出。类似于器件100,每个p掺杂阱134典型地电耦接至源极和屏蔽的电位,但对于其中该区域用于场终止区中的一些情形可以处于浮置状态。每个P掺杂阱134都具有优选在导电上升部126R(是导电迹线)处或下方终止的末端。存在由于曲率半径效应引起的在每个p掺杂阱134末端处发生击穿的可能性。然而,设置在p掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗与阱134末端相邻的每个n掺杂平台130的部分,由此显著减小阱134末端周围的电位和电场。然而,减小量的电场仍在阱134的末端周围存在,并且能够以径向方式(即,曲率半径效应)在阱134的末端处集中。然而,利用图17中示出的构造,阱134的末端基本上由栅极上升部126R屏蔽,并且该构造基本减小在区域末端处的曲率半径效应(如先前参考图11的器件100描述的)。如果阱134的末端延伸超过设置在它上面的导电上升部126R下部的远侧,那么将会丧失这种屏蔽。如果阱134的末端不延伸超过导电上升部126R下部的远侧,并进一步与导电上升部126R下部最远侧间隔开等于或大于阱134深度的距离L2,那么获得最佳的这种屏蔽效应。在优选的实施中,L2等于或大于阱134的深度加上在阱134和导电上升部126R之间的分隔距离,其中该分隔距离等于用于该图中示出的构造的氧化物层106的薄部分。
图18示出了连接区250的一种变形250′的剖面图,其包括设置在外延层(epi layer)104中并在屏蔽流道金属下面的电浮置p掺杂阱134C。(该p掺杂区通过在它和适合从外部电路接收电位的导电层之间不形成直接电连接而使其浮置。)浮置p掺杂阱134C充当在外延层104和在它上面的氧化物层106的部分之间的缓冲屏蔽。由于屏蔽流道金属通常处于接地电位并且外延层104的下面部分通常处于漏极电位,所以在屏蔽流道金属和外延层104之间的氧化物层106的部分能够经受高电场。为了减小在p掺杂阱134C的末端处的曲率半径效应,这些末端可以设置在栅极上升部126R附近或下面。
图19示出了连接区250的另一种变形250″的剖面图,其包括连续p掺杂阱134′代替图17中示出的两个阱134。连续p掺杂阱134′从器件区120A延伸到器件区120B,并穿过连接区250″,并电耦接至源极金属层110(又耦接至屏蔽流道金属)。因为阱134′没有侧边缘或角,所以没有与连续p掺杂阱134′相关的曲率半径效应。连续p掺杂阱134′也充当在外延层104和它上面的氧化物层106之间的缓冲屏蔽。如上面指出的,由于屏蔽流道金属通常处于接地电位并且外延层104的下面部分通常处于漏极电位,所以在屏蔽流道金属和外延层104之间的氧化物层106的部分能够经受高电场。
在举例说明连接区150、250、250′和250″的所有实施方式中,可以理解,每个连接区都具有产生无源器件的带有平台130、130′的相邻部分的一个以上的材料体(material body)的构造,其平台。材料体可以包括掺杂区、介电层、导电层等。相反,每个器件区120、120A、120B具有产生有源器件的带有平台130、130′的部分的一个以上材料体的构造平台。
现在参考图20中示出的半导体器件300描述并举例说明另一个实施方式。半导体器件300具有与图1-3中示出的半导体器件100基本相同的平面图(俯视图)。图20是沿半导体器件300的芯片的左侧部分的放大图,类似于图3中示出的器件100的左侧部分的放大图。半导体器件300包括以基本相同方式设置的与器件100基本相同的元件,并进一步包括环绕在先前描述的沟槽122、222和平台130、230的阵列。图21和图22示出了沿阵列的底部,并沿图20中示出的切割线21-21和22-22,周边沟槽(perimeter trench)320与沟槽122、222和平台130、230的阵列的剖面。周边沟槽320包括内衬它的相对侧壁的介电层321,以及设置在沟槽中的导电电极324。导电电极324可以电耦接至导电层,例如屏蔽流道,从而接收接地电位,或可以与带有电位的任何导电层去耦接,由此处于浮置电位。周边屏蔽320与沟槽222隔开在相邻沟槽122之间的间隔数量级的距离。间隙区(gap region)330设置在周边屏蔽320和沟槽222之间。没有电位通过任何导电层耦接至间隙区330的顶部,并且间隙区330中的电位是浮置的。当周边沟槽电极324处于浮置电位时,在它和浮置间隙区330上的电位能够浮置从而设定关于漏极电位的平衡电位(补偿电位,equalizing potential),并能够由此减小对间隙区330中的电荷不平衡的敏感度。因此,变得比如果这些间隙区330通过常规接地p阱固定在源极电位处更容易在间隙区330中实现电荷平衡条件。当周边沟槽电极324耦接至接地电位时实现基本相同的益处。间隙区330的宽度可以等于或小于平台130宽度的1.25倍,并且沿周边沟槽320各个侧面的间隙区330的宽度可以不同。例如,沿周边沟槽320(以及沟槽122和平台130的主阵列)左右竖直侧的间隙区330的宽度可以小于沿周边沟槽320(以及该主阵列)顶部和底部水平侧的间隙区330的宽度。
图23和图24是示出了沿主沟槽122和平台130的末端,并沿图20中示出的切割线23-23和24-24,周边沟槽320的剖面图。图23和图24的剖面基本上与对于器件100的图10和图11的剖面相同,加上添加了周边沟槽320和间隙区330。元件102-107、120、122、123、123C、123S、124、124R、125、125C、125S、126、126R、134、150、屏蔽流道、栅极流道和沟道截断环具有关于彼此的相同的相对关系。如上面指出的,由于曲率半径效应引起的击穿的一个可能区域,特别是对于高电压器件,存在于在屏蔽上升部部分124R的末端处的介电侧面层123S中,如图23中通过点“A”指示的(与图10相同)。如先前描述的,通过在介电侧面层123S上方并以距离L1超过沟槽122的末端延伸顶侧屏蔽流道金属(其为导电迹线),能够显著减少这种可能的击穿区域。距离L1可以等于或大于沟槽122的深度。周边沟槽320还通过移动电场远离点A而减轻可能的击穿区域。如上面指示的,当周边沟槽电极324处于浮置电位时,在它和浮置间隙区330上的电位能够浮置从而设定关于漏极电位的平衡电位,并能够由此减小对间隙区330中电荷不平衡的敏感度。因此,变得比如果这些间隙区330通过常规接地p阱固定在源极电位下更容易在间隙区330中实现电荷平衡条件。当周边沟槽电极324耦接至接地电位(这可以通过设置在屏蔽电极324和屏蔽流道金属之间的导电材料的接触通孔(contact via)325来完成)时实现基本相同的益处,其中接触通孔325电耦接至屏蔽流道和屏蔽电极324二者。
相同的以上益处能够通过在浮置间隙区330中使用浮置p掺杂阱334基本实现。这种实施方式通过图25-28举例说明,除了添加了浮置p掺杂阱334之外,其与图21-24中的剖面相同。没有接地电位电压耦接至阱334。图29示出了设置在沟槽222和周边沟槽320之间的在间隙区330的部分中的浮置p掺杂阱334。阱334左延伸至与周边沟槽320相邻。尽管阱334已经作为与周边沟槽320相邻设置的连续条示出,但可以理解,阱334可以是分段的(在连续条带中具有间隙)。阱334的任何分段区的末端可以设置在屏蔽流道和其它导电迹线下面,以最小化曲率半径效应。
当使用具有接地或浮置电极324的周边沟槽320时,在周边沟槽320的角转向(corner turn)处可存在电荷不平衡。这是因为间隙区330经历周边沟槽320的两个侧面而不是一个,如在图30的放大俯视图中示出的。周边沟槽的电极324试图消耗尽比间隙区330的转角区中存在的电荷更多的电荷。这种电荷不平衡能够通过缩短与周边沟槽320的水平支柱相邻的沟槽222的长度而得到解决。这作为器件400提供,其除了缩短沟槽之外,与器件300相同。沟槽222的缩短减小了沟槽222在间隙区300转角上的电荷成像效应,并由此补偿周边沟槽的电极324的过度成像。图31示出了缩短的沟槽222的剖面,连同未缩短长度的轮廓以进行比较。沟槽222的末端比沟槽122的末端与周边沟槽320隔得更远。器件300的p型阱334可以添加到具有器件400,其中器件400具有以上描述的的构造的任一种。器件400的p型阱334可以处于浮置电位或处于固定电位(例如,接地电位)。
图32示出了根据本发明的包括数个特征的另一示例性半导体器件500的俯视图。器件500包括位于在芯片中部的有源器件区120,如前面所述参照器件100,以及如上所述的源极金属层110、源极焊盘111、栅极焊盘112、连接区150。不失一般性,器件区120可实现一个竖直的、沟槽屏蔽的功率MOSFET器件。如下面更详细描述和示出的,该示例性MOSFET器件包括与平台(mesa)阵列交错的沟槽阵列、设置在沟槽底部中的绝缘屏蔽电极(shield electrode)、设置在屏蔽电极上方的沟槽中的绝缘栅电极(gate electrode)、设置在平台中的源极区(source region)、设置在源极区上的源电极(source electrode)、以及设置在半导体器件背侧处的漏电极(drain electrode)。各个源极焊盘111和栅极焊盘适合接收外部连接,例如提供源极电位的焊线(wire bond)或焊料凸点(solder bump),并在每侧上可以具有150微米的尺寸。
沟道截断环(channel stopper)设置在芯片周边处或附近,并通过间隙与屏蔽流道和器件区120顶部部分隔开。沟道截断环是常规的,并且可以包括遮盖且接触一条掺杂半导体区的金属的隔离环(isolated ring),其围绕芯片周边形成一个环。必需注意,器件100、器件500不包括在这种间隙中通常出现的常规场终止结构(field termination structure)。在有源区120中的器件500的剖面、连接区150、左右无源区、上方无源区可以与示于器件100及其在图5-14中的各种变型的那些基本相同。
作为与器件100的不同,器件500包括设置在栅极焊盘下方的多个沟槽522、522′、522″以及平台530、530′、530″,左右栅极流道,以及顶部屏蔽流道,如图中所示。通常,沟槽522和平台530不延伸到器件区120中至任何明显的程度(器件区120的顶部边缘可以覆盖沟槽522中的一个)。沟槽522、522′、522″可以具有如上所述沟槽122、220、222相同的构造,或者其更改的构造,平台530、530′、530″可以是为未掺杂的,或者掺杂以具有类似于平台130的阱区。如下文更详细的描述,各个沟槽522、522′、522″可以具有电浮置的或电耦接至源极焊盘111(例如接地)的屏蔽电极。各个沟槽522、522′、522″可以包括栅极电极,或者可以不包括栅极电极。类似地,各个平台530可以是电浮置的或电耦接至源极焊盘111(例如接地)。源极金属层110可以包括源极金属延伸部110a和110b,其在栅极焊盘112的任意侧上向下延伸,可以选择性耦接至各种沟槽522、522′、522″以及平台530、530′、530″以提高至其的接地电位。沟槽522、522′、522″以及平台530、530′、530″有助于在器件区120的底部边缘形成电场,从而有助于控制器件500的击穿电压特性。沟槽522、522′、522″以及平台530、530′、530″还有助于栅极焊盘与施加于在器件500的底部表面的漏极的电压屏蔽,从而减少在器件的栅极和漏极电极之间的电容。屏蔽的量可以通过以下选择:沟槽522、522′、522″以及平台530、530′、530″的构造,改变这些浮置或接地状态的沟槽和平台的量,如下更具体描述的。
图33是沿图32所示剖面线33-33的器件500部分的剖视图。剖面穿过在栅极焊盘112和邻近栅极焊盘112设置的屏蔽流道。器件500包括N+掺杂半导体衬底102、设置在半导体衬底102上的一个或多个外延生长半导体n型层104(“外延半导体层”)、设置在无源和第一场终止区中的外延半导体层104上方的氧化物层106、设置在氧化物层106上方的介电层107。栅极焊盘112和屏蔽流道设置在介电层的上方。作为示例性制造工艺的制造,并不是对器件500的构造的限制,氧化物层106在栅极焊盘112下方的“D”点终止。该点大致对应于源极延伸部110a和110b的下端,在图32标注。
器件500进一步包括设置在外延半导体层中的多个沟槽522、522′、522″,以及如图33所示设置的交错在沟槽522、522′、522″之间的多个半导体材料的平台530、530′、530″。沟槽522具有类似于沟槽122(图6-7中所示)的构造,具有:衬有介电层523的相对侧壁、设置在沟槽底部附近的侧壁之间的屏蔽电极524、设置在屏蔽电极524上方的介电层525、以及设置在介电层525上方且在沟槽侧壁之间的第二电极526(其包括栅电极)。沟槽522′有类似于沟槽222(图6-7中所示)的构造,具有:衬有介电层523′的相对侧壁、设置在沟槽底部附近的侧壁之间的屏蔽电极524、设置在屏蔽电极524上方的介电层525、以及设置在介电层上方且在沟槽侧壁之间的栅电极526。然而,不同于沟槽522的介电层523,如沿着栅电极526′的深度测量时,介电层523′沿着面对终止边缘的侧壁的厚度比沿着面对沟槽522的侧壁的厚度更厚。在图中通过标号527表示较厚区。较厚的电介质527减小介电层中的电场,并由此增大它的击穿电压。沟槽522′可以具有与各个沟槽522相同的宽度,并且栅电极526′可以具有小于沟槽522的栅电极526的宽度。沟槽522″具有类似于沟槽220(图6-7中所示)的构造,具有衬有介电层523″的相对侧壁、设置在侧壁之间(优选从外延半导体层104顶部到沟槽底部附近)的屏蔽电极524″。各个屏蔽电极524、524″可以是电浮置的或电耦接至源极金属层110。各个栅电极526、526′可以是电浮置的,或电耦接至栅极焊盘112,或电耦接至源极金属层110。沟槽522″提供对沟槽522和522′的漏极电位的附加屏蔽。
各个平台530设置在两个相邻的沟槽522和522′之间,并可以包括设置在与层104顶面相邻的外延半导体层104中的p型阱534。平台530′设置在沟槽522′和522″之间。p-掺杂区539可以包括平台530′,或省略。还有,p掺杂阱534可以设置在平台530′中,阱从沟槽522′延伸到沟槽522″。各个平台530″设置在两个相邻的沟槽522″和522′之间。p掺杂阱534可以被包括在各个平台530″中,或省略,如图33所示。如下所述,各个阱534可以耦接至源极层110的电位,或者可以电隔离并为电浮置状态。可以对平台530、530′、530″的宽度选择使得在上述电荷平衡条件下,在平台中的n型区为被电极524、524′、524″耗尽电子(例如载流子)。如上所述,当平台宽度和平台的N漂移区132的掺杂的乘积在1×1011cm-2到1×1013cm-2范围内时,通常能够实现电荷平衡条件。如上所述,有源区的平台130通常设计成提供该条件。典型地,平台530、530′、530″的电荷平衡条件通过选择平台530、530′、530″的宽度等于或小于器件区120的平台130的宽度的1.25倍来实现。如果平台530″被构造成处于电荷平衡条件且不具有p掺杂阱534,它将处于电浮置状态。
如上所述,沟槽522、522′、522″、栅电极526、526′和平台530、530′、530″可以分别构造成处于电浮置状态,或电耦接至电位。其示例性构造示于以下描述的序列剖面。
图34示出了沿图32所示切线34-34的上述沟槽和平台的剖视图。在这该区域,源极延伸部110a叠置在沟槽522、522′和平台530上方,通孔绝缘层106-107形成至各个平台530的中部以允许源极延伸部110a电接触至在高p型掺杂的小区域535的各个p阱534。部分的介电层107覆盖沟槽522的顶部。这种构造将p阱534和平台530的顶部电耦接至源极金属层110的电位(例如接地)。如果平台530及其阱534旨在构造成浮置状态,那么不形成上述通孔,剖面看起来像图33所示那样,只不过栅极流道和源极延伸部110a代替栅极焊盘112。前述高掺杂的通孔和区535可以用与在器件区域中用于形成p+区135和源极金属110至阱134的通孔相同的制造工艺进行,如图6所示和如上所述。如果该示例性工艺用于在图34中所示的剖面的区域,类似于源极区136(如图6中所示)的源极区636可以设置在最右边的阱区534,作为示例性制造工艺的制造品。源极区636不妨碍在源极延伸部110a与阱534之间的电接触,它们在源极延伸部110a和110b下方的产生小有源器件。如果需要,源极延伸部的宽度可以通过在栅极焊盘112的一侧或两侧将其延伸而加宽以增加器件的有源区。最左边的阱534不具有源极区636,并构造为反向偏压p-n二极管。如果需要,示例性工艺的掩模可以容易地更改为省略在源极延伸部110a和110b下方的源极区636。如果栅电极526和526′要耦接至源极金属层110(例如“接地的”),光掩模可以容易地更改为去除层106和107位于栅电极上方的部分,使得源极流道110a和110b可以电接触栅电极。
图35示出了沿图32所示切线35-35的沟槽522、522′、522″以及平台530、530′、530″的剖视图。在该区域,栅电极526和526′的顶部通过导电上升部126R电耦接在一起,其参照器件100如上所述。导电上升部126R通过设置在平台530上方的氧化物层106′与平台530电隔离。导电上升部126R又电耦接至栅极流道和栅极焊盘112,如图35和32所示,参照器件100如上所述。在典型的实施方式中,上升部126R和栅电极526和526′由相同的材料形成,如多晶硅。在一些实施方式中,如上所述,在沟槽522上方的电介质107的岛可以省略。如果栅极526或526′打算构造为浮置状态或接地到源极金属110,那么不进行上述与栅极上升部电连接,剖面看起来像如图33中所示的那样,只不过栅极流道代替了栅极焊盘112。用于限定上升部126R的光刻胶掩模可以容易地更改以便不进行连接。
如36示出了沿图32所示切线36-36的沟槽522、522′、522″以及平台530、530′、530″的剖视图。在该区域,屏蔽流道叠置在沟槽522、522′、522″以及平台530、530′、530″的上方。如图中所示,从屏蔽流道至沟槽522、522′、522″的屏蔽电极524和524′的接触通过经由介电层107和氧化物层106形成的通孔(例如,接触开口)制成。该构造通过屏蔽流道将屏蔽电极524和524′电耦接至源极金属层110,以及耦接至在源极焊盘111接收的电位(例如,接地)。通过不形成在屏蔽流道和屏蔽接触之间的通孔,各个屏蔽电极524和524′可以置于电浮置状态。需要时用于限定通孔的光掩模可以容易地更改为省略通孔。应当注意,阱534和掺杂区539没有出现在剖面中,因为这些区域在到达屏蔽流道的中点之前已经终止,如在图11-13所示的器件100的构造和前面所述的那样。
浮置的沟槽522、522′、522″和浮置的平台530、530′、530″产生在栅极焊盘112和在衬底背侧的漏电极之间的浮置电位屏蔽,这通过电容分隔作用减少了在栅极焊盘112和漏电极之间的电容。在该构造中,浮置沟槽和浮置平台没有显著影响在栅极焊盘112和源极焊盘111之间的电容。另一方面,使用“接地的”沟槽522、522′、522″和“接地的”平台530、530′、530″将在栅极焊盘112和漏电极之间的电容减少至显著更大程度,因为这些结构提供了栅极焊盘112和漏电极之间的固定电位屏蔽,基本没有电容分隔作用发生。然而,该构造显著增加了在栅极焊盘112和源极焊盘111之间的电容。不同的电路应用通常受益于上述电容的不同比率,从而可以调节浮置沟槽/平台和“接地的”沟槽/平台的混合以提供所需的比率,而同时防止在栅极焊盘112下方的区域中发生雪崩击穿。通常,接地的沟槽/平台邻近器件区120设置,浮置沟槽/平台设置在栅极焊盘112的外边缘,因为接地的沟槽/平台的电结构比浮置沟槽/平台的结构更类似于器件区120的沟槽和平台的电结构。
对于其中平台具有耦接至源极金属层110(例如,“接地的”)的阱534、和其中沟槽522构造成像沟槽122的区域,击穿特性与器件区120中的那些基本相同。对于其中平台具有耦接至源极金属层110(例如,“接地的”)的阱534、和其中沟槽522′耦接至源极金属层110的区域,必须调节(例如缩小)沟槽之间的间隔距离以在平台中提供良好的电荷平衡条件(例如耗尽电子)。该调节使得击穿电压特性与在器件区120中的基本相同或比其更好。这样的调节可以由本领域技术人员使用计算机模拟或参数试验结构进行。对于其中平台是浮置的(有或没有阱534)的区域,几乎没有击穿的风险。然而,在浮置区中的电位分别可以影响使用接地的沟槽和平台的相邻区域,应该调整(例如,缩小)在浮置的沟槽和平台之间的间隔距离以提供浮置平台的良好电荷平衡条件,以便在相邻区域中形成电位分布。
图37-39示出了根据本发明的包括数个特征的另一示例性半导体器件600的各种剖面图。器件600具有如图32所示器件500的相同俯视图,并且与器件500基本相同,只不过包括了一些附加的特征。因此,只要其与器件600的以下描述不冲突,器件500的以上描述就应用于器件600。图37示出了在图32中示出的沿着线33-33获得的剖面图。作为第一个特征,器件600包括器件500相同的元件加上在外延层104的顶部表面的平台530″中设置的多个p掺杂导电区634。区634可以包括比阱534更深的阱,但是其具有的掺杂水平与阱534相当(例如,在阱534的掺杂的0.5倍至2倍的范围内),以实现良好的电荷平衡条件。作为用于制作区域634的示例性制造工艺的结果,第一p型尾部区639A形成在最左的沟槽522″和最左的区域634的左侧,第二p型尾部区639B形成在最右的沟槽522″和最右的区域634的右侧。第二尾部区639B与区域539结合,以在平台530′中形成连续的p型阱。如下所示,在平台530′中的阱电耦接至在该器件的另一剖面图的源极金属层110(例如“接地的”)。在该器件的另一剖面图中区域634和沟槽522、522′、522″也耦接至源极金属层110。第一尾部区639A置于电浮置状态。以器件500中的栅电极526和526′经由栅极上升部126R耦接至栅极焊盘112的相同的方式,栅电极526和526′耦接至栅极焊盘112,如图35所示。
图38示出了在图32中所示的线34-34获取的器件600的剖面图,其中源极延伸部110a叠置在沟槽522、522′和平台530的上方。除以下外该剖面图与器件500相同:添加区域634、639A以及639B,添加在源极延伸部110a与通过区域639B和539的结合形成的阱之间的电接触部。该电接触部包括在结合的区域中高p型掺杂的小区域535以及经由绝缘层106-107并至在平台530′的中心线处的p型区535形成的小通孔,其允许源极延伸部110a电接触至各个p型区539和639B。
图39示出了在图32示出的沿线36-36获取的器件600的剖面图,其中屏蔽流道叠置在沟槽522、522′、522″和平台530、530′、530″的上方。除了以下外该剖面图与器件500的相同:介电层106和107的一些岛被去除,以便屏蔽流道能够电接触至平台530″顶部的p型区域634。如果平台宽度和沟槽宽度足够大,那么至沟槽和平台的接触可以经由分开的通孔进行(例如,经由单独的通孔而不是单个通孔)。
对于器件600的构造,设置在栅极焊盘112下方的沟槽和平台电耦接至源极层110,从而将栅极焊盘112的全部区域与在芯片背部表面的漏电极屏蔽。这显著减少了器件的栅极-漏极电容,但增加了栅极-源极电容。
尽管用n型外延层和p型掺杂阱区说明上面的实施例,但可认识到本发明和实施方式可用p型外延层和n型掺杂阱区实施。即,本发明和实施方式可用颠倒的层和区域的掺杂极性实施。
尽管本发明的各种实施例在上下文中大多以N沟道屏蔽栅极MOSFET描述,但这些实施例可在各种其它类型的器件中实施,例如P沟道MOSFET(即,除全部硅区域的导电型颠倒之外结构相似于在上面描述的MOSFET的晶体管);N沟道屏蔽栅极IGBT(即,除使用P型衬底替代N型衬底之外结构相似于在上面描述的MOSFET的晶体管);N沟道屏蔽栅极IGBT(即,结构相似于在上面描述的MOSFET,但除衬底保持N型之外具有相反导电性的硅区的晶体管);屏蔽栅极同步整流管(即,集成屏蔽栅极MOSFET和肖特基);TMBS整流管,以及上面器件的超结变更(即,具有交替导电型硅的列的器件)。
“一”、“一个”和“该”的任何叙述希望意为一个或更多,除相反特殊表示之外。
在此采用的术语和措辞用作描述的术语并且不用作限制的术语,并且没有在使用这样的术语和措辞中排斥示出和描述特征的等效的意图,认可在要求的本发明范畴内各种修改是可能的。
此外,本发明一个或更多实施例的一个或更多特征可与本发明其它实施例的一个或更多特征结合,而不背离本发明的范畴。
尽管本发明关于说明的实施例特别描述,但认识到各种替换、修改、适应和等效安排可基于本公开做出,并且希望在本发明和权利要求的范畴之内。
Claims (32)
1.一种半导体器件,包括:
第一多个平行沟槽,在半导体区中延伸,各个沟槽具有竖直堆叠其中的屏蔽电极和栅电极,所述屏蔽电极和栅电极彼此电绝缘;
第一焊盘,适于接受第一外部连接,并电耦接至所述第一多个平行沟槽的所述屏蔽电极;
第二焊盘,适于接受第二外部连接;
导电迹线,电耦接至第二焊盘和所述第一多个平行沟槽的至少一个沟槽的所述栅电极;
第二多个平行沟槽,在半导体区中延伸并设置在所述第二焊盘和所述导电迹线中的至少一个的下方,所述第二多个平行沟槽的各个沟槽具有设置在其中的第一电极。
2.根据权利要求1所述的半导体器件,其中,所述第二多个沟槽中的至少一个沟槽的第一电极包括电耦接至所述第一焊盘的屏蔽电极。
3.根据权利要求2所述的半导体器件,所述第二多个沟槽中的所述至少一个沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和栅电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
4.根据权利要求1所述的半导体器件,其中,所述第二多个沟槽中的至少一个沟槽的第一电极是电浮置的。
5.根据权利要求4所述的半导体器件,其中,所述第二多个沟槽中的所述至少一个沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
6.根据权利要求1所述的半导体器件,其中,所述第二多个沟槽中的至少一个沟槽的第一电极包括电耦接至所述第一焊盘的屏蔽电极;
并且
其中,所述第二多个沟槽中的至少另一个沟槽的所述第一电极是电浮置的。
7.根据权利要求1所述的半导体器件,进一步包括交错在所述第二多个平行沟槽之间的半导体材料的多个平台,其中至少一个平台是电浮置的。
8.根据权利要求7所述的半导体器件,其中,电浮置的所述至少一个平台的任一侧上的沟槽具有电浮置的第一电极。
9.根据权利要求7所述的半导体器件,其中,电浮置的所述至少一个平台的任一侧上的沟槽具有电耦接至所述第一焊盘的第一电极。
10.根据权利要求1所述的半导体器件,进一步包括:
交错在所述第一多个平行沟槽之间的半导体材料的第一多个平台,所述第一多个平台具有最大宽度;以及
交错在所述第二多个平行沟槽之间的半导体材料的第二多个平台,所述第二多个平台中的各个平台具有的宽度等于或小于所述第一多个平台的所述最大宽度的1.25倍。
11.根据权利要求1所述的半导体器件,其中所述第二多个平行沟槽中的至少一个沟槽设置在所述第二焊盘的下方,其中所述第二多个沟槽的至少另一个沟槽设置在所述导电迹线的下方。
12.根据权利要求1所述的半导体器件,进一步包括:
交错在所述第一多个平行沟槽之间的半导体材料的第一多个平台;
交错在所述第二多个平行沟槽之间的半导体材料的第二多个平台;以及
设置在半导体区中的第一导电型的多个阱区,各个阱设置在所述第二多个平台的相应平台中并在所述第二多个平行沟槽的相邻沟槽之间。
13.根据权利要求12所述的半导体器件,其中,至少一个阱区是电浮置的。
14.根据权利要求13所述的半导体器件,其中,与所述至少一个阱相邻设置的沟槽的所述第一电极电耦接至所述第一焊盘。
15.根据权利要求14所述的半导体器件,其中与所述至少一个阱相邻设置的所述沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
16.根据权利要求13所述的半导体器件,其中,与所述至少一个阱相邻设置的所述沟槽的第一电极是电浮置的。
17.根据权利要求13所述的半导体器件,其中,与所述至少一个阱的第一侧相邻设置的第一沟槽的所述第一电极电耦接至所述第一焊盘,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的所述第一电极电耦接至所述第一焊盘。
18.根据权利要求17所述的半导体器件,其中,与所述至少一个阱相邻设置的所述沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
19.根据权利要求13所述的半导体器件,其中与所述至少一个阱的第一侧相邻设置的第一沟槽的所述第一电极是电浮置的,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的所述第一电极是电浮置的。
20.根据权利要求13所述的半导体器件,其中,与所述至少一个阱的第一侧相邻设置的第一沟槽的所述第一电极电耦接至所述第一焊盘,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的所述第一电极是电浮置的。
21.根据权利要求20所述的半导体器件,其中所述第一沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
22.根据权利要求12所述的半导体器件,其中所述第一多个平台具有最大宽度,所述第二多个平台中的各个平台具有的宽度等于或小于所述第一多个平台的最大宽度的1.25倍。
23.根据权利要求12所述的半导体器件,其中,至少一个阱区电耦接至所述第一焊盘。
24.根据权利要求23所述的半导体器件,其中,与所述至少一个阱相邻设置的沟槽的所述第一电极是电浮置的。
25.根据权利要求23所述的半导体器件,其中与所述至少一个阱的第一侧相邻设置的第一沟槽的第一电极是电浮置的,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的所述第一电极是电浮置的。
26.根据权利要求23所述的半导体器件,其中与所述至少一个阱相邻设置的所述沟槽的第一电极电耦接至所述第一焊盘。
27.根据权利要求26所述的半导体器件,其中,与所述至少一个阱相邻设置的所述沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
28.根据权利要求23所述的半导体器件,其中与所述至少一个阱的第一侧相邻设置的所述第一沟槽的第一电极电耦接至所述第一焊盘,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的第一电极电耦接至所述第一焊盘。
29.根据权利要求28所述的半导体器件,其中,与所述至少一个阱相邻设置的所述沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
30.根据权利要求23所述的半导体器件,其中与所述至少一个阱的第一侧相邻设置的第一沟槽的所述第一电极电耦接至所述第一焊盘,其中与所述至少一个阱的第二侧相邻设置的第二沟槽的所述第一电极是电浮置的。
31.根据权利要求30所述的半导体器件,其中所述第一沟槽进一步包括竖直堆叠在该沟槽的屏蔽电极上的栅电极,所述屏蔽电极和第二电极彼此电绝缘,所述栅电极电耦接至所述第二焊盘。
32.根据权利要求26所述的半导体器件,其中,所述第一多个平台具有最大宽度,所述第二多个平台中的各个平台具有的宽度等于或小于所述第一多个平台的所述最大宽度的1.25倍。
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KR (3) | KR101773159B1 (zh) |
CN (1) | CN102246306B (zh) |
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CN102246306B (zh) | 2014-12-10 |
TWI501392B (zh) | 2015-09-21 |
US20180012958A1 (en) | 2018-01-11 |
KR20170103015A (ko) | 2017-09-12 |
US9293526B2 (en) | 2016-03-22 |
US20100140695A1 (en) | 2010-06-10 |
KR101892201B1 (ko) | 2018-08-27 |
US8304829B2 (en) | 2012-11-06 |
WO2010077510A3 (en) | 2010-08-26 |
DE112009004071T5 (de) | 2012-06-28 |
US10868113B2 (en) | 2020-12-15 |
KR20160106195A (ko) | 2016-09-09 |
TW201029176A (en) | 2010-08-01 |
US9748329B2 (en) | 2017-08-29 |
US20140048869A1 (en) | 2014-02-20 |
US20150206937A1 (en) | 2015-07-23 |
KR101773159B1 (ko) | 2017-08-30 |
KR20110098788A (ko) | 2011-09-01 |
KR101654250B1 (ko) | 2016-09-05 |
WO2010077510A2 (en) | 2010-07-08 |
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