CN102074516B - 半导体元件封装及其制作方法 - Google Patents

半导体元件封装及其制作方法 Download PDF

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CN102074516B
CN102074516B CN2010101947797A CN201010194779A CN102074516B CN 102074516 B CN102074516 B CN 102074516B CN 2010101947797 A CN2010101947797 A CN 2010101947797A CN 201010194779 A CN201010194779 A CN 201010194779A CN 102074516 B CN102074516 B CN 102074516B
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base plate
circuit base
opening
semiconductor element
connection pad
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CN102074516A (zh
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金锡奉
尹妍霰
李瑜镛
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Advanced Semiconductor Engineering Inc
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Abstract

本发明揭示一种具有电磁干扰屏蔽的半导体元件封装及其制作方法。在一实施例中，一种半导体元件封装包括一线路基板、一电子元件、一封装胶体以及一导电层。线路基板包括一承载面、一底面以及一接垫，其中底面相对于承载面。电子元件邻近承载面并电性连接至线路基板。封装胶体邻近承载面并包覆电子元件。封装胶体包括一中心部与一围绕中心部的周边部，其中周边部的厚度小于中心部的厚度，且形成在周边部的一开口暴露出接垫。导电层共形地覆盖封装胶体，并穿过开口以连接至接垫。本发明的半导体元件封装可增加切割工艺产量，可有效地加强封装结构的电磁干扰屏蔽的效果，并可增加封装结构的可靠度。

Description

半导体元件封装及其制作方法
技术领域
本发明涉及一种半导体元件封装及其制作方法，且特别是涉及一种具有电磁干扰屏蔽(electromagnetic interference shielding)的半导体元件封装及其制作方法。
背景技术
半导体元件日益复杂，而至少部分的原因是源于使用者对于增加处理速度(processing speed)与缩小元件尺寸的需求。虽然增加处理速度与缩小元件尺寸的好处相当显著，但是这些半导体元件的特性亦会产生问题。特别是，较高的时脉速度(clock speed)会使信号准位(signal level)转换的频率增加，以致于频率较高或波长较短的电磁发射(electromagnetic emission)强度增加。电磁发射可从一源半导体元件(source semiconductor device)辐射出并入射邻近的半导体元件。若是对邻近的半导体元件的电磁发射强度够高，则电磁发射会不利于(邻近的)半导体元件的运作。此现象有时被称为电磁干扰(electromagnetic interference，EMI)。尺寸较小的半导体元件会使电磁干扰的问题更加严重，因为这些(尺寸较小的)半导体元件会以较高的密度配置于一电子系统中，以致于邻近的半导体元件接收到较强且不希望得到的电磁发射。
减少电磁干扰的一种方法是在半导体元件封装中屏蔽一组半导体元件。特别是，可通过在封装体外部加装接地的导电罩体(casing)或是导电壳体(housing)来达到屏蔽的效果。当由封装体内部辐射出的电磁发射撞射到罩体的内表面时，至少部分的电磁发射被电性短路，以降低可穿透罩体且不利于邻近的半导体元件的电磁发射强度。相同地，当由邻近的半导体元件辐射出的电磁发射撞射到罩体的外表面时，会发生相似的电性短路以降低封装体中的半导体元件所受到的电磁干扰。
虽然导电罩体可减少电磁干扰，但是使用导电罩体会有许多缺点。特别是，罩体一般是通过粘着剂而固定在半导体元件封装的外部。不幸的是，由于粘着剂的接合性会受到温度、湿度以及其他环境因素的影响而降低，因此，罩体容易剥离或脱落。而且，当将罩体固定至封装体时，罩体以及封装体的尺寸与形状需相互配合，且二者的配合度需在一较小的容忍范围内。使尺寸与形状能够相互配合，以及使罩体与封装体的相对位置具有一定的准确度会导致制作成本提高并耗费工艺时间。由于需要使尺寸与形状能相互配合，因此，不同尺寸与形状的半导体元件封装需要搭配不同的罩体，以容纳不同的封装体，而这会进一步地增加制作成本与时间。
克服前述背景中所提及的问题的半导体元件封装及其制作方法如下所述。
发明内容
本发明提供一种具有电磁干扰屏蔽的半导体元件封装及其制作方法。
本发明提出一种半导体元件封装包括一线路基板、一电子元件、一封装胶体以及一导电层。线路基板包括一承载面、一底面以及一接垫，其中底面相对于承载面。电子元件邻近承载面并电性连接至线路基板。封装胶体邻近承载面并包覆电子元件。封装胶体包括一中心部与一围绕中心部的周边部，其中周边部的厚度小于中心部的厚度，且形成在周边部的一开口暴露出线路基板的接垫。导电层共形地覆盖封装胶体，并穿过开口以连接线路基板的接垫。
在本发明的一实施例中，线路基板包括一侧面，侧面延伸于承载面与底面之间。封装胶体的周边部包括一侧面。周边部的侧面实质上与线路基板的侧面共平面。
在本发明的一实施例中，周边部的厚度实质上相等。
在本发明的一实施例中，导电层的厚度实质上相等。
在本发明的一实施例中，开口暴露接垫的一顶面，且导电层覆盖开口的一侧壁以及接垫的顶面。接垫可邻近线路基板的承载面。
在本发明的一实施例中，接垫配置于线路基板中，开口贯穿封装胶体的周边部以及线路基板，以及导电层覆盖开口的一侧壁以及连接接垫，接垫暴露于侧壁。接垫可邻近承载面或邻近底面。
在本发明的一实施例中，半导体元件封装还包括一填充物，其配置于开口中。
在本发明的一实施例中，接垫接地。
在本发明的一实施例中，开口包括一圆形孔洞、一线形开槽或是一环形沟槽。
本发明提出一种半导体元件封装的制作方法，包括：(1)提供一线路基板条，其中线路基板条包括一承载面、一底面以及一线路基板，底面相对于承载面；(2)配置一电子元件，电子元件邻近承载面，其中电子元件连接线路基板；(3)形成一封装胶体，封装胶体邻近承载面并包覆电子元件；(4)沿着线路基板的一边缘对封装胶体进行一半切切割工艺，以形成封装胶体的一周边部，周边部沿着线路基板的边缘延伸，其中封装胶体的周边部的厚度小于封装胶体的一中心部的厚度；(5)在周边部形成一开口，以暴露线路基板的一接垫；(6)形成一导电层，以共形地覆盖封装胶体，其中导电层通过开口而连接至线路基板的接垫。
在本发明的一实施例中，周边部的厚度实质上相等。
在本发明的一实施例中，半导体元件封装的制作方法还包括沿着线路基板的边缘对封装胶体的周边部进行一全切割工艺，以使线路基板与线路基板条的其他部分分离，并使周边部与封装胶体的其他部分分离。
在本发明的一实施例中，形成开口的方法包括激光钻孔。此外，接垫邻近线路基板条的承载面。导电层可覆盖开口的一侧壁与接垫的一顶面。
在本发明的一实施例中，形成开口的方法包括机械钻孔。此外，接垫配置于线路基板条的一内层中，且开口贯穿封装胶体的周边部以及线路基板条。导电层覆盖开口的一侧壁并连接暴露于侧壁的接垫。
在本发明的一实施例中，半导体元件封装的制作方法还包括在形成导电层之后填充开口，其中填充开口的方法包括电镀一金属材料或是印刷一非导电材料至开口中。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A～图1H绘示本发明一实施例的半导体元件封装的工艺示意图。
图2示范性地绘示图1E中的结构的立体图。
图3A～图3C绘示本发明一实施例的图1E的结构的局部俯视图。
图4A～图4D绘示本发明另一实施例的半导体元件封装的工艺中的某些步骤的示意图。
图5绘示本发明一实施例的半导体元件封装结构的剖面图。
图6绘示本发明另一实施例的半导体元件封装结构的剖面图。
附图标记说明
100、500、600：封装结构
102：线路基板条
110：线路基板
110a：承载面
110b：底面
112：接垫
112a、130a、134b：顶面
115：顶线路层
117a：第一内线路层
117b：第二内线路层
119、130b、136a、134a：侧壁(或侧面)
120：电子元件(或半导体元件)
130：封装胶体
132：中心部
134：周边部
136：开口
138：填充物
140：导电层
150：焊球
180：导电凸块
190：切割线
T1、T2：厚度
W1、W2、W3：宽度
具体实施方式
定义
下列的定义可应用在关于本发明的某些实施例的某些方面。在此将详述这些定义。
在此所使用的单词“一”与“该”可代表多个，除非上下文明显指出“一”与“该”代表单数个。因此，举例来说，当提到一接地元件时，可包括多个接地元件的情况，除非上下文明显指出“一”代表单数个。
在此所使用的词“组”代表一或多个元件的群体。因此，举例来说，一组膜层可包括单一膜层或多个膜层。一组的元件亦可代表该组的构件。一组的元件可以是彼此相同或彼此不同。在一些例子中，一组的元件可共有一或多个相同的特性。
在此所使用的词“邻近”代表接近或是邻接。邻近的元件可以是彼此分离或是彼此实质上接触或直接接触。在一些例子中，邻近的元件可彼此相连或是彼此为一体成型。
在此所使用的词例如“内”、“顶”、“底”、“上”、“下”、“向下”以及“横向”代表一组元件的相对方向(方位)，例如依照图所示，但是毋须以特定的方向制作或是使用这些元件。
在此所使用的词“连接”代表操作上的耦接(coupling)或是连接(linking)。连接元件可以是彼此直接耦接或是彼此间接耦接，例如通过另一组元件。
在此所使用的词“实质上”、“基本上”代表一可以考虑的程度或范围。当其与一事件或情况并用时，该词可代表该事件或情况准确发生的例子以及该事件或情况发生在一近似值的例子，例如计算此处所描述的工艺操作的一般容忍度。
在此所使用的词“导电的”代表一种传导电流的能力。导电材料一般是相当于表现出轻微或是无反抗电流流动的材料。导电率的单位为S·m-1(Siemens per meter)。通常，导电材料是导电率约大于104S·m-1的材料，例如至少约105S·m-1或是至少约106S·m-1。材料的导电率有时会随温度而变。除非有特别说明，否则都是指室温下的材料导电率。
本发明可用来制作多种封装结构，例如堆叠式封装(tacked typepackage)、多芯片封装(multiple-chip package)或高频率元件封装(highfrequency device package)。
图1A～图1H绘示本发明一实施例的半导体元件封装的工艺示意图。
请参照图1A，一线路基板条102具有多个线路基板110，线路基板110是由多条后续的切割线190(图1A中的虚线)所定义出来的，其中各线路基板110包括一承载面110a、一底面110b与一组接垫112(或是其他的接地元件)，接垫112连接至接地面或是任何其他功能的平面或是参考平面。各线路基板110也包括延伸于承载面110a与底面110b之间的一侧面，如图5、6所示(以下将会述及)。相同于线路基板110中的其他线路层，接垫112可以由金属(例如铜)构成。接垫112可位于线路基板110的任一线路层上，并与该线路层一体成型或是配置于该线路层中。在本实施例中，接垫112位于线路基板条102的承载面110a上，并与一顶线路层115一体成型。
请参照图1B，多个电子元件120(或半导体元件120)配置于承载面110a上，并分别以倒装接合的方式通过多个导电凸块180电性连接至线路基板110。在其他实施例中，电子元件120连接到线路基板110的方法可以是引线接合或是其他可行的连接方法。在此，电子元件120可为一芯片。电子元件120优选地是配置于线路基板110的一中心部之中。另外，本发明的实施例并不限定各线路基板110上所配置的电子元件120的数量。在本实施例中，各线路基板110接合有一电子元件120。然而，在其他实施例中，封装结构可包括各线路基板110上配置有多个电子元件120。
请参照图1C，进行一封胶工艺，以于线路基板条102上形成一封装胶体130，用以包覆芯片120、接垫112与各线路基板110的至少局部。封胶工艺例如为一覆盖成型工艺(over-molding process)。封装胶体130的材料例如为环氧树脂或是硅胶。
请参照图1D，在封装胶体130上沿着各线路基板110的边缘(例如沿着切割线190)进行一半切切割工艺(half-cutting process)，以移除部分的封装胶体130。特别是，半切切割工艺利用一切割工具(未绘示)部分切割封装胶体130，因此，可在各线路基板110的边缘上形成封装胶体130的一周边部134，其中周边部134的厚度T2小于封装胶体130的一中心部132的厚度T1。此外，周边部134的厚度T2实质上相等，也就是周边部134的一顶面134b实质上是平坦的。由于形成在两直接相邻的线路基板110边缘上的周边部134的厚度实质上相等，因此，可降低用以制作周边部134的半切切割工艺的复杂度。举例来说，以单一实质上水平的切割可制得横跨两直接相邻的线路基板110的顶面134b。
请参照图1E，在半切切割工艺之后，在周边部134上相对各线路基板110形成至少一开口136，以暴露出线路基板110的接垫112。
图2示范性地绘示图1E中的结构的立体图。如图2所示，多个开口136形成在封装胶体130中并围绕各芯片120。在本实施例中，是采用激光钻孔工艺(laser drilling process)。由于激光对于封装胶体130的切割速度远大于对于金属的切割速度，因此，激光钻孔工艺容易切穿封装胶体130，且当遇到接垫112时切割速度会显著降低或停止切割。因此，形成在封装胶体130的周边部134的激光开口136会暴露出线路基板110的承载面110a上的接垫112。虽然在此是采用激光钻孔工艺，但也可以采用其他可行的移除方法，例如化学蚀刻或机械研磨，且前述方法皆包含在本发明的范围中。
此外，为符合不同的需求，可改变开口136的形状以使其具有不同的外形(profile)。图3A～图3C绘示本发明一实施例的图1E的结构的局部俯视图。请参照图3A～图3C，其绘示具有不同外形的多个开口136，其中图3A的开口136为圆形孔洞，图3B的开口136为线形开槽(linear slot)，图3C的开口136为环形沟槽。接垫112的形状可相同(或相似)于开口136的形状，或者是可独立选择两者的形状。
请参照图1F，形成一导电层140，以共形地覆盖封装胶体130，其中导电层140通过封装胶体130的开口136而连接至线路基板110的对应接垫112。导电层140可作为电磁干扰屏蔽，其直接配置于封装胶体130上，而毋须使用外加的金属壳体，故可降低制作成本与时间。特别是，导电层140共形地覆盖封装胶体130的中心部132的顶面130a、封装胶体130的中心部132的侧壁130b(或侧面130b)、封装胶体130的周边部134的顶面134b、各开口136的侧壁136a(或是侧面136a)以及各接垫112的顶面112a。可通过沉积金属材料的方式形成导电层140，以使导电层140可共形地覆盖封装胶体130以及开口136所暴露出的接垫112，其中沉积金属材料的方式例如喷涂印刷(spray coating method)、电镀(或无电镀)或溅镀(sputteringmethod)。金属材料例如为铝、铜、铬、金、银、镍、锡、不锈钢、焊料及前述的组合。导电层140的优选厚度介于1微米与20微米之间。导电层140的厚度实质上是一致的。
此外，在导电层140形成之后，可选择性地进行一填充工艺(fillingprocess)，以一填充物138填充开口136，从而增加结构刚性(structuralrigidity)。举例来说，可通过在开口136中电镀一金属材料或是印刷一非导电材料的方式形成填充物138。本发明的多个实施例皆不限制填充物138的材料或形成方式。
请参照图1G，在各线路基板110的底面110b上可选择性地形成多个焊球150，且形成焊球150的方法包括植球工艺(ball mounting process)、印刷工艺或是其他可形成焊球的方法。
请参照图1H，进行一切单工艺(singulation process)，其沿着各线路基板110的边界(例如沿着切割线190，如图1H中的虚线所示)全切割(full-cutting)封装胶体130的周边部134，以分离线路基板110以及分离封装胶体130的对应的部分，从而获得多个独立的封装结构100。全切割工艺(full-cutting process)例如是刀具切割工艺(blade sawing process)或是激光切割工艺。
由于在形成开口136并将导电层140电性连接至接垫112之前，有先利用半切切割工艺来减少封装胶体130的厚度，故可减少钻出浅深度(shallowdepth)的开口136所需耗费的时间，进而可增加封装工艺的产量。
一般而言，前述的半切切割工艺或是前述的全切割工艺的切割道(cuttingpath)的宽度或深度可依遮蔽需求、或是封装体的其他电子特性、或是工艺参数而作改变。优选的是，请参照图1H，半切切割工艺的切割道的宽度W1是介于500微米与900微米之间，全切割工艺的切割道的宽度W2是介于250微米与350微米之间，各开口的宽度W3是介于50微米与100微米之间。
依照本发明的多个实施例，下述的多个实施例是更进一步地修改图1A～图1H所示的半导体元件封装的制作方法。或者是，在图1A～图1D的工艺步骤之后，如图4A所示，形成的开口136贯穿封装胶体130的周边部134以及线路基板条102。接垫112位于对应的线路基板110的承载面110a、底面110b或内层上。在本实施例中，各接垫112与对应的线路基板110的第一内线路层117a或是第二内线路层117b为一体成型。机械钻孔或是其他可行的方法皆可用来形成开口136。各接垫112被对应的开口136贯穿，且暴露于开口136的侧壁136a。
请参照图4B，形成一导电层140以共形地覆盖封装胶体130，其中导电层140通过开口136而覆盖各开口136的侧壁136a，并接触侧壁136a所暴露出的接垫112，以连接对应的接垫112。此外，可选择性地进行一填充工艺，以一填充物138填充开口136。
请参照图4C与图4D，可选择性地进行一植球工艺以形成多个焊球150，以及进行上述的一切单工艺，以获得多个独立的封装结构100。
图5绘示本发明一实施例的半导体元件封装结构的剖面图。请参照图5，一封装结构500包括一线路基板110、一电子元件120、一封装胶体130以及一导电层140。线路基板110可为一积层板(laminate substrate)并具有一承载面110a与一底面110b，且具有至少一接垫112(图5绘示二接垫112)，接垫112电性连接至导电层140。在此，接垫112可位于线路基板110的承载面110a，并电性连接至接地面或任何其他功能的平面或是参考平面。在本实施例中，接垫112与线路基板110的一顶线路层115为一体成型。电子元件120可为一配置于承载面110a上并电性连接至线路基板110的芯片，且此芯片是通过多个导电凸块180而倒装接合至线路基板110，或是可通过其他可行的接合方式接合至线路基板110(例如引线接合)。封装胶体130覆盖承载面110a并包覆承载面110a上的电子元件120。封装胶体130包括一中心部132与一围绕中心部132的周边部134，其中周边部134的厚度T2小于中心部132的厚度T1。举例来说，T2可小于约2/3的T1，例如约为1/10～2/3的T1，或是约为1/10～1/2的T1。周边部134的厚度T2实质上可以是一致的，例如周边部134的顶面134b实质上是平坦的。此外，对条状封装结构进行一切单工艺以得封装结构500(如同图1H所述)，其中封装胶体130的周边部134的一侧壁134a(或是一侧面134a)可与线路基板110的一侧壁119(或一侧面119)共平面。
封装胶体130具有至少一位于周边部134中的开口136(图5绘示多个开口136)以暴露出线路基板110的多个接垫112。导电层140共形地覆盖封装胶体130并通过开口136而连接线路基板110的接垫112。导电层140的材料例如为铜、铬、金、银、镍、铝、或是前述材料的合金、锡、不锈钢或焊料。各开口136暴露出对应的接垫112的一顶面112a，且导电层140覆盖开口136的一侧壁136a以及接垫112的顶面112a。导电层140的详细结构相似于图1F所示。再者，开口136的详细结构相似于图3A～图3C所示。
一由金属或是不导电材料所构成的填充物138可配置于各开口136中。通过暴露线路基板110的接垫112，导电层140可电性连接至接地面或是线路基板110的其他参考平面。举例来说，可在封装结构中建立一电性接地途径以作为电磁干扰屏蔽，而毋须使用外加的接地平面。焊球150配置于线路基板110的底面110b。
图6绘示本发明另一实施例的半导体元件封装结构的剖面图。请参照图6，封装结构600相似于图5的封装结构500，两者的差异之处在于接垫112位于线路基板110的内层上，其中接垫112与第一内线路层117a或是第二内线路层117b为一体成型，且开口136贯穿封装胶体130的周边部134以及线路基板110，而多个填充物138填满于开口136中。导电层140覆盖各开口136的侧壁136a，并连接侧壁136a所暴露出的各接垫112。
简而言之，为电性连接导电层与基板的接垫，可在使导电层电性连接至下方的接垫之前，进行一半切切割工艺以降低封装胶体的部分厚度，如此一来，由于钻孔深度较浅，故可增加工艺产量。在本实施例的封装结构中，导电层共形地覆盖封装胶体与线路基板，并作为一电磁干扰屏蔽层，以保护封装结构免于受到周围辐射源的辐射。实质上完全覆盖的导电层可有效地加强封装结构的电磁干扰屏蔽的效果。此外，可增加封装结构的可靠度。另外，此种设计可相容于高频元件的封装结构，特别是射频元件(radio frequencydevice)。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定为准。

Claims (19)

1.一种半导体元件封装，包括：
一线路基板，包括：
一承载面；
一底面，相对于该承载面；以及
一接垫，配置于该线路基板中；
一电子元件，邻近该承载面并电性连接至该线路基板；
一封装胶体，邻近该承载面并包覆该电子元件，该封装胶体包括一中心部与一围绕该中心部的周边部，其中：
该周边部的厚度小于该中心部的厚度；
形成在该周边部的一开口暴露出该线路基板的该接垫；
一导电层，共形地覆盖该封装胶体，并穿过该开口以连接该线路基板的该接垫；以及
一填充物，配置于该开口中。
2.如权利要求1所述的半导体元件封装，其中：
该线路基板包括一侧面，该侧面延伸于该承载面与该底面之间；
该封装胶体的该周边部包括一侧面；以及
该周边部的该侧面共平面于该线路基板的该侧面。
3.如权利要求1所述的半导体元件封装，其中该周边部的厚度相等。
4.如权利要求1所述的半导体元件封装，其中该开口暴露该接垫的一顶面，且该导电层覆盖该开口的一侧壁以及该接垫的该顶面。
5.如权利要求4所述的半导体元件封装，其中该接垫邻近该线路基板的该承载面。
6.如权利要求1所述的半导体元件封装，其中：
该开口贯穿该封装胶体的该周边部以及该线路基板；以及
该导电层覆盖该开口的一侧壁以及连接该接垫，该接垫暴露于该侧壁。
7.如权利要求6所述的半导体元件封装，其中该接垫邻近该承载面或邻近该底面。
8.如权利要求1所述的半导体元件封装，其中该接垫接地。
9.如权利要求1所述的半导体元件封装，其中该开口包括一圆形孔洞、一线形开槽或是一环形沟槽。
10.一种半导体元件封装的制作方法，包括：
提供一线路基板条，该线路基板条包括：
一承载面；
一底面，相对于该承载面；以及
一线路基板；
配置一电子元件，该电子元件邻近该承载面，其中该电子元件连接该线路基板；
形成一封装胶体，该封装胶体邻近该承载面并包覆该电子元件；
沿着该线路基板的一边缘对该封装胶体进行一半切切割工艺，以形成该封装胶体的一周边部，该周边部沿着该线路基板的该边缘延伸，其中该封装胶体的该周边部的厚度小于该封装胶体的一中心部的厚度；
在该周边部形成一开口，以暴露该线路基板的一接垫；
形成一导电层，以共形地覆盖该封装胶体，其中该导电层通过该开口而连接至该线路基板的该接垫；以及
填充该开口。
11.如权利要求10所述的半导体元件封装的制作方法，其中该周边部的厚度相等。
12.如权利要求10所述的半导体元件封装的制作方法，还包括沿着该线路基板的该边缘对该封装胶体的该周边部进行一半切切割工艺，以使该线路基板与该线路基板条的其他部分分离，并使该周边部与该封装胶体的其他部分分离。
13.如权利要求10所述的半导体元件封装的制作方法，其中形成该开口的方法包括激光钻孔。
14.如权利要求13所述的半导体元件封装的制作方法，其中该接垫邻近该线路基板条的该承载面。
15.如权利要求13所述的半导体元件封装的制作方法，其中该导电层覆盖该开口的一侧壁与该接垫的一顶面。
16.如权利要求10所述的半导体元件封装的制作方法，其中形成该开口的方法包括机械钻孔。
17.如权利要求16所述的半导体元件封装的制作方法，其中该接垫配置于该线路基板条的一内层中，且该开口贯穿该封装胶体的该周边部以及该线路基板条。
18.如权利要求16所述的半导体元件封装的制作方法，其中该导电层覆盖该开口的一侧壁并连接暴露于该侧壁的该接垫。
19.如权利要求10所述的半导体元件封装的制作方法，其中填充该开口的方法包括电镀一金属材料或是印刷一非导电材料至该开口中。
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