CN106057688A - 具有屏蔽件的集成电路封装系统及其制造方法 - Google Patents

具有屏蔽件的集成电路封装系统及其制造方法 Download PDF

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Publication number
CN106057688A
CN106057688A CN201610218946.4A CN201610218946A CN106057688A CN 106057688 A CN106057688 A CN 106057688A CN 201610218946 A CN201610218946 A CN 201610218946A CN 106057688 A CN106057688 A CN 106057688A
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substrate
integrated circuit
shielding construction
conformal
conduction
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CN106057688B (zh
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韩丙浚
沈权
沈一权
朴敬熙
林耀剑
具敎王
尹仁相
蔡升龙
曺成源
金成洙
李勋泽
梁悳景
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

一种集成电路封装系统及其制造方法包括：基板，在基板顶侧、基板底侧与竖直侧部之间具有内部电路；集成电路，其联接到内部电路；模制封装体，其直接形成于集成电路和基板的基板顶侧上；以及，导电适形屏蔽结构，其直接施加到模制封装体上、竖直侧部上，并且在基板底侧下方延伸以联接到内部电路。

Description

具有屏蔽件的集成电路封装系统及其制造方法
技术领域
本发明大体而言涉及集成电路封装系统，并且更特定而言涉及用于封装具有电磁干扰屏蔽件的集成电路管芯的系统。
背景技术
电子产品已经变成了我们日常生活的重要组成部分。对诸如半导体电路、晶体管、二极管和其它电子装置等部件的封装变得越来越小和越来越薄，并且具有越来越多的功能和连接。在封装部件时，对于以可靠方式屏蔽部件免受外部电磁干扰的这种需要可能会影响到制造工艺。
在更小空间中有更多功能的这种商业需求可能使得制造商使部件极其紧密地安装在一起。电磁场的联结可能影响到这些部件的可靠操作。在部件上提供电磁屏蔽件的要求可能会增加成本并且降低部件的制造成品率。成本降低的额外压力可能迫使制造商做出折衷，这种折衷可能会降低集成电路产品的长期可靠性。
因此，仍然需要具有屏蔽件的集成电路封装系统，能减小封装大小、支持增加的功能并且维持制造成品率和长期可靠性。鉴于对于大批量、小尺寸和可靠性方面的广泛的商业压力，寻找这些问题的解决方案越来越重要。鉴于商业竞争压力的不断增加，以及消费者期望的增高和市场上有意义的产品差别化方面机会的减少，找到这些问题的答案日益关键。另外，降低成本、提高效率和性能、以及满足竞争压力的需要对找到这些问题的答案的关键必要性增添了更大的紧迫性。
已经长期地寻找对于这些问题的解决方案，但是之前的进展并未教导或建议任何解决方案，因而，本领域技术人员长期不能获取对于这些问题的解决方案。
发明内容
本发明提供一种制造集成电路封装系统的方法，包括：提供基板，具有在基板顶侧、基板底侧与竖直侧部之间的内部电路；将集成电路联接到内部电路；将模制封装体直接形成于集成电路和基板的基板顶侧上；以及，将导电适形屏蔽结构直接施加到模制封装体上、竖直侧部上，并且在基板底侧下方延伸以联接内部电路。
本发明提供一种集成电路封装系统，包括：基板，具有在基板顶侧、基板底侧与竖直侧部之间的内部电路；集成电路，其联接到内部电路；模制封装体，其直接形成于集成电路和基板的基板顶侧上；以及，导电适形屏蔽结构，其直接施加到模制封装体上、竖直侧部上，并且在基板底侧下方延伸以联接到内部电路。
本发明的某些实施例除了以上提及的那些步骤或元件之外还具有其它步骤或元件，或者具有替代以上提及的那些步骤或元件的其它步骤或元件。从阅读参照附图作出的下列详细描述中，本领域技术人员将清楚这些步骤或元件。
附图说明
图1是集成电路封装系统的第一实施例的底视图。
图2是沿着图1的截面线2-2的集成电路封装系统的第一实施例的截面图。
图3是本发明的第二实施例中的集成电路封装系统的底视图。
图4是本发明的第三实施例中的集成电路封装系统的截面图。
图5是本发明的第四实施例中的集成电路封装系统的截面图。
图6是本发明的第五实施例中的集成电路封装系统的截面图。
图7是在制造的掩模形成阶段，集成电路封装系统的掩模丝网(maskingscreen)的截面图。
图8是在制造的封装锯切阶段，集成电路封装系统的切单结构(singulationstructure)的截面图。
图9是在制造的施加阶段，集成电路封装组件的封装组件阵列的截面图。
图10是集成电路封装系统的物理气相沉积(physical vapor deposition，PVD)制造工具的截面图。
图11是本发明的第六实施例中的集成电路封装系统的截面图。
图12是本发明的第七实施例中的集成电路封装系统的截面图。
图13是本发明的第八实施例中的集成电路封装系统的截面图。
图14是在制造的系统互连包封阶段，集成电路封装系统的互连包封的截面图。
图15是在制造的封装锯切阶段，集成电路封装系统的切单结构的截面图。
图16是在制造的施加阶段，集成电路封装组件的封装组件阵列的截面图。
图17是在本发明的另一实施例中集成电路封装系统的制造方法的流程图。
具体实施方式
对下面的实施例进行足够详细的描述，以使本领域普通技术人员能够制造和使用本发明。可以理解，基于当前的公开内容，其它实施例将是显而易见的，且可作出系统、工艺或机械的变化而不偏离本发明的范围。
在下面的描述中，给出多个具体细节以提供对本发明的彻底理解。然而，显然可在没有这些具体描述情况下实施本发明。为了避免使本发明变得模糊不清，没有对某些熟知的电路、系统、构造及工艺步骤进行详细描述。
示出系统实施例的附图是半图解式的，并且没有按比例绘制，具体地，一些尺寸是为了清晰地呈现，在附图中被夸张示出。类似地，尽管附图中的视图为了易于描述通常示出类似的取向，但是图中的这个描绘多半是任意的。一般来讲，可以在任何取向来操作本发明。
相同的附图标记在所有附图中都用于指代相同的元件。为了方便描述，将实施例编号为第一实施例、第二实施例等，这些实施例并非意图具有任何其他重要性或者对本发明提供限制。
为了说明的目的，本文中所使用的术语“水平”被定义为平行于集成电路的平面或有源表面的平面，而不管其取向如何。术语“竖直”是指垂直于刚才定义的水平的方向。如附图中所示，诸如“上方”、“下方”、“底部”、“顶部”、“侧面”(如在“侧壁”中)、“较高”、“较低”、“较上”、“上面”和“下面”等术语是相对于水平面定义的。术语“在…上”意指在元件之间存在直接接触，而没有中间元件。
本文中所使用的术语“处理”包括在形成所描述的结构时所需要的对材料或光刻胶的沉积、该材料或光刻胶的图案化、曝光、显影、蚀刻、清洁和/或移除。术语“抵靠”表示接触或压靠一物体或结构。
现参看图1，示出了集成电路封装系统100的第一实施例的底视图。集成电路封装系统100的第一实施例的底视图描绘了集成电路封装102，集成电路封装102具有：系统互连104的阵列，其安装成与阻焊剂层(solder resist layer)106接触；以及，导电适形屏蔽结构(conductive conformal shield structure)108，其在集成电路封装102的周围区域中暴露。阻焊剂层106可以是聚合物薄膜、环氧化物层、塑料涂层等。应了解集成电路封装102可以是任何类型的封装结构，包括晶片级封装(wafer level package,WLP)、单个集成电路封装、多芯片封装、集成无源装置(integrated passive device,IPD)、在封装中的封装、在封装上的封装或者多技术封装。
导电适形屏蔽结构108可以是导电涂层，诸如铜、锌、银、锡、合金；或导电树脂层，所述导电树脂层被喷涂、被电镀、被溅射、被印刷、被涂刷、被层合或通过物理气相沉积(PVD)而施加，以与阻焊剂层106接触，或者与阻焊剂层106间隔开而使基板底层110暴露。在一实施例中，导电适形屏蔽结构108可以在集成电路封装系统100的底侧和基板底层110的下方暴露出。
应了解系统互连104的数量和位置只是示例并且实际数量和位置可以不同。举例而言，集成电路封装系统100被示出为正方形，具有相同数量列和行的系统互连104，但是应了解系统互连104可以在集成电路封装系统100上形成任何图案。截面线2-2可以在图2中示出集成电路封装系统100的视图的位置和方向。
现参看图2，示出了沿着图1的截面线2-2的集成电路封装系统100的第一实施例的截面图。集成电路封装系统100的第一实施例的截面图描绘了集成电路封装102具有第一集成电路202，第一集成电路202具有通过芯片互连206诸如焊球、焊料凸块、柱形凸起或支柱互连而联接到基板顶侧204的有源侧。第一集成电路202可以电联接到基板210的内部电路208。内部电路208可以是接触衬垫、经由互连填充、系统互连衬垫、路由迹线、离散部件衬垫或其组合。内部电路208可以在基板210内形成再分布层。
第二集成电路212和离散部件214可以通过芯片互连206或导电粘合剂216(诸如焊糊料、导电环氧化物、导电胶带等)联接到基板顶侧204。离散部件214可以是电阻器、电容器、电感器、电压调节器、二极管、晶体管等。第二集成电路212可以是集成电路管芯、集成电路封装、模拟或混合电路、存储器等。模制封装主体(molded package body)218可以直接形成于第一集成电路202、第二集成电路212、离散部件214和基板顶侧204上。
阻焊剂层106可以直接形成于基板底侧110、系统互连104和基板内部电路208上。阻焊剂层106可以一直延伸到基板底侧110的边缘，或者可以与所述边缘间隔开而使基板底部110暴露。
导电适形屏蔽结构108可以直接形成于模制封装主体218上、基板210的竖直侧部220上和基板底侧110的周围区域上。导电适形屏蔽结构108可以电连接到内部电路208，内部电路208延伸到基板210的竖直侧部220，或者在基板底侧110上暴露。导电适形屏蔽结构108可以在基板底侧110下方延伸并且可以在基板210下方水平地延伸。内部电路208可以将导电适形屏蔽结构108电连接到系统互连104中的一个，该系统互连104向集成电路封装系统100提供接地连接。
已经发现集成电路封装102可以提供薄且可靠的平台，用于将多个集成电路组装为屏蔽了EMI的单个封装形式。集成电路封装102能在进一步组装之前进行测试，并且能表示可靠并且可制造的封装以维持集成电路封装系统100的电完整性。
现参看图3，示出了本发明的第二实施例中的集成电路封装系统300的底视图。集成电路封装系统100的第二实施例300的底视图描绘了集成电路封装302，集成电路封装302包括系统互连104，系统互连104定位于集成电路封装302的中央区域中。阻焊剂106可以施加到集成电路封装302的底部上。
多个电镀通孔304可以沿着集成电路封装302的每个周围边缘对准。电镀通孔304可以具有电镀导电材料(诸如铜、银、锡、锌或其合金)的圆柱形中央部分。多个电镀通孔304可以各具有足够宽以在切单后保留的直径，举例而言，直径可以在100μm至200μm的范围并且可以在切单后提供至少5μm。电镀通孔304的顶部和底部可以延伸超过圆柱形中央部分，以连接图2的内部电路208。导电适形屏蔽结构108可以形成为包括电镀通孔304。
应了解系统互连104的数量和数字只是示例，并且系统互连104的实际数量和位置可以是不同的。多个电镀通孔304的定位只是示例，但是多个电镀通孔304将沿着集成电路封装302的划片街区(saw street)。
现参看图4，示出了本发明的第三实施例中的集成电路封装系统400的截面图。集成电路封装系统400的截面图描绘了邻近基板210的竖直侧部220的电镀通孔304。阻焊剂106可以覆盖基板底层110。导电适形屏蔽结构108可以形成于模制封装体218上，并且可以包括电镀通孔304的顶部和底部，因为它们直接定位于划片街区上并且在基板210的竖直侧部220上呈现固体导电表面。导电适形屏蔽结构108可以包括电镀通孔304的顶部和底部，因为它们在基板210的竖直侧部220处电连接。
导电适形屏蔽结构108可以在基板底侧110下方延伸并且与阻焊剂106直接接触。系统互连104可以联接到基板底侧110并且与阻焊剂106接触。导电适形屏蔽结构108的一部分可以跨阻焊剂106延伸以便提供俘获机构(capturemechanism)，该俘获机构可以防止导电适形屏蔽结构108剥离。应了解导电适形屏蔽结构108包括电镀通孔304，因为它们在基板210的竖直侧部220处电连接。
应了解图2的第一集成电路202、图2的第二集成电路212和图2的离散部件214中的任一个可以于集成电路封装系统400中实施。为了清楚和易于描述，它们并未示出。
已经发现导电适形屏蔽结构108可以形成为包括电镀通孔304，以便增加在导电适形屏蔽结构108内的电接触件。通过增加电镀通孔304的数量，可以增加导电适形屏蔽结构108的结构完整性。
现参看图5，示出了本发明的第四实施例中的集成电路封装系统500的截面图。集成电路封装系统500的截面图描绘了邻近基板210的竖直侧部220的电镀通孔304。阻焊剂106可以覆盖基板底层110。系统互连104可以联接到基板底侧110并且与阻焊剂106接触。导电适形屏蔽结构108可以形成于模制封装体218上并且可以包括电镀通孔304，因为它们直接定位于划片街区上并且在基板210的竖直侧部220上呈现固体导电表面。多个电镀通孔304可以各具有在100μm至200μm范围的直径并且在切单后至少5μm将保持就位。
导电适形屏蔽结构108可以在基板底侧110下方延伸并且与基板底侧110直接接触。导电适形屏蔽结构108的一部分可以跨基板底侧110延伸以便提供俘获机构，该俘获机构可以防止导电适形屏蔽结构108剥离。应了解导电适形屏蔽结构108包括电镀通孔304，因为它们在基板210的竖直侧部220处电连接。
应了解图2的第一集成电路202、图2的第二集成电路212和图2的离散部件214中的任一个可以于集成电路封装系统500中实施。为了清楚和易于描述，它们并未示出。
已经发现导电适形屏蔽结构108可以形成为包括电镀通孔304，以便增加在导电适形屏蔽结构108内的电接触件。通过增加电镀通孔304的数量，可以增加导电适形屏蔽结构108的结构完整性。
现参看图6，示出了本发明的第五实施例中的集成电路封装系统600的截面图。集成电路封装系统600的截面图描绘了邻近基板210的竖直侧部220的电镀通孔304。阻焊剂106可以覆盖基板底层110。系统互连104可以联接到基板底侧110并且与阻焊剂106接触。导电适形屏蔽结构108可以形成于模制封装体218上并且可以包括电镀通孔304，因为它们直接定位于划片街区上并且在基板210的竖直侧部220上呈现固体导电表面。
导电适形屏蔽结构108可以在基板底侧110下方延伸并且与阻焊剂106直接接触。导电适形屏蔽结构108的一部分可以跨基板底侧110延伸以便提供俘获机构，该俘获机构可以防止导电适形屏蔽结构108剥离。应了解导电适形屏蔽结构108包括电镀通孔304，因为它们在基板210的竖直侧部220处电连接。
应了解图2的第一集成电路202、图2的第二集成电路212和图2的离散部件214中任一个可以于集成电路封装系统600中实施。为了清楚和易于描述，它们并未示出。
已经发现导电适形屏蔽结构108可以形成为包括电镀通孔304，以便增加在导电适形屏蔽结构108内的电接触件。通过增加电镀通孔304的数量，可以增加导电适形屏蔽结构108的结构完整性。
现参看图7，示出了在制造的掩模形成阶段，集成电路封装系统100的掩模丝网701的截面图。集成电路封装系统100的掩模丝网701的截面图描绘了载体702，载体702上安装有模制封装条带(molded package strip)704。载体702可以由金属、陶瓷、塑料、纤维、玻璃等组成。模制封装条带704可以具有系统互连104和背向载体702的阻焊剂106。
印刷丝网(printing screen)706可以定位于晶片基板708上。印刷丝网706可以用来图案化互连掩模710，诸如糊料、膜、有机硅环氧化物或者可固化的耐热材料。印刷丝网706可以阻挡互连掩模710围绕模制封装条带704的划片街区712的分布。印刷丝网706的定位可以允许切单锯(singulation saw)(未示出)在划片街区712和邻近划片街区712的固定尺寸上接近。
已经发现印刷丝网706可以在批量生产环境中限定图1的导电适形屏蔽结构108的水平延伸尺寸。这些尺寸是可预测的并且可重复的。
现参看图8，示出了在制造的封装锯切阶段，集成电路封装系统100的切单结构801的截面图。集成电路封装系统100的切单结构801的截面图描绘了切单锯802，切单锯802从图7的模制封装条带704分离集成封装组件804。
掩模间距806可以确立图7的划片街区712的宽度和水平重叠距离808，其可以大于或等于在基板底侧110上10μm的水平间距。应了解这些实施例中的某些实施例可以消除掩模间距806并且直接锯穿互连掩模710。在这些实施例中，图1的导电适形屏蔽结构108可以抵靠图1的阻焊剂106，其中，阻焊剂106在基板底侧110下方延伸。
现参看图9，示出了在制造的施加阶段，集成电路封装组件902的封装组件阵列901的截面图。封装阵列组件901的截面图描绘了已经转移到沉积带904的集成封装组件804。沉积带904可以定位集成电路封装组件902，使得导电适形屏蔽结构108可以形成于所有暴露表面上。沉积带904可以是聚酰亚胺层或其它耐热粘合剂层，以在涂布过程中维持集成封装组件804的位置从而施加导电适形屏蔽结构108。应了解导电适形屏蔽结构108可以通过喷涂、电镀、溅射、印刷、涂刷、层合或通过物理气相沉积(PVD)而施加。
应了解图2的基板210的图2的竖直侧部220可以具有由于切单锯802从图7的模制封装条带704分离集成封装组件804而暴露的金属层。导电适形屏蔽结构108可以形成与竖直侧部220的暴露部分或者基板底侧110的暴露部分的直接物理和电连接。导电适形屏蔽结构108的物理和电连接可以防止导电适形屏蔽结构108在搬运期间剥离或损坏并且保证安全和高品质装置。
已经发现集成电路封装组件902可以防止在施加导电适形屏蔽结构108期间污染系统互连104。如果导电适形屏蔽结构108污染系统互连104，图1的集成电路封装102可能在制造测试中失败并且可能是不合格的。通过实施集成电路封装组件902，系统互连104受到保护避免污染和可能的短路。
现参看图10，示出了图1的集成电路封装系统100的物理气相沉积(PVD)制造工具1001的截面图。PVD制造工具1001的截面图描绘了PVD卡盘(PVDchuck)1002，PVD卡盘1002支承PVD芯片载体1004，PVD芯片载体1004具有真空吸持机构(vacuum chucking mechanism)1006。
真空吸持机构1006可以具有多个真空腔室1008，多个真空腔室1008具有安装于其周围上的粘合剂坝(adhesive dam)1010。粘合剂坝1010可以密封于集成电路封装102上以形成真空密封。粘合剂坝1010定位成暴露在真空腔室1008外侧的基板底侧110的周围1012。真空腔室1008可以包括互连粘合剂1011，诸如具有良好机械阻力和耐热性的柔顺聚合物。在真空腔室1008内的压力可以在PVD过程之前减小，以便将集成电路封装102锁定在粘合剂坝1010上的适当位置。在一实施例中，真空腔室1008可以维持在与PVD腔室(未示出)相同的压力从而避免压差，压差可能会破坏粘合剂坝1010。
PVD卡盘1002可以放置于PVD腔室(未示出)中，PVD腔室可以将导电适形屏蔽结构108沉积到集成电路包装102的所有暴露表面上。导电适形屏蔽结构108可以直接形成于模制封装主体218顶部上、基板210的竖直侧部220上和基板底侧110的周围1012上。
已经发现物理气相沉积(PVD)制造工具1001可以大量地在集成电路封装102上重复地产生导电适形屏蔽结构108。通过相对于互连粘合剂1011来定位粘合剂坝1010，可以控制周围1012的准确尺寸以防止污染系统互连104。
现参看图11，示出了本发明的第六实施例中的集成电路封装系统1100的截面图。集成电路封装系统1100的截面图包括集成电路封装1102。集成电路封装1102可以具有第一集成电路202，第一集成电路202通过芯片互连206联接到多层基板1104。模制封装体218可以直接形成于第一集成电路202、芯片互连206和多层基板1104上。
导电适形屏蔽结构108可以形成于模制封装体218、竖直侧部220和基板底侧110上。在集成电路封装系统1100中，多层基板1104的竖直侧部220没有暴露的金属。通过跨基板底侧110施加导电适形屏蔽结构108，能做出物理和电连接。系统互连104可以联接到基板底侧110并且与阻焊剂106接触。导电适形屏蔽结构108附连到基板底侧110上能防止导电适形屏蔽结构108剥离并且保证集成电路封装系统1100为可靠和可制造装置。导电适形屏蔽结构108可以跨基板底侧110延伸大于或等于10μm以做出电连接。
现参看图12，示出了本发明的第七实施例中的集成电路封装系统1200的截面图。集成电路封装系统1200的截面图描绘了分层基板1202，分层基板1202具有联接到导电适形屏蔽结构108的顶部内层1204。阻焊剂106可以覆盖基板底层110。导电适形屏蔽结构108可以形成于模制封装体218上和分层基板1202的竖直侧部220上以包括顶部内层1204，因为顶部内层1204直接定位于划片街区上并且在分层基板1202的竖直侧部220上呈现固体导电表面。
导电适形屏蔽结构108可以在基板底侧110下方延伸并且与基板底侧110直接接触。导电适形屏蔽结构108的一部分可以跨基板底侧110延伸以便提供俘获机构，该俘获机构可以防止导电适形屏蔽结构108剥离。应了解导电适形屏蔽结构108包括顶部内层1204，因为它在分层基板1202的竖直侧部220处电连接。
导电适形屏蔽结构108可以接触竖直侧部220附近的阻焊剂106，其中导电适形屏蔽结构108可以跨基板底侧110延伸大于或等于10μm的距离。阻焊剂沟槽1206可以定位于离导电适形屏蔽结构108的水平部分的端部至少10μm处。阻焊剂沟槽1206可以一直穿透到基板底侧110并且具有大于或等于10μm的宽度。阻焊剂沟槽1206可以增强图10的粘合剂坝1010的粘附，以便防止导电适形屏蔽结构108扩展超过其预期的覆盖范围。
应了解图2的第一集成电路202、图2的第二集成电路212和图2的离散部件214中的任一个可以于集成电路封装系统1200中实施。为了清楚和易于描述，它们并未示出。
已经发现导电适形屏蔽结构108可以形成为包括顶部内层1204以便增加在导电适形屏蔽结构108内的电接触件。通过增加顶部内层1204的连接数量，可以增加导电适形屏蔽结构108的结构完整性。
现参看图13，示出了本发明的第八实施例中的集成电路封装系统1300的截面图。集成电路封装系统1300的截面图描绘了分层基板1202，分层基板1202具有联接到导电适形屏蔽结构108的顶部内层1204。阻焊剂106可以覆盖基板底层110。导电适形屏蔽结构108可以形成于模制封装体218上和分层基板1202的竖直侧部220上以包括顶部内层，因为顶部内层1204直接定位于划片街区上并且在分层基板1202的竖直侧部220上呈现固体导电表面。
导电适形屏蔽结构108可以在基板底侧110下方延伸并且与阻焊剂106直接接触。应了解导电适形屏蔽结构108包括顶部内层1204，因为它在分层基板1202的竖直侧部220处电连接。导电适形屏蔽结构108可以抵靠竖直侧部220附近的阻焊剂106，其中导电适形屏蔽结构108可以沿着基板底侧110延伸大于0μm的距离。
导电适形屏蔽结构108可以在基板底侧110下方延伸大于0μm的距离。阻焊剂沟槽1206可以定位于离导电适形屏蔽结构108的边缘至少10μm处。阻焊剂沟槽1206可以一直穿透到基板底侧110并且具有大于或等于10μm的宽度。阻焊剂沟槽1206可以增强图10的粘合剂坝1010的粘附，以防止导电适形屏蔽结构108扩展超过其预期的覆盖范围。
应了解图2的第一集成电路202、图2的第二集成电路212和图2的离散部件214中任一个可以于集成电路封装系统1300中实施。为了清楚和易于描述，它们并未示出。
已经发现导电适形屏蔽结构108可以形成为包括顶部内层1204以便增加在导电适形屏蔽结构108内的电接触件。通过增加顶部内层1204的连接数量，可以增加导电适形屏蔽结构108的结构完整性。
现参看图14，示出了在制造的系统互连包封阶段，集成电路封装系统100的互连包封1401的截面图。集成电路封装系统100的互连包封1401的截面图描绘了载体702，载体702上安装有模制封装条带704。载体702可以由金属、陶瓷、塑料、纤维、玻璃等组成。模制封装条带704可以包括系统互连104和背向载体702施加到晶片基板708上的阻焊剂106。
互连包封层1402，诸如糊料、膜、有机硅环氧化物或可固化的耐热材料可以形成于系统互连104和晶片基板708的阻焊剂106上。互连包封层1402覆盖模制封装条带704的划片街区712。
已经发现互连包封层1402可以在搬运期间向系统互连104提供保护层。互连包封层1402可以完全包封系统互连104和阻焊剂106的所有暴露表面。
现参看图15，示出了在制造的封装锯切阶段，图1的集成电路封装系统100的切单结构1501的截面图。集成电路封装系统100的切单结构1501的截面图描绘了切单锯802，切单锯802从图7的模制封装条带704分离集成封装组件804。
划片街区间距1502可以确立图7的划片街区712的宽度。应了解这些实施例中的某些实施例可以直接切穿互连包封层1402。在此实施例中，图1的导电适形屏蔽结构108可以抵靠图1的阻焊剂106，其中，其在基板底侧110下方延伸。
现参看图16，示出了在制造的施加阶段，集成电路封装组件1602的封装组件阵列1601的截面图。封装阵列组件1601的截面图描绘了已经转移到沉积带904的集成封装组件804。沉积带904可以定位集成电路封装组件1602使得导电适形屏蔽结构108可以形成于所有暴露表面上。沉积带904可以是聚酰亚胺层或其它耐热粘合剂层，以在涂布过程中维持集成封装组件804的位置来施加导电适形屏蔽结构108。应了解导电适形屏蔽结构108可以通过喷涂、电镀、溅射、印刷、涂刷、层合或通过物理气相沉积(PVD)而施加。
应了解图2的基板210的图2的竖直侧部220可以具有由于切单锯802从图7的模制封装条带704分离集成封装组件804而暴露的金属层。导电适形屏蔽结构108可以形成与竖直侧部220的暴露部分的直接物理和电连接。导电适形屏蔽结构108的物理和电连接可以防止导电适形屏蔽结构108在搬运期间剥离或损坏并且保证安全和高品质装置。
已经发现集成电路封装组件1602能防止在施加导电适形屏蔽结构108期间污染系统互连104，因为它们完全被互连包封层1402包封。如果导电适形屏蔽结构108污染了系统互连104，图1的集成电路封装102可能在制造测试中失败并且可能是不合格的。通过实施集成电路封装组件1602，系统互连104受到保护避免污染和可能的短路。
现参看图17，示出了在本发明的另一实施例中集成电路封装系统100的制造方法1700的流程图。该方法1700包括：在框1702，提供基板，其在基板顶侧、基板底侧与竖直侧部之间具有内部电路；在框1704，将集成电路联接到内部电路；在框1706，将模制封装体直接形成于集成电路和基板的基板顶侧上；以及，在框1708，将导电适形屏蔽结构直接施加到模制封装体上、竖直侧部上并且在基板底侧下方延伸以联接内部电路。
所得的方法、工艺、设备、装置、产品和/或系统简单，具有成本效益，不复杂，高度通用并且有效，可以通过改动已知技术来令人惊讶地并且不明显地实施，因此容易适合于高效率地、经济地制造集成电路封装系统，充分与常规制造方法或工艺和技术兼容。
本发明的另一重要方面是，它有价值地支持并服务于降低成本、简化系统和提高性能的历史趋势。
本发明的这些和其它有价值的方面因此至少将本技术的状态推进到下一水平。
尽管已经结合特定的最佳模式描述了本发明，但是要理解，根据前面的描述，许多替代、修改和变化对于本领域的技术人员将是显而易见的。因此，本发明意图包含属于权利要求的范围内的所有这样的替代、修改和变化。在本文中到目前为止阐述的或在附图中示出的所有内容要从说明性、而非限制性的意义上来进行解释。

Claims (10)

1.一种制造集成电路封装系统的方法，包括：
提供基板，其在基板顶侧、基板底侧与竖直侧部之间具有内部电路；
将集成电路联接到所述内部电路；
将模制封装体直接形成于所述集成电路上和所述基板的所述基板顶侧上；以及
将导电适形屏蔽结构直接施加到所述模制封装体上、所述竖直侧部上，并且在所述基板底侧下方延伸以联接所述内部电路。
2.根据权利要求1所述的方法，还包括：邻近所述竖直侧部形成电镀通孔。
3.根据权利要求1所述的方法，其中，将所述导电适形屏蔽结构施加到所述竖直侧部上包括：联接电镀通孔。
4.根据权利要求1所述的方法，其中，将所述导电适形屏蔽结构施加于所述基板底侧下方包括：抵靠阻焊剂。
5.根据权利要求1所述的方法，还包括：形成阻焊剂沟槽，以暴露所述导电适形屏蔽结构附近的所述基板底侧。
6.一种集成电路封装系统，包括：
基板，具有在基板顶侧、基板底侧与竖直侧部之间的内部电路；
集成电路，其联接到所述内部电路；
模制封装体，其直接形成于所述集成电路上和所述基板的所述基板顶侧上；以及
导电适形屏蔽结构，其直接施加到所述模制封装体上、所述竖直侧部上，并且在所述基板底侧下方延伸以联接所述内部电路。
7.根据权利要求6所述的系统，还包括：邻近所述竖直侧部的电镀通孔。
8.根据权利要求6所述的系统，其中施加到所述竖直侧部上的所述导电适形屏蔽结构包括电镀通孔，所述电镀通孔联接到所述导电适形屏蔽结构。
9.根据权利要求6所述的系统，其中施加于所述基板底侧下方的所述导电适形屏蔽结构包括阻焊剂，所述导电适形屏蔽结构抵靠所述阻焊剂。
10.根据权利要求6所述的系统，还包括：阻焊剂沟槽，其形成于所述基板底侧上，靠近所述导电适形屏蔽结构。
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US11145603B2 (en) 2021-10-12

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