TWI695468B - 具有屏蔽之積體電路封裝系統以及其製法 - Google Patents

具有屏蔽之積體電路封裝系統以及其製法 Download PDF

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TWI695468B
TWI695468B TW105110868A TW105110868A TWI695468B TW I695468 B TWI695468 B TW I695468B TW 105110868 A TW105110868 A TW 105110868A TW 105110868 A TW105110868 A TW 105110868A TW I695468 B TWI695468 B TW I695468B
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Taiwan
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substrate
integrated circuit
solder resist
package
shielding structure
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TW105110868A
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TW201712821A (zh
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韓丙濬
沈一權
朴敬熙
耀劍 林
具敎王
尹仁相
蔡昇龍
曺成源
金成洙
李勳擇
梁悳景
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新加坡商星科金朋有限公司
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Abstract

一種積體電路封裝系統及其製法包括：基板，其係具有在基板頂面、基板底面及數個垂直面之間的內部電路；積體電路，其係耦合至該內部電路；模造封裝體，其係直接形成於該積體電路及該基板之基板頂面上；以及導電保形屏蔽結構，其係直接鋪設至該模造封裝體、該等垂直面上且在耦合至該內部電路之該基板底面下面延伸。

Description

具有屏蔽之積體電路封裝系統以及其製法
本發明大體有關於一種積體電路封裝系統，且更特別的是有關於一種用於封裝具有電磁干擾屏蔽之積體電路晶粒的系統。
電子產品已變成日常生活不可或缺的一部份。諸如半導體電路、電晶體、二極體及其他電子裝置之類的組件的封裝件已變得更小更薄以及有更多功能和連接。在封裝組件時，由於需要以可靠的方式屏蔽組件免於受到外界電磁干擾，所以可能會影響製程。
在更小空間中要有更多功能的商業需求可能促使製造商製作極度緊密地安裝的組件。電磁場的聯結可能衝擊這些組件的可靠操作。要求提供組件的電磁屏蔽可能增加成本且減少組件的製造良率。減少成本的額外壓力可能迫使製造商做出減少積體電路產品之長期可靠性的妥協。
因此，仍亟須具有屏蔽的積體電路封裝系統，它可減少封裝件尺寸，支援增加的功能，以及維持製造良 率氶長期可靠性。鑑於高容積，小尺寸及可靠性的廣泛商業壓力，找出這些問題的答案越來越重要。鑑於持續遞增的商業競爭壓力，以及消費者預期的增長和市場上重大產品差異化的機會在遞減，使得找出這些問題的答案至關重要。另外，減少成本、改善效率及效能和滿足競爭壓力的需要也增加必需找出這些問題答案的急迫性。
長期以來大家都在尋找這些問題的解決方案，但是先前的開發沒有教導或建議任何解決方案，因此熟諳此藝者一直在思索解決這些問題的方案。
本發明提供一種製造積體電路封裝系統之方法，其係包含下列步驟：提供基板，其具有在基板頂面、基板底面及數個垂直面之間的內部電路；將積體電路耦合至該內部電路；直接在該積體電路及該基板之該基板頂面上形成模造封裝體；以及直接鋪設導電保形屏蔽結構於該模造封裝體、該等垂直面上且在該基板底面下面延伸用以耦合該內部電路。
本發明提供一種積體電路封裝系統，其係包括：基板，其係具有在基板頂面、基板底面及數個垂直面之間的內部電路；積體電路，其係耦合至該內部電路；模造封裝體，其係直接形成於該積體電路及該基板之基板頂面上；以及導電保形屏蔽結構，其係直接鋪設至該模造封裝體、該等垂直面上且在耦合至該內部電路之該基板底面下面延伸。
某些本發明具體實施例有其他的步驟或元件可供加入或取代以上所提及的。熟諳此藝者閱讀以下參考附圖的詳細說明可明白該等步驟或元件。
100:積體電路封裝系統
102:積體電路封裝件
104:系統互連件
106:阻焊劑/阻焊劑層
108:導電保形屏蔽結構
110:基板底層/基板底面/基板底部
202:第一積體電路
204:基板頂面
206:晶片互連件
208:內部電路
210:基板
212:第二積體電路
214:離散組件
216:導電黏著劑
218:模造封裝體
220:垂直面
300‧‧‧積體電路封裝系統
302‧‧‧積體電路封裝件
304‧‧‧鍍通孔
400、500、600‧‧‧積體電路封裝系統
701‧‧‧光罩網版
702‧‧‧載板
704‧‧‧模造封裝件條
706‧‧‧印刷網版
708‧‧‧晶圓基板
710‧‧‧互連件遮罩
712‧‧‧切割道
801‧‧‧單切結構
802‧‧‧單切鋸
804‧‧‧整合封裝總成
806‧‧‧遮罩間隔
808‧‧‧水平重疊距離
901‧‧‧封裝總成陣列
902‧‧‧積體電路封裝總成
904‧‧‧沉積膜帶
1001‧‧‧物理氣相沉積(PVD)製造工具
1002‧‧‧PVD夾頭
1004‧‧‧PVD晶片載板
1006‧‧‧真空吸盤機構
1008‧‧‧真空室
1010‧‧‧黏著劑壩體
1011‧‧‧互連件黏著劑
1012‧‧‧周邊
1100‧‧‧積體電路封裝系統
1102‧‧‧積體電路封裝件
1104‧‧‧多層基板
1200‧‧‧積體電路封裝系統
1202‧‧‧層狀基板
1204‧‧‧頂部內層
1206‧‧‧阻焊劑溝槽
1300‧‧‧積體電路封裝系統
1401‧‧‧互連件包封物
1402‧‧‧互連件包封層
1501‧‧‧單切結構
1502‧‧‧切割道間隔
1601‧‧‧封裝總成陣列
1602‧‧‧積體電路封裝總成
1700‧‧‧方法
1702‧‧‧步驟
1704‧‧‧步驟
1706‧‧‧步驟
1708‧‧‧步驟
第1圖的仰視圖圖示積體電路封裝系統的第一具體實施例。
第2圖為積體電路封裝系統之第一具體實施例沿著第1圖之剖面線2-2繪出的橫截面圖。
第3圖根據本發明第二具體實施例圖示積體電路封裝系統的仰視圖。
第4圖根據本發明第三具體實施例圖示積體電路封裝系統的橫截面圖。
第5圖根據本發明第四具體實施例圖示積體電路封裝系統的橫截面圖。
第6圖根據本發明第五具體實施例圖示積體電路封裝系統的橫截面圖。
第7圖的橫截面圖圖示積體電路封裝系統在製造之光罩形成階段的光罩網版。
第8圖的橫截面圖圖示積體電路封裝系統在製造之封裝件切割階段的單切結構。
第9圖的橫截面圖圖示積體電路封裝總成在製造之鋪設階段的封裝總成陣列。
第10圖為積體電路封裝系統之物理氣相沉積(PVD)製造工具的橫截面圖。
第11圖根據本發明第六具體實施例圖示積體電路封裝系統的橫截面圖。
第12圖根據本發明第七具體實施例圖示積體電路封裝系統的橫截面圖。
第13圖根據本發明第八具體實施例圖示積體電路封裝系統的橫截面圖。
第14圖的橫截面圖圖示積體電路封裝系統在製造之系統互連件包封階段的互連件包封物。
第15圖的橫截面圖圖示積體電路封裝系統在製造之封裝件切割階段的單切結構。
第16圖的橫截面圖圖示積體電路封裝總成在製造之鋪設階段的封裝總成陣列。
第17圖的流程圖根據本發明另一具體實施例圖示製造積體電路封裝系統的方法。
以下充分詳述數個具體實施例使得熟諳此藝者能夠製造及使用本發明。應瞭解，基於本揭示內容仍有其他具體實施例，而且可做出系統、方法或機械改變而不脫離本發明的範疇。
以以下說明中，給出許多特定細節供徹底了解本發明。不過，應瞭解，在沒有該等特定細節下仍可實施本發明。為了避免混淆本發明，不詳細揭示一些眾所周知的電路、系統組態和製程步驟。
圖示系統具體實施例的附圖為半圖解式且不 按比例繪製，特別是，圖中有些尺寸為了圖示清楚而加以誇大。同樣，儘管附圖中的視圖為了便於描述而大體以相同的方向圖示，然而大部份是用任意的方式描繪附圖。大體而言，可用任何方位操作本發明。
所有附圖中類似及相同的特徵用相同的元件符號描述。編號為第一具體實施例、第二具體實施例等等的具體實施例是為了便於描述而非旨在賦予任何其他意義或提供本發明的限制。
為了解釋，本文所用的術語“水平面”是定義為與積體電路之平面或主動表面平行的平面，而不管它的方向。術語“垂直”係指與剛才所定義之水平面垂直的方向。諸如“上方”、“下方”、“底面”、“頂面”、“側面”(如“側壁”)、“高於”、“低於”、“上面”、“上方”、以及“下面”之類的術語都是以水平面來定義，如附圖所示。術語“在…上”意指在元件之間呈直接實體接觸而沒有中介元件。
如用於本文的術語“加工”係包括沉積材料或光阻劑、圖案化、曝光、顯影、蝕刻、清洗、及/或移除材料或光阻劑，如在形成述及結構時要做的。用語“抵靠”意指接觸或貼著物件或結構。
第1圖圖示積體電路封裝系統100之第一具體實施例的仰視圖。積體電路封裝系統100之第一具體實施例的仰視圖圖示具有系統互連件104陣列的積體電路封裝件102，該陣列經安裝成與阻焊劑層106接觸，以及導 電保形屏蔽結構108在積體電路封裝件102的周圍區域露出。阻焊劑層106可為聚合物膜、環氧樹脂層、塑膠塗層或其類似者。應瞭解，積體電路封裝件102可為任何類型的封裝件結構，包括晶圓級封裝件(WLP)、單一積體電路封裝件、多晶片封裝件、整合被動裝置(IPD)、封裝件內封裝件(package-in-package)、封裝件上封裝件(package-on-package)或多技術封裝件(rmulti-technology package)。
導電保形屏蔽結構108可為用物理氣相沉積(PVD)噴塗、鍍覆、濺鍍、印刷、刷塗、覆膜或鋪設的導電塗層，例如銅、鋅、銀、錫、合金或導電樹脂層，它與阻焊劑層106接觸或與其隔開讓基板底層110露出。在一具體實施例中，導電保形屏蔽結構108可暴露積體電路封裝系統100的底面以及低於基板底層110的高度。
應瞭解，系統互連件104的個數及位置僅為示範且實際的個數及位置可不同。例如，圖示積體電路封裝系統100為有相等行列數之系統互連件104的方形，然而應瞭解，系統互連件104可在積體電路封裝系統100上形成任何圖案。剖面線2-2可顯示積體電路封裝系統100在第2圖中的視線位置及方向。
第2圖為積體電路封裝系統100之第一具體實施例沿著第1圖之剖面線2-2繪出的橫截面圖。積體電路封裝系統100之第一具體實施例的橫截面圖圖示積體電路封裝件102具有第一積體電路202，該第一積體電路202 具有主動面以供晶片互連件206(例如，焊球、銲錫凸塊、釘狀凸塊(stud bump)或柱狀互連件)耦合至基板頂面204。第一積體電路202可電氣耦合至基板210的內部電路208。內部電路208可為接觸墊、填充導孔互連件、系統互連件墊、路由跡線、離散組件墊或彼等之組合。內部電路208可形成在基板210內的重分配層。
第二積體電路212及離散組件214可用晶片互連件206或導電黏著劑216(例如，焊膏、導電環氧樹脂、導電膠帶或其類似者)耦合至基板頂面204。離散組件214可為電阻器、電容器、電感器、電壓調整器、二極體、電晶體或其類似者。第二積體電路212可為積體電路晶粒、積體電路封裝件、類比或混合電路、記憶體或其類似者。模造封裝體218可直接形成於第一積體電路202、第二積體電路212、離散組件214及基板頂面204上。
阻焊劑層106可直接形成於基板底面110、系統互連件104及基板內部電路208上。阻焊劑層106可一路延伸到基板底面110的邊緣或與該邊緣有間隔而讓基板底部110露出。
導電保形屏蔽結構108可直接形成於模造封裝體218、基板210的垂直面220及基板底面110的周圍區域上。導電保形屏蔽結構108可電氣連接至延伸至基板210之垂直面220或在基板底面110上暴露的內部電路208。導電保形屏蔽結構108可在基板底面110下面延伸且可在基板210下面水平延伸。內部電路208可使導電保形屏蔽 結構108電氣連接至系統互連件104中提供連接至積體電路封裝系統100之接地的一者。
已發現，積體電路封裝件102可提供薄且可靠的平台用以將多個積體電路組裝成有EMI屏蔽的單一封裝件格式。積體電路封裝件102能夠在進一步組裝之前受測而且可代表可靠又可製造的封裝件用以維持積體電路封裝系統100的電氣完整性。
請參考第3圖，其仰視圖圖示根據本發明第二具體實施例的積體電路封裝系統300。積體電路封裝系統100之第二具體實施例300的仰視圖圖示包括位於積體電路封裝件302中心區域之系統互連件104的積體電路封裝件302。阻焊劑106可鋪設於積體電路封裝件302的底部。
複數個鍍通孔304可沿著積體電路封裝件302的各個周圍邊緣對齊。鍍通孔304可具有鍍覆導電材料的圓柱中心部份，例如銅、銀、錫、鋅或彼等之合金。複數個鍍通孔304各自可具有夠寬的直徑以在單切(singulation)後有剩餘，例如直徑的範圍可在100至200微米之間以及在單切後可提供至少5微米。鍍通孔304的頂部及底部可延伸超出圓柱中心部份用以連接第2圖的內部電路208。導電保形屏蔽結構108可經形成含有鍍通孔304。
應瞭解，系統互連件104的位置及個數僅為示範而且系統互連件104的實作個數及位置可不同。複數個鍍通孔304的定位僅為示範，但複數個鍍通孔304會沿 著積體電路封裝件302的切割道(saw street)。
請參考第4圖，其橫截面圖圖示根據本發明第三具體實施例的積體電路封裝系統400。積體電路封裝系統400的橫截面圖圖示鄰近基板210之垂直面220的鍍通孔304。阻焊劑106可覆蓋基板底層110。導電保形屏蔽結構108可形成於模造封裝體218上且可包括鍍通孔304的頂部及底部，因為它們直接定位於切割道上且在基板210的垂直面220上存在實體傳導面。導電保形屏蔽結構108可包括鍍通孔304的頂部及底部，因為它們在基板210的垂直面220電氣連接。
導電保形屏蔽結構108可在基板底面110下面延伸且直接接觸阻焊劑106。系統互連件104可耦合至基板底面110且接觸阻焊劑106。導電保形屏蔽結構108的一部份可延伸越過阻焊劑106以便提供可防止導電保形屏蔽結構108剝離的捕捉機構。應瞭解，導電保形屏蔽結構108包括鍍通孔304，因為它們在基板210的垂直面220電氣連接。
應瞭解，積體電路封裝系統400中可實作第2圖之第一積體電路202、第2圖之第二積體電路212及第2圖之離散組件214中之任一者。為求便於說明，未圖示彼等。
已發現，導電保形屏蔽結構108可經形成含有鍍通孔304以便增加在導電保形屏蔽結構108內的電氣接觸。藉由增加鍍通孔304個數，可增加導電保形屏蔽結 構108的結構完整性。
請參考第5圖，其橫截面圖圖示根據本發明第四具體實施例的積體電路封裝系統500。積體電路封裝系統500的橫截面圖圖示鄰近基板210之垂直面220的鍍通孔304。阻焊劑106可覆蓋基板底層110。系統互連件104可耦合至基板底面110且接觸阻焊劑106。導電保形屏蔽結構108可形成於模造封裝體218上且可包括鍍通孔304，因為它們直接定位於切割道上且在基板210的垂直面220上存在實體傳導面。複數個鍍通孔304可各自有在100至200微米之間的直徑範圍以及在單切後在適當地方仍有至少5微米。
導電保形屏蔽結構108可在基板底面110下面延伸且直接接觸基板底面110。導電保形屏蔽結構108的一部份可延伸越過基板底面110以便提供可防止導電保形屏蔽結構108剝離的捕捉機構。應瞭解，導電保形屏蔽結構108包括鍍通孔304，因為它們在基板210的垂直面220電氣連接。
應瞭解，積體電路封裝系統500中可實作第2圖之第一積體電路202、第2圖之第二積體電路212及第2圖之離散組件214中之任一者。為求便於說明，未圖示彼等。
已發現，導電保形屏蔽結構108可經形成含有鍍通孔304以便增加在導電保形屏蔽結構108內的電氣接觸。藉由增加鍍通孔304個數，可增加導電保形屏蔽結 構108的結構完整性。
請參考第6圖，其橫截面圖圖示根據本發明第五具體實施例的積體電路封裝系統600。積體電路封裝系統600的橫截面圖圖示鄰近基板210之垂直面220的鍍通孔304。阻焊劑106可覆蓋基板底層110。系統互連件104可耦合至基板底面110且接觸阻焊劑106。導電保形屏蔽結構108可形成於模造封裝體218上且可包括鍍通孔304，因為它們直接定位於切割道上且在基板210的垂直面220上存在實體傳導面。
導電保形屏蔽結構108可在基板底面110下面延伸且直接接觸阻焊劑106。導電保形屏蔽結構108的一部份可延伸越過基板底面110以便提供可防止導電保形屏蔽結構108剝離的捕捉機構。應瞭解，導電保形屏蔽結構108包括鍍通孔304，因為它們在基板210的垂直面220電氣連接。
應瞭解，積體電路封裝系統600中可實作第2圖之第一積體電路202、第2圖之第二積體電路212及第2圖之離散組件214中之任一者。為求便於說明，未圖示彼等。
已發現，導電保形屏蔽結構108可經形成含有鍍通孔304以便增加在導電保形屏蔽結構108內的電氣接觸。藉由增加鍍通孔304個數，可增加導電保形屏蔽結構108的結構完整性。
請參考第7圖，其橫截面圖圖示積體電路封 裝系統100在製造之光罩形成階段的光罩網版(masking screen)701。積體電路封裝系統100之光罩網版701的橫截面圖圖示有模造封裝件條(rmolded package strip)704裝在其上的載板702。載板702可由金屬、陶瓷、塑膠、纖維、玻璃或其類似者構成。模造封裝件條704可具有背離載板702的系統互連件104及阻焊劑106。
印刷網版706可定位於晶圓基板708上。印刷網版706可用來圖案化互連件遮罩710，例如膏、膜、矽氧樹脂環氧樹脂或可固化耐熱材料。印刷網版706可阻擋互連件遮罩710分佈於模造封裝件條704的切割道712四周。印刷網版706的定位允許單切鋸(未圖示)接近切割道712上方以及鄰近切割道712的固定尺寸。
已發現，印刷網版706可界定第1圖之導電保形屏蔽結構108在量產環境中的水平延伸尺寸。該等尺寸可預測且可重覆。
請參考第8圖，其橫截面圖圖示積體電路封裝系統100在製造之封裝件切割階段的單切結構801。積體電路封裝系統100之單切結構801的橫截面圖圖示單切鋸802已使整合封裝總成804與第7圖之模造封裝件條704分離。
遮罩間隔806可建立第7圖之切割道712的寬度與水平重疊距離808，它可大於或等於在基板底面110上之10微米的水平間隔。應瞭解，有些具體實施例可排除遮罩間隔806以及直接切穿互連件遮罩710。在這些具體 實施例中，第1圖的導電保形屏蔽結構108可抵靠第1圖之阻焊劑106，在此它是在基板底面110下面延伸。
請參考第9圖，其橫截面圖圖示積體電路封裝總成902在製造之鋪設階段的封裝總成陣列901。封裝總成陣列901的橫截面圖圖示已轉印至沉積膜帶(deposition tape)904的整合封裝總成804。沉積膜帶904可定位積體電路封裝總成902，使得導電保形屏蔽結構108可形成於所有的暴露表面上。沉積膜帶904可為聚亞醯胺層或其他耐熱黏著劑層用以在鋪設導電保形屏蔽結構108的塗佈製程期間維持整合封裝總成804的位置。應瞭解，導電保形屏蔽結構108的鋪設方式可為噴塗、鍍覆、濺鍍、印刷、刷塗、覆膜、或透過物理氣相沉積(PVD)。
應瞭解，第2圖之基板210的第2圖之垂直面220可具有被單切鋸802暴露的金屬層，單切鋸802已使整合封裝總成804與第7圖之模造封裝件條704分離。導電保形屏蔽結構108可形成至垂直面220之暴露部份或基板底面110之暴露部份的直接實體和電氣連接。導電保形屏蔽結構108的實體和電氣連接可防止導電保形屏蔽結構108在處理期間剝離或受損且確保為安全及品質保證的裝置。
已發現，積體電路封裝總成902可防止系統互連件104在鋪設導電保形屏蔽結構108期間污染。如果導電保形屏蔽結構108污染系統互連件104，則第1圖的積體電路封裝件102可能會無法通過製造測試而被剔除。 藉由實作積體電路封裝總成902，可保護系統互連件104免於污染及可能的短路。
請參考第10圖，其橫截面圖圖示第1圖之積體電路封裝系統100的物理氣相沉積(PVD)製造工具1001。PVD製造工具1001的橫截面圖圖示PVD夾頭1002支撐具有真空吸盤機構1006之PVD晶片載板1004。
真空吸盤機構1006可具有有黏著劑壩體(adhesive dam)1010裝在其周邊上的多個真空室1008。黏著劑壩體1010可密封積體電路封裝件102以形成真空密封。黏著劑壩體1010經定位成可暴露基板底面110在真空室1008外面的周邊1012。真空室1008可包括互連件黏著劑1011，例如有良好機械耐熱性的相容聚合物。在PVD製程之前可減少真空室1008內的壓力以便將積體電路封裝件102鎖定於黏著劑壩體1010上。在一具體實施例中，真空室1008可維持與PVD室(未圖示)相同的壓力以避免可能使黏著劑壩體1010失敗的壓力差。
PVD夾頭1002可放入可沉積導電保形屏蔽結構108於積體電路封裝件102之所有暴露表面上的PVD室(未圖示)內。導電保形屏蔽結構108可直接形成於模造封裝體218的頂部、基板210的垂直面220、以及基板底面110的周邊1012上。
已發現，物理氣相沉積(PVD)製造工具1001可大量重覆地在積體電路封裝件102上製造導電保形屏蔽結構108。藉由相對於互連件黏著劑1011來定位黏著劑壩 體1010，可控制周邊1012的準確尺寸以防污染到系統互連件104。
請參考第11圖，其橫截面圖圖示根據本發明之第六具體實施例的積體電路封裝系統1100。積體電路封裝系統1100的橫截面圖包括積體電路封裝件1102。積體電路封裝件1102可具有通過晶片互連件206耦合至多層基板1104的第一積體電路202。模造封裝體218可直接形成於第一積體電路202、晶片互連件206及多層基板1104上。
導電保形屏蔽結構108可形成於模造封裝體218、垂直面220及基板底面110上。在積體電路封裝系統1100中，多層基板1104的垂直面220沒有暴露金屬。藉由鋪設越過基板底面110的導電保形屏蔽結構108，可達到實體和電氣連接。系統互連件104可耦合至基板底面110且接觸阻焊劑106。導電保形屏蔽結構108附著至基板底面110可防止導電保形屏蔽結構108剝離且保證為積體電路封裝系統1100的可靠可製造裝置。導電保形屏蔽結構108可延伸越過基板底面110大於或等於10微米用以製作電氣連接。
請參考第12圖，其橫截面圖圖示根據本發明之第七具體實施例的積體電路封裝系統1200。積體電路封裝系統1200的橫截面圖圖示有耦合至導電保形屏蔽結構108之頂部內層1204的層狀基板1202。阻焊劑106可覆蓋基板底層110。導電保形屏蔽結構108可形成於模造封裝體218及層狀基板1202的垂直面220上以含有頂部內層 1204，因為頂部內層1204可直接定位於切割道上以及在層狀基板1202之垂直面220上存在實體傳導面。
導電保形屏蔽結構108可在基板底面110下面延伸且直接接觸基板底面110。導電保形屏蔽結構108的一部份可延伸越過基板底面110以便提供可防止導電保形屏蔽結構108剝離的捕捉機構。應瞭解，導電保形屏蔽結構108包括頂部內層1204，因為在層狀基板1202的垂直面220處電氣連接。
導電保形屏蔽結構108可接觸在垂直面220附近的阻焊劑106，在此導電保形屏蔽結構108可延伸越過基板底面110一段大於或等於10微米的距離。阻焊劑溝槽1206可與導電保形屏蔽結構108之水平部份的末端至少有10微米的距離。阻焊劑溝槽1206可一路穿透到基板底面110而且有大於或等於10微米的寬度。阻焊劑溝槽1206可增強第10圖之黏著劑壩體1010的黏性以防導電保形屏蔽結構108蔓延超出它的預期涵蓋範圍。
應瞭解，積體電路封裝系統1200中實作第2圖之第一積體電路202、第2圖之第二積體電路212及第2圖之離散組件214中之任一者。為求便於說明，未圖示彼等。
已發現，導電保形屏蔽結構108可經形成含有頂部內層1204以便增加在導電保形屏蔽結構108內的電氣接觸。藉由增加頂部內層1204的連接數，可增加導電保形屏蔽結構108的結構完整性。
請參考第13圖，其橫截面圖圖示根據本發明之第八具體實施例的積體電路封裝系統1300。積體電路封裝系統1300的橫截面圖圖示有耦合至導電保形屏蔽結構108之頂部內層1204的層狀基板1202。阻焊劑106可覆蓋基板底層110。導電保形屏蔽結構108可形成於模造封裝體218及層狀基板1202的垂直面220上以含有頂部內層1204，因為頂部內層1204可直接定位於切割道上以及在層狀基板1202之垂直面220上存在實體傳導面。
導電保形屏蔽結構108可在基板底面110下面延伸且直接接觸阻焊劑106。應瞭解，導電保形屏蔽結構108包括頂部內層1204，因為在層狀基板1202的垂直面220處電氣連接。導電保形屏蔽結構108可抵靠在垂直面220附近的阻焊劑106，在此導電保形屏蔽結構108可沿著基板底面110延伸一段大於0微米的距離。
導電保形屏蔽結構108可在基板底面110下面延伸一段大於0微米的距離。阻焊劑溝槽1206可與導電保形屏蔽結構108的邊緣至少有10微米的距離。阻焊劑溝槽1206可一路穿透到基板底面110而且有大於或等於10微米的寬度。阻焊劑溝槽1206可增強第10圖之黏著劑壩體1010的黏性以防導電保形屏蔽結構108蔓延超出它的預期涵蓋範圍。
應瞭解，積體電路封裝系統1300中可實作第2圖之第一積體電路202、第2圖之第二積體電路212及第2圖之離散組件214中之任一者。為求便於說明，未圖示 彼等。
已發現，導電保形屏蔽結構108可經形成含有頂部內層1204以便增加在導電保形屏蔽結構108內的電氣接觸。藉由增加頂部內層1204的連接數，可增加導電保形屏蔽結構108的結構完整性。
請參考第14圖，其橫截面圖圖示積體電路封裝系統100在製造之系統互連件包封(encasing)階段的互連件包封物1401。積體電路封裝系統100之互連件包封物1401的橫截面圖圖示有裝在其上之模造封裝件條704的載板702。載板702可由金屬、陶瓷、塑膠、纖維、玻璃或其類似者構成。模造封裝件條704可包括以背離載板702的方式鋪設於晶圓基板708的系統互連件104及阻焊劑106。
互連件包封層1402，例如膏、膜、矽氧樹脂環氧樹脂或可固化耐熱材料，可形成於晶圓基板708的系統互連件104及阻焊劑106上。互連件包封層1402覆蓋模造封裝件條704的切割道712。
已發現，互連件包封層1402可提供系統互連件104在處理期間的保護層。互連件包封層1402可完全包封系統互連件104及阻焊劑106的所有暴露表面。
請參考第15圖，其橫截面圖圖示第1圖之積體電路封裝系統100在製造之封裝件切割階段的單切結構1501。積體電路封裝系統100的單切結構1501的橫截面圖圖示單切鋸802已使整合封裝總成804與第7圖之模造封 裝件條704分離。
切割道間隔1502可建立第7圖之切割道712的寬度。應瞭解，有些具體實施例可直接切穿互連件包封層1402。在此具體實施例中，第1圖的導電保形屏蔽結構108可抵靠在基板底面110下面延伸的第1圖之阻焊劑106。
請參考第16圖，其橫截面圖圖示積體電路封裝總成1602在製造之鋪設階段的封裝總成陣列1601。封裝總成陣列1601的橫截面圖圖示已轉印至沉積膜帶904的整合封裝總成804。沉積膜帶904可定位積體電路封裝總成1602使得導電保形屏蔽結構108可形成於所有的暴露表面上。沉積膜帶904可為聚亞醯胺層或其他耐熱黏著劑層，用以在鋪設導電保形屏蔽結構108的塗佈製程期間維持整合封裝總成804的位置。應瞭解，導電保形屏蔽結構108的鋪設方式可為噴塗、鍍覆、濺鍍、印刷、刷塗、覆膜、或透過物理氣相沉積(PVD)。
應瞭解，第2圖之基板210的第2圖之垂直面220可具有被單切鋸802暴露的金屬層，單切鋸802已使整合封裝總成804與第7圖之模造封裝件條704分離。導電保形屏蔽結構108可形成至垂直面220之暴露部份的直接實體和電氣連接。導電保形屏蔽結構108的實體和電氣連接可防止導電保形屏蔽結構108在處理期間剝離或受損且確保為有安全及品質保證的裝置。
已發現，積體電路封裝總成1602可防止系統 互連件104在鋪設導電保形屏蔽結構108期間受到污染，因為它們被互連件包封層1402完全包封。如果導電保形屏蔽結構108會污染到系統互連件104，則第1圖的積體電路封裝件102便無法通過製造測試而被剔除。藉由實作積體電路封裝總成1602，可保護系統互連件104免於污染及可能的短路。
請參考第17圖，其流程圖根據本發明另一具體實施例圖示製造積體電路封裝系統100的方法1700。方法1700包括：在步驟1702，提供一基板，其具有在一基板頂面、一基板底面及數個垂直面之間的內部電路；在步驟1704，將一積體電路耦合至該內部電路；在步驟1706，直接在該積體電路及該基板之該基板頂面上形成一模造封裝體；以及在步驟1708，直接鋪設一導電保形屏蔽結構於該模造封裝體、該等垂直面上且在該基板底面下面延伸用以耦合該內部電路。
所得方法、製程、設備、裝置、產品及/或系統簡單明瞭、有成本效益、不複雜、高度通用及有效，而且令人意外及不明顯的是，它的具體實作可藉由修改習知技術，從而輕易適合用來有效及經濟地製造完全相容於習知製造方法或製程及技術的積體電路封裝系統。
本發明的另一重要態樣在於有價值地支援及服務節省成本、簡化系統及提高效能的歷史趨勢。
結果，本發明以上及其他有價值的態樣可促進技術狀態至少到下一個階段。
儘管已結合特定的最佳樣式來描述本發明，顯然熟諳此藝者基於上述說明應瞭解，仍有許多替代、修改及變體。因此，希望所有的替代、修改及變體皆落入隨附申請專利範圍的範疇。所有迄今為止在本文及附圖中提及的事項應被解釋成只是用來做圖解說明而沒有限定本發明的意思。
1700‧‧‧方法
1702‧‧‧步驟
1704‧‧‧步驟
1706‧‧‧步驟
1708‧‧‧步驟

Claims (12)

  1. 一種鋪設保形屏蔽結構於積體電路(IC)封裝件上之方法，該IC封裝件包含基板、在該基板的第一面上之模造封裝體、在該基板之相對於該第一面的第二面上之複數個互連件及在該基板之該第二面上的阻焊劑層，該阻焊劑層具有用以暴露該基板的該第二面之阻焊劑溝槽，該阻焊劑溝槽圍繞該阻焊劑層的外圍連續延伸，該方法係包括：在該基板的該第二面上屏蔽該等互連件；以及鋪設保形屏蔽結構於該模造封裝體以及該基板之未被屏蔽的數個暴露表面上。
  2. 如申請專利範圍第1項所述之方法，其中，該IC封裝件係為模造封裝件條的複數個IC封裝件之其中一者，該方法進一步包含：於屏蔽該等互連件之前，將該模造封裝件條以該等IC封裝件的該等互連件背離載板的方式放置於該載板上；於屏蔽該等互連件之後，沿著該模造封裝件條的數個切割道單切該模造封裝件條，以獲得個別的數個IC封裝件；自該載板移除被單切的數個IC封裝件；以及於鋪設保形屏蔽結構之前，將該單切的數個IC封裝件以被屏蔽的該等互連件面對膜帶的方式放置於該膜帶上。
  3. 如申請專利範圍第2項所述之方法，其中，屏蔽該等互連件包括：將印刷網版放置於該模造封裝件條上方，以使該等互連件藉由該印刷網版中的數個開口暴露；將互連件遮罩鋪設於該印刷網版的該等開口中，以覆蓋該等互連件；以及自該模造封裝件條移除該印刷網版。
  4. 如申請專利範圍第3項所述之方法，其中，該印刷網版包括該等切割道上方用以定義該等開口的數個部分；其中，單切該模造封裝件條係包括使用具有寬度小於該印刷網版的該等部分的寬度之單切鋸來單切該模造封裝件條，使得該基板的該第二面之周邊未被該互連件遮罩覆蓋，以便後續供該保形屏蔽結構舖設於該基板上。
  5. 如申請專利範圍第2項所述之方法，其中，屏蔽該等互連件係包含：舖設互連件包封層於該模造封裝件條上方以覆蓋該等互連件，以及其中，單切該模造封裝件條係包括：切穿該模造封裝件條上之該互連件包封層。
  6. 如申請專利範圍第1項所述之方法，其中，在該基板的該第二面上屏蔽該等互連件係包含：使用PVD晶片載板支撐該IC封裝件，該PVD晶片載板具有接合於該阻焊劑溝槽的黏著劑壩體。
  7. 一種積體電路封裝系統，包含：基板，係具有在基板頂面、基板底面及數個垂直面之間的內部電路； 積體電路，係耦合至該內部電路；模造封裝體，係直接形成於該積體電路及該基板之該基板頂面上；導電保形屏蔽結構，係直接於該模造封裝體和該等垂直面上；以及阻焊劑層，係在該基板底面上，該阻焊劑層具有用以暴露該基板底面之阻焊劑溝槽，該阻焊劑層鄰近該導電保形屏蔽結構，該導電保形屏蔽結構電氣耦合至該內部電路，且該阻焊劑溝槽圍繞該阻焊劑層的外圍連續延伸。
  8. 如申請專利範圍第7項所述之系統，進一步包含：鄰近該等垂直面並自該等垂直面暴露之數個鍍通孔。
  9. 如申請專利範圍第7項所述之系統，其中，鋪設至該等垂直面上的該導電保形屏蔽結構包括：耦合至該導電保形屏蔽結構之鍍通孔。
  10. 如申請專利範圍第7項所述之系統，其中，該阻焊劑層抵靠該導電保形屏蔽結構。
  11. 如申請專利範圍第7項所述之系統，其中，該阻焊劑溝槽係在該阻焊劑層與該導電保形屏蔽之間的該基板底面上。
  12. 如申請專利範圍第7項所述之系統，其中，該導電保形屏蔽結構係直接在該基板底面的一部分上並通過該等垂直面或該基板底面而耦合至該內部電路。
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