TWI376779B - Semiconductor device packages and manufacturing method thereof - Google Patents

Semiconductor device packages and manufacturing method thereof Download PDF

Info

Publication number
TWI376779B
TWI376779B TW099116087A TW99116087A TWI376779B TW I376779 B TWI376779 B TW I376779B TW 099116087 A TW099116087 A TW 099116087A TW 99116087 A TW99116087 A TW 99116087A TW I376779 B TWI376779 B TW I376779B
Authority
TW
Taiwan
Prior art keywords
opening
circuit substrate
pad
peripheral portion
encapsulant
Prior art date
Application number
TW099116087A
Other languages
English (en)
Other versions
TW201119003A (en
Inventor
Seokbong Kim
Yeonsun Yun
Yuyong Lee
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Publication of TW201119003A publication Critical patent/TW201119003A/zh
Application granted granted Critical
Publication of TWI376779B publication Critical patent/TWI376779B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1376779 ASEK2276-NEW-FINAL-TW-20100520 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件封裝及其製作方法， 且特別是有關於一種具有電磁干擾屏蔽（electromagnetic interference shielding )的半導體元件封裝及其製作方法。 【先前技術】 半導體元件日益複雜，而至少部分的原因是源於使用 者對於增加處理速度（processing speed)與縮小元件尺寸 的需求。雖然增加處理速度與縮小元件尺寸的好處相當顯 著，但是這些半導體元件的特性亦會產生問題。特別是， 較高的時脈速度（clock speed)會使訊號準位（signal levd ) 轉換的頻率增加，以致於頻率較高或波長較短的電磁發射 (electromagnetic emission)強度增加。電磁發射可從一源 半導體元件（source semiconductor device)輻射而出並入 射鄰近的半導體元件。若是對鄰近的半導體元件的電磁發 射強度夠高，則電磁發射會不利於（鄰近的）半導體元件 的運作。此現象有時被稱為電磁干擾（dectr〇magnetic interference ’ EMI)。尺寸較小的半導體元件會使電磁干 擾的問，更加嚴重’因駿些（尺寸較㈣）半導體元件 會以較问的岔度配置於一電子系統中，以致於鄰近的半導 體元件接收到較強且不希望得到的電磁發射。 -组:擾Γ種方法是在半導體元件封褒中屏蔽 .，且牛導體讀。_是，可料在縣料部加農接地 ASEK2276-NEW-FINAL-TW-20100520 的導電罩體（easing)或是導電殼體（hQUSing)來達到屏 蔽的效果。當由封裝體内部輻射出的電磁發射撞射到罩體 的内表面時，至少部分的電磁發射被電性短路，以降低可 牙透罩體且不利於鄰近的半導體元件的電磁發射強度。相 同地，當由鄰近的半導體元件輻射出的電磁發射撞射到罩 體的外表面時，會發生相似的電性短路以降低封裝 半導體元件所受到的電磁干擾。 _ 雖然導電罩體可減少電磁干擾，但是使用導電罩體會 有許多缺點。制是’罩體―般是藉由黏著劑而固定在半 導體7L件雌的外部。不幸岐，㈣轉㈣接合性會 受到溫度、Μ以及其他環境因素㈣響叫低，因此: 罩體容易剝離或脫落。而且，當將罩體固定至封裝體時， 罩體以及難體的尺寸與形狀需相互配合，且二^的配合 度需在-較小的容忍範圍内。使尺寸與形狀能夠相互 合’以及縣n與縣體的姆位置具有—定的準奋 導致製作成本提高並耗費製程_。由於f要使尺ϋ 狀能相互配合，目此，不㈤尺寸與雜的半導體 ^ 需要搭配不同的罩體’以容納不同的封裝體，^ 步地增加製作成本與時間。 ° 運一 導體元件封裴及其 克服如述背景中所提及的問題的半 製作方法如下所述。 【發明内容】 本發明提供-種具有電磁干擾屏蔽的半導體元件封 ASEK2276-NEW-FINAL-TW-20100520 裝及其製作方法。 本發明提出-種半導體元件封裝 電子元件'-封裝膠體《及一導電 載:鄰接塾，其中底面相對於承載面。電子 70件钟近承載面並轉錢路基板 載面並包覆電子稀。龍膠體包括—中心料體^中 心部的周邊部，其中周邊部的厚度小於中心部的厚度反 形成在周邊部的-開口暴露出線路基板的接塾。導電層兴 形地覆蓋縣轉，並σ以連絲路基板的接塾。 在本發明之-實施例中，線路基板包括一側面，側面 延伸於承載面與底面之間。封裝膠體的周邊部包括一側 面。周邊部的侧面實質上與線路基板的側面共平面。 在本發明之一實施例中，周邊部的厚度實質上相等。 在本發明之一實施例中，導電層的厚度實質上相等。 在本發明之一實施例中，開口暴露接墊的一頂面，真 導電層覆蓋開口的一側壁以及接墊的頂面β接墊可鄰近線 路基板的承載面。 在本發明之一實施例中，接墊配置於線路基板中，開 口貫穿封裝膠體的周邊部以及線路基板，以及導電層覆蓋 開口的—側壁以及連接接墊，接墊暴露於側壁。接蛰巧鄰 近承載面或鄰近底面。 在本發明之一實施例中，半導體元件封裝更包栝/填 充物，其配置於開口中。 ASEK2276-NEW-FINAL.TW-20100520 在本發明之一實施例中，接塾係接地。 在本發明之-實施例中，開 形開槽或是-環形溝槽。 _孔洞、一線 (I)tt明種半導體元件輕㈣作枝，包括. U)棱供一線路基板條，其中 匕栝. -底面以及-㈣Μ，基板條包括—承载面、 電子开株φ 相對於承載面；(2)配置- 電子7G件，電子兀件鄰近承载面其 基板；（3)形成—封裝膠體 接線路 =元件;⑷沿著線路基板的:邊覆 以形成封裝膠體的-周邊部，周邊‘著 封裝膝體的―中心、部的厚度；（5)在周邊部形成一開口， 路基板的一接墊；（6)形成一導電層，以共形地 i、、膠體，其中導電層透過開口而連接至線路基 接墊。 在本發明之一實施你丨中，周邊部的厚度實質上相萼。 • « , . ·. · · " 在本發明之一實施例中，半導體元件封裝的製作方法 更包括沿著線路基板的邊緣對封裝膠體的周邊部進行一全 切割製程，以使線路基板與線路基板條的其他部分分離， 並使周邊部與封裝膠體的其他部分分離。 在本發明之一實施例中，形成開口的方法包括雷射鑽 孔。此外’接塾•鄰近線路基板條的承載面。導電層可覆蓋 開口的一侧壁與接墊的一頂面。 1376779 ASEK2276-NEW-FINAL-TW-20100520 在本發明之-實補中，職開σ的方法 孔。此外，接墊配置於線路基板條的一内層中，且^ 穿封裝膠體的周邊部以及線路基板條。導電芦 汗貝 一側壁並連接暴露於側壁的接塾。 1 β 〇的 在本發明之-實施财，轉體元件㈣的製 更包括在形成導電層之後填充開σ，其中填充開口的方法 包括電鍍一金屬材料或是印刷一非導電材料至開口中。 為讓本發明<上述特徵和優點能更明顯易懂，下 舉實施例，並配合所附圖式作詳細說明如下。 守 【實施方式】 下列的定討應用在關於本發明之某些實施例 些方面。在此將詳述這些定義。 /、 在此所制的單詞『―』與『該』可代表複數個 t下文明顯指出『-』與『該』代表單數個。因此，舉 =來二:’當提到-接地元件時，可包括多個接地元件 况，除非上下文明顯指出『―』代表單數個。. f此所使用的5司『组』代表—或多個元件的群體。因 組的元件可以是彼此相 組的元件可共有一或多 =舉=來說層可包括單—騎或多個膜層。一 、，且的元件亦可代表該組的構件。 同或彼此不同。在—些例子中， 個相同的特性。 元株ΐ此!^使用的詞『鄰近』代表接近或是鄰接。鄰近的 σ以疋彼齡離或是彼此實質±錢或直接接觸。在 1376779 ASEK2276-NE W-FINAL-TW-20100520 一些例子中’鄰近的元件可彼此相連或是彼此為一體成型。 在此所使用的詞例如『内』、『頂』、『底』、『上、 『下』、『向下』以及『橫向』代表—組元件的相對方向 (方位），例如依照圖所示，但是毋須以特定的方向製作 或是使用這些元件。
日在此所使用的詞『連接』代表操作上的耦接（⑺叩丨丨邶） 或疋連接（linking) 〇連接元件可以是彼此直接耦接或是 彼此間接輕接，例如透過.另一組元件。. 在此所使用的詞『實質上』、『基本上』代表一可以 考慮的程度綠圍。當其與―事件或情況則時，該詞可 =表該事件骑況準確發生的赃以及該事件或情況發生 二近似錢例子’例如計#此處所描述的製程操作的一 知^各忍磨。 力所使用的同『導電的』代表一種傳導電流的能
般是相當於表現出輕微或是無反抗電流流 3材枓。導電率的單位為s.ra] (siemenspermeter)。 =，導f材料是一導電率約大於1 〇4 S.m-1的材料，例如 ^^約1〇 或是至少約lOk.m-i。材唞的導電率有時 =而變。除非有特別說明，否則都是指室溫下的材 製作f種封裝結構，例如堆叠式封裝
Pa-.)(mUWP^ package)。 封裝（high frequency device ，[s. ] 9 1376779 ASEK2276-NE W-FINAL-TW-20100520 圖1A〜圖1H繪示本發明一實施例之半導體元件封裝 的製程示意圖。 請參關1A，-線路基板條102具有多個線路基板 110 ’線路基板110是由多條後續的切割線19〇 (圖中 的虛線）所定義出來的，其中各線路基板110包括一承載 面110a、一底面UOb與一組接墊112(或是其他的接地元 件），接墊112連接至接地面或是任何其他功能的平面或 是參考平面。各線路基板110也包括延却於承载面u〇a 與底面110b之間的一侧面，如圖5、6所示（以下將會述 及,）。相同於線路基板110中的其他線路層，接墊^可 以是由金屬（例如銅）所構成。接墊112可 no的任-線路層上，並與該線路層—體‘=== 該線路層中。在本實施例中，接塾112位於線路基板條1〇2 的承載面110a上，並與一頂線路層115 一體成型。 請參照圖1B，多個電子元件_或半導體元件12〇) 配置於承載面110a上，ϋ分別以覆晶接合財式透過多個 導電凸塊180電性連接至線路基板11〇。在其他實施例中， 電元件120連接到線珞基板11〇的方法可以是打線接合 或疋其他可行的連接方法。在此，電子元件12()可為一晶 ^電子元件120較佳地是配置於線路基板110的一中心 琿之中。另外，本發明之實施例並不限定各線路基板11〇 上所配置的電子元件12〇的數量。在本實關巾，各線路 基板11〇係接合有一電子元件12〇。然而，在其他實施例 t，封裝結構可包括各線路基板11〇上配置有多個電子元 1376779 » • ASEK2276-NEW-FINAL-TW-20100520 件 120。 凊參照圖1C’進行—封膜制户、 上形成-封裝膠體130,用以^ = ’以於線路基板條102 線路基板no的至少局部。封12()、接墊112與各 ^ (evening process) 環氧樹脂献130㈣質例如為 請參照圖1D，在封裝膠體13 的邊緣（例如沿著切割、線19〇)推：者^線路基板110 .,,,進仃一半切切割製程 曰a = mg pr=ess)，以移除部分的封震膠體13〇。特 二ί切切副衣程利用一切割工具（未繪示）部分切割 封跡體⑽’因此，可在各鱗基板110的邊緣上形成 封裝膠體130的一周邊部以，其中周邊部m的厚度g 小於封裝雜13G的—巾心部132的厚度TWb外，周邊 部134的厚度T2實質上相等，也就是周邊部134的一頂 面134b η質上是平坦的。由於形成在兩直接相鄰的線路基 板110邊緣上的周邊部134的厚度實質上相尊，因此，可 降低用以製作周邊部134的半切蝴製料複雜度。舉例 來說，以單一實質上水平的切割可製得橫跨兩直接相鄰的 線路基板110的頂面134b。 5月參照圖1E，在半切切割製程之^後，在周邊部134 上相對各線路基板11〇形成至少一開口 136，以暴露出:線 路基板110的接墊H2。 圖2示範性地繪示圖1E中的結構的立體圖。如圖2 所示，多個開口 136係形成在封裝膠體130中並圍繞各晶 1376779 ASEK2276-NE W-FINAL-TW-20100520 片12〇。在本實施例+ ’是採用雷射鑽孔製程（laser drilling process)。由於雷射對於封骏膠體13〇的切割速度遠大於 對於金屬的⑽j速度’因此，雷射鑽孔製程容易切穿封裝 膠體130，且當遇到· 112時切槪度會顯著降低或停 止切J因此，形成在封裝膠體130的周邊部134的雷射 開口 136會暴露^線路基板11()的承载面丨伽上的接塾 ⑴。雖'然在此是採用雷射鑽孔製程，但也可以採用其他可 行的移除方法’例如化學_錢械研磨，赠述方法皆 包含在本發明的範圍中。
你甘L卜為符合不同的需求，可改變開口 136的形狀t 拍二二不同的外形（Pr〇flle)。® 3A〜圖3C繪示本Ί 之圖1E之結構的局部上視圖。請參照圖3心 L二，示具有不同外形的多個開口136,其中圖 (linear slot^ ^ ^ ^ 〇 圖3C的開口 136為環形溝槽。接墊u 趣1 口136的形狀，或者㈣
而連接至細魏縣職i3G關口13 為電磁對應接塾112。導電層14〇可< ^蚊八直接配置於封裝膠體130上，而毋多 導電層，可降低製作成本與時間。特別是 130a、封扭地覆蓋封裝膠體130的中心部132的頂i 1遍，膠體⑽的中心部132的側壁働（或^ (S) 12 1376779 ASEK2276-NEW-FINAL-TW-20100520 130b)、封裝膠體130的周邊部134的頂面134b、各開口 136的側壁136a (或是側面136a)以及各接墊112的頂面 112a。可藉由沉積金屬材料的方式形成導電層14〇，以使 導電層140可共形地覆蓋封裝膠體13〇以及開口 136所暴 露出的接墊112，其中沉積金屬材料的方式例如噴塗印刷 (spmy coating meth〇d)、電鍍（或無電鍍）或濺鍍 (sputteringmethod)。金屬材料例如為鋁、銅、鉻、金、 銀、鎳、錫、不銹鋼、焊料及前述之組合。導電層14〇的 較佳厚度是介於1微米與2〇微米之間。導電層14〇的厚度 實質上是一致的。 此外，在導電層140形成之後，可選擇性地進行一填 充製程（fillingprocess)，以一填充物138填充開口 136， 從而增加結構剛性（structuralrigidity)。舉例來說可藉 由在開口 136中電鍍一金屬材料或是印刷一非導電材料的 方式开>成填充物138。本發明的多個實施例皆不限制填充 物138的材質或是形成方式。 、 凊參照圖1G，在各線路基板no的底面u〇b上可選 擇=地形成多個銲球15〇，且形成銲球15〇的方法包括植 球製程（ball mounting process )、印刷製程或是其他可带 成銲球的方法。 y 請參照w m，進行一切單製程（singulationpr〇cess)， "係沿著各線路基板no的邊界（例如沿著切割線i9〇， θ 1H中的虛線所示）全切割（fuu_cutting)封褒膠體 130的周邊部134，以分離線路基板以及分離封裝膠體
[S.1 13 1376779 ASEK2276-NE W-FINAL-TW-20100520 no之對應的部分，從而獲得多個獨立的塊結構刚。全 切割製程（full-cutting process )例如是刀具切割製程（此如 sawing process)或是雷射切割製程。 由於在形成開口 136並將導電層14〇電性連接至接墊 112之前’有先㈣_製程來減少封裝 13 厚度，故可減少鑽出淺深度（shall〇w depth)的開口 136 所需耗費的時間，進而可增加封裝製程的產量。 一般而言，前述的半切切割製程或是前述的全切割製 程的切割道（cutting path)的寬度或深度可依遮蔽需^、 或是封裝體的其他電子特性、或是製程參數而作改變。較 ，的是，請參照圖1H，半切切割製程的切割道的寬度W1 :介於5〇0微米與_微米之間，全切割製程的切割道的 寬度W2是介於250微米與350微米之間，各開口的寬度 W3是介於50微米與ι〇〇微米之間。 依照本發明的多個實施例，下述的多個實施例是更進 厂步，修改圖1A〜圖1H所示的半導體元件封裝的製作方 法二或者是，在圖1A〜圖id的製程步驟之後，如圖4A ，不，形成的開口 136係貫穿封裝膠體13〇的周邊部134 =及線路基板條撤。錄ι12位於對應的線路基板11〇 接承载面110a、底面110b或内層上。在本實施例中，各 第塾112與對應的線路基板110的第一内線路層117a或是 方線路層117b為一體成型^機械鑽扎或是其他可行的 母^皆可用來形成開口 136。各接墊U2被對應的開口 u6 貝，且暴露於開口 136的側壁136a。 ASEK2276-NEW-FINAL-TW-20100520 請參照圖4B，形成一導電層140以共形地覆蓋封裝 膠體130,其中導電層140透過開口 136而覆蓋各開口 I% 的側壁136a’並接觸側壁136a所暴露出的接墊in，以連 接對應的接墊112。此外，可選擇性地進行一填充製程， 以一填充物138填充開口 136。 請參照圖4C與圖4D，可選擇性地進行一植球製程以 形成多個銲球150，以及進行上述的一切單製程，以獲得 多個獨立的封裝結構100。 又 圖5繪示本發明一實施例之半導體元件封裝結構的剖 .面圖。請參照圖5，一封裝結構50〇包括一線路基板u〇、 电子元件120、一封裝膠體13〇以及一導電層14〇。線路 基板Π0可為一積層板（laminate substrate)並具有一承載 面ll〇a與一底面110b，且具有至少一接墊112 (圖5繪示 一接墊112)，接墊112電性連接至導電層14〇。在此，接 墊112可位於線路基板11〇的承載面u〇a，並電性連接至 接地面或任何其他功能的平面或是參考平面。在本實施例 中’接塾—m與線路基板110的一頂線路層lls為一體成 型。電子兀件120可為-配置於承載面腕上並電性連接 至線路基板UG的晶片，且此晶片是透過多個導電凸塊18〇 而覆晶接合至線路基板11Q，或是可藉由其他可行的接合 =式接合至線路基板110(例如打線接合）。封裝躁體請 设蓋承載面110a並包覆承载面U0a上的電子元件120。 =裝膠體130包括—中心部132與—圍繞中心部132的周 邊部134’其中周邊部134的厚度T2小於中心部132的厚 1376779 ASEK2276-NEW-FIN AL-T W-20100520 度T1。舉例來說’ T2可小於約2/3的T1，例如約為1/1〇 〜2/3 1 Ή ’或是約為1/1〇〜1/2的Tl。周邊部134的厚 度T2只貝上可以是一致的，例如周邊部134的頂面13牝 實質上是平坦的。此外，對條狀龍結構進行—切單製程 以得封裝結構5〇0(如同圖1H所述），其中封裝膠體13〇 的周邊部m的-讎134a(u—側面134a)可與線路 基板110的一側壁119 (或一侧面119)丘平面。 封裝膠體130具有至少—位於周邊部134中的開口 136 (圖5緣示多個開π 136)以暴露出線路基板11〇的多 個接墊112。導電層140共形地覆蓋封裝膠體13〇並透過 p幵 1 口 136而連接線路基板110的接墊η:。導電廣⑽的 材質例如為銅、鉻、金、銀、鎳'銘、或是前述材質之合 金、錫、不_或焊料L 136暴露出對應的接塾112 的頂面112a，且導電廣14〇覆蓋開口 136的一侧壁13如 固及接塾_112的頂面112a。導電層14〇的詳細結構相似於 圖1F所示。再者，開口 136的詳細結構相似於圖3八〜圖 =所不。-由金屬或是不導電材料所構賴填充物 ^己置於各開口 136中。藉由暴露線路基板11G的接塾 =，導杨M0可電性連接至接地面或是線路基板ιι〇 ^他參考平面。舉例來說，可在封裝結構_建立一電性 途徑以作為電磁干擾屏蔽，而毋須使用外加的接地平 面。鲜球150配置於線路基板110的底面ll〇b。 園本發㈣—實關之轉體元件封裝結構纪 。’面圖。4參照圖6，封裝結構_相似於® 5的封裝驾 1376779 ASEK2276-NEW^FINAL-TW-201OO520 構500，兩者的差異之處在於接墊112位於線路基板110 的内層上’其中接塾112與第一内線路層117a或是第二内 3L117b為―體成型，且開σ 136貫穿封裝膠體13〇 、°邊^134以及線路基板110，而多個填充物138填滿 導電層140覆蓋各開口136的側壁撕， 並連接側壁136a所暴露出的各接墊112。 導^紐連接導電層與基板的接塾，可在使 以降低封裝膠體的部分厚度，如此一 ::，製程產量。在本實施例的封裝：： 層可有效地加強封|結構之電磁干ί 屏蔽的效果。此外，可增加封裝結構的可 種设计可相容於高頻元件的封裝結構， (radio frequency device)。 疋射頻元件 ，然本發明已以實施例揭露如上，然 本發明，任何所屬技術領域中具有通常知气去1限疋 本發明之精神和範圍内，當可作些許者’在不脫離 發明之保護範圍當視後附之申請專利範： 【圖式簡單說明】 圖1A〜圖1H繪示本發明—實施例 一 的製程示意圖。 半V體元件封裝 { S.1 17 1376779 ASEK2276-NEW-FINAL-TW-20100520 圖2示範性地繪示圖1E中的結構的立體圖。 圖3A〜圖3C繪示本發明一實施例之圖1E之結構的局 部上視圖。 圖4A〜圖4D繪示本發明另一實施例之半導體元件封 裝的製程中的某些步驟的示意圖。 圖5繪示本發明一實施例之半導體元件封裝結構的剖 面圖。 圖6繪示本發明另一實施例之半導體元件封裝結構的 剖面圖。 【主要元件符號說明】 100、500、600 :封裝結構 102 :線路基板條 110 :線路基板 110a :承載面 110b :底面 112 :接墊 112a、130a、134b :頂面 115 :頂線路層 117a :第一内線路層 117b :第二内線路層 119、130b、136a、134a :側壁（或側面） 120 :電子元件（或半導體元件） 130 :封裝膠體

Claims (1)

  1. ^ fei 民梦(更)正本 沏-3-26 七、 申請專利範圍： 1· 一種半導體元件封裝，包括： 〜線路基板，包括： 一承載面； 一底面，相對於該承載面；以及 一接墊； 板； -電子兀件，鄰近該承載面並電性連接至該線路基 扭_〜封裝膠體，鄰近該承载面並包覆該電子元件，診4+ 、多體包括一中心部與一圍繞該中心部的周邊部，其^ 該周邊部的厚度小於該中心部的厚度； ▲形成在該周邊部的一開口暴露出該線路基板的 5亥接塾； :導電層’共職覆蓋該封裝雜，並穿過該開口以 接4線路基板的該接墊；以及 一填充物，配置於該開口中。 2. 如申請專利範圍第1項所述之半導體元件封装， 其中： 、 該線路基板包括-側面，制伸於該承載面與該 底面之間； ' 該封裝膠體的該周邊部包括一侧面；以及 該周邊部的該側面實質上共平面於該線路基板的該側 面。 3. 如巾料職圍第丨項所述之半導體元件封裝， 20 1376779 其中該周邊部的厚度實質上相等。 4. 如申請專利範圍第1項所述之半導體元件封敦， 其中該開口暴露該接墊的一頂面，且該導電層覆蓋該開^口 的—側壁以及該接墊的該頂面。 "汗口 5.如申請專利範圍第4項所述之半導體元件封穿 其中該接墊鄰近該線路基板的該承載面。 、
    6·如申請專利範圍第1項所述之半導體元件封裝 其中： * 該接墊配置於該線路基板中； '該開口貫穿該封裝膠體的該周邊部以及該線路基板 該導電層覆蓋該開口的一侧壁以及連接該接墊， 墊暴露於該側壁。 7. 如申請專利範圍第6項所述之半導體元件封妒， 其中該接墊鄰近該承載面或鄰近該底面。 义，
    8. 如申請專利範圍第1項所述之半導體元件封驶 其中該接墊係接地。 、、， 9. 如申請專利範圍第1項所述之半導體元件封妒， 其中該開口包括一圓形孔洞、一線形開槽或是一環形溝^。 10. —種半導體元件封裝的製作方法，包括：v/ k供一線路基板條，該線路基板條包括： 一承載面； 一底面，相對於該承載面；以及 一線路基板； S 21 101-3-26 電早配fr電子元件，該電子元件鄰近該承載面，其中該 宅子凡件連接該線路基板； 人 電子封裝膠體’該封裝膠體鄰近該承載面並包覆該 ㈣1 =賴祕基㈣—邊緣對該封㈣體進行一半切 ’以形成該封裝膠體的一周邊部，該周邊部沿著 j路基板㈣邊緣延伸’其中該封裝雜的該周邊 厗度小於該封裝膠體的一中心部的厚度； q 签；在該周邊部形成—開σ，以暴露該線路基板的—接 成""導電層’以共形地覆蓋該封裝膠體，其中該導 電曰透過該開口而連接至該線路基板的該接墊；以及 配置一填充物於該開口中。 ^如申請專利範圍第10項所述之半導體元件 的I作方法，其中該周邊部的厚度實質上相等。 、 α如申請專利範㈣10項所述之半導體 ===更包括沿著該線路基板的該邊緣對該封裝^ ί _製程，以使該線路基板座兮 線路基板條的其他部分分離，並使關邊 ^ 的其他部分分離。 η郷體 13. 如申請專利範圍第1〇項所述之半導體元 的製作方法，其中形成該開口的方法包括雷射鑽孔。封裝 14. 如申請專利範圍第U項所述之半導體 的製作方法，其中該接㈣近魏路基板條賴承載面。、 1376779 1〇1·3-26 15. 如申請專利範圍第13項所述之半導體元件 的製作方法’其中該導電層覆蓋該開口的—側壁與該= 的一頂面。 、X塾 16. 如申請專利範圍第1〇項所述之半導體元件 的製作方法’其巾形成該開口的方法包括機械鑽孔。、、 17. 如申請專利範圍第16項所述之半導體元件
    ^製作方法’其中該接減置於該線路基板條的—内^ 中’且該開口貫㈣封轉體的該周邊部以及該線路基& .χ 丁兩号不』乾圍第16項所述之半導體元件封穿 作方法，其中該導電層覆蓋該開口的—側壁並連接i 露於該側壁的該接墊。 使恭 的制Γ 士 ”請專_圍第1G項所述之半導體元件封農 中^ 〉，更包括在形成該導電層之後填充該開口，i 電法包括電鍵-金屬材料或是印刷-非導
    S 23 1376779八、圓式: 〆年多月日修正替換頁
    S 1376779
    〇22ί %
    § g Ο g CD '—丽 § (S »r_g 二 5 V v i 〇 ^ t—丽 U §g i' 1376779
    1376779
    Dmcsa qm
    〇0U 061 I q〇£loocl § § 8i【061 8Π 1-Ί-Ψ_Λ—I-H CVJC2 Kl
    oil q〇u cvlu m JL丽 1376779
    ou q〇u ou oslCNJu s OL 丽
    S mem
    1376779
    Η
    丽
    CD ΓΌ 丽
    s 1376779 囑1囑_啤·_
    ^ ^ S S β
    ^ul ^22012
    I— Oil 2
    CVJU Ds s V寸丽 ou 0
    OU a寸® ou q〇u s Ds s 1376779
    V ^―· V
    0 0
    opoooo OU ,r t i 1 概 OU 0 0-0000 § Douoorol 不
    olooloRp o寸丽 trol § qi OSl s 09£l s 不 oouoofl οοίι 0U _ 0 £olDolocyQ 3 mria α寸丽 001 s 1376779
    1仙l g 參 g p 〇
    LO Μ g
    1376779 μ年？月么日修(更)正替換頁
    S
TW099116087A 2009-11-19 2010-05-20 Semiconductor device packages and manufacturing method thereof TWI376779B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/622,415 US8030750B2 (en) 2009-11-19 2009-11-19 Semiconductor device packages with electromagnetic interference shielding

Publications (2)

Publication Number Publication Date
TW201119003A TW201119003A (en) 2011-06-01
TWI376779B true TWI376779B (en) 2012-11-11

Family

ID=44010683

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099116087A TWI376779B (en) 2009-11-19 2010-05-20 Semiconductor device packages and manufacturing method thereof

Country Status (3)

Country Link
US (1) US8030750B2 (zh)
CN (1) CN102074516B (zh)
TW (1) TWI376779B (zh)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8841759B2 (en) * 2006-12-23 2014-09-23 Lg Innotek Co., Ltd. Semiconductor package and manufacturing method thereof
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) * 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
CN101960588A (zh) * 2008-03-14 2011-01-26 松下电器产业株式会社 半导体装置以及半导体装置的制造方法
WO2009144960A1 (ja) * 2008-05-30 2009-12-03 三洋電機株式会社 半導体モジュール、半導体モジュールの製造方法および携帯機器
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100110656A1 (en) 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8110902B2 (en) * 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8368185B2 (en) * 2009-11-19 2013-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI489610B (zh) 2010-01-18 2015-06-21 矽品精密工業股份有限公司 具電磁遮蔽之封裝結構之製法
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US9362196B2 (en) * 2010-07-15 2016-06-07 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
TWI540698B (zh) 2010-08-02 2016-07-01 日月光半導體製造股份有限公司 半導體封裝件與其製造方法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
KR101179399B1 (ko) * 2010-10-04 2012-09-04 삼성전기주식회사 크로스토크를 저감하기 위한 인쇄회로기판
US8520399B2 (en) * 2010-10-29 2013-08-27 Palo Alto Research Center Incorporated Stretchable electronics modules and circuits
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8654537B2 (en) * 2010-12-01 2014-02-18 Apple Inc. Printed circuit board with integral radio-frequency shields
US8279625B2 (en) 2010-12-14 2012-10-02 Apple Inc. Printed circuit board radio-frequency shielding structures
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8969136B2 (en) * 2011-03-25 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
TW201240058A (en) * 2011-03-28 2012-10-01 Universal Scient Ind Shanghai Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same
US9179538B2 (en) 2011-06-09 2015-11-03 Apple Inc. Electromagnetic shielding structures for selectively shielding components on a substrate
CN102509722A (zh) * 2012-01-06 2012-06-20 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN103219295B (zh) * 2012-01-20 2015-12-16 环旭电子股份有限公司 适形掩模封装结构及检测方法
US8937376B2 (en) 2012-04-16 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor packages with heat dissipation structures and related methods
CN102664170B (zh) * 2012-04-19 2015-06-17 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8704341B2 (en) 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US8653634B2 (en) 2012-06-11 2014-02-18 Advanced Semiconductor Engineering, Inc. EMI-shielded semiconductor devices and methods of making
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
TWI448224B (zh) * 2012-09-24 2014-08-01 Universal Scient Ind Shanghai 電子模組以及其製造方法
US8952503B2 (en) 2013-01-29 2015-02-10 International Business Machines Corporation Organic module EMI shielding structures and methods
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9837701B2 (en) 2013-03-04 2017-12-05 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna substrate and manufacturing method thereof
US9129954B2 (en) 2013-03-07 2015-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna layer and manufacturing method thereof
US9536850B2 (en) * 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
US9172131B2 (en) 2013-03-15 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna
CN104347535B (zh) * 2013-07-31 2017-05-24 环旭电子股份有限公司 电子封装模块及其制造方法
US9814166B2 (en) 2013-07-31 2017-11-07 Universal Scientific Industrial (Shanghai) Co., Ltd. Method of manufacturing electronic package module
US9881875B2 (en) 2013-07-31 2018-01-30 Universal Scientific Industrial (Shanghai) Co., Ltd. Electronic module and method of making the same
TWI554196B (zh) * 2013-07-31 2016-10-11 環旭電子股份有限公司 電子封裝模組及其製造方法
US9355864B2 (en) 2013-08-06 2016-05-31 Tel Nexx, Inc. Method for increasing adhesion of copper to polymeric surfaces
US10586771B2 (en) * 2013-12-16 2020-03-10 Utac Headquarters Pte, Ltd Conductive shield for semiconductor package
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
TWI557860B (zh) * 2014-07-08 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP6242763B2 (ja) * 2014-07-18 2017-12-06 Ｔｏｗａ株式会社 電子部品パッケージの製造方法
TWI553818B (zh) * 2014-08-08 2016-10-11 日月光半導體製造股份有限公司 電子封裝模組之製造方法以及電子封裝模組結構
US10242957B2 (en) * 2015-02-27 2019-03-26 Qualcomm Incorporated Compartment shielding in flip-chip (FC) module
USD772181S1 (en) * 2015-04-02 2016-11-22 Genesis Photonics Inc. Light emitting diode package substrate
US9461001B1 (en) 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
KR20170019023A (ko) * 2015-08-10 2017-02-21 에스케이하이닉스 주식회사 전자기 간섭 차폐부를 갖는 반도체 패키지 및 제조 방법
CN106711089A (zh) * 2015-11-12 2017-05-24 上海联星电子有限公司 Rb-igbt芯片的制作方法及rb-igbt芯片
KR102497577B1 (ko) 2015-12-18 2023-02-10 삼성전자주식회사 반도체 패키지의 제조방법
US9953929B2 (en) * 2016-03-18 2018-04-24 Intel Corporation Systems and methods for electromagnetic interference shielding
JP6597576B2 (ja) * 2016-12-08 2019-10-30 株式会社村田製作所 インダクタ、および、ｄｃ−ｄｃコンバータ
JP6974960B2 (ja) * 2017-04-21 2021-12-01 株式会社ディスコ 半導体パッケージの製造方法
US10978406B2 (en) * 2017-07-13 2021-04-13 Mediatek Inc. Semiconductor package including EMI shielding structure and method for forming the same
US10290678B2 (en) 2017-09-26 2019-05-14 Globalfoundries Singapore Pte. Ltd. Magnetic shielding package structure for MRAM device and method for producing the same
KR102574453B1 (ko) * 2018-09-03 2023-09-04 삼성전자 주식회사 우수한 열 방출 특성 및 전자기 차폐 특성을 갖는 반도체 패키지
KR102677777B1 (ko) * 2019-04-01 2024-06-25 삼성전자주식회사 반도체 패키지
KR20220003342A (ko) * 2020-07-01 2022-01-10 삼성전기주식회사 전자 소자 패키지 및 이의 제조방법

Family Cites Families (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439460A1 (de) * 1964-10-19 1968-12-12 Siemens Ag Elektrisches Bauelement,insbesondere Halbleiterbauelement,mit einer aus isolierendemStoff bestehenden Huelle
JPS59172253A (ja) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp 半導体装置
JPS59189142A (ja) * 1983-04-12 1984-10-26 Ube Ind Ltd 導電性熱可塑性樹脂組成物
US4814205A (en) * 1983-12-02 1989-03-21 Omi International Corporation Process for rejuvenation electroless nickel solution
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
FR2649530B1 (fr) * 1989-07-06 1994-04-29 Alsthom Gec Brin supraconducteur multifilamentaire
US5140745A (en) 1990-07-23 1992-08-25 Mckenzie Jr Joseph A Method for forming traces on side edges of printed circuit boards and devices formed thereby
US5557142A (en) 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
JP2616280B2 (ja) 1991-04-27 1997-06-04 株式会社村田製作所 発振器及びその製造方法
DE4340594C2 (de) * 1992-12-01 1998-04-09 Murata Manufacturing Co Verfahren zur Herstellung und zum Einstellen der Charakteristik eines oberflächenmontierbaren chipförmigen LC-Filters
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5355016A (en) 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
FI117224B (fi) * 1994-01-20 2006-07-31 Nec Tokin Corp Sähkömagneettinen häiriönpoistokappale, ja sitä soveltavat elektroninen laite ja hybridimikropiirielementti
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
JP3541491B2 (ja) * 1994-06-22 2004-07-14 セイコーエプソン株式会社 電子部品
US5677511A (en) 1995-03-20 1997-10-14 National Semiconductor Corporation Overmolded PC board with ESD protection and EMI suppression
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
DE29514398U1 (de) 1995-09-07 1995-10-19 Siemens AG, 80333 München Abschirmung für Flachbaugruppen
US5847930A (en) 1995-10-13 1998-12-08 Hei, Inc. Edge terminals for electronic circuit modules
JP3432982B2 (ja) * 1995-12-13 2003-08-04 沖電気工業株式会社 表面実装型半導体装置の製造方法
US5998867A (en) 1996-02-23 1999-12-07 Honeywell Inc. Radiation enhanced chip encapsulant
JP2938820B2 (ja) * 1996-03-14 1999-08-25 ティーディーケイ株式会社 高周波モジュール
US5694300A (en) 1996-04-01 1997-12-02 Northrop Grumman Corporation Electromagnetically channelized microwave integrated circuit
JP2850860B2 (ja) * 1996-06-24 1999-01-27 住友金属工業株式会社 電子部品の製造方法
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US6150193A (en) 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
JPH10284935A (ja) 1997-04-09 1998-10-23 Murata Mfg Co Ltd 電圧制御発振器およびその製造方法
US5895229A (en) * 1997-05-19 1999-04-20 Motorola, Inc. Microelectronic package including a polymer encapsulated die, and method for forming same
JP3834426B2 (ja) * 1997-09-02 2006-10-18 沖電気工業株式会社 半導体装置
US6566596B1 (en) * 1997-12-29 2003-05-20 Intel Corporation Magnetic and electric shielding of on-board devices
US5977626A (en) 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6194250B1 (en) * 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
JP3617368B2 (ja) * 1999-04-02 2005-02-02 株式会社村田製作所 マザー基板および子基板ならびにその製造方法
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6255143B1 (en) * 1999-08-04 2001-07-03 St. Assembly Test Services Pte Ltd. Flip chip thermally enhanced ball grid array
FR2799883B1 (fr) 1999-10-15 2003-05-30 Thomson Csf Procede d'encapsulation de composants electroniques
US6261680B1 (en) * 1999-12-07 2001-07-17 Hughes Electronics Corporation Electronic assembly with charge-dissipating transparent conformal coating
DE10002852A1 (de) * 2000-01-24 2001-08-02 Infineon Technologies Ag Abschirmeinrichtung und elektrisches Bauteil mit einer Abschirmeinrichtung
US20010033478A1 (en) 2000-04-21 2001-10-25 Shielding For Electronics, Inc. EMI and RFI shielding for printed circuit boards
US6757181B1 (en) * 2000-08-22 2004-06-29 Skyworks Solutions, Inc. Molded shield structures and method for their fabrication
US6448632B1 (en) 2000-08-28 2002-09-10 National Semiconductor Corporation Metal coated markings on integrated circuit devices
US6586822B1 (en) * 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
TW454321B (en) * 2000-09-13 2001-09-11 Siliconware Precision Industries Co Ltd Semiconductor package with heat dissipation structure
CN2457740Y (zh) 2001-01-09 2001-10-31 台湾沛晶股份有限公司 集成电路晶片的构装
US20020093108A1 (en) * 2001-01-15 2002-07-18 Grigorov Ilya L. Flip chip packaged semiconductor device having double stud bumps and method of forming same
US6472743B2 (en) 2001-02-22 2002-10-29 Siliconware Precision Industries, Co., Ltd. Semiconductor package with heat dissipating structure
JP3718131B2 (ja) 2001-03-16 2005-11-16 松下電器産業株式会社 高周波モジュールおよびその製造方法
US6900383B2 (en) * 2001-03-19 2005-05-31 Hewlett-Packard Development Company, L.P. Board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces
JP3878430B2 (ja) * 2001-04-06 2007-02-07 株式会社ルネサステクノロジ 半導体装置
TW495943B (en) * 2001-04-18 2002-07-21 Siliconware Precision Industries Co Ltd Semiconductor package article with heat sink structure and its manufacture method
US6614102B1 (en) 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
JP3865601B2 (ja) * 2001-06-12 2007-01-10 日東電工株式会社 電磁波抑制体シート
JP3645197B2 (ja) 2001-06-12 2005-05-11 日東電工株式会社 半導体装置およびそれに用いる半導体封止用エポキシ樹脂組成物
US6740959B2 (en) * 2001-08-01 2004-05-25 International Business Machines Corporation EMI shielding for semiconductor chip carriers
US7126218B1 (en) * 2001-08-07 2006-10-24 Amkor Technology, Inc. Embedded heat spreader ball grid array
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
TW550997B (en) 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
KR100431180B1 (ko) * 2001-12-07 2004-05-12 삼성전기주식회사 표면 탄성파 필터 패키지 제조방법
JP2003273571A (ja) 2002-03-18 2003-09-26 Fujitsu Ltd 素子間干渉電波シールド型高周波モジュール
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
CN1323435C (zh) * 2002-07-19 2007-06-27 松下电器产业株式会社 模块部件
JP3738755B2 (ja) * 2002-08-01 2006-01-25 日本電気株式会社 チップ部品を備える電子装置
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
JP4178880B2 (ja) * 2002-08-29 2008-11-12 松下電器産業株式会社 モジュール部品
US6781231B2 (en) * 2002-09-10 2004-08-24 Knowles Electronics Llc Microelectromechanical system package with environmental and interference shield
US7205647B2 (en) * 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
US6962869B1 (en) 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment
WO2004060034A1 (ja) * 2002-12-24 2004-07-15 Matsushita Electric Industrial Co., Ltd. 電子部品内蔵モジュール
US20040150097A1 (en) * 2003-01-30 2004-08-05 International Business Machines Corporation Optimized conductive lid mounting for integrated circuit chip carriers
TWI235469B (en) * 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
US7187060B2 (en) * 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
CN1774959A (zh) 2003-04-15 2006-05-17 波零公司 用于印刷电路板的电磁干扰屏蔽
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
JP4377157B2 (ja) * 2003-05-20 2009-12-02 Ｎｅｃエレクトロニクス株式会社 半導体装置用パッケージ
US6867480B2 (en) * 2003-06-10 2005-03-15 Lsi Logic Corporation Electromagnetic interference package protection
TWI236118B (en) 2003-06-18 2005-07-11 Advanced Semiconductor Eng Package structure with a heat spreader and manufacturing method thereof
CN1810068A (zh) * 2003-06-19 2006-07-26 波零公司 印刷电路板的emi吸收屏蔽
KR100541084B1 (ko) * 2003-08-20 2006-01-11 삼성전기주식회사 표면 탄성파 필터 패키지 제조방법 및 그에 사용되는패키지 시트
JP2005072095A (ja) * 2003-08-20 2005-03-17 Alps Electric Co Ltd 電子回路ユニットおよびその製造方法
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
US6943423B2 (en) 2003-10-01 2005-09-13 Optopac, Inc. Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof
US6992400B2 (en) * 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US7276724B2 (en) * 2005-01-20 2007-10-02 Nanosolar, Inc. Series interconnected optoelectronic device module assembly
US7327015B2 (en) * 2004-09-20 2008-02-05 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP4453509B2 (ja) * 2004-10-05 2010-04-21 パナソニック株式会社 シールドケースを装着された高周波モジュールとこの高周波モジュールを用いた電子機器
US7629674B1 (en) 2004-11-17 2009-12-08 Amkor Technology, Inc. Shielded package having shield fence
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
US7656047B2 (en) * 2005-01-05 2010-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method
JP2006190767A (ja) * 2005-01-05 2006-07-20 Shinko Electric Ind Co Ltd 半導体装置
EP1860694A1 (en) 2005-03-16 2007-11-28 Yamaha Corporation Semiconductor device, semiconductor device manufacturing method and cover frame
US7446265B2 (en) 2005-04-15 2008-11-04 Parker Hannifin Corporation Board level shielding module
JP4614278B2 (ja) * 2005-05-25 2011-01-19 アルプス電気株式会社 電子回路ユニット、及びその製造方法
US8186048B2 (en) * 2007-06-27 2012-05-29 Rf Micro Devices, Inc. Conformal shielding process using process gases
US7451539B2 (en) 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
WO2007060784A1 (ja) * 2005-11-28 2007-05-31 Murata Manufacturing Co., Ltd. 回路モジュールの製造方法および回路モジュール
US7445968B2 (en) 2005-12-16 2008-11-04 Sige Semiconductor (U.S.), Corp. Methods for integrated circuit module packaging and integrated circuit module packages
US7342303B1 (en) * 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
JP5598787B2 (ja) * 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
DE102006019080B3 (de) * 2006-04-25 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Herstellungsverfahren für ein gehäustes Bauelement
US20080128890A1 (en) * 2006-11-30 2008-06-05 Advanced Semiconductor Engineering, Inc. Chip package and fabricating process thereof
JP5120266B6 (ja) 2007-01-31 2018-06-27 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US7745910B1 (en) * 2007-07-10 2010-06-29 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
US20090035895A1 (en) * 2007-07-30 2009-02-05 Advanced Semiconductor Engineering, Inc. Chip package and chip packaging process thereof
US7651889B2 (en) * 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
EP2051298B1 (en) * 2007-10-18 2012-09-19 Sencio B.V. Integrated Circuit Package
US7723157B2 (en) * 2007-12-28 2010-05-25 Walton Advanced Engineering, Inc. Method for cutting and molding in small windows to fabricate semiconductor packages
US8022511B2 (en) 2008-02-05 2011-09-20 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8350367B2 (en) 2008-02-05 2013-01-08 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
US8212339B2 (en) 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8120152B2 (en) 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US7906371B2 (en) 2008-05-28 2011-03-15 Stats Chippac, Ltd. Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
US7772046B2 (en) 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
TWI453877B (zh) * 2008-11-07 2014-09-21 Advanced Semiconductor Eng 內埋晶片封裝的結構及製程
US7829981B2 (en) * 2008-07-21 2010-11-09 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US20100110656A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US7741151B2 (en) * 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
US20100207257A1 (en) 2009-02-17 2010-08-19 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US8110902B2 (en) 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof

Also Published As

Publication number Publication date
CN102074516A (zh) 2011-05-25
US8030750B2 (en) 2011-10-04
CN102074516B (zh) 2012-07-25
TW201119003A (en) 2011-06-01
US20110115066A1 (en) 2011-05-19

Similar Documents

Publication Publication Date Title
TWI376779B (en) Semiconductor device packages and manufacturing method thereof
CN207781575U (zh) 经封装的电子装置
US8368185B2 (en) Semiconductor device packages with electromagnetic interference shielding
KR101587561B1 (ko) 리드프레임 어레이를 구비하는 집적회로 패키지 시스템
TWI225696B (en) Semiconductor package and method for manufacturing the same
US8873244B2 (en) Package structure
KR20150099118A (ko) 자기 차폐부를 가지는 반도체 패키지 제조방법
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
US10600743B2 (en) Ultra-thin thermally enhanced electro-magnetic interference shield package
US9589906B2 (en) Semiconductor device package and method of manufacturing the same
TW200919693A (en) Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same
TWI500130B (zh) 封裝基板及其製法暨半導體封裝件及其製法
TW201110247A (en) Method of forming package structure
JP2010263080A (ja) 半導体装置
TW200805590A (en) Semiconductor package and fabrication method thereof
CN208767298U (zh) 传感器封装
TW201250976A (en) Semiconductor structure with recess and manufacturing method thereof
TWI681529B (zh) 樹脂密封型半導體裝置及其製造方法
CN211088270U (zh) 芯片封装结构和光学传感器
EP2613349B1 (en) Semiconductor package with improved thermal properties
CN207250482U (zh) 晶圆级芯片封装结构
TW201015674A (en) Package and fabricating method thereof
US12057378B2 (en) Semiconductor devices and methods of manufacturing semiconductor devices
JP2006165109A (ja) 半導体装置及びその製造方法
TWI314362B (en) Manufacturing method of package substrate for image sensor and its structure