CN101658078A - 小间距微触点及其形成方法 - Google Patents
小间距微触点及其形成方法 Download PDFInfo
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- CN101658078A CN101658078A CN200880011888A CN200880011888A CN101658078A CN 101658078 A CN101658078 A CN 101658078A CN 200880011888 A CN200880011888 A CN 200880011888A CN 200880011888 A CN200880011888 A CN 200880011888A CN 101658078 A CN101658078 A CN 101658078A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 47
- 238000004377 microelectronic Methods 0.000 claims abstract description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 69
- 239000002184 metal Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 230000005855 radiation Effects 0.000 claims description 14
- 230000008859 change Effects 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000004224 protection Effects 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims 7
- 239000010410 layer Substances 0.000 description 64
- 230000008569 process Effects 0.000 description 30
- 238000010586 diagram Methods 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000000565 sealant Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002195 soluble material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- Pressure Sensors (AREA)
Abstract
一种方法包括:向加工过程中的衬底10施加最终耐蚀刻材料34,使得所述最终耐蚀刻材料34至少部分覆盖与所述衬底10一体并从所述衬底的表面18向上突出的第一微触点部分32;以及蚀刻所述衬底10的表面以便留下所述第一微触点部分32下方并与之一体的第二微触点部分36,所述最终耐蚀刻材料34至少部分保护所述第一微触点部分32在进一步蚀刻步骤中不被蚀刻。一种微电子单元,包括:衬底10,以及多个沿竖直方向从所述衬底10突出的微触点38,每个微触点38包括与所述衬底相邻的基部区域42和远离所述衬底的顶端区域32,每个微触点38具有水平尺度,所述水平尺度是所述基部区域42中竖直位置的第一函数,且是所述顶端区域32中竖直位置的第二函数。
Description
对相关申请的交叉引用
本申请要求享有2007年3月13日提交的美国专利申请No.11/717,587的优先权,该申请是2005年6月24日提交的美国专利申请No.11/166,982的部分延续,后者要求享有2004年6月25日提交的美国临时专利申请No.60/583,109的申请日权益。申请No.11/166,982也是2004年10月6日提交的美国专利申请No.10/959,465的部分延续。申请No.10/959,465还要求享有2003年10月6日提交的美国临时专利申请No.60/508,970、2003年12月30日提交的60/533,210、2003年12月30日提交的60/533,393以及2003年12月30日提交的60/533,437的申请日权益。据此通过引用将所有前述申请的公开并入于此。
背景技术
本发明涉及微电子封装、制造微电子封装所用的部件以及制造封装和部件的方法。
细长柱或引脚形式的微触点元件可以用于将微电子封装连接到电路板以及用于微电子封装中的其他连接。在一些情况下,通过蚀刻包括一个或多个金属层的金属结构来形成微触点。蚀刻工艺限制了微触点的尺寸。常规的蚀刻工艺通常不能形成高度与最大宽度比(在此称为“高宽比”)大的微触点。一直难以或不能形成具有相当高度且间距或相邻微触点之间的跨度非常小的微触点阵列。此外,通过常规蚀刻工艺形成的微触点配置受到限制。
出于这些和其他原因,希望有进一步改善。
发明内容
在一个实施例中,一种形成微触点的方法包括(a)在衬底的顶表面上的选定位置处提供第一耐蚀刻材料;(b)在未被所述第一耐蚀刻材料覆盖的位置处蚀刻所述衬底的顶表面,由此在所述选定位置处形成从所述衬底向上突出的第一微触点部分;(c)在所述第一微触点部分上提供第二耐蚀刻材料;以及(d)进一步蚀刻所述衬底以在所述第一微触点部分下方形成第二微触点部分,所述第二耐蚀刻材料至少部分保护所述第一微触点部分在所述进一步蚀刻步骤期间不被蚀刻。在另一个实施例中,一种形成微触点的方法包括:(a)向加工过程中的衬底施加最终耐蚀刻材料,使得所述最终耐蚀刻材料至少部分覆盖与所述衬底一体并从所述衬底的表面向上突出的第一微触点部分;以及(b)蚀刻所述衬底的表面,以便留下所述第一微触点部分下方并与之一体的第二微触点部分,所述最终耐蚀刻材料至少部分保护所述第一微触点部分在所述进一步蚀刻步骤期间不被蚀刻。
在又一实施例中,一种微电子单元包括:(a)衬底;以及(b)多个沿竖直方向从所述衬底突出的微触点,每个微触点包括与所述衬底相邻的基部区域和远离所述衬底的顶端区域,每个微触点具有水平尺度,所述水平尺度是所述基部区域中竖直位置的第一函数,且是所述顶端区域中竖直位置的第二函数。
在又一实施例中,一种微电子单元包括:衬底,多个沿竖直方向从所述衬底突出的微触点,其中两个相邻微触点之间的间距小于150微米。
在又一实施例中,一种微电子单元包括:(a)衬底;以及(b)多个沿竖直方向从所述衬底突出的细长微触点,每个微触点包括与衬底相邻的基部区域和远离所述衬底的顶端区域,每个微触点具有轴以及环形表面,所述环形表面在所述竖直方向上沿着所述轴向着或远离轴倾斜,使得所述环形壁的斜率在所述顶端区域和所述基部区域之间的边界处突变。
在另一个实施例中,一种微电子单元包括(a)衬底;以及(b)多个沿竖直方向从所述衬底突出的微触点,每个微触点具有与所述衬底相邻的近侧部分和在竖直方向上从所述近侧部分远离所述衬底延伸的细长远侧部分,所述柱的宽度在所述近侧部分和远侧部分之间的接合处以阶梯式的方式增大。
附图说明
图1是衬底的示意图。
图2是具有光刻胶层的图1的衬底的不意图。
图3是具有光刻胶层和掩模的图1的衬底的透视示意图。
图4是被蚀刻的图1衬底的示意图。
图5是具有第二光刻胶的图1的衬底的示意图。
图6是第二光刻胶已显影的图1的衬底的示意图。
图7是被第二次蚀刻的图1衬底的示意图。
图8A-8D是微触点的范例轮廓。
图9是描绘第一实施例的流程图。
图10是描绘第二实施例的流程图。
图11是应用中的多层衬底的示意图。
图12是微电子单元的示意图。
图13是两个相邻微电子单元的示意图。
图14是微电子组件的示意图。
图15是根据本发明另一个实施例的微电子组件的示意图。
图16是具有额外柱部分的图15的组件的示意图。
具体实施方式
介绍第一方法或实施例。图1是三元金属衬底10的示意图。三元金属衬底10具有迹线层12、蚀刻停止层14、厚层16和顶表面18。迹线层12和厚层16可以由容易蚀刻的第一金属,例如铜形成,而蚀刻停止层14可以由诸如镍的金属形成,镍基本可以抵抗用于蚀刻铜的蚀刻。尽管提到了铜和镍,但衬底10也可以由任何期望的适当材料形成。
图2是具有第一光刻胶层20的图1的三元金属衬底10的示意图。第一光刻胶20沉积于顶表面18上。第一光刻胶20可以是在暴露于诸如光的辐射时硬化或发生化学反应的任何类型材料。于是,可以使用任何耐蚀刻材料。也可以使用正性和负性光刻胶,它们是现有技术中公知的。如本文所使用的,相对于微电子元件,而不是基于重力的方向来理解术语“顶部”、“底部”和其他方向性术语。
图3是具有第一光刻胶层20和掩模22的图1的三元金属衬底的透视示意图。掩模22常常是被称为光掩模或荫罩的其上印刷有不透明区的透明板,在掩模22上生成具有被掩模22覆盖的区域的图案24,用附图标记26表示之,以及未被掩模22覆盖的区域,用附图标记28表示之。分别具有被覆盖和未被覆盖区域26和28的图案24允许选择性向辐射暴露第一光刻胶20的多个部分。
一旦将掩模22放到第一光刻胶20顶部,就提供辐射。最常见的辐射形式为紫外线光。这种辐射使未覆盖区域28处的第一光刻胶20曝光,使得未覆盖区域28不可溶。在使用负性光刻胶时是相反的情况:覆盖的区域26变得不可溶。在对第一光刻胶20曝光后,去除掉掩模22。然后利用溶液冲洗,对第一光刻胶20进行显影,溶液去除掉第一光刻胶20未变为不可溶的位置中的第一光刻胶20。于是,光刻胶的曝光和显影在衬底10的表面18顶部留下不可溶材料的图案。这种不可溶材料的图案复制了掩模22的图案24。
在光刻胶曝光和显影之后,如图4所示蚀刻衬底。一旦达到一定深度的蚀刻,就中断蚀刻过程。例如,可以在预定时间之后终止蚀刻过程。蚀刻过程在厚层16处留下从衬底10向上突出的第一微触点部分32。由于蚀刻剂侵蚀厚层16,因此它去除掉第一光刻胶20边缘下方的材料,允许第一光刻胶20从第一微触点部分32顶部横向突出,用悬突体30表示之。第一光刻胶20保留在如掩模22确定的特定位置处。
一旦将厚层16蚀刻到期望深度,在三元金属衬底10上沉积第二层光刻胶34(图5)。在这种情况下,在此前已经蚀刻掉厚层16的位置向厚层16上沉积第二光刻胶34。于是,第二光刻胶34也覆盖第一微触点部分32。如果使用电泳光刻胶,由于其固有的化学性质,第二光刻胶34不会沉积到第一光刻胶20上。
在下一步,将具有第一和第二光刻胶20和34的衬底暴露于辐射,然后对第二光刻胶显影。如图6所示,第一光刻胶20在厚层16的部分上方横向突出,由悬突体30表示。该悬突体30防止第二光刻胶34被暴露于辐射,于是防止其被显影和去除,导致第二光刻胶34的一部分粘附到第一微触点部分32。于是,第一光刻胶20充当了第二光刻胶34的掩模。通过冲洗使第二光刻胶34显影,以便去除暴露于辐射的第二光刻胶34。这在第一微触点部分32上留下第二光刻胶34的未曝光部分。
一旦已经对第二光刻胶34的部分曝光和显影,则执行第二蚀刻过程,去除三元金属衬底10的厚层16的额外部分,由此如图7所示在第一微触点部分32下方形成第二微触点部分36。在该步骤期间,仍然粘附于第一微触点部分32的第二光刻胶34保护第一微触点部分32,以免其再次被蚀刻。
可以根据需要将这些步骤重复任意次数,以生成优选的高宽比和间距,形成第三、第四或第n微触点部分。在到达蚀刻停止层14时,可以停止该过程。作为最后步骤,可以分别整体剥离第一和第二光刻胶20和34。
这些过程获得了图8A到8D所示的微触点38。这些图还示出了利用这里所述的过程可以实现的各种轮廓。参考图8A-8C,微触点38具有也称为顶端区域的第一部分32和也称为基部区域的第二部分36。假设上述步骤中使用的第一光刻胶点是圆形的,每个微触点一般将是绕中心轴51(图8A)的回转体形式,中心轴51沿着竖直或Z方向从衬底的其余部分向上且大致垂直于蚀刻停止层14的平面延伸。第一和第二部分的宽度或直径X随着每个部分之内Z或高度方向上的位置变化。换言之,在第一部分之内,X=F1(Z),在第二部分之内,X=F2(Z)。在第一和第二部分之间的边界52处斜率或dX/dZ可能会突变。微触点的具体功能以及(因此)形状由第一和第二蚀刻步骤中使用的蚀刻条件决定。例如,可以改变蚀刻剂的组分和蚀刻温度以改变蚀刻剂侵蚀金属层的速率。而且,可以改变蚀刻剂与金属层的接触的机械性质。可以强制将蚀刻剂向衬底喷射,或者可以将衬底浸入蚀刻剂中。在蚀刻第一和第二部分期间的蚀刻条件可以相同或不同。
在图8A中所示的微触点中,第一部分32具有环形表面44,该表面在向下方向上向外张开,因此斜率或dX/dZ的大小在向下方向上增大。第二部分36也具有向外张开的环形表面46;第二部分的斜率或dX/dZ的大小在边界52处最小,沿着朝向柱基部的方向逐渐增大。在边界52处斜率有很大变化。在微触点与层14结合的微触点基部,第二部分的最大宽度或直径X显著大于第一部分的最大宽度或直径。在图8B中,第二部分36的最大宽度仅稍微大于第一部分32的最大宽度。而且,第二部分在柱基部和边界52之间的位置具有最小宽度,因此宽度沿着向上的方向逐渐减小到最小,然后从最小沿着向上方向到边界52逐渐增加。通常将这种形状称为“冷却塔”形状。在图8B的微触点中,在部分之间的边界52处斜率或dX/dZ改变符号。在图8C中,第二部分36在接近其微触点基部处具有其最小宽度。
最后,图8D示出了具有超过两部分的微触点38的轮廓。在将这里所述的过程步骤执行很多次的情况下,可以获得这种轮廓。于是,可以看出,这种特定的微触点38具有四个部分,分别是第一和第二部分32和36,以及第三和第四部分40和42。这四个部分可以具有任何尺度,根据需要可以比另一部分更宽或更细。在这种情况下,可以有多于一个边界。图8A-8D仅仅是典型轮廓,可以实现各种轮廓。尽管在图8A-8D的每个图中绘示了仅包括两个微触点或柱的阵列,但在实践中可以形成包括很多柱的柱阵列。在图8A-8D的每幅图中所示的实施例中,阵列中所有的微触点或柱都是由单个金属层16(图1)形成的。每个微触点在微触点基部覆盖蚀刻停止层14的一部分,在这里微触点连接到金属层12。如下文所述,通常在微触点之间的区域中去除蚀刻停止层14,通常蚀刻金属层12或以其他方式处理其以将其转换成连接到微触点的迹线或其他导电特征。然而,每个微触点的主体,从其基部到其顶端,是一个整体,没有诸如焊缝的接头,并且整体具有基本均匀的组分。而且,因为处于微触点远离层12和14的末端的微触点顶端表面18’是金属层16(图1)原顶表面18的一部分,因此这些顶端表面基本是平坦和水平的,所有微触点的顶端表面基本彼此共面。
在替代实施例中,在第一蚀刻步骤之后不是仅去除选定位置的第一光刻胶20,而是可以去除整个第一光刻胶20。在这种情况下,可以在衬底10的整个表面上沉积第二光刻胶34。然后将掩模22置于第二光刻胶34上。必需要正确对准掩模22,以便仅暴露第一微触点部分32上先前曝光的位置。然后对第二光刻胶34显影,并可以在衬底10上进行进一步蚀刻。
图9是示出了第一实施例的流程图。从步骤100开始,提供衬底。然后,在步骤102,向衬底上沉积光刻胶n。然后,在步骤104,将掩模置于光刻胶n顶部。在步骤106,将光刻胶n暴露于辐射。接下来,在步骤108,去除掩模,然后在步骤110,在选定位置对光刻胶n显影,并蚀刻衬底。
接下来,在步骤112沉积另一光刻胶,被称为n+1。然后,在步骤114,将该n+1光刻胶暴露于辐射。接下来,在步骤116,在选定位置去除光刻胶n+1,再次蚀刻衬底。然后,在步骤118评估是否实现了期望的微触点高度。如果尚未实现期望的微触点高度,在步骤120,过程返回到步骤112,向衬底上沉积另一光刻胶。如果在步骤122实现了期望高度,然后在步骤124去除剩余的光刻胶,工艺结束。
图10是描绘第二实施例的流程图。第二实施例的步骤200-210与第一实施例的步骤100-110相同。然而,在步骤212,去除整个光刻胶n。然后,在步骤214,向衬底上沉积另一层光刻胶n+1。接下来,在步骤216将掩模放回到衬底上。在该步骤期间,必需要对准掩模,使其图案与将掩模放在光刻胶n上时位于基本相同的位置。接下来,在步骤218,将光刻胶n+1暴露于辐射,并去除掩模。
接下来,在步骤220中,选择性去除光刻胶n+1并再次蚀刻衬底。也可以重复这一过程,直到实现期望的微触点高度。于是,在步骤222,评估是否已实现期望的微触点高度。如果在步骤224尚未实现优选高度,那么过程返回到步骤212,在步骤212,整体去除光刻胶,并沉积另一光刻胶n+1,在其上继续步骤。然而,如果在步骤224已实现期望高度,则在步骤228去除剩余光刻胶,过程结束。
可以将蚀刻停止层14和薄层12统一为电介质层,然后可以蚀刻薄层12以形成迹线,以便提供具有连接到迹线的微触点并具有从电介质层突出的微触点的部件。例如,可以将这种结构用作半导体芯片封装的元件。例如,可以使用2005年12月27日提交的美国专利申请No.11/318,822,在此通过引用将其公开内容并入本文。
这里所述的结构可以是多层衬底10的一体部分,例如,多层衬底10的顶层,如图11所示。可以将微触点38焊接到管芯54。焊料56可围绕微触点38一部分进行吸附。吸附实现了微触点38和管芯54之间非常好的接触。除焊接56之外,也可以使用其他键合工艺。微触点38的周围是底填料58,用于将管芯54粘合到微触点38和衬底10。根据需要可以使用任何类型的底填料58,或可以省去底填料58。在微触点38下方为迹线60和电介质层62。端子64设置于衬底10的底部。
某些封装包括堆叠的微电子芯片。这使得封装能够在衬底上占据小于堆叠中芯片总表面积的表面积。可以将包括利用本文所述过程制造的微触点的封装堆叠起来。参考共同待审的2005年5月27日提交的美国专利申请No.11/140,312和美国专利No.6,782,610,在此通过引用将其公开并入。可以用这里论述的过程替换在这些公开内容中教导的微触点蚀刻步骤。
尽管上文论述了三元金属衬底,但可以使用具有任意数量层的适当衬底,例如单种金属。此外,不使用光刻胶,可以使用耐蚀刻金属,例如金,或其他对用于蚀刻厚金属层的蚀刻剂基本能抵抗的金属。例如,可以使用耐蚀刻金属替代上述第一光刻胶20。可以在向期望点位置施加诸如有孔光刻胶的掩模之后,向厚层16顶部电镀耐蚀刻金属点。在向厚层顶部电镀耐蚀刻金属之后,蚀刻厚层以形成如上所述的微触点。耐蚀刻金属可以留在微触点顶端原地。在将耐蚀刻金属用作第二耐蚀刻材料(替代上述第二光刻胶34)的情况下,可以使用掩模将第二耐蚀刻金属的沉积仅限制到微触点的第一部分32,使得微触点之间的区域保持没有耐蚀刻金属。或者,可以在蚀刻第一微触点部分32时去除整个第一层耐蚀刻金属,然后可以沉积第二层耐蚀刻金属,以保护第一微触点部分32。
参考图12,微电子单元70被图示为具有微触点72。微触点72具有蚀刻停止层74。微触点72从已经形成为迹线76的金属层竖直突出。迹线76之间可以有间隙或空间78。第一层电介质80可以粘附于与迹线76相邻的单元70的底面。第一层电介质80中的开口82允许迹线76形成电子接触。第二层电介质84可以形成于单元70的顶面上。
从这些工艺形成的微触点可以具有从大约40微米到大约200微米范围内的典型高度。此外,微触点之间典型的间距可以小于200微米,优选小于150微米。具体而言,参考图13,示出了两个具有顶端直径d和微触点高度h的微触点。由两个微触点的纵轴之间的距离界定间距P。在很多应用中,尤其是使用微触点连接到半导体芯片的触点时,例如在下文参考图14所述的结构中,希望提供小间距。然而,在通过单次蚀刻过程由单个金属层形成微触点的过程中,使间距P小于一定最小间距P0(P0等于直径d加高度h的和)通常是不实际的。于是,P0=d+h。理论上,可以通过减小顶端直径d来减小最小间距。然而,不可能使顶端直径小于零。此外,在很多情况下,不希望将顶端直径减小到低于大约20或30微米。例如,引脚顶端和用于在蚀刻期间保护顶端的光刻胶点之间的粘附力与顶端面积成正比,因此与顶端直径的平方成正比。因此,利用非常小的顶端直径,可以在处理期间移开光刻胶点。于是,利用常规工艺,难以形成具有非常小间距的微触点。
然而,使用所述工艺的微触点之间的间距可以小于P0(P<P0),例如P=(0.9)P0或更小。例如,如果顶端的直径d为30微米,高度h为60微米,常规工艺将实现90微米的间距P0。然而,这里所述的工艺具有至少两次蚀刻,能够实现大约80微米或更小的间距P。换言之,多步蚀刻过程能够由单金属层形成具有常规蚀刻过程无法实现的间距、顶端直径和高度组合的一体金属微触点或柱。随着蚀刻步骤数量增大,对于给定顶端直径和高度而言的最小可实现间距减小。
现在参考图14,示出了微电子封装90,其使用了具有如上所述的微触点38的封装元件或芯片载体。芯片载体包括第一电介质层62,第一电介质层62可以由诸如聚酰亚胺、BT树脂或通常用于芯片载体的类型的其他电介质材料形成。芯片载体还包括连接到一些或全部微触点38的迹线60。迹线包括端子61。微触点从电介质层62的第一侧突出,如从图14中所看到的,面向上方。电介质层62具有开口82,端子61通过开口82在第一电介质层62的第二或面向下方的表面处露出。载体还包括任选的第二电介质层84。
微触点38的顶端键合到诸如半导体芯片或管芯54的微电子元件的触点55。例如,可以将微触点的顶端焊接键合到微电子元件的触点55。可以采用其他键合过程,例如低共熔键合或扩散键合。封装后得到的微电子元件使得微电子元件上的一些或全部触点55通过微触点和迹线连接到端子61。可以通过将端子61键合到电路板上的焊盘94来将封装的微电子元件安装到电路面板92,例如印刷电路板。例如,可以利用焊球96在开口82处将电路面板92上的焊盘94焊接到端子61。
即使在触点55密集分布的情况下,微触点38和微电子元件的触点55之间的连接也能够提供可靠的连接。如上所述,可以形成具有合理顶端直径和高度的微触点38。可感知的顶端直径能够在每个微触点的顶端和微电子元件的触点之间提供基本的键合面积。在使用中,芯片54相对于电路面板92不同的热膨胀和收缩可以被微触点38的弯折和倾斜容纳。这种动作因微触点的高度而增强。此外,因为微触点是由公共金属层形成的,所以微触点的高度是均匀的,处于非常紧密的容限之内。这有助于在微触点顶端和芯片或其他微电子元件的触点之间衔接和形成牢固的键合。
芯片载体的结构可以变化。例如,芯片载体可以仅包括一个电介质层。迹线可以设置于电介质层的任一侧。或者,芯片载体可以包括多层电介质,且可以包括多层迹线以及其他特征,例如导电接地平面。
用于本发明另一实施例的过程使用了具有从诸如电介质层502的表面的表面526突出的柱部分550(图15)的结构。柱部分550可以由任何工艺形成,但最好通过类似于上文所述那些的蚀刻工艺来形成。在形成部分550之后,可以在柱部分550的顶端533上涂覆金属或其他导电层502。例如,可以在包括部分550的结构上层压层502,并将其以冶金方式键合到柱部分550的顶端。选择性处理层502,以便去除远离柱部分550的层材料,但留下覆盖柱部分550的层厚的至少一部分,由此形成与柱部分550对准的额外柱部分504(图16),从而形成合成微触点,每个合成微触点包括靠近衬底的近侧柱部分550和远离衬底的远侧柱部分504,远侧部分沿竖直或Z方向从近侧部分突出。应用于层502的处理可以包括如上所述使用与柱部分550对准的耐蚀刻材料506的点的蚀刻过程。可以施加诸如电介质密封剂508的保护层以在蚀刻层502之前覆盖柱部分550。或者或额外地,柱部分550可以在蚀刻层502之前被电镀或以其他方式覆盖有耐蚀刻导电材料,例如镍或金。
可以重复构建后续柱部分的过程,以在部分504上形成额外部分,因此可以形成基本任何长度的微触点。长的微触点实现了柱顶端更大的弹性和运动。当在已形成的柱部分周围原地留下一个或多个电介质密封剂层,例如图15和16中的层508时,希望密封剂是顺从的,从而其基本不限制柱的弯曲。在其他实施例中,在使用部件之前去除密封剂。尽管结合类似于上述的电介质衬底522和迹线528例示了微触点,但可以将该过程用于在基本任何结构上制造微触点。
如图16所示,每个微触点都具有水平或宽度尺度x,x在近侧柱部分550的竖直或z方向范围上变化,在近侧柱部分550和远侧部分504之间的接合处基本以阶梯方式突然增大,并沿着远侧部分的竖直范围变化。宽度随着竖直位置的变化斜率也在柱部分之间的接合处突变。每个柱部分之内水平或宽度尺度变化的图案取决于用于蚀刻或以其他方式形成这种柱部分的过程。例如,在另一实施例中,可以通过如上所述的多阶段蚀刻过程形成远侧柱部分504,使得每个远侧柱部分包括不同的子部分,子部分具有定义宽度x沿竖直或z方向变化的不同函数。
还参考了以下参考文献,在此通过引用将它们并入本文:2004年11月10日提交的美国专利申请No.10/985,126、2005年12月27日提交的11/318,822、2005年12月23日提交的11/318,164、2005年6月24日提交的11/166,982、2005年5月27日提交的11/140,312以及美国专利No.7,176,043。
尽管在此已经参考具体实施例描述了本发明,要理解这些实施例仅仅是本发明的原理和应用的例示。因此要理解,可以对例示性实施例作出很多修改,并且可以想到其他布置,而不会脱离如所附权利要求定义的本发明的精神和范围。
Claims (37)
1、一种形成微触点的方法,包括:
(a)在衬底的顶表面上的选定位置处提供第一耐蚀刻材料;
(b)在未被所述第一耐蚀刻材料覆盖的位置处蚀刻所述衬底的顶表面,由此在所述选定位置处形成从所述衬底向上突出的第一微触点部分;
(c)在所述第一微触点部分上提供第二耐蚀刻材料;以及
(d)进一步蚀刻所述衬底以在所述第一微触点部分下方形成第二微触点部分,所述第二耐蚀刻材料至少部分保护所述第一微触点部分在所述进一步蚀刻步骤期间不被蚀刻。
2、根据权利要求1所述的方法,其中,执行蚀刻所述顶表面的步骤,使得所述第一耐蚀刻材料从所述第一微触点部分横向突出。
3、根据权利要求1所述的方法,其中,提供所述第二耐蚀刻材料的步骤包括沉积所述第二耐蚀刻材料以及将所沉积的材料暴露于辐射。
4、根据权利要求3所述的方法,其中,在将所沉积的材料暴露于辐射的步骤期间,所述横向突出的第一耐蚀刻材料保护所沉积的第二耐蚀刻材料的多个部分不受辐射。
5、根据权利要求1所述的方法,还包括去除所述第一和第二耐蚀刻材料。
6、根据权利要求1所述的方法,其中,在选定位置提供所述第一耐蚀刻材料的步骤包括在所述衬底的顶表面上沉积所述第一耐蚀刻材料,所述暴露步骤包括在所述第一耐蚀刻材料上放置掩模。
7、根据权利要求6所述的方法,其中,将所述第一耐蚀刻材料和所述掩模暴露于辐射。
8、根据权利要求1所述的方法,还包括形成第三微触点部分。
9、根据权利要求1所述的方法,其中,所述第一和第二耐蚀刻材料为金。
10、根据权利要求1所述的方法,其中,所述第一和第二耐蚀刻材料为光刻胶。
11、一种形成微触点的方法,包括:
(a)向加工过程中的衬底施加最终耐蚀刻材料,使得所述最终耐蚀刻材料至少部分覆盖与所述衬底一体并从所述衬底的表面向上突出的第一微触点部分;以及
(b)蚀刻所述衬底的表面,以便留下处于所述第一微触点部分下方并与之一体的第二微触点部分,所述最终耐蚀刻材料至少部分保护所述第一微触点部分在所述进一步蚀刻步骤期间不被蚀刻。
12、根据权利要求11所述的方法,还包括通过如下方式形成所述加工过程中的衬底
(c)在所述衬底的顶表面上的选定位置处提供预备耐蚀刻材料;以及
(d)蚀刻所述衬底的所述顶表面,以便去除所述衬底中的未被所述预备耐蚀刻材料覆盖的部分,由此留下从被蚀刻表面向上突出的所述第一微触点部分。
13、根据权利要求12所述的方法,其中,在选定位置处提供所述预备耐蚀刻材料的步骤包括在整个所述顶表面上方提供所述预备耐蚀刻材料,并在所述预备耐蚀刻材料顶部提供掩模以将所述预备耐蚀刻材料暴露于辐射。
14、根据权利要求11所述的方法,其中,所述第一微触点部分具有竖直延伸的侧壁,并且所述最终耐蚀刻材料至少部分覆盖所述第一微触点部分的所述侧壁。
15、根据权利要求11所述的方法,还包括去除所述预备耐蚀刻材料和所述最终耐蚀刻材料。
16、一种微电子单元包括:
(a)衬底;以及
(b)多个沿竖直方向从所述衬底突出的微触点,每个微触点包括与所述衬底相邻的基部区域和远离所述衬底的顶端区域,每个微触点具有水平尺度,所述水平尺度是所述基部区域中竖直位置的第一函数,并且是所述顶端区域中竖直位置的第二函数。
17、根据权利要求16所述的微电子单元,其中,所述第一和第二函数相当不同。
18、根据权利要求16所述的微电子单元,其中,水平尺度相对于竖直位置的斜率在所述基部区域和所述顶端区域之间的边界处突变。
19、根据权利要求16所述的微电子单元,其中,所述多个微触点的每一个都具有纵轴和由第一和第二纵轴之间的距离定义的间距,其中所述间距小于大约200微米。
20、根据权利要求19所述的微电子单元,其中,所述间距小于大约150微米。
21、根据权利要求16所述的微电子单元,其中,在所述基部区域和所述顶端区域之间设置有另一区域。
22、根据权利要求16所述的微电子单元,其中,在每个所述微触点之内,所述基部区域和所述顶端区域被形成为金属整体。
23、根据权利要求16所述的微电子单元,其中,所述衬底包括电介质层和沿着所述电介质层延伸的迹线,至少一些所述迹线连接到至少一些所述微触点。
24、一种微电子单元,包括:
衬底;
多个沿竖直方向从所述衬底突出的微触点,其中两个相邻微触点之间的间距小于150微米。
25、根据权利要求24所述的微电子单元,其中,所述间距小于h+d,其中h是每个微触点的竖直高度,d是每个微触点在该微触点远离所述衬底的顶端处的直径。
26、根据权利要求24所述的微电子单元,其中,每个微触点具有至少大约50微米的高度,和至少大约20微米的顶端直径。
27、根据权利要求24所述的微电子单元,其中,每个微触点具有顶端,所述顶端具有基本平坦的水平表面。
28、一种微电子单元包括:
(a)衬底;以及
(b)多个沿竖直方向从所述衬底突出的细长微触点,每个微触点包括与所述衬底相邻的基部区域和远离所述衬底的顶端区域,每个微触点具有轴以及环形表面,所述环形表面在所述竖直方向上沿着所述轴向着或远离轴倾斜,使得所述环形壁的斜率在所述顶端区域和所述基部区域之间的边界处突变。
29、根据权利要求28所述的微电子单元,其中,在每个所述微触点之内,所述基部区域和所述顶端区域被形成为金属整体。
30、根据权利要求28所述的微电子单元,其中,相邻微触点之间的间距小于大约150微米,并且每个微触点具有大约60微米到大约150微米的高度。
31、根据权利要求30所述的微电子单元,其中,每个微触点具有至少大约20微米的顶端直径。
32、根据权利要求28所述的微电子单元,其中,所述间距小于h+d,其中h是每个微触点的竖直高度,d是每个微触点在该微触点远离所述衬底的顶端处的直径。
33、根据权利要求28所述的微电子单元,其中,所述衬底包括电介质层和沿着所述电介质层延伸的迹线,至少一些所述迹线连接到至少一些所述微触点。
34、根据权利要求33所述的微电子单元,其中,所述微触点从所述电介质层的第一侧突出,所述单元还包括在所述电介质层的第二侧处露出且通过所述迹线电连接到至少一些所述微触点的端子。
35、一种组件,所述组件包括根据权利要求34所述的微电子单元和具有连接到所述微触点的触点的微电子元件。
36、根据权利要求32所述的组件,其中,在所述基部区域和所述顶端区域之间设置有另一区域。
37、一种微电子单元包括:
(a)衬底;以及
(b)多个沿竖直方向从所述衬底突出的微触点,每个微触点具有与所述衬底相邻的近侧部分和在竖直方向上从所述近侧部分远离所述衬底延伸的细长远侧部分,所述柱的宽度在所述近侧部分和远侧部分之间的接合处以阶梯式的方式增大。
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-
2007
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-
2008
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- 2008-03-13 JP JP2009553652A patent/JP5980468B2/ja active Active
- 2008-03-13 KR KR1020097020647A patent/KR101466252B1/ko active IP Right Grant
- 2008-03-13 WO PCT/US2008/003473 patent/WO2008112318A2/en active Application Filing
- 2008-03-13 CN CN200880011888A patent/CN101658078A/zh active Pending
-
2014
- 2014-01-30 US US14/168,386 patent/US20140145329A1/en not_active Abandoned
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103108490A (zh) * | 2011-11-11 | 2013-05-15 | 深南电路有限公司 | 一种超厚铜线路板的线路加工方法 |
CN103108490B (zh) * | 2011-11-11 | 2015-10-07 | 深南电路有限公司 | 一种超厚铜线路板的线路加工方法 |
CN111165079A (zh) * | 2017-09-29 | 2020-05-15 | Lg伊诺特有限公司 | 印刷电路板及其制造方法 |
CN111165079B (zh) * | 2017-09-29 | 2024-02-23 | Lg伊诺特有限公司 | 印刷电路板及其制造方法 |
Also Published As
Publication number | Publication date |
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US20080003402A1 (en) | 2008-01-03 |
WO2008112318A2 (en) | 2008-09-18 |
JP5980468B2 (ja) | 2016-08-31 |
JP2010521587A (ja) | 2010-06-24 |
US20140145329A1 (en) | 2014-05-29 |
CN104681450A (zh) | 2015-06-03 |
KR101466252B1 (ko) | 2014-11-27 |
WO2008112318A3 (en) | 2008-11-13 |
KR20090122274A (ko) | 2009-11-26 |
US8641913B2 (en) | 2014-02-04 |
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