CN101636821B - 平坦化的金属化高密度功率mosfet - Google Patents

平坦化的金属化高密度功率mosfet Download PDF

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CN101636821B
CN101636821B CN2008800017293A CN200880001729A CN101636821B CN 101636821 B CN101636821 B CN 101636821B CN 2008800017293 A CN2008800017293 A CN 2008800017293A CN 200880001729 A CN200880001729 A CN 200880001729A CN 101636821 B CN101636821 B CN 101636821B
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黎建
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Vishay Siliconix Inc
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Abstract

本发明提出了一种用于制造功率MOSFET的方法。该方法包括制造功率MOSFET的多个层以形成有源区域上表面，以及在该有源区域上进行化学机械抛光处理以形成基本上平坦的表面。然后，在基本上平坦的表面上进行金属化沉积处理，随后完成功率MOSFET的制造。

Description

平坦化的金属化高密度功率MOSFET
技术领域
本申请涉及高密度功率MOSFET半导体器件。
背景技术
功率MOSFET（金属氧化物半导体场效应晶体管）是模拟电路和数字电路应用中所采用的最常用的场效应晶体管之一。
通常，利用与平面结构相反的垂直结构制造沟槽式的功率MOSFET。该垂直结构能够使晶体管承受高阻断电压和高电流。同样地，利用该垂直结构，元件面积大体上与该元件可承受的电流成比例，并且元件厚度与击穿电压成比例。
功率MOSFET元件的几何形状通常通过光刻法来光刻地予以限定。光刻处理用于限定元件区域，并且一层在另一层之上地构建元件。复杂的器件通常具有构建成的多个不同的层，各层具有多个元件，各层具有不同的配线，并且各层堆叠在其前一层的上面。当在硅片的下表面上构建器件元件时，所得到的这些复杂器件的表面布局通常类似于常见的地球上的“山脉”而具有“凸起”和“低谷”。
但是实际上存在一个问题，即现有技术的功率MOSFET元件具有带有大量的表面起伏的有源区域。现有技术的功率MOSFET器件的有源区域因为构建于下面的硅之上的分层的元件而具有许多凸起和低谷。为了能够使元件之间互相连接，这样的表面起伏被厚的金属层所覆盖，该金属层被优化为填充低谷并覆盖凸起。该金属层通常厚度为几微米以上（例如在常见的高密度功率MOSFET器件中）。
该厚金属层会导致许多问题。一个问题在于，尽管该金属层被设计为填充低谷，但在低谷太窄而不能获得有效填充的地方仍会存在空隙。这样的空隙会成为将缺陷引入到最终的功率MOSFET器件中的主要区域。另一个问题在于，该厚金属层的沉积在制造过程中是非常昂贵的。因此，需要提供一种功率MOSFET的制造方法，以避免在平坦化表面处理方面的厚金属层问题。
发明内容
本申请的实施例提出了一种用于高密度功率MOSFET的方法和系统，其避免了现有技术中的厚金属层问题。本申请的实施例消除了最终器件中因其有源区域表面中高的纵横比的间隙而产生的空隙。
在一个实施例中，本申请提供了一种用于制造高密度功率MOSFET的方法。该方法包括：制造功率MOSFET和集成的肖特基器件的多个层以形成有源区域的上表面，其中，氧化沉积物形成在栅极的上方，所述氧化沉积物在所述栅极上方的表面上延伸，与所述氧化沉积物相邻且低于所述氧化沉积物的源极接触部形成在源极的上方，以及在该有源区域的上表面上进行CMP（化学机械抛光）处理以形成基本上平坦的表面，其中，所述源极接触部与所述氧化沉积物共面。然后，在基本上平坦的表面上进行金属化沉积处理，随后完成了功率MOSFET和肖特基器件的制造。在一个实施例中，通过金属化沉积处理所沉积的金属层的厚度小于4微米。因而，在高密度功率MOSFET器件的制造中，CMP处理避免了例如高纵横比的表面特征所引起的问题。
在一个实施例中，CMP处理主要用于对同时具有小几何形状（例如源极接触部）和大几何形状（例如栅极接触部）的功率MOSFET上的表面起伏进行平坦化。
附图说明
构成本申请文件一部分的附图示出了本发明的实施例，这些附图和说明书一起用于阐述本发明的原理。附图中：
图1示出了具有较厚金属层的传统功率MOSFET的示意性横剖面图。
图2示出了具有较厚金属层201的高密度功率MOSFET的示意性横剖面图。
图3是表示高密度功率MOSFET的纵横比的图。
图4是表示对本发明一个实施例的高密度功率MOSFET的有源区域的上表面进行平坦化处理之前的图。
图5是表示对本发明一个实施例的高密度功率MOSFET的有源区域的上表面进行平坦化处理之后的图。
图6是表示对本发明一个实施例的高密度功率MOSFET的已平坦化的有源区域的上表面进行薄的金属化沉积处理之后的图。
图7是表示本发明一个实施例的具有集成的肖特基器件的高密度功率MOSFET的图。
具体实施方式
现在详细描述本发明的优选实施例，附图示出了这些优选实施例的示例。尽管下面结合优选实施例说明本发明，但应当理解，本发明并不局限于这些实施例。相反，在所附权利要求所限定的本发明的精神和范围内，本发明将包括各种变化、修改及其等同物。而且，在以下本发明实施例的详细说明中，为了提供对本发明的全面理解，阐述了许多具体细节。但是，本领域的普通技术人员应当理解，可以在不具备这些具体细节的情况下实现本发明。而且，因为众所周知的方法、步骤、元件和电路不是本发明实施例的重要方面，所以不对其作详细描述。
本发明的各实施例的目的是提供具有基本上平坦化的有源区域上表面的带薄金属层的高密度功率MOSFET。本发明的各实施例还用于提供制造该高密度功率MOSFET的方法。在一个实施例中，该方法包括制造功率MOSFET的多个层以形成有源区域的上表面，以及在该有源区域上进行CMP（化学机械抛光）处理以形成基本上平坦的表面。然后，在基本上平坦的表面上进行金属化沉积处理，随后完成功率MOSFET的制造。在一个实施例中，通过金属化沉积处理所沉积的金属层厚度小于4微米。以下进一步说明本发明的各实施例及其优点。
图1示出了具有较厚铝金属层101的传统功率MOSFET的示意性横剖面图。如图1所示，功率MOSFET100的横剖面图示出了多个源极接触部（例如接触部102）。各个栅极区域（例如103-104）被如示例性的氧化物层110所示的氧化物层（例如SiO2）包围。n+区域（区域109）为源极。图中示出了漏极区N-108和N+107。图1的实施例示出了相对较厚的金属层101，在此情况下，厚度105约为5μm。通过沉积厚的金属层101以有效地覆盖和填充下面的有源区域表面的表面起伏。金属层101旨在填充所述的氧化沉积物之间的区域并且与源极接触部（例如接触部102）有效的粘连。金属层101因其厚度带来了不平坦的表面。5μm厚的金属层101的金属化沉积层给功率MOSFET100的制造过程增加了巨大的费用。例如，在气相金属沉积机中，多个晶片需要花费大量的时间例如用来形成要求厚度的金属层。在沉积机中所花费的增加的时间降低了机器的总产量以及制造过程的总产量，从而增加了MOSFET器件的单位成本。
图2示出了具有较厚金属层201的高密度功率MOSFET的示意性横剖面图。类似于图1，图2示出了高密度功率MOSFET200的示意性横剖面图，示出了多个源极接触部（例如接触部202）。如同图1，图2的实施例示出了较厚金属层201，在此情况下，厚度约为5μm。通过沉积厚金属层201以有效地覆盖和填充下面的有源区域表面的表面起伏，但是金属层201面对的一个另外的问题就是必须填充所示的氧化沉积物之间的高纵横比的低谷。由于功率MOSFET200是高密度功率MOSFET，所以与较低密度的功率MOSFET（例如图1的MOSFET100）相比，跨过模具区域的源漏极氧化沉积物之间的间隙宽度较小。
金属层201的更具挑战性的任务在于，必须填充所述的氧化沉积物之间的高纵横比区域，同时与源极接触部（例如接触部202）进行有效的粘连。高纵横比区域给金属化沉积处理带来了更大的困难。
图3是表示高密度功率MOSFET200的纵横比的图。纵横比是指间隙的宽度（例如宽度301）和间隙的深度（例如深度302）之间的比值。通常，与相对较浅的宽间隙相反，相对较深的窄间隙的纵横比更高。对于高密度功率MOSFET200来说，确保有效填充高纵横比的间隙并因此确保与源极接触部（例如接触部202）有效接触是更难以解决的，因而通常需要更厚的金属化沉积层201。即使金属层201具有更大的厚度，但高纵横比的间隙仍可能导致空隙和类似的未填充缺陷。这样的空隙将会在最终的高密度功率MOSFET200中产生排气作用（outgassing）和类似的缺陷。因此，金属层201比图1所示的金属层101更昂贵。
图4是表示对本发明一个实施例的高密度功率MOSFET400的有源区域的上表面进行平坦化处理之前的图。如图4所示，功率MOSFET400的横剖面图示出了多个源极接触部（例如接触部402）。在图4的MOSFET400实施例中，源极接触部是钨接触部。
图5是表示对本发明一个实施例的高密度功率MOSFET400的有源区域的上表面进行平坦化处理之后的图。如图5所示，功率MOSFET400的横剖面图示出了平坦化之后的有源区域上表面501。如图5所示，氧化沉积物和钨接触部被抛光，一直到二者共面为止。不论间隙的纵横比如何，都必须被随后的金属化沉积层填充，从而平坦的上有源区域表面有效地去除了任何间隙。这使随后的金属化沉积更有效。
在一个实施例中，在有源区域上表面501上所进行的平坦化处理是钨最优化CMP处理。该钨最优化CMP处理配置为确保具有氧化物子区域和钨子区域的有源区域的有效抛光。
图6是表示对本发明一个实施例的高密度功率MOSFET400的平坦化的有源区域上表面进行薄的金属化沉积处理之后的图。如图6所示，功率MOSFET400的横剖面图示出了被薄的铝金属层602覆盖的有源区域上表面。还示出了金属层602具有接触部603和604。平坦的上有源区域表面没有任何表面起伏，所以可被薄的金属化沉积层有效且高效地填充。薄的金属化沉积层的厚度601小于5μm。例如，在一个实施例中，厚度601为4μm。类似地，在一个实施例中，厚度601为3μm以下。
用于本实施例的高密度功率MOSFET400的薄的金属化沉积处理比传统的较厚的金属化沉积处理便宜并且花费较少的制造时间。由于CMP处理去除了有源区域上表面的表面起伏，所以薄的金属化沉积处理也比传统的较厚的金属化沉积处理更有效，这样就排除了制造缺陷的主要来源。因而，在高密度功率MOSFET器件的制造中，CMP处理防止了例如高纵横比的表面特征所引起的问题的发生。
图7示出了本发明一个实施例的具有集成的肖特基（Schottky）器件700的高密度功率MOSFET。如图7所示，器件700包括高密度功率MOSFET区域701和肖特基器件702。在该示例中，示出了与高密度功率MOSFET的栅极区域相比相对较长的区域705。
另外，应当指出，尽管图1至图7示出了示例性的N沟道器件，但本发明的各实施例也可利用P沟道器件容易地实施。该实施方式也在本发明的范围内。
以上对本发明具体实施例的说明是为了解释和说明而给出的。这些说明不是穷尽的或者不是将本发明限制于所公开的具体形式，显然可以根据上述教导做出各种改变和变化。选择和说明这些实施例的目的是最佳地解释本发明的原理及其实际应用，从而使本领域技术人员最大限度地利用本发明，并且具有各种变化方案的各种实施例也适合于预期的具体应用。应当指出，本发明的保护范围通过所附的权利要求及其等同物限定。

Claims (13)

1.一种用于制造功率MOSFET的方法，该方法包括：
制造功率MOSFET和集成的肖特基器件的多个层，以形成有源区域的上表面，其中，氧化沉积物形成在栅极的上方，所述氧化沉积物在所述栅极上方的表面上延伸，与所述氧化沉积物相邻且低于所述氧化沉积物的源极接触部形成在源极的上方；
在所述有源区域的上表面上进行化学机械抛光处理，以形成基本上平坦的表面，其中，所述源极接触部与所述氧化沉积物共面；
在所述基本上平坦的表面上进行金属化沉积处理；以及
完成所述功率MOSFET和肖特基器件的制造。
2.如权利要求1所述的方法，其中，所述有源区域包括二氧化硅子区域和钨子区域。
3.如权利要求2所述的方法，其中，所述化学机械抛光处理包括钨最优化处理。
4.如权利要求1所述的方法，其中，所述金属化沉积处理被配置为沉积小于4微米深的金属层。
5.如权利要求4所述的方法，其中，所述金属层被配置为接纳多个接合线，所述的多个接合线用于完成所述功率MOSFET的制造。
6.如权利要求1所述的方法，其中，所述功率MOSFET是高密度功率MOSFET。
7.一种用于制造高密度功率MOSFET的方法，该方法包括：
制造功率MOSFET和集成的肖特基器件的多个层，以形成有源区域的上表面，其中，氧化沉积物形成在栅极的上方，所述氧化沉积物在所述栅极上方的表面上延伸，与所述氧化沉积物相邻且低于所述氧化沉积物的源极接触部形成在源极的上方；
在所述有源区域上进行化学机械抛光处理，以形成基本上平坦的表面，其中，所述源极接触部与所述氧化沉积物共面；
在所述基本上平坦的表面上进行金属化沉积处理，其中所述金属化沉积处理被配置为沉积小于4微米深的金属层；以及
完成所述功率MOSFET和集成的肖特基器件的制造。
8.如权利要求7所述的方法，其中，所述有源区域包括二氧化硅子区域和钨子区域。
9.如权利要求8所述的方法，其中，所述化学机械抛光处理包括钨最优化处理。
10.如权利要求7所述的方法，其中，所述金属化沉积处理被配置为沉积小于2微米深的金属层。
11.如权利要求10所述的方法，其中，所述金属层被配置为接纳多个接合线，所述多个接合线用于完成所述功率MOSFET的制造。
12.如权利要求7所述的方法，其中，所述有源区域的上表面是高纵横比的表面。
13.如权利要求7所述的方法，其中，所述功率MOSFET是N沟道器件或P沟道器件。
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TWI471943B (zh) 2015-02-01
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US9437729B2 (en) 2016-09-06
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WO2008086295A1 (en) 2008-07-17
DE112008000110T5 (de) 2009-11-19
TW200837841A (en) 2008-09-16
US20080164515A1 (en) 2008-07-10
KR20090131284A (ko) 2009-12-28
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