CN100550324C - 三栅晶体管及其制造方法 - Google Patents
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Abstract
本发明的实施方案提供用于为绝缘体上硅晶体管制造实现一致硅体高度的方法。对于一个实施方案来说,牺牲氧化物层被设置在半导体衬底上。蚀刻所述氧化物层以形成沟槽。然后用半导体材料填充沟槽。然后以氧化物层的剩余物为基准,平坦化半导体材料,并且然后氧化物层的剩余物被移除。这样被暴露的半导体鳍具有达到在指定容限内的一致高度。
Description
技术领域
本发明的实施方案一般涉及集成电路器件制造的领域并且更具体地涉及三栅晶体管制造。
背景技术
朝着增加集成电路器件(IC器件)的功能的数量的趋势一直在继续。随着晶体管的尺寸减小,当前晶体管制造工艺中的严重缺点变得明显。例如,典型的绝缘体上硅(SOI)晶体管是通过用绝缘体(例如,玻璃或硅氧化物)层覆盖衬底来制造的。然后,第二硅晶片被结合到绝缘体层并且被薄化到期望厚度(即,由晶体管尺寸确定)。这种薄化工艺非常难以以很大的精确度来控制。
图1A-1D图示根据现有技术用于生成三栅SOI晶体管的部分制造工艺。如图1A中所示,通常为硅衬底的载体晶片(carrier wafer)101具有设置在其上的通常为二氧化硅的绝缘体层102。例如,可以在硅衬底上生长二氧化硅层。
如图1B中所示,然后转移晶片(transfer wafer)103被结合到绝缘体层102,所述绝缘体层102可以帮助结合。可以通过热致氢结合工艺(heat-induced hydrogen bondingprocess)实现载体晶片到绝缘体层的结合。可以是例如硅的转移晶片约为600微米厚。
然后,转移晶片基于晶体管尺寸被薄化到期望厚度。这个厚度通常为约50-100nm。可以通过几种典型工艺中的一种来完成转移晶片的薄化。例如,可以使用湿法蚀刻和抛光工艺研磨转移晶片到期望厚度。用于薄化转移晶片的可替换的方法包括转移层(transferlayer)的氢注入以生成转移晶片的脆弱区域。然后,被结合的对(pair)被加热,以实现氢掺杂界面的高温劈开(cleave)。随后,转移晶片表面被抛光或者以其他方式被处理以平坦化表面或者进一步降低厚度。这些方法提供达到在约几百埃范围内的厚度控制。如图1C中所示,转移晶片103已被薄化到用于晶体管的硅体(silicon body)的期望尺寸,导致薄膜层104。薄膜层104的厚度由硅体的期望高度(Hsi)确定。然后,薄膜层104被选择性地蚀刻以生成用于晶体管的硅体。如图1D中所示,使用光刻技术选择性地蚀刻薄膜层104导致硅体105具有期望体宽度(Wsi)和体高度(Hsi)。
对于典型的晶体管设计结构来说,栅长度与Hsi成比例,其中Hsi等于栅长度的约三分之一。对于栅长度为约20-100nm的典型晶体管来说,期望Hsi大于约20nm。使用当前的制造方法,可能生成合适的薄膜层。但是,随着栅长度并且因此期望Hsi降低,当前的制造方法显示出严重的缺点。
Hsi值必须在整个晶片上一致以生产具有一致特性的晶体管。例如,与Hsi直接成比例的晶体管阈值电压不应该以大于约10%的幅度变化。因此,确定Hsi的薄膜层厚度不应该以大于10%的幅度变化。
薄化转移层以获得薄膜层的方法能够生产约20nm厚度的薄膜层,所述厚度不会以大于约10%的幅度变化。但是,这些方法不能为更薄的薄膜层产生所需要的一致性。因此,当前制造SOI晶体管的方法不能制作栅长度小于约50nm的晶体管。
此外,结合载体晶片与转移晶片的工艺,以及薄化转移晶片到期望厚度的工艺昂贵并且难以控制。
发明内容
根据本发明的一个方面,提供了一种半导体制造方法包括:在半导体衬底上设置沟槽层;选择性地移除所述沟槽层的部分以便所述沟槽层的剩余物形成一个或更多个沟槽,所述沟槽层的部分的移除暴露所述半导体衬底;用半导体材料填充所述一个或更多个沟槽,所述填充操作包括在所述一个或更多个沟槽内部外延地生长所述半导体材料;从所述一个或更多个沟槽移除任何多余的半导体材料,所述多余的半导体材料为延伸到所述沟槽层剩余物的表面之上的填充所述沟槽的半导体材料;以及移除所述沟槽层的额外部分以将所述半导体材料暴露为一个或更多个半导体鳍,其中所述沟槽层包括多个层,所述多个层包括设置在所述半导体衬底上的第一氧化物层、设置在所述第一氧化物层上的氮化物层,以及设置在所述氮化物层上的第二氧化物层。
根据本发明的另一个方面,提供了一种半导体制造方法包括:在半导体衬底上设置第一氧化物层;在所述第一氧化物层上设置氮化物层;在所述氮化物层上设置第二氧化物层;选择性地蚀刻所述第二氧化物层、氮化物层和第一氧化物层的部分以限定一个或更多个沟槽;用半导体材料填充所述一个或更多个沟槽,所述填充操作包括在所述一个或更多个沟槽内部外延地生长所述半导体材料;从所述一个或多个沟槽移除所述多余的半导体材料,所述多余的半导体材料为延伸到所述第二氧化层的表面之上的填充所述沟槽的半导体材料;以及选择性地蚀刻所述第二氧化物层和所述氮化物层的剩余物以便形成一个或更多个半导体体。
根据本发明的再一个方面,提供了一种集成电路器件,包括:衬底;以及一个或更多个根据前述权利要求中任何一项形成在所述衬底上的晶体管,每个晶体管具有半导体体,每个半导体体具有小于20nm的高度,每个半导体体的高度在指定高度的5%的容限内一致。
附图说明
通过查阅以下描述和被用来图示本发明的实施方案的附图,本发明可以被最佳地理解。在附图中:
图1A-1D图示根据现有技术用于生成三栅SOI晶体管的工艺;
图2图示根据本发明的一个实施方案,用于提供硅体高度Hsi中增强的一致性的工艺;以及
图3A-3G图示根据本发明的一个实施方案的三栅晶体管的制造。
具体实施方式
在以下描述中,阐述了许多具体的细节。但是,应该理解无需使用这些具体的细节可以实现本发明。此外,公知电路,结构和技术没有以详细方式示出,以免模糊对本文描述的理解。
在整个说明书中提及“一个实施方案”或“实施方案”意味着关于该实施方案描述的特定特征、结构或特性被包括在本发明的至少一个实施方案中。因此,“在一个实施方案中”或“在实施方案中”在整个说明书中不同地方的出现不一定全是指同一实施方案。并且,特定特征,结构或特性可以在一个或更多个实施方案中以任意适当的方式被结合。
此外,发明方面处于比以上所公开的单个实施方案的全部特征少的状态。因此,在具体实施方式之后的的权利要求书特此明确地被并入具体实施方式中,其中每项权利要求独自作为本发明单独的实施方案。
图2图示根据本发明的一个实施方案,用于提供硅体高度Hsi中增强的一致性的工艺。图2中所示的工艺200以操作205开始,在所述操作205中沟槽层被设置在衬底层上。对于一个实施方案来说,可以使用化学气相沉积(CVD)工艺将沟槽层设置在衬底层上。对于一个实施方案来说,衬底层为硅。对于可替换的实施方案来说,衬底层可以是诸如锗(Ge)或砷化镓(GaAs)的另一种半导体材料。对于一个实施方案来说,基于晶体管的栅长度的规格确定沟槽层厚度。即,选择沟槽层厚度等于期望的Hsi值。
在操作210,移除沟槽层被选择的部分,由此形成沟槽。对于一个实施方案来说,沟槽层为可以使用常规蚀刻工艺选择性地蚀刻的材料。对于各种可替换的实施方案来说,沟槽层可以是多个层,每层的材料都与其他层材料不同。在一个这种实施方案中,沟槽层的多个层对不同的蚀刻工艺敏感。
在操作215,用半导体材料(例如,硅)填充由操作210形成的沟槽。对于一个实施方案来说,使用选择性外延工艺用外延硅填充沟槽。在可替换的实施方案中,以一些其他方式填充沟槽。例如,可以使用均厚沉积(Blanket Disposition)工艺用多晶硅填充沟槽。
在操作220,多余的半导体材料被移除。即,延伸到沟槽层剩余物的表面之上的填充沟槽的半导体材料被移除。对于一个实施方案来说,采用化学机械抛光(CMP)来平坦化半导体材料的表面。
在操作225,沟槽层的剩余物被移除以暴露半导体鳍(即,填充沟槽的半导体材料)。对于一个实施方案来说,半导体鳍的高度达到在少于5%的范围内一致。
图3A-3G图示根据本发明的一个实施方案的三栅晶体管的制造。图3A示出硅衬底301。多层沟槽层被设置在硅衬底301上。沟槽层包括第一氧化物(例如,SiO2)层302、氮化物(例如,Si3N4)层303,和第二氧化物(例如,SiO2)层304。三栅体厚度Hsi最终将由非常可控制的第二氧化物层的厚度确定。
图3B图示用来限定晶体管体的光致抗蚀剂掩模层305的应用。光致抗蚀剂掩模层305的图形化确定硅体的宽度Wsi。
图3C图示用来限定沟槽306a和306b的沟槽层蚀刻。对于一个实施方案来说,一系列三种不同的干法蚀刻工艺被采用。在这个实施方案中,使用选择性干法蚀刻工艺蚀刻第二氧化物层304,在所述蚀刻工艺中氮化物层303充当蚀刻终止层(etch stop)。然后,使用不同的选择性干法蚀刻工艺蚀刻氮化物层303,在所述蚀刻工艺中第一氧化物层302充当蚀刻终止层。最后,使用干法蚀刻工艺蚀刻第一氧化物层302,所述蚀刻工艺是充分选择性的,以在硅衬底301的表面上终止。
如所指示的,图3D图示光致抗蚀剂层305已被去掉后,用硅307填充沟槽306a和306b。如以上所说明的,可以通过包括多晶硅的外延生长或均厚沉积的各种可替换的方法来用硅填充沟槽。
图3E图示被平坦化到第二氧化物层304的平面(level)的硅307。对于一个实施方案来说,使用CMP工艺实现平坦化。对于一个实施方案来说,使用抛光工艺移除第二氧化物层304并且氮化物层303被用作抛光终止层。对于这个实施方案来说,抛光在氧化物与氮化物之间具有高选择性。对于可替换的实施方案来说,第二氧化物层304被选择性地蚀刻到氮化物层303。随后,使用湿法蚀刻工艺蚀刻氮化物层303,所述蚀刻工艺使用例如磷酸。第一氧化物层302为这种工艺充当蚀刻终止层。
图3F图示用于随着沟槽层(例如,第二氧化物层304和氮化物层303)的移除而暴露的三栅晶体管的硅体。如图3F中所示,沟槽层的部分(例如,第一氧化物层302)可以被保留以实现下面所解释的晶体管的有利性质。形成栅体的硅307具有达到在指定容限内的一致高度。对于一个实施方案来说,硅307的高度Hsi为约10nm并且在5%的误差范围内一致。
图3G图示通过形成围绕硅307的栅308而制造的三栅晶体管。栅308可以是,例如,金属或者本领域中已知的另一适当材料。
总则
本发明的实施方案包括各种操作。许多方法以它们最基本的形式被描述,但是操作可以被添加到任意一种方法或者从任意一种方法被删除而不会背离本发明的基本范围。例如,在图2的操作205中所描述的沟槽层可以被设置在为各种可替换物质的衬底上并且可以是如图3A所图示的包括多于一个层。并且,沟槽层的部分可以被保留以实现优点。如图3F和3G中所示,第一氧化物层的部分被保留以减少晶体管中的边缘电容(fringecapacitance)。
如以上所描述的,可以以包括例如多晶硅的均厚沉积的多个方式来用硅填充在沟槽层中形成的沟槽。对于其中使用多晶硅的均厚沉积的实施方案来说,在沉积后采用退火工艺以使硅退火为单晶。
虽然已经依据几个实施方案对本发明进行了描述,但是本领域中的那些技术人员将发现本发明不仅限于所描述的实施方案,而是可以由处于所附的权利要求书的精神和范围内的修改和替换来实施。因此,本文的描述应该被认为是例证性而不是限制性的。
Claims (17)
1.一种制造晶体管的鳍状半导体体的方法,包括:
在半导体衬底上设置沟槽层;
选择性地移除所述沟槽层的部分以便所述沟槽层的剩余物形成一个或更多个沟槽,所述沟槽层的部分的移除暴露所述半导体衬底;
用半导体材料填充所述一个或更多个沟槽,所述填充操作包括在所述一个或更多个沟槽内部,将所述半导体材料外延地生长在所暴露的半导体衬底上或将所述半导体材料均厚沉积在所暴露的半导体衬底上;
从所述一个或更多个沟槽移除任何多余的半导体材料,所述多余的半导体材料为延伸到所述沟槽层剩余物的表面之上的填充所述沟槽的半导体材料;以及
移除所述沟槽层的额外部分以将所述半导体材料暴露为一个或更多个半导体鳍,其中所述沟槽层包括多个层,所述多个层包括设置在所述半导体衬底上的第一氧化物层、设置在所述第一氧化物层上的氮化物层,以及设置在所述氮化物层上的第二氧化物层。
2.如权利要求1所述的方法,其中移除所述沟槽层的额外部分的操作包括移除所述第二氧化物层的任何剩余部分、所述氮化物层的任何剩余部分,以及保留所述第一氧化物层的任何剩余部分的至少一些部分。
3.如权利要求1所述的方法,其中所述一个或更多个沟槽具有约10nm的深度。
4.如权利要求3所述的方法,其中所述一个或更多个半导体鳍具有约10nm的高度,所述高度达到在5%的范围内一致。
5.如权利要求1所述的方法,其中从所述一个或更多个沟槽移除任何多余半导体材料的操作包括将所述半导体材料平坦化到所述沟槽层的表面。
6.如权利要求5所述的方法,其中所述平坦化操作是通过化学机械抛光工艺实现的。
7.一种制造晶体管的半导体体的方法,包括:
在半导体衬底上设置第一氧化物层;
在所述第一氧化物层上设置氮化物层;
在所述氮化物层上设置第二氧化物层;
选择性地蚀刻所述第二氧化物层、氮化物层和第一氧化物层的部分以限定一个或更多个沟槽;
用半导体材料填充所述一个或更多个沟槽,所述填充操作包括在所述一个或更多个沟槽内部外延地生长所述半导体材料或均厚沉积所述半导体材料;
从所述一个或更多个沟槽移除所述多余的半导体材料,所述多余的半导体材料为延伸到所述第二氧化层的表面之上的填充所述沟槽的半导体材料;以及
选择性地蚀刻所述第二氧化物层和所述氮化物层的剩余物以便形成一个或更多个半导体体。
8.如权利要求7所述的方法,其中所述一个或更多个沟槽具有约10nm的深度。
9.如权利要求7所述的方法,其中所述一个或更多个半导体体具有小于20nm的高度,所述高度达到在5%的范围内一致。
10.如权利要求9所述的方法,其中所述一个或更多个半导体体具有约10nm的高度。
11.如权利要求7所述的方法,其中从所述一个或更多个沟槽移除任何多余的半导体材料的操作包括将所述半导体材料平坦化到所述第二氧化物层的表面。
12.如权利要求11所述的方法,其中所述平坦化操作是通过化学机械抛光工艺实现的。
13.如权利要求7所述的方法,其中所述半导体衬底包括从由硅、锗和砷化镓组成的组中选择的半导体材料。
14.如权利要求7所述的方法,其中所述半导体衬底包括硅,所述第一氧化物层包括SiO2,所述氮化物层包括Si3N4,以及所述第二氧化物层包括SiO2。
15.一种具有鳍状晶体管体的集成电路器件,包括:
衬底;以及
一个或更多个根据前述权利要求中任何一项的方法形成在所述衬底上的晶体管,每个晶体管具有半导体体,每个半导体体具有小于20nm的高度,每个半导体体的高度在指定高度的5%的容限内一致。
16.如权利要求15所述的集成电路器件,其中所述一个或更多个晶体管为三栅晶体管。
17.如权利要求16所述的集成电路器件,其中每个半导体体具有约10nm的高度。
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US7655989B2 (en) * | 2006-11-30 | 2010-02-02 | International Business Machines Corporation | Triple gate and double gate finFETs with different vertical dimension fins |
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2004
- 2004-01-16 US US10/760,028 patent/US7268058B2/en not_active Expired - Lifetime
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2005
- 2005-01-10 WO PCT/US2005/000947 patent/WO2005071730A1/en active Application Filing
- 2005-01-10 CN CNB2005800072795A patent/CN100550324C/zh not_active Expired - Fee Related
- 2005-01-10 JP JP2006549560A patent/JP2007521667A/ja active Pending
- 2005-01-10 EP EP05711376A patent/EP1704590A1/en not_active Withdrawn
- 2005-01-13 TW TW094101018A patent/TWI297212B/zh not_active IP Right Cessation
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2007
- 2007-07-25 US US11/828,290 patent/US20070262389A1/en not_active Abandoned
Non-Patent Citations (2)
Title |
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FinFET-A Self-Aligned Double-Gate MOSFET Scalableto20nm. Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski,HidekiTakeuchi, Kazuya Asano.IEEE TRANSACTIONS ON ELECTRON DEVICES,Vol.47 No.12. 2000 |
FinFET-A Self-Aligned Double-Gate MOSFET Scalableto20nm. Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski,HidekiTakeuchi, Kazuya Asano.IEEE TRANSACTIONS ON ELECTRON DEVICES,Vol.47 No.12. 2000 * |
Also Published As
Publication number | Publication date |
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US20070262389A1 (en) | 2007-11-15 |
WO2005071730A1 (en) | 2005-08-04 |
JP2007521667A (ja) | 2007-08-02 |
TWI297212B (en) | 2008-05-21 |
EP1704590A1 (en) | 2006-09-27 |
TW200535933A (en) | 2005-11-01 |
US20050158970A1 (en) | 2005-07-21 |
CN1930671A (zh) | 2007-03-14 |
US7268058B2 (en) | 2007-09-11 |
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