WO2017153882A1 - Semiconductor device, manufacturing method thereof, and display device including the semiconductor device - Google Patents

Semiconductor device, manufacturing method thereof, and display device including the semiconductor device Download PDF

Info

Publication number
WO2017153882A1
WO2017153882A1 PCT/IB2017/051280 IB2017051280W WO2017153882A1 WO 2017153882 A1 WO2017153882 A1 WO 2017153882A1 IB 2017051280 W IB2017051280 W IB 2017051280W WO 2017153882 A1 WO2017153882 A1 WO 2017153882A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide semiconductor
semiconductor film
film
equal
insulating film
Prior art date
Application number
PCT/IB2017/051280
Other languages
English (en)
French (fr)
Inventor
Shunpei Yamazaki
Junichi Koezuka
Kenichi Okazaki
Masami Jintyou
Yukinori Shima
Original Assignee
Semiconductor Energy Laboratory Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co., Ltd. filed Critical Semiconductor Energy Laboratory Co., Ltd.
Priority to KR1020187025833A priority Critical patent/KR20180123028A/ko
Publication of WO2017153882A1 publication Critical patent/WO2017153882A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a manufacturing method of the semiconductor device.
  • Another embodiment of the present invention relates to a display device including the semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.
  • one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.
  • a semiconductor device generally means a device that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each one embodiment of a semiconductor device.
  • An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may each include a semiconductor device.
  • Patent Document 1 discloses a semiconductor device whose field-effect mobility (in some cases, simply referred to as mobility or ⁇ ) is improved by stacking a plurality of oxide semiconductor layers, among which the oxide semiconductor layer serving as a channel contains indium and gallium where the proportion of indium is higher than the proportion of gallium.
  • Patent Document 1 Japanese Published Patent Application No. 2014-007399
  • Non-Patent Document 1 M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In 2 0 3 -Ga 2 Zn0 4 -ZnO System at 1350 °C", J. Solid State Chem., 1991, Vol. 93, pp. 298-315.
  • the field-effect mobility of a transistor that uses an oxide semiconductor film as a channel region is preferably as high as possible.
  • the transistor has a problem with its characteristics, that is, the transistor tends to be normally on. Note that "normally on” means a state where a channel exists without application of a voltage to a gate electrode and a current flows through the transistor.
  • oxygen vacancies which are formed in the oxide semiconductor film adversely affect the transistor characteristics.
  • hydrogen is trapped in oxygen vacancies formed in the oxide semiconductor film to serve as a carrier supply source.
  • the carrier supply source generated in the oxide semiconductor film causes a change in the electrical characteristics, typically, shift in the threshold voltage, of the transistor including the oxide semiconductor film.
  • the amount of oxygen vacancies in the oxide semiconductor film is too large, for example, the threshold voltage of the transistor is shifted in the negative direction, and the transistor has normally-on characteristics.
  • the amount of oxygen vacancies is preferably small or the amount with which the normally-on characteristics are not exhibited.
  • an object of one embodiment of the present invention is to improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Another object of one embodiment of the present invention is to prevent a change in electrical characteristics of a transistor including an oxide semiconductor film and to improve reliability of the transistor. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.
  • One embodiment of the present invention is a semiconductor device including an oxide semiconductor film.
  • the semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film.
  • the oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film.
  • the first to third oxide semiconductor films contain the same element.
  • the second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.
  • the semiconductor device includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a second gate electrode over the second insulating film.
  • the oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film.
  • the first to third oxide semiconductor films contain the same element.
  • the second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.
  • the semiconductor device includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a second gate electrode over the second insulating film.
  • the first gate electrode and the second gate electrode are connected through an opening provided in the first insulating film and the second insulating film.
  • the first gate electrode and the second gate electrode each include a region positioned outside an edge portion of the oxide semiconductor film.
  • the oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film.
  • the first to third oxide semiconductor films contain the same element.
  • the second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.
  • the first to third oxide semiconductor films separately contain In, M ⁇ M is Al, Ga, Y, or Sn), and Zn.
  • M be greater than or equal to 0.5 and less than or equal to 1.5 and Zn be greater than or equal to 5 and less than or equal to 7 when In is 5.
  • the second oxide semiconductor film be a composite oxide semiconductor that includes a first region and a second region.
  • the first region contains ⁇ ⁇ ⁇ , ⁇ , ⁇ (M represents Al, Ga, Y, or Sn, and a, b, c, and d each represent a given number).
  • the second region contains ln x Zn y z (x, y, and z each represent a given number).
  • the second oxide semiconductor film include a region thicker than one or both of the first oxide semiconductor film and the third oxide semiconductor film.
  • one or both of the first oxide semiconductor film and the third oxide semiconductor film contain a crystal part.
  • the crystal part preferably has c-axis alignment.
  • Another embodiment of the present invention is a display device including a display element and the semiconductor device described in any one of the above embodiments.
  • Another embodiment of the present invention is a display module including the display device and a touch sensor.
  • Another embodiment of the present invention is an electronic device including the display device, the display module, or the semiconductor device described in any one of the above embodiments.
  • the electronic device further includes an operation key or a battery.
  • Another embodiment of the present invention is a manufacturing method of a semiconductor device including an oxide semiconductor film.
  • the method includes the following steps: forming a first insulating film, forming an oxide semiconductor film over the first insulating film, forming a second insulating film and a third insulating film over the oxide semiconductor film, and forming a gate electrode over the second insulating film.
  • the step of forming the oxide semiconductor film includes the following steps: forming a first oxide semiconductor film, forming a second oxide semiconductor film over the first oxide semiconductor film, and forming a third oxide semiconductor film over the second oxide semiconductor film.
  • the first to third oxide semiconductor films are successively formed with a sputtering apparatus in vacuum.
  • the oxygen partial pressure of the second oxide semiconductor film be lower than the oxygen partial pressure of one or both of the first oxide semiconductor film and the third oxide semiconductor film.
  • One embodiment of the present invention can improve field-effect mobility and reliability of a transistor including an oxide semiconductor film.
  • One embodiment of the present invention can prevent a change in electrical characteristics of a transistor including an oxide semiconductor film and improve the reliability of the transistor.
  • One embodiment of the present invention can provide a semiconductor device with low power consumption.
  • One embodiment of the present invention can provide a novel semiconductor device.
  • One embodiment of the present invention can provide a novel display device.
  • FIGS. lA to 1C are a top view and cross-sectional views illustrating a semiconductor device.
  • FIGS. 2A to 2C are a top view and cross-sectional views illustrating a semiconductor device.
  • FIGS. 3 A and 3B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 4A and 4B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 5A and 5B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 6A and 6B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 7A and 7B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 8A and 8B are cross-sectional views illustrating a semiconductor device.
  • FIGS. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIGS. lOA to IOC are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIGS. 11 A to l lC are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIGS. 12A and 12B are schematic views illustrating diffusion paths of oxygen or excess oxygen diffused into an oxide semiconductor film.
  • FIGS. 13 A and 13B are schematic views illustrating a top structure and a cross-sectional structure of an oxide semiconductor film.
  • FIGS. 14A and 14B are schematic views illustrating a top structure and a cross-sectional structure of an oxide semiconductor film.
  • FIGS. 15A and 15B are schematic views illustrating a top structure and a cross-sectional structure of an oxide semiconductor film.
  • FIGS. 16A and 16B are schematic views illustrating a top structure and a cross-sectional structure of an oxide semiconductor film.
  • FIG. 17 illustrates an atomic ratio of an oxide semiconductor film.
  • FIGS. 18A and 18B illustrate a sputtering apparatus.
  • FIG. 19 illustrates energy bands in a transistor in which an oxide semiconductor is used for its channel region.
  • FIGS. 20A to 20C are cross-sectional TEM images and an HR-TEM image of an oxide semiconductor film.
  • FIGS. 21 A to 21C are cross-sectional TEM images and an HR-TEM image of an oxide semiconductor film.
  • FIGS. 22A to 22C are cross-sectional TEM images and an HR-TEM image of an oxide semiconductor film.
  • FIGS. 23A to 23C show XRD measurement results and electron diffraction patterns of an oxide semiconductor film.
  • FIGS. 24A to 24C show XRD measurement results and electron diffraction patterns of an oxide semiconductor film.
  • FIGS. 25A to 25C show XRD measurement results and electron diffraction patterns of an oxide semiconductor film.
  • FIGS. 26A and 26B show electron diffraction patterns.
  • FIG. 27 shows a line profile of an electron diffraction pattern.
  • FIG. 28 shows luminance profiles of electron diffraction patterns, relative luminance R of the luminance profiles, and full widths at half maximum of the profiles.
  • FIGS. 29A1, 29A2, 29B1, 29B2, 29C1, and 29C2 show electron diffraction patterns and luminance profiles.
  • FIG. 30 shows relative luminance estimated from electron diffraction patterns of oxide semiconductor films.
  • FIGS. 31A1, 31A2, 31B1, 31B2, 31C1, and 31C2 show cross-sectional TEM images and cross-sectional TEM images obtained through analysis thereof.
  • FIGS. 32A to 32C show SIMS measurement results of oxide semiconductor films.
  • FIG. 33 is a top view illustrating one mode of a display device.
  • FIG. 34 is a cross-sectional view illustrating one mode of a display device.
  • FIG. 35 is a cross-sectional view illustrating one mode of a display device.
  • FIG. 36 is a cross-sectional view illustrating one mode of a display device.
  • FIG. 37 is a cross-sectional view illustrating one mode of a display device.
  • FIG. 38 is a cross-sectional view illustrating one mode of a display device.
  • FIGS. 39A to 39D are cross-sectional views illustrating a method for forming an EL layer.
  • FIG. 40 is a conceptual diagram illustrating a droplet discharge apparatus.
  • FIGS. 41 A to 41C are a block diagram and circuit diagrams illustrating a display device.
  • FIG. 42 illustrates a display module.
  • FIGS. 43 A to 43E illustrate electronic devices.
  • FIGS. 44A to 44G illustrate electronic devices.
  • FIGS. 45A and 45B are perspective views illustrating a display device.
  • FIG. 46 shows an EDX mapping image of a cross section of a sample of Example.
  • FIGS. 47A and 47B show BF-STEM images of cross sections of samples of Example.
  • FIGS. 48A and 48B show XRD measurement results of samples of Example and XRD analysis positions.
  • a transistor is an element having at least three terminals of a gate, a drain, and a source.
  • the transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel region.
  • a drain a drain terminal, a drain region, or a drain electrode
  • a source a source terminal, a source region, or a source electrode
  • source and drain functions of a source and a drain might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification and the like.
  • the expression “electrically connected” includes the case where components are connected through an "object having any electric function".
  • an object having any electric function there is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object.
  • Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and elements with a variety of functions as well as an electrode and a wiring.
  • parallel means that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and accordingly also covers the case where the angle is greater than or equal to -5° and less than or equal to 5°.
  • perpendicular means that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also covers the case where the angle is greater than or equal to 85° and less than or equal to 95°.
  • film and “layer” can be interchanged with each other.
  • conductive layer can be changed into the term “conductive film” in some cases.
  • insulating film can be changed into the term “insulating layer” in some cases.
  • the off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as non-conduction state and cutoff state).
  • the off state of an n-channel transistor means that a voltage (V gs ) between its gate and source is lower than the threshold voltage (J3 ⁇ 4 and the off state of a p-channel transistor means that the gate-source voltage V gs is higher than the threshold voltage F t .
  • the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate- source voltage V gs is lower than the threshold voltage V t h- [0036]
  • the off-state current of a transistor depends on V gs in some cases.
  • the off-state current of a transistor is lower than or equal to ⁇ may mean “there is V gs with which the off-state current of the transistor becomes lower than or equal to ⁇ .
  • the off-state current of a transistor means “the off-state current in an off state at predetermined V gs ", “the off-state current in an off state at V gs in a predetermined range", “the off-state current in an off state at V gs with which sufficiently reduced off-state current is obtained", or the like.
  • the assumption is made of an n-channel transistor where the threshold voltage V th is 0.5 V and the drain current is 1 x 10 "9 A at V gs of 0.5 V, 1 x 10 "13 A at V gs of 0.1 V, 1 x 10 "19 A at V gs of -0.5 V, and 1 x 10 "22 A at V gs of -0.8 V.
  • the drain current of the transistor is 1 x 10 ⁇ 19 A or lower at V gs of -0.5 V or at V gs in the range of -0.8 V to -0.5 V; therefore, it can be said that the off-state current of the transistor is 1 x 10 ⁇ 19 A or lower. Since there is V gs at which the drain current of the transistor is 1 x 10 ⁇ 22 A or lower, it may be said that the off-state current of the transistor is 1 x 10 ⁇ 22 A or lower.
  • the off-state current of a transistor with a channel width W is sometimes represented by a current value in relation to the channel width W or by a current value per given channel width (e.g., 1 ⁇ ). In the latter case, the off-state current may be expressed in the unit with the dimension of current per length (e.g., ⁇ / ⁇ ).
  • the off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5 °C to 35 °C).
  • an off-state current of a transistor is lower than or equal to ⁇ may refer to a situation where there is V gs at which the off-state current of a transistor is lower than or equal to / at room temperature, 60 °C, 85 °C, 95 °C, 125 °C, a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5 °C to 35 °C).
  • the off-state current of a transistor depends on voltage F dS between its drain and source in some cases.
  • the off-state current in this specification may be an off-state current at V ds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V.
  • the off-state current might be an off-state current at V d s at which the required reliability of a semiconductor device or the like including the transistor is ensured or V d s at which the semiconductor device or the like including the transistor is used.
  • an off-state current of a transistor is lower than or equal to ⁇ may refer to a situation where there is V g s at which the off-state current of a transistor is lower than or equal to / at V d s of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, V ds at which the required reliability of a semiconductor device or the like including the transistor is ensured, or V d s at which the semiconductor device or the like including the transistor is used.
  • off-state current a drain may be replaced with a source. That is, the off-state current sometimes refers to a current that flows through a source of a transistor in an off state.
  • the term "leakage current” sometimes expresses the same meaning as off-state current.
  • the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is off, for example.
  • the threshold voltage of a transistor refers to a gate voltage (Fg) at which a channel is formed in the transistor.
  • the threshold voltage of a transistor may refer to a gate voltage (F g ) at which the value of [A] x L [ ⁇ ]/ ⁇ [ ⁇ ] is 1 x 10 ⁇ 9 [A] where L is channel length and W is channel width.
  • a “semiconductor” can have characteristics of an "insulator” when the conductivity is sufficiently low, for example. Further, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the "semiconductor” and the "insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. An “insulator” in this specification and the like can be called a “semi-insulator” in some cases.
  • a “semiconductor” can have characteristics of a “conductor” when the conductivity is sufficiently high, for example. Further, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the "semiconductor” and the "conductor” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.
  • an impurity in a semiconductor refers to an element that is not a main component of the semiconductor.
  • an element with a concentration of lower than 0.1 atomic% is an impurity.
  • the semiconductor contains an impurity, the density of states (DOS) may be formed therein, the carrier mobility may be decreased, or the crystallinity may be decreased, for example.
  • the impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specific examples include hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • oxygen vacancies may be formed by entry of impurities such as hydrogen, for example.
  • impurities such as hydrogen, for example.
  • examples of the impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
  • a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, a metal oxide used in an active layer of a transistor is called an oxide semiconductor in some cases. In other words, an OS FET is a transistor including a metal oxide or an oxide semiconductor.
  • a metal oxide including nitrogen is also called a metal oxide in some cases.
  • a metal oxide including nitrogen may be called a metal oxynitride.
  • CAAC c-axis aligned crystal
  • CAC cloud-aligned composite
  • An oxide semiconductor formed by a sputtering method using the above-mentioned target at a substrate temperature of higher than or equal to 100 °C and lower than or equal to 130 °C is referred to as sIGZO, and an oxide semiconductor formed by a sputtering method using the above-mentioned target with the substrate temperature set at room temperature (R.T.) is referred to as tIGZO.
  • sIGZO has one or both of the nano crystal (nc) crystal structure and the CAAC crystal structure.
  • tIGZO has the nc crystal structure.
  • room temperature (R.T.) herein also refers to a temperature of the time when a substrate is not heated intentionally.
  • CAC-OS or CAC-metal oxide has a function of a conductor in a part of the material and has a function of a dielectric (or insulator) in another part of the material; as a whole, CAC-OS or CAC-metal oxide has a function of a semiconductor.
  • the conductor has a function of letting electrons (or holes) serving as carriers flow
  • the dielectric has a function of not letting electrons serving as carriers flow.
  • CAC-OS or CAC-metal oxide includes conductor regions and dielectric regions.
  • the conductor regions have the above-described function of the conductor, and the dielectric regions have the above-described function of the dielectric.
  • the conductor regions and the dielectric regions in the material are separated at the nanoparticle level.
  • the conductor regions and the dielectric regions are unevenly distributed in the material. When observed, the conductor regions are coupled in a cloud-like manner with their boundaries blurred, in some cases.
  • CAC-OS or CAC-metal oxide can be called a matrix composite or a metal matrix composite.
  • the conductor regions and the dielectric regions each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material, in some cases.
  • FIGS. lA to 1C to FIGS. 12A and 12B a semiconductor device of one embodiment of the present invention and a manufacturing method of the semiconductor device are described with reference to FIGS. lA to 1C to FIGS. 12A and 12B.
  • FIG. 1A is a top view of a transistor 100 that is a semiconductor device of one embodiment of the present invention.
  • FIG. IB is a cross-sectional view taken along a dashed dotted line X1-X2 in FIG. 1 A
  • FIG. 1C is a cross-sectional view taken along a dashed dotted line Y1-Y2 in FIG. 1A. Note that in FIG. 1A, some components of the transistor 100 (e.g., an insulating film serving as a gate insulating film) are not illustrated to avoid complexity.
  • the direction of the dashed dotted line XI -X2 may be referred to as a channel length direction
  • the direction of the dashed dotted line Y1-Y2 may be referred to as a channel width direction.
  • FIG. 1A some components are not illustrated in some cases in top views of transistors described below.
  • the transistor 100 illustrated in FIGS. lAto 1C is a top-gate transistor.
  • the transistor 100 includes an insulating film 104 over a substrate 102; an oxide semiconductor film 108 over the insulating film 104; an insulating film 110 over the oxide semiconductor film 108; a conductive film 112 over the insulating film 110; and an insulating film 116 over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112.
  • a region of the oxide semiconductor film 108 which overlaps with the conductive film 112 includes an oxide semiconductor film 108 1 over the insulating film 104, an oxide semiconductor film 108 2 over the oxide semiconductor film 108 1, and an oxide semiconductor film 108 3 over the oxide semiconductor film 108 2.
  • the oxide semiconductor films 108 1 to 108_ 3 contain the same element.
  • the oxide semiconductor films 108 1 to 108_ 3 each independently contain In, M (M is Al, Ga, Y, or Sn), and Zn.
  • the oxide semiconductor film 108 includes regions 108n which do not overlap with the conductive film 112 and is in contact with the insulating film 116.
  • the regions 108n are regions where the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 become n-type. Note that the regions 108n are in contact with the insulating film 116.
  • the insulating film 116 contains nitrogen or hydrogen. Nitrogen or hydrogen in the insulating film 116 is added to the regions 108n to increase the carrier density, thereby making the regions 108n n-type.
  • the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 each independently include a region in which the atomic proportion of In is greater than the atomic proportion of M.
  • neighbor includes the following: when In is 4, M is greater than or equal to 1.5 and less than or equal to 2.5, and Zn is greater than or equal to 2 and less than or equal to 4.
  • the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 can be formed using the same sputtering target owing to their substantially the same compositions. This can reduce manufacturing cost. [0062]
  • compositions of the oxide semiconductor films 108 1, 108 2, and 108 3 are not limited to these.
  • the term "neighborhood" includes the following: when In is 5, is greater than or equal to 0.5 and less than or equal to 1.5, and Zn is greater than or equal to 5 and less than or equal to 7.
  • the transistor 100 can have high field-effect mobility. Specifically, the field-effect mobility of the transistor 100 can exceed 10 cm 2 /Vs, preferably exceed 30 cm 2 /Vs.
  • the use of the transistor with high field-effect mobility in a gate driver that generates a gate signal allows a display device to have a narrow frame.
  • the use of the transistor with high field-effect mobility in a source driver (particularly in a demultiplexer connected to an output terminal of a shift register included in a source driver) that is included in a display device and supplies a signal from a signal line can reduce the number of wirings connected to the display device.
  • the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 each independently include a region in which the atomic proportion of In is higher than the atomic proportion of M, the field-effect mobility might be low if the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 have low crystallinity.
  • the oxide semiconductor film 108 2 includes a region having lower crystallinity than one or both of the oxide semiconductor film 108 1 and the oxide semiconductor film 108 3.
  • the crystallinity of the oxide semiconductor film 108 can be determined by analysis by X-ray diffraction (XRD) or with a transmission electron microscope (TEM).
  • the oxide semiconductor film 108 2 has a region with low crystallinity, the following effects can be achieved.
  • Oxygen vacancies formed in the oxide semiconductor film 108 adversely affect the transistor characteristics and therefore cause a problem.
  • hydrogen is trapped in oxygen vacancies formed in the oxide semiconductor film 108 to serve as a carrier supply source.
  • the carrier supply source generated in the oxide semiconductor film 108 causes a change in the electrical characteristics, typically, shift in the threshold voltage, of the transistor 100 including the oxide semiconductor film 108. Therefore, it is preferable that the amount of oxygen vacancies in the oxide semiconductor film 108 be as small as possible.
  • the insulating film in the vicinity of the oxide semiconductor film 108 contains excess oxygen.
  • one or both of the insulating film 110 which is formed over the oxide semiconductor film 108 and the insulating film 104 which is formed below the oxide semiconductor film 108 contain excess oxygen. Oxygen or excess oxygen is transferred from the insulating film 104 and/or the insulating film 110 to the oxide semiconductor film 108, whereby oxygen vacancies in the oxide semiconductor film can be reduced.
  • FIGS. 12A and 12B are schematic views illustrating the diffusion paths of oxygen or excess oxygen diffused into the oxide semiconductor film 108.
  • FIG. 12A is the schematic view in the channel length direction and FIG. 12B is that in the channel width direction.
  • Oxygen or excess oxygen of the insulating film 110 is diffused to the oxide semiconductor film 108 2 and the oxide semiconductor film 108 1 from above, i.e., through the oxide semiconductor film 108 3 (Route 1 in FIGS. 12A and 12B).
  • oxygen or excess oxygen of the insulating film 110 is diffused into the oxide semiconductor film 108 through the side surfaces of the oxide semiconductor film 108 1, the oxide semiconductor film 108 2, and the oxide semiconductor film 108 3 (Route 2 in FIG. 12B).
  • the oxide semiconductor film 108 2 includes a region having lower crystallinity than the oxide semiconductor film 108 1 and the oxide semiconductor film 108 3, the region serves as a diffusion path of excess oxygen, so that excess oxygen can also be diffused to the oxide semiconductor film 108 1 and the oxide semiconductor film 108 3 that have higher crystallinity than the oxide semiconductor film 108 2 by Route 2 shown in FIG. 12B. It is thus preferable that the oxide semiconductor film 108 2 be thicker than the oxide semiconductor film 108 1 and the oxide semiconductor film 108 3 to widen the oxygen diffusion path.
  • the oxygen or excess oxygen might also be diffused from the insulating film 104 into the oxide semiconductor film 108.
  • a stacked-layer structure that includes the oxide semiconductor films having different crystal structures is formed in a semiconductor device of one embodiment of the present invention and the region with low crystallinity serves as a diffusion path of excess oxygen, whereby the semiconductor device can be highly reliable.
  • the oxide semiconductor film 108 only includes an oxide semiconductor film with low crystallinity, impurities (e.g., hydrogen or moisture) may enter the oxide semiconductor film 108, or the oxide semiconductor film 108 may be damaged. Impurities such as hydrogen or moisture entering the oxide semiconductor film 108 adversely affect the transistor characteristics to cause a problem. For this reason, the less the oxide semiconductor film 108 contains impurities such as hydrogen or moisture, the better.
  • impurities e.g., hydrogen or moisture
  • the crystallinity of each of the lower oxide semiconductor film (the oxide semiconductor film 108 1) and the upper oxide semiconductor film (the oxide semiconductor film 108 3) is increased in one embodiment of the present invention. Owing to this, impurities that might enter the oxide semiconductor film 108 2 can be suppressed. Particularly when the oxide semiconductor film 108 3 has high crystallinity, damage that might be caused when the insulating film 110 is formed can be suppressed.
  • the surface of the oxide semiconductor film 108 that is, the surface of the oxide semiconductor film 108 3 is easily damaged because it is the formation surface of the insulating film 110. However, the damage that might be caused when the insulating film 110 is formed can be suppressed because the oxide semiconductor film 108 3 includes a high-crystallinity region.
  • the oxide semiconductor film 108 an oxide semiconductor film in which the impurity concentration is low and the density of defect states is low, in which case the transistor can have more excellent electrical characteristics.
  • the state in which the impurity concentration is low and the density of defect states is low (the amount of oxygen vacancies is small) is referred to as "highly purified intrinsic” or “substantially highly purified intrinsic”.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density.
  • a transistor in which a channel region is formed in the oxide semiconductor film rarely has a negative threshold voltage (is rarely normally on).
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. Furthermore, the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely low off-state current; even when an element has a channel width of 1 x 10 6 ⁇ and a channel length of 10 ⁇ , the off-state current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, that is, less than or equal to 1 x 10 ⁇ 13 A, at a voltage (drain voltage) between a source electrode and a drain electrode of from 1 V to 10 V.
  • the oxide semiconductor film 108 2 sometimes has a high carrier density.
  • the Fermi level is sometimes high relative to the conduction band of the oxide semiconductor film 108 2. This lowers the conduction band minimum of the oxide semiconductor film 108 2, so that the energy difference between the conduction band minimum of the oxide semiconductor film 108 2 and the trap level, which might be formed in a gate insulating film (here, the insulating film 110), is increased in some cases.
  • the increase of the energy difference can reduce trap of charges in the gate insulating film and reduce variation in the threshold voltage of the transistor, in some cases.
  • the oxide semiconductor film 108 2 has a higher carrier density, the oxide semiconductor film 108 can have higher field-effect mobility.
  • a composite oxide semiconductor that includes a first region containing In a 3 ⁇ 4 Zn c Or f (M represents Al, Ga, Y, or Sn, and a, b, c, and d each represent a given number) and a second region containing ln x Zn y z (x, y, and z each represent a given number) as the oxide semiconductor film 108 2.
  • M represents Al, Ga, Y, or Sn
  • a, b, c, and d each represent a given number
  • a second region containing ln x Zn y z (x, y, and z each represent a given number) as the oxide semiconductor film 108.
  • the transistor 100 may further include an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the region 108n through an opening 141a formed in the insulating films 116 and 118; and a conductive film 120b electrically connected to the region 108n through an opening 141b formed in the insulating films 116 and 118.
  • the insulating film 104 may be referred to as a first insulating film
  • the insulating film 110 may be referred to as a second insulating film
  • the insulating film 116 may be referred to as a third insulating film
  • the insulating film 118 may be referred to as a fourth insulating film.
  • the conductive films 112, 120a, and 120b function as a gate electrode, a source electrode, and a drain electrode, respectively.
  • the insulating film 110 functions as a gate insulating film.
  • the insulating film 110 includes an excess oxygen region. Since the insulating film 110 includes the excess oxygen region, excess oxygen can be supplied to the oxide semiconductor film 108. As a result, oxygen vacancies that might be formed in the oxide semiconductor film 108 can be filled with excess oxygen, and the semiconductor device can have high reliability.
  • excess oxygen may be supplied to the insulating film 104 that is formed below the oxide semiconductor film 108. In that case, excess oxygen contained in the insulating film 104 might also be supplied to the regions 108n, which is not desirable because the resistance of the regions 108n might be increased. In contrast, in the structure in which the insulating film 110 formed over the oxide semiconductor film 108 contains excess oxygen, excess oxygen can be selectively supplied only to a region overlapping with the conductive film 112. [0087]
  • the substrate 102 there is no particular limitation on a material and the like of the substrate 102 as long as the material has heat resistance high enough to withstand at least heat treatment to be performed later.
  • a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102.
  • a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, an SOI substrate, or the like can be used, or any of these substrates provided with a semiconductor element may be used as the substrate 102.
  • a glass substrate having any of the following sizes can be used: the 6th generation (1500 mm x 1850 mm), the 7th generation (1870 mm x 2200 mm), the 8th generation (2200 mm x 2400 mm), the 9th generation (2400 mm x 2800 mm), and the 10th generation (2950 mm x 3400 mm).
  • the 6th generation (1500 mm x 1850 mm) the 7th generation (1870 mm x 2200 mm), the 8th generation (2200 mm x 2400 mm), the 9th generation (2400 mm x 2800 mm), and the 10th generation (2950 mm x 3400 mm).
  • a flexible substrate may be used as the substrate 102, and the transistor
  • the transistor 100 may be provided directly on the flexible substrate.
  • a separation layer may be provided between the substrate 102 and the transistor 100.
  • the separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate 102 and transferred onto another substrate. In such a case, the transistor 100 can be transferred to a substrate having low heat resistance or a flexible substrate as well.
  • the insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate.
  • the insulating film 104 can be formed to have a single-layer structure or stacked-layer structure including an oxide insulating film and/or a nitride insulating film.
  • at least a region of the insulating film 104 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film.
  • oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108 by heat treatment.
  • the thickness of the insulating film 104 can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm.
  • the thickness of the insulating film 104 can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm.
  • the insulating film 104 can be formed to have a single-layer structure or stacked-layer structure including silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga-Zn oxide, or the like.
  • the insulating film 104 has a stacked-layer structure including a silicon nitride film and a silicon oxynitride film.
  • oxygen can be efficiently introduced into the oxide semiconductor film 108.
  • the conductive film 112 functioning as a gate electrode and the conductive films 120a and 120b functioning as a source electrode and a drain electrode can each be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co); an alloy including any of these metal elements as its component; an alloy including a combination of any of these metal elements; or the like.
  • a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co); an alloy including any of these metal
  • the conductive films 112, 120a, and 120b can be formed using an oxide conductor or an oxide semiconductor, such as an oxide including indium and tin (In-Sn oxide), an oxide including indium and tungsten (In-W oxide), an oxide including indium, tungsten, and zinc (In-W-Zn oxide), an oxide including indium and titanium (In-Ti oxide), an oxide including indium, titanium, and tin (In-Ti-Sn oxide), an oxide including indium and zinc (In-Zn oxide), an oxide including indium, tin, and silicon (In-Sn-Si oxide), or an oxide including indium, gallium, and zinc (In-Ga-Zn oxide).
  • an oxide conductor or an oxide semiconductor such as an oxide including indium and tin (In-Sn oxide), an oxide including indium and tungsten (In-W oxide), an oxide including indium, tungsten, and zinc (In-W-Zn oxide), an oxide including indium and titanium (In-Ti oxide), an oxide including
  • an oxide conductor is described.
  • an oxide conductor may be referred to as OC.
  • oxygen vacancies are formed in an oxide semiconductor, and then hydrogen is added to the oxygen vacancies, so that a donor level is formed in the vicinity of the conduction band.
  • This increases the conductivity of the oxide semiconductor; accordingly, the oxide semiconductor becomes a conductor.
  • the oxide semiconductor having become a conductor can be referred to as an oxide conductor.
  • Oxide semiconductors generally transmit visible light because of their large energy gap. Since an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band, the influence of absorption due to the donor level is small in an oxide conductor, and an oxide conductor has a visible light transmitting property comparable to that of an oxide semiconductor.
  • a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive films 112, 120a, and 120b.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti
  • the use of a Cu-X alloy film results in lower fabrication costs because the film can be processed by wet etching.
  • any one or more elements selected from titanium, tungsten, tantalum, and molybdenum are preferably included in the conductive films 112, 120a, and 120b.
  • a tantalum nitride film is particularly preferable as each of the conductive films 112, 120a, and 120b.
  • a tantalum nitride film has conductivity and a high barrier property against copper or hydrogen. Because a tantalum nitride film releases little hydrogen from itself, it can be favorably used as the conductive film in contact with the oxide semiconductor film 108 or the conductive film in the vicinity of the oxide semiconductor film 108.
  • the conductive films 112, 120a, and 120b can be formed by electroless plating.
  • a material that can be deposited by electroless plating for example, one or more elements selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. It is further favorable to use Cu or Ag because the resistance of the conductive film can be reduced.
  • an insulating layer including at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.
  • PECVD plasma enhanced chemical vapor deposition
  • the insulating film 110 that is in contact with the oxide semiconductor film 108 functioning as a channel region of the transistor 100 is preferably an oxide insulating film and preferably includes a region including oxygen in excess of the stoichiometric composition (oxygen-excess region).
  • the insulating film 110 is an insulating film capable of releasing oxygen.
  • the insulating film 110 is formed in an oxygen atmosphere, or the deposited insulating film 110 is subjected to heat treatment in an oxygen atmosphere, for example.
  • hafnium oxide has higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, by using hafnium oxide, the thickness of the insulating film 110 can be made large as compared with the case of using silicon oxide; thus, leakage current due to tunnel current can be low. That is, it is possible to provide a transistor with a low off-state current.
  • hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure, in order to obtain a transistor with a low off-state current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples.
  • the insulating film 110 have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible.
  • the signals include a signal due to an E 7 center observed at a g-factor of 2.001. Note that the E 7 center is due to the dangling bond of silicon.
  • a silicon oxide film or a silicon oxynitride film whose spin density of a signal due to the E 7 center is lower than or equal to 3 x 10 17 spins/cm 3 and preferably lower than or equal to 5 x 10 16 spins/cm 3 may be used.
  • a signal due to nitrogen dioxide (N0 2 ) might be observed in the insulating film 110.
  • the signal is divided into three signals according to the N nuclear spin; a first signal, a second signal, and a third signal.
  • the first signal is observed at a ⁇ --factor of greater than or equal to 2.037 and less than or equal to 2.039.
  • the second signal is observed at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003.
  • the third signal is observed at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966.
  • insulating film 110 It is suitable to use an insulating film whose spin density of a signal due to nitrogen dioxide (N0 2 ) is higher than or equal to 1 x 10 17 spins/cm 3 and lower than 1 x 10 18 spins/cm 3 as the insulating film 110, for example.
  • a nitrogen oxide (NO x ) such as nitrogen dioxide (N0 2 ) forms a state in the insulating film 110.
  • the state is positioned in the energy gap of the oxide semiconductor film 108.
  • nitrogen oxide (NO x ) is diffused to the interface between the insulating film 110 and the oxide semiconductor film 108, an electron might be trapped by the state on the insulating film 110 side.
  • the trapped electron remains in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, leading to a positive shift of the threshold voltage of the transistor. Accordingly, the use of a film with a low nitrogen oxide content as the insulating film 110 can reduce a shift of the threshold voltage of the transistor.
  • a silicon oxynitride film As an insulating film that releases a small amount of nitrogen oxide (NO x ), for example, a silicon oxynitride film can be used.
  • the silicon oxynitride film releases more ammonia than nitrogen oxide (NO x ) in thermal desorption spectroscopy (TDS) analysis; the typical released amount of ammonia is greater than or equal to 1 x 10 18 molecules/cm 3 and less than or equal to 5 x 10 19 molecules/cm 3 .
  • the released amount of ammonia is the total amount of ammonia released by heat treatment in a range of 50 °C to 650 °C or 50 °C to 550 °C in TDS analysis.
  • nitrogen oxide (NO x ) reacts with ammonia and oxygen in heat treatment, the use of an insulating film that releases a large amount of ammonia reduces nitrogen oxide (NO x ).
  • the nitrogen concentration in the film is preferably lower than or equal to 6 x 10 20 atoms/cm 3 .
  • the oxide semiconductor film 108 can be formed using the materials described above.
  • the oxide semiconductor film 108 includes In-M-Zn oxide
  • the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide satisfy In > M.
  • the oxide semiconductor film 108 is formed of In-M-Zn oxide
  • a target including polycrystalline In-M-Zn oxide facilitates formation of the oxide semiconductor film 108 having crystallinity.
  • the atomic ratio of metal elements in the formed oxide semiconductor film 108 varies from the above atomic ratios of metal elements of the sputtering targets in a range of ⁇ 40%.
  • the atomic ratio of the oxide semiconductor film 108 may be 4:2:3 or in its neighborhood.
  • the atomic ratio of the oxide semiconductor film 108 may be 5: 1 :6 or in its neighborhood.
  • the energy gap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more. With the use of an oxide semiconductor having such a wide energy gap, the off-state current of the transistor 100 can be reduced.
  • the oxide semiconductor film 108 may have a non-single-crystal structure.
  • the non-single-crystal structure include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) which will be described later, a polycrystalline structure, a microcrystalline structure, and an amorphous structure.
  • CAAC-OS c-axis-aligned crystalline oxide semiconductor
  • the insulating film 116 contains nitrogen or hydrogen.
  • a nitride insulating film can be used as the insulating film 116, for example.
  • the nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, or the like.
  • the hydrogen concentration in the insulating film 116 is preferably higher than or equal to 1 x 10 22 atoms/cm 3 .
  • the insulating film 116 is in contact with the region 108n of the oxide semiconductor film 108.
  • the concentration of an impurity (nitrogen or hydrogen) in the region 108n in contact with the insulating film 116 is increased, leading to an increase in the carrier density of the region 108n.
  • an oxide insulating film can be used as the insulating film 118.
  • a layered film of an oxide insulating film and a nitride insulating film can be used as the insulating film 118.
  • the insulating film 118 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide.
  • the insulating film 118 preferably functions as a barrier film against hydrogen, water, and the like from the outside.
  • the thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
  • FIG. 2A is a top view of the transistor 150.
  • FIG. 2B is a cross-sectional view taken along a dashed-dotted line X1-X2 in FIG. 2A.
  • FIG. 2C is a cross-sectional view taken along a dashed-dotted line Y1-Y2 in FIG. 2A.
  • the transistor 150 illustrated in FIGS. 2A to 2C includes the conductive film 106 over the substrate 102; the insulating film 104 over the conductive film 106; the oxide semiconductor film 108 over the insulating film 104; the insulating film 110 over the oxide semiconductor film 108; the conductive film 112 over the insulating film 110; and the insulating film 116 over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112.
  • the oxide semiconductor film 108 has a structure similar that in the transistor 100 shown in FIGS. 1A to 1C.
  • the transistor 150 shown in FIGS. 2A to 2C includes the conductive film 106 and an opening 143 in addition to the components of the transistor 100 described above. [0123]
  • the opening 143 is provided in the insulating films 104 and 110.
  • the conductive film 106 is electrically connected to the conductive film 112 through the opening 143.
  • the same potential is applied to the conductive film 106 and the conductive film 112.
  • different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143.
  • the conductive film 106 may be used as a light-blocking film without providing the opening 143.
  • the conductive film 106 is formed using a light-blocking material, for example, light from the bottom that irradiates the oxide semiconductor film 108 where a channel region is formed can be reduced.
  • the conductive film 106 functions as a first gate electrode (also referred to as a bottom-gate electrode), the conductive film 112 functions as a second gate electrode (also referred to as a top-gate electrode), the insulating film 104 functions as a first gate insulating film, and the insulating film 110 functions as a second gate insulating film.
  • the conductive film 106 can be formed using a material similar to the above-described materials of the conductive films 112, 120a, and 120b. It is particularly suitable to use a material containing copper as the conductive film 106 because the resistance can be reduced. It is favorable that, for example, each of the conductive films 106, 120a, and 120b has a stacked-layer structure in which a copper film is over a titanium nitride film, a tantalum nitride film, or a tungsten film. In that case, by using the transistor 150 as a pixel transistor and/or a driving transistor of a display device, parasitic capacitance generated between the conductive films 106 and 120a and between the conductive films 106 and 120b can be reduced.
  • the conductive films 106, 120a, and 120b can be used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 150, but also as power source supply wirings, signal supply wirings, connection wirings, or the like of the display device.
  • the transistor 150 in FIGS. 2A to 2C has a structure in which conductive films functioning as a gate electrode are provided over and under the oxide semiconductor film 108.
  • a semiconductor device of one embodiment of the present invention may have a plurality of gate electrodes.
  • the oxide semiconductor film 108 faces the conductive film 106 functioning as a first gate electrode and the conductive film 112 functioning as a second gate electrode and is positioned between the two conductive films functioning as the gate electrodes.
  • the length of the conductive film 112 in the channel width direction is larger than the length of the oxide semiconductor film 108 in the channel width direction.
  • the whole oxide semiconductor film 108 is covered with the conductive film 112 with the insulating film 110 placed therebetween. Since the conductive film 112 is connected to the conductive film 106 through the opening 143 provided in the insulating films 104 and 110, a side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 placed therebetween.
  • the conductive film 106 and the conductive film 112 are connected through the opening 143 provided in the insulating films 104 and 110, and each include a region positioned outside an edge portion of the oxide semiconductor film 108.
  • Such a structure enables the oxide semiconductor film 108 included in the transistor 150 to be electrically surrounded by electric fields of the conductive film 106 functioning as a first gate electrode and the conductive film 112 functioning as a second gate electrode.
  • a device structure of a transistor, like that of the transistor 150, in which electric fields of the first gate electrode and the second gate electrode electrically surround the oxide semiconductor film 108 in which a channel region is formed can be referred to as a surrounded channel (S-channel) structure.
  • the transistor 150 Since the transistor 150 has the S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 106 or the conductive film 112; thus, the current drive capability of the transistor 150 can be improved and high on-state current characteristics can be obtained. As a result of the high on-state current, it is possible to reduce the size of the transistor 150. Furthermore, since the transistor 150 has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 150 can be increased.
  • an opening different from the opening 143 may be formed on the side of the oxide semiconductor film 108 on which the opening 143 is not formed.
  • one of the gate electrodes may be supplied with a signal A, and the other gate electrode may be supplied with a fixed potential V ⁇ .
  • one of the gate electrodes may be supplied with the signal A, and the other gate electrode may be supplied with a signal B.
  • one of the gate electrodes may be supplied with a fixed potential a, and the other gate electrode may be supplied with the fixed potential V ⁇ > .
  • the signal A is, for example, a signal for controlling the on/off state.
  • the signal A may be a digital signal with two kinds of potentials, a potential VI and a potential V2 (VI > V2).
  • the potential VI can be a high power supply potential
  • the potential V2 can be a low power supply potential.
  • the signal A may be an analog signal.
  • the fixed potential is, for example, a potential for controlling a threshold voltage FthA of the transistor.
  • the fixed potential may be the potential VI or the potential V2. In that case, a potential generator circuit for generating the fixed potential is not necessary, which is preferable.
  • the fixed potential V may be different from the potential VI or the potential V2.
  • the threshold voltage can be high in some cases.
  • the fixed potential V may be, for example, lower than the low power supply potential.
  • a high fixed potential can lower the threshold voltage VM O A in some cases.
  • the drain current flowing when the gate-source voltage V G% is a high power supply potential and the operating speed of the circuit including the transistor can be increased in some cases.
  • the fixed potential may be, for example, higher than the low power supply potential.
  • the signal B is, for example, a signal for controlling the on/off state.
  • the signal B may be a digital signal with two kinds of potentials, a potential V3 and a potential V4 (V3 > V4).
  • the potential V3 can be a high power supply potential
  • the potential V4 can be a low power supply potential.
  • the signal B may be an analog signal.
  • the signal B may have the same digital value as the signal A. In this case, it may be possible to increase the on-state current of the transistor and the operating speed of the circuit including the transistor.
  • the potential VI and the potential V2 of the signal A may be different from the potential V3 and the potential V4 of the signal B.
  • the potential amplitude of the signal B V3 - V4
  • the potential amplitude of the signal B V3 - V4
  • the signal B may have a digital value different from that of the signal A.
  • the signal A and the signal B can separately control the transistor, and thus, higher performance can be achieved.
  • the transistor which is, for example, an n-channel transistor can function by itself as a NAND circuit, a NOR circuit, or the like in the following case: the transistor is turned on only when the signal A has the potential VI and the signal B has the potential V3, or the transistor is turned off only when the signal A has the potential V2 and the signal B has the potential V4.
  • the signal B may be a signal for controlling the threshold voltage V t hA-
  • the potential of the signal B in a period in which the circuit including the transistor operates may be different from the potential of the signal B in a period in which the circuit does not operate.
  • the potential of the signal B may vary depending on the operation mode of the circuit. In this case, the potential of the signal B is not changed as frequently as the potential of the signal A in some cases.
  • the signal B may be an analog signal having the same potential as the signal A, an analog signal whose potential is a constant times the potential of the signal A, an analog signal whose potential is higher or lower than the potential of the signal A by a constant, or the like. In this case, it may be possible to increase the on-state current of the transistor and the operating speed of the circuit including the transistor.
  • the signal B may be an analog signal different from the signal A. In this case, the signal A and the signal B can separately control the transistor, and thus, higher performance can be achieved.
  • the signal A may be a digital signal, and the signal B may be an analog signal.
  • the signal A may be an analog signal, and the signal B may be a digital signal.
  • the transistor When both of the gate electrodes of the transistor are supplied with the fixed potentials, the transistor can function as an element equivalent to a resistor in some cases.
  • the effective resistance of the transistor can be sometimes low (high) when the fixed potential V a or the fixed potential is high (low).
  • the effective resistance can be lower (higher) than that of a transistor with only one gate in some cases.
  • the other components of the transistor 150 are similar to those of the transistor 100 described above and have similar effects.
  • FIGS. 3A and 3B are cross-sectional views of a transistor 160.
  • the top view of the transistor 160 is not illustrated because it is similar to that of the transistor 150 in FIG. 2 A.
  • the transistor 160 illustrated in FIGS. 3A and 3B includes an insulating film 122 over the conductive films 120a and 120b and the insulating film 118.
  • the other components of the transistor 160 are similar to those of the transistor 150 and have similar effects.
  • the insulating film 122 has a function of covering unevenness and the like caused by the transistor or the like.
  • the insulating film 122 has an insulating property and is formed using an inorganic material or an organic material.
  • the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film.
  • the organic material include photosensitive resin materials such as an acrylic resin and a polyimide resin.
  • FIGS. 4A and 4B are cross-sectional views of a transistor 170.
  • the top view of the transistor 170 is not illustrated because it is similar to that of the transistor 150 in FIG. 2A.
  • the transistor 170 illustrated in FIGS. 4 A and 4B is different from the transistor 150 in the stacked-layer structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 in the transistor 170 includes a conductive film 112 1 over the insulating film 110 and the conductive film 112 2 over the conductive film 112 1.
  • a conductive film 112 1 over the insulating film 110 and the conductive film 112 2 over the conductive film 112 1.
  • an oxide conductive film is used as the conductive film 112 1, so that excess oxygen can be added to the insulating film 110.
  • the oxide conductive film can be formed by a sputtering method in an atmosphere containing an oxygen gas.
  • an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, an oxide including indium, gallium, and zinc, or the like can be used, for example.
  • the conductive film 112 2 is connected to the conductive film 106 through the opening 143.
  • the opening 143 By forming the opening 143 after a conductive film to be the conductive film 112 1 is formed, the shape illustrated in FIG. 4B can be obtained.
  • the structure in which the conductive film 112 2 is connected to the conductive film 106 can decrease the contact resistance between the conductive film 112 and the conductive film 106.
  • the conductive film 112 and the insulating film 110 in the transistor 170 have a tapered shape. More specifically, the lower edge portion of the conductive film 112 is positioned outside the upper edge portion of the conductive film 112. The lower edge portion of the insulating film 110 is positioned outside the upper edge portion of the insulating film 110. In addition, the lower edge portion of the conductive film 112 is formed in substantially the same position as that of the upper edge portion of the insulating film 110.
  • the transistor 170 in which the conductive film 112 and the insulating film 110 have a rectangular shape is favorable because of better coverage with the insulating film 116.
  • the other components of the transistor 170 are similar to those of the transistor 150 described above and have similar effects.
  • the transistors 100, 150, 160, and 170 in FIGS. 1 A to 1C to FIGS. 4 A and 4B each include the oxide semiconductor film 108 having a three-layer structure of the oxide semiconductor films 108 1 to 108 3, one embodiment of the present invention is not limited thereto.
  • the oxide semiconductor film 108 may have a two-layer structure of the oxide semiconductor films 108 2 and 108 3 as shown in FIG. 5A and 5B to FIGS. 8A and 8B.
  • FIGS. 5 A and 5B are cross-sectional views of a transistor 100A.
  • FIG. 5 A is a cross-sectional view in the channel length direction.
  • FIG. 5B is a cross-sectional view in the channel width direction. Note that the transistor 100A has a structure similar to that of the transistor 100 except that the oxide semiconductor film 108 has a two-layer structure.
  • FIGS. 6A and 6B are cross-sectional views of a transistor 150A.
  • FIG. 6A is a cross-sectional view in the channel length direction.
  • FIG. 6B is a cross-sectional view in the channel width direction. Note that the transistor 150A has a structure similar to that of the transistor 150 except that the oxide semiconductor film 108 has a two-layer structure.
  • FIGS. 7A and 7B are cross-sectional views of a transistor 160A.
  • FIG. 7A is a cross-sectional view in the channel length direction.
  • FIG. 7B is a cross-sectional view in the channel width direction. Note that the transistor 160A has a structure similar to that of the transistor 160 except that the oxide semiconductor film 108 has a two-layer structure.
  • FIGS. 8 A and 8B are cross-sectional views of a transistor 170A.
  • FIG. 8 A is a cross-sectional view in the channel length direction.
  • FIG. 8B is a cross-sectional view in the channel width direction. Note that the transistor 170A has a structure similar to that of the transistor 170 except that the oxide semiconductor film 108 has a two-layer structure.
  • FIGS. 9A to 9D to FIGS. 11 A to 11C are cross-sectional views in the channel length direction and the channel width direction illustrating the manufacturing method of the transistor 150.
  • the conductive film 106 is formed over the substrate 102.
  • the insulating film 104 is formed over the substrate 102 and the conductive film 106.
  • a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film are formed over the insulating film 104.
  • the first to third oxide semiconductor films are processed into an island shape to form oxide semiconductor films 108 1a, 108 2a, and 108 3a (see FIG. 9A).
  • the conductive film 106 can be formed using a material selected from the above-mentioned materials.
  • a layered film of a 50-nm-thick tungsten film and a 400-nm-thick copper film is formed with a sputtering apparatus.
  • a wet etching method and/or a dry etching method can be used.
  • the copper film is etched by a wet etching method and then the tungsten film is etched by a dry etching method.
  • the insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate.
  • a sputtering method a CVD method
  • an evaporation method a pulsed laser deposition (PLD) method
  • PLD pulsed laser deposition
  • a printing method a coating method, or the like as appropriate.
  • a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed with a PECVD apparatus.
  • oxygen may be added to the insulating film 104.
  • oxygen added to the insulating film 104 an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, or the like may be used.
  • Oxygen can be added by an ion doping method, an ion implantation method, a plasma treatment method, or the like.
  • a film that suppresses oxygen release may be formed over the insulating film 104, and then, oxygen may be added to the insulating film 104 through the film.
  • the film that suppresses oxygen release can be formed using a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.
  • the amount of oxygen added to the insulating film 104 can be increased.
  • the oxide semiconductor films 108 1a, 108 2a, and 108 3a are preferably formed successively in a vacuum using a sputtering apparatus.
  • impurities such as hydrogen and water
  • the oxygen partial pressure of the oxide semiconductor film 108 2a is preferably lower than that of the oxide semiconductor film 108 1a and/or the oxide semiconductor film 108 3a.
  • an inert gas e.g., a helium gas, an argon gas, or a xenon gas
  • the oxygen gas may be mixed.
  • the proportion of the oxygen gas in the whole deposition gas (hereinafter also referred to as oxygen flow rate ratio) in forming the oxide semiconductor film 108 1 a is higher than or equal to 70 % and lower than or equal to 100 %, preferably higher than or equal to 80 % and lower than or equal to 100 %, further preferably higher than or equal to 90 % and lower than or equal to 100 %.
  • the oxygen flow rate ratio in forming the oxide semiconductor film 108 2a is higher than 0 % and lower than or equal to 20 %, preferably higher than or equal to 5 % and lower than or equal to 15 %.
  • the oxygen flow rate ratio in forming the oxide semiconductor film 108 3a is higher than or equal to 70 % and lower than or equal to 100 %, preferably higher than or equal to 80 % and lower than or equal to 100 %, further preferably higher than or equal to 90 % and lower than or equal to 100 %.
  • oxide semiconductor film 108 2a may be formed at a lower substrate temperature than the oxide semiconductor film 108 1 a and/or the oxide semiconductor film 108_3a.
  • the oxide semiconductor film 108 2a is formed at a substrate temperature higher than or equal to room temperature and lower than 150 °C, preferably higher than or equal to room temperature and lower than or equal to 140 °C.
  • the oxide semiconductor film 108 1a and the oxide semiconductor film 108 3a are formed at a substrate temperature higher than or equal to room temperature and lower than or equal to 300 °C, preferably higher than or equal to room temperature and lower than or equal to 200 °C.
  • the substrate temperatures when the metal oxides 108 1a, 108 2a, and 108 3a are formed are preferably the same (e.g., higher than or equal to room temperature and lower than 150 °C) because the productivity is increased.
  • the oxide semiconductor film 108 2a can have a region with lower crystallinity than the metal oxides 108 1a and 108 3a.
  • the thickness of the oxide semiconductor film 108 1 a is greater than or equal to 1 nm and less than 20 nm, preferably greater than or equal to 5 nm and less than or equal to 10 nm.
  • the thickness of the oxide semiconductor film 108 2a is greater than or equal to 20 nm and less than or equal to 100 nm, preferably greater than or equal to 20 nm and less than or equal to 50 nm.
  • the thickness of the oxide semiconductor film 108 3a is greater than or equal to 1 nm and less than 20 nm, preferably greater than or equal to 5 nm and less than or equal to 15 nm.
  • the crystallinity of the oxide semiconductor film 108 can be increased.
  • a large-sized glass substrate e.g., the 6th generation to the 10th generation
  • the oxide semiconductor film 108 is formed at a substrate temperature higher than or equal to 200 °C and lower than or equal to 300 °C
  • the substrate 102 might be changed in shape (distorted or warped).
  • the change in the shape of the glass substrate can be suppressed by forming the oxide semiconductor film 108 at a substrate temperature higher than or equal to 100 °C and lower than 200 °C.
  • a gas which is highly purified to have a dew point of -40 °C or lower, preferably -80 °C or lower, further preferably -100 °C or lower, still further preferably -120 °C or lower is used, whereby entry of moisture or the like into the oxide semiconductor film can be minimized.
  • a chamber in a sputtering apparatus is preferably evacuated to be a high vacuum state (to the degree of about 5 x 10 ⁇ 7 Pa to 1 x 10 ⁇ 4 Pa) with an adsorption vacuum evacuation pump such as a cryopump in order to remove water or the like, which serves as an impurity for the oxide semiconductor film, as much as possible.
  • the oxide semiconductor films 108 1a, 108 2a, and 108 3a are formed in the following conditions.
  • the oxide semiconductor film 108 1 a is formed by a sputtering method using an
  • the substrate temperature is room temperature, and an oxygen gas at a flow rate of 200 seem is used as a deposition gas (percentage of oxygen flow rate: 100%).
  • the substrate temperature is room temperature, and an oxygen gas at a flow rate of 20 seem and an argon gas at a flow rate of 180 seem is used as a deposition gas (percentage of oxygen flow rate: 10%).
  • the substrate temperature is room temperature, and an oxygen gas at a flow rate of 200 seem is used as a deposition gas (percentage of oxygen flow rate: 100%).
  • a wet etching method and/or a dry etching method can be used for processing the first to third oxide semiconductor films into the oxide semiconductor films 108 1a to 108 3a, respectively.
  • the oxide semiconductor films 108 1a, 108 2a, and 108 3a are formed and then may be dehydrated or dehydrogenated by heat treatment.
  • the temperature of the heat treatment is typically higher than or equal to 150 °C and lower than the strain point of the substrate, higher than or equal to 250 °C and lower than or equal to 450 °C, or higher than or equal to 300 °C and lower than or equal to 450 °C.
  • the heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton.
  • the heat treatment may be performed in an inert gas atmosphere first, and then, in an oxygen atmosphere. It is preferable that the above inert gas atmosphere and the above oxygen atmosphere do not contain hydrogen, water, and the like.
  • the treatment time may be longer than or equal to 3 minutes and shorter than or equal to 24 hours.
  • An electric furnace, an RTA apparatus, or the like can be used for the heat treatment.
  • the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened.
  • the hydrogen concentration in the oxide semiconductor film which is measured by SIMS, can be 5 x 10 19 atoms/cm 3 or lower, 1 x
  • an insulating film 110 0 is formed over the insulating film 104 and the oxide semiconductor film 108 (see FIG. 9B).
  • a silicon oxide film or a silicon oxynitride film can be formed with a plasma-enhanced chemical vapor deposition apparatus (a PECVD apparatus or simply referred to as a plasma CVD apparatus).
  • a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas.
  • the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride.
  • oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given.
  • a silicon oxynitride film having few defects can be formed as the insulating film 110 0 with a PECVD apparatus under the conditions that the flow rate of the oxidizing gas is more than
  • a dense silicon oxide film or a dense silicon oxynitride film can be formed under the following conditions: the substrate placed in a vacuum-evacuated treatment chamber of a PECVD apparatus is held at a temperature higher than or equal to 280 °C and lower than or equal to 400 °C, the pressure in the treatment chamber into which a source gas is introduced is set to be higher than or equal to 20 Pa and lower than or equal to 250 Pa, preferably higher than or equal to 100 Pa and lower than or equal to 250 Pa, and a high-frequency power is supplied to an electrode provided in the treatment chamber.
  • the insulating film 110 0 may be formed by a PECVD method using a microwave.
  • a microwave refers to a wave in the frequency range of 300 MHz to 300 GHz.
  • electron temperature and electron energy are low.
  • the proportion of power used for acceleration of electrons is low, and therefore, much more power can be used for dissociation and ionization of molecules.
  • plasma with a high density (high-density plasma) can be excited. This method causes little plasma damage to the deposition surface or a deposit, so that the insulating film 110 0 having few defects can be formed.
  • the insulating film 110 0 can also be formed by a CVD method using an organosilane gas.
  • organosilane gas the following silicon-containing compound can be used: tetraethyl orthosilicate (TEOS) (chemical formula: Si(OC 2 H 5 ) 4 ), tetramethylsilane (TMS) (chemical formula: Si(CH 3 ) 4 ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2 H 5 ) 3 ), trisdimethylaminosilane (SiH(N(CH 3 ) 2 ) 3 ), or the like.
  • TEOS tetraethyl orthosilicate
  • TMS tetramethylsilane
  • TMS tetramethylcyclotetrasiloxane
  • a 100-nm-thick silicon oxynitride film is formed with a PECVD apparatus.
  • a mask is formed by lithography in a desired position over the insulating film 110 0, and then, the insulating film 110 0 and the insulating film 104 are partly etched, so that the opening 143 reaching the conductive film 106 is formed (see FIG. 9C).
  • a wet etching method and/or a dry etching method can be used.
  • the opening 143 is formed by a dry etching method.
  • a conductive film 112 0 is formed over the conductive film 106 and the insulating film 110 0 so as to cover the opening 143.
  • oxygen might be added to the insulating film 110 0 during the formation of the conductive film 112 0 (see FIG. 9D).
  • FIG. 9D oxygen added to the insulating film 110 0 is schematically shown by arrows. Furthermore, the conductive film 112 0 formed to cover the opening 143 is electrically connected to the conductive film 106.
  • the conductive film 112 0 is preferably formed by a sputtering method in an atmosphere containing an oxygen gas. Formation of the conductive film 112 0 in an atmosphere containing an oxygen gas allows suitable addition of oxygen to the insulating film 110 0. Note that a method for forming the conductive film 112 0 is not limited to a sputtering method, and other methods such as an ALD method may be used.
  • a 100-nm-thick IGZO film containing an In-Ga-Zn oxide In:Ga:Zn
  • oxygen addition treatment may be performed on the insulating film 110 0 before or after the formation of the conductive film 112 0.
  • the oxygen addition treatment can be performed in a manner similar to that of the oxygen addition that can be performed after the formation of the insulating film 104.
  • a mask 140 is formed by a lithography process in a desired position over the conductive film 112 0 (see FIG. 10A).
  • etching is performed from above the mask 140 to process the conductive film
  • the conductive film 112 0 and the insulating film 110 0 are processed by a dry etching method.
  • the thickness of the oxide semiconductor film 108 in a region not overlapping with the conductive film 112 is decreased in some cases. In other cases, in the processing into the conductive film 112 and the insulating film 110, the thickness of the insulating film 104 in a region not overlapping with the oxide semiconductor film 108 is decreased.
  • an etchant or an etching gas e.g., chlorine
  • an etchant or an etching gas might be added to the oxide semiconductor film 108 or the constituent element of the conductive film 112 0 or the insulating film 110 0 might be added to the oxide semiconductor film 108.
  • the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112, whereby part of the oxide semiconductor film 108, which is in contact with the insulating film 116 becomes the region 108n. Furthermore, the oxide semiconductor film 108 overlapping with the conductive film 112 includes oxide semiconductor films 108 1, 108 2, and 108 3 (see FIG. IOC).
  • the insulating film 116 can be formed using a material selected from the above-mentioned materials.
  • a 100-nm-thick silicon nitride oxide film is formed with a PECVD apparatus.
  • plasma treatment and deposition treatment are performed at 220 °C.
  • the plasma treatment is performed before deposition under the following conditions: an argon gas at a flow rate of 100 seem and a nitrogen gas at a flow rate of 1000 seem are introduced into a chamber, the pressure in the chamber is set to 40 Pa, and power of 1000 W is supplied to an RF power source (27.12 MHz).
  • the deposition treatment is performed under the following conditions: a silane gas at a flow rate of 50 seem, a nitrogen gas at a flow rate of 5000 seem, and an ammonia gas at a flow rate of 100 seem are introduced into the chamber; the pressure in the chamber is set to 100 Pa; and power of 1000 W is supplied to the RF power source (27.12 MHz).
  • the insulating film 116 includes a silicon nitride oxide film
  • nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the region 108n in contact with the insulating film 116.
  • the temperature in forming the insulating film 116 is the above-mentioned temperature, release of excess oxygen contained in the insulating film 110 to the outside can be suppressed.
  • the insulating film 118 is formed over the insulating film 116 (see FIG. 11A).
  • the insulating film 118 can be formed using a material selected from the above-mentioned materials.
  • a 300-nm-thick silicon oxynitride film is formed with a PECVD apparatus.
  • a mask is formed over desired positions of the insulating film 118 by lithography, and the insulating film 118 and the insulating film 116 are partly etched.
  • the openings 141a and 141b reaching the region 108n are formed (see FIG. 11B).
  • a wet etching method and/or a dry etching method can be used.
  • the insulating films 118 and 116 are processed by a dry etching method.
  • a conductive film is formed over the region 108n and the insulating film 118 to cover the openings 141a and 141b, and processed into desired shapes, so that the conductive films 120a and 120b are formed (see FIG. 11C).
  • the conductive films 120a and 120b can be formed using a material selected from the above-mentioned materials.
  • a layered film including a 50-nm-thick tungsten film and a 400-nm-thick copper film is formed with a sputtering apparatus.
  • a wet etching method and/or a dry etching method can be used.
  • the copper film is etched by a wet etching method and then the tungsten film is etched by a dry etching method.
  • the transistor 150 in FIGS. 2A to 2C can be fabricated.
  • the films included in the transistor 150 can be formed by, other than the above methods, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or an ALD method.
  • a coating method or a printing method can be used.
  • a thermal CVD method may be used.
  • a metal organic chemical vapor deposition (MOCVD) method can be given.
  • Deposition by a thermal CVD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and a source gas and an oxidizer are supplied to the chamber at a time and react with each other in the vicinity of the substrate or over the substrate.
  • a thermal CVD method has an advantage that no defect due to plasma damage is caused.
  • the films such as the conductive films, the insulating films, the oxide semiconductor films, and the metal oxide films that are described above can be formed by a thermal CVD method such as an MOCVD method.
  • a thermal CVD method such as an MOCVD method.
  • trimethylindium (In(CH 3 ) 3 ), trimethylgallium (Ga(CH 3 ) 3 ), and dimethylzinc (Zn(CH 3 ) 2 ) are used.
  • triethylgallium (Ga(C 2 H 5 ) 3 ) can be used instead of trimethylgallium and diethylzinc (Zn(C 2 H 5 ) 2 ) can be used instead of dimethylzinc.
  • hafnium oxide film is formed with a deposition apparatus employing an ALD method
  • two kinds of gases are used, namely, ozone (0 3 ) as an oxidizer and a source gas that is obtained by vaporizing liquid containing a solvent and a hafnium precursor (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH 3 ) 2 ] 4 ) or tetraki s(ethy lmethy 1 ami de)hafnium) .
  • hafnium precursor hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH 3 ) 2 ] 4
  • tetraki s(ethy lmethy 1 ami de)hafnium hafnium alkoxide or hafnium amide such
  • an aluminum oxide film is formed with a deposition apparatus employing an ALD method
  • two kinds of gases are used, namely, H 2 0 as an oxidizer and a source gas that is obtained by vaporizing liquid containing a solvent and an aluminum precursor (e.g., trimethylaluminum (TMA, A1(CH 3 ) 3 )).
  • a source gas that is obtained by vaporizing liquid containing a solvent and an aluminum precursor (e.g., trimethylaluminum (TMA, A1(CH 3 ) 3 )).
  • TMA trimethylaluminum
  • A1(CH 3 ) 3 aluminum precursor
  • hexachlorodisilane is adsorbed on a surface on which a film is to be formed, and radicals of an oxidizing gas (0 2 or dinitrogen monoxide) are supplied to react with the adsorbate.
  • a WF 6 gas and a B 2 H 6 gas are sequentially introduced to form an initial tungsten film, and then, a WF 6 gas and an H 2 gas are used to form a tungsten film.
  • an SiFL. gas may be used instead of a B 2 H 6 gas.
  • an oxide semiconductor film such as an In-Ga-Zn-0 film is formed with a deposition apparatus employing an ALD method
  • an In(CH 3 ) 3 gas and an 0 3 gas are used to form an In-0 layer
  • a Ga(CH 3 ) 3 gas and an 0 3 gas are used to form a Ga-0 layer
  • a Zn(CH 3 ) 2 gas and an 0 3 gas are used to form a Zn-0 layer.
  • a mixed compound layer such as an In-Ga-0 layer, an In-Zn-0 layer, or a Ga-Zn-0 layer may be formed by using these gases.
  • an H 2 0 gas that is obtained by bubbling water with an inert gas such as Ar may be used instead of an 0 3 gas, it is preferable to use an 0 3 gas, which does not contain H.
  • the transistor includes an oxide semiconductor film.
  • the transistor does not necessarily include an oxide semiconductor film.
  • a channel region, the vicinity of the channel region, a source region, or a drain region of the transistor may be formed using a material containing silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or the like.
  • an oxide semiconductor film of one embodiment of the present invention will be described with reference to FIGS. 13A and 13B to FIGS. 32A to 32C.
  • An oxide semiconductor film of one embodiment of the present invention preferably contains at least indium and zinc.
  • aluminum, gallium, yttrium, tin, or the like is preferably contained.
  • one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.
  • an oxide semiconductor film contains indium, an element , and zinc
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • the element M can be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. Note that two or more of the above elements may be used in combination as the element in some cases.
  • FIGS. 13A and 13B, FIGS. 14A and 14B, FIGS. 15A and 15B, and FIGS. 16A and 16B are schematic views of oxide semiconductor films of embodiments of the present invention.
  • FIG. 13A, FIG. 14A, FIG. 15A, and FIG. 16A are schematic views of top surfaces of the oxide semiconductor films (a-b plane direction) and FIG. 13B, FIG. 14B, FIG. 15B, and FIG. 16B are schematic views of cross sections of oxide semiconductor films (c-axis direction) each formed over a substrate (Sub.).
  • an oxide semiconductor film of one embodiment of the present invention includes Region A and Region B. That is, an oxide semiconductor film of one embodiment of the present invention is a composite oxide semiconductor in which Region A and Region B are mixed.
  • Region A is represented by ln x Zn y z (x, y, and z each represent a given number) and Region B is represented by Ina 3 ⁇ 4Zn c Or f (M represents Al, Ga, Y, or Sn and a, b, c, and d each represent a given number).
  • Region A may contain M.
  • the In concentration in Region A is higher than that in Region B.
  • Region A is In-rich and Region B is In-poor.
  • the In concentration in Region A be greater than or equal to 1.1 times, further preferably greater than or equal to two times and less than or equal to 10 times the In concentration in Region B.
  • Region A is basically formed to have an almost circular shape in the a-b plane direction.
  • Region A is basically formed to have an almost elliptical shape in the c-axis direction.
  • Region A has an island-like shape and is surrounded by Region B.
  • Regions A are unevenly distributed in Region B. For this reason, two or more Regions A might be connected to be shaped like connected circles or connected ellipses. Note that the switching characteristics of the transistor are degraded (for example, the off-state current of the transistor is increased) when all of Regions A are connected in the c-axis direction; thus, Regions A are preferably scattered as shown in FIGS. 13A and 13B.
  • the proportion of scattered Regions A can be adjusted by changing, for example, the formation conditions or composition of the composite oxide semiconductor. For example, it is possible to form a composite oxide semiconductor in which the proportion of Regions A is low as shown in FIGS. 14A and 14B or a composite oxide semiconductor in which the proportion of Regions A is high as shown in FIGS. 15A and 15B. In a composite oxide semiconductor, the proportion of Regions A is not always lower than that of Region B. In a composite oxide semiconductor with an extremely high proportion of Regions A, depending on the observation range, Region B is sometimes formed in Region A.
  • the size of the island-like shape of Region A can be adjusted by changing, for example, the formation conditions or composition of the composite oxide semiconductor.
  • the island-like regions have various sizes in the schematic views in FIGS. 13A and 13B, FIGS. 14A and 14B, and FIGS. 15A and 15B, Regions A with substantially the same size are scattered as shown in FIGS. 16A and 16B in some cases.
  • Region A is sometimes observed as having a size of greater than or equal to 0.1 nm and less than or equal to 5 nm or greater than or equal to 0.3 nm and less than or equal to 3 nm in an EDX mapping image of a cross-sectional photograph.
  • Region A Since Region A is In-rich, it has a function of increasing carrier mobility. Thus, a transistor that uses an oxide semiconductor film including Region A can have increased on-state current and increased field-effect mobility. In contrast, since Region B is In-poor, it has a function of reducing carrier mobility. Thus, a transistor that uses an oxide semiconductor film including Region B can have reduced off-state current. In other words, Region A contributes to the on-state current and field-effect mobility of a transistor and Region B contributes to the switching characteristics of the transistor. [0238]
  • an oxide semiconductor film of one embodiment of the present invention is a composite oxide semiconductor in which Region A and Region B are mixed and have different functions that are complementary.
  • an oxide semiconductor film of one embodiment of the present invention is an In-Ga-Zn oxide (hereinafter referred to as IGZO), in which Ga is used as the element , the oxide semiconductor film can be called complementary IGZO (abbreviation: C/IGZO).
  • Region A and Region B are stacked in a layered manner, for example, interaction does not take place or is unlikely to take place between Region A and Region B, so that the function of Region A and that of Region B are independently performed in some cases.
  • an oxide semiconductor film of one embodiment of the present invention is the above-described composite oxide semiconductor or C/IGZO, a function of achieving high field-effect mobility and a function of achieving excellent switching characteristics can be obtained at the same time.
  • FIGS. 13 A and 13B illustrate an example in which the oxide semiconductor film is formed over the substrate; however, one embodiment of the present invention is not limited to this example and an insulating film such as a base film or an interlayer film or another semiconductor film such as an oxide semiconductor film may be formed between the substrate and the oxide semiconductor film.
  • an insulating film such as a base film or an interlayer film or another semiconductor film such as an oxide semiconductor film may be formed between the substrate and the oxide semiconductor film.
  • the phase diagram in FIG. 17 can be used to show the atomic ratio of an element Xto an element Y to an element Z in a substance.
  • the atomic ratio of the element Xto the element Y to the element Z is denoted by x:y.z. This atomic ratio can be shown as coordinates (x:y:z) in FIG. 17. Note that the proportion of oxygen atoms is not shown in FIG. 17.
  • broken lines indicate a line where the atomic ratio [In]: [AJJ: [Zn] is (1+ ⁇ ):(1- ⁇ ): 1, where -1 ⁇ a ⁇ 1, a line where the atomic ratio [In] : [A/] : [Zn] is (1+ ⁇ ):(1- ⁇ ):2, a line where the atomic ratio [In] : [AJJ: [Zn] is (1+ ⁇ ):(1- ⁇ ):3, a line where the atomic ratio [In] : [AJJ : [Zn] is (1+ ⁇ ):(1- ⁇ ):4, and a line where the atomic ratio [In]: [A/] : [Zn] is (1+ ⁇ ):(1- ⁇ ):5.
  • Dashed-dotted lines indicate a line where the atomic ratio [In]: [A/] : [Zn] is 1 : 1 :/?, where
  • the oxide semiconductor film shown in FIG. 17 with an atomic ratio of [In] : [A/] : [Zn] 0:2: 1 or an atomic ratio that is in the neighborhood thereof tends to have a spinel crystal structure.
  • Region A in FIG. 17 is an example of a preferable range of the atomic ratio of In to to
  • Region A includes a line where the atomic ratio [In]: [A/] : [Zn] is ( ⁇ + ⁇ ):0:(1- ⁇ ) -Kj ⁇ l).
  • Region B in FIG. 17 is an example of a preferable range of the atomic ratio of In to to
  • An oxide semiconductor film with an atomic ratio represented by Region B is an oxide semiconductor film that has high crystallinity.
  • the oxide semiconductor film is formed with a sputtering apparatus
  • a film having an atomic ratio different from the atomic ratio of the target is formed in some cases. Specifically, depending on the substrate temperature during deposition, the atomic proportion of [Zn] in a deposited film is lower than that of [Zn] in the target in some cases.
  • FIGS. 18A and 18B An example of the sputtering apparatus is described with reference to FIGS. 18A and 18B.
  • FIG. 18A is a cross-sectional view of a deposition chamber 2501 of the sputtering apparatus.
  • FIG. 18B is a plan view of a magnet unit 2530a and a magnet unit 2530b of the sputtering apparatus.
  • the deposition chamber 2501 illustrated in FIG. 18A includes a target holder 2520a, a target holder 2520b, a backing plate 2510a, a backing plate 2510b, a target 2500a, a target 2500b, a member 2542, and a substrate holder 2570.
  • the target 2500a is placed over the backing plate 2510a.
  • the backing plate 2510a is placed over the target holder 2520a.
  • the magnet unit 2530a is placed under the target 2500a with the backing plate 2510a therebetween.
  • the target 2500b is placed over the backing plate 2510b.
  • the backing plate 2510b is placed over the target holder 2520b.
  • the magnet unit 2530b is placed under the target 2500b with the backing plate 2510b therebetween.
  • the magnet unit 2530a includes a magnet 2530N1, a magnet 2530N2, a magnet 2530S, and a magnet holder 2532.
  • the magnet 2530N1, the magnet 2530N2, and the magnet 2530S are placed over the magnet holder 2532 in the magnet unit 2530a.
  • the magnet 2530N1, the magnet 2530N2, and the magnet 2530S are spaced.
  • the magnet unit 2530b has a structure similar to that of the magnet unit 2530a.
  • the target 2500a, the backing plate 2510a, and the target holder 2520a are separated from the target 2500b, the backing plate 2510b, and the target holder 2520b by the member 2542.
  • the member 2542 is preferably an insulator.
  • the member 2542 may be a conductor or a semiconductor.
  • the member 2542 may be a conductor or a semiconductor whose surface is covered with an insulator.
  • the target holder 2520a and the backing plate 2510a are fixed to each other with a screw (e.g., a bolt) and have the same potential.
  • the target holder 2520a has a function of supporting the target 2500a with the backing plate 2510a positioned therebetween.
  • the target holder 2520b and the backing plate 2510b are fixed to each other with a screw (e.g., a bolt) and have the same potential.
  • the target holder 2520b has a function of supporting the target 2500b with the backing plate 2510b positioned therebetween.
  • the backing plate 2510a has a function of fixing the target 2500a.
  • the backing plate 2510b has a function of fixing the target 2500b.
  • Magnetic lines of force 2580a and 2580b formed by the magnet unit 2530a are illustrated in FIG. 18 A.
  • the magnet unit 2530a has a structure in which the magnet 2530N1 having a rectangular or substantially rectangular shape, the magnet 2530N2 having a rectangular or substantially rectangular shape, and the magnet 2530S having a rectangular or substantially rectangular shape are fixed to the magnet holder 2532.
  • the magnet unit 2530a can be oscillated horizontally as shown by an arrow in FIG. 18B.
  • the magnet unit 2530a may be oscillated with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
  • the magnetic field over the target 2500a changes in accordance with oscillation of the magnet unit 2530a.
  • the region with an intense magnetic field is a high-density plasma region; thus, sputtering of the target 2500a easily occurs in the vicinity of the region.
  • the target 2500a and the target 2500b are each an In-Ga-Zn oxide target.
  • the deposition model of an oxide semiconductor film of one embodiment of the present invention can be presumed in the following manner.
  • the gases introduced into the sputtering apparatus are an argon gas and an oxygen gas. Furthermore, a potential applied to a terminal VI connected to the target holder 2520a is lower than a potential applied to a terminal V2 connected to the substrate holder 2570. A potential applied to a terminal V4 connected to the target holder 2520b is lower than the potential applied to the terminal V2 connected to the substrate holder 2570. The potential applied to the terminal V2 connected to the substrate holder 2570 is a ground potential. A potential applied to a terminal V3 connected to the magnet holder 2532 is a ground potential.
  • the potentials applied to the terminals VI, V2, V3, and V4 are not limited to the above-described potentials. Not all the target holder 2520, the substrate holder 2570, and the magnet holder 2532 are necessarily supplied with potentials. For example, the substrate holder 2570 may be electrically floating. Note that it is assumed that a power source capable of controlling a potential applied to the terminal VI is electrically connected to the terminal VI . As the power source, a DC power source, an AC power source, or an RF power source may be used.
  • an argon gas or an oxygen gas is ionized to be separated into cations and electrons, and plasma is created. Then, the cations in the plasma are accelerated toward the targets 2500a and 2500b by the potential VI applied to the target holder 2520a and the potential V4 applied to the target holder 2520b. Sputtered particles are generated when the cations collide with the targets 2500a and 2500b, and the sputtered particles are deposited on the substrate 2560.
  • the targets 2500a and 2500b are each an In-Ga-Zn oxide target
  • the cations collide with the targets 2500a and 2500b, so that Ga and Zn each of which has a smaller relative atom mass than In are sputtered from the targets 2500a and 2500b preferentially to be deposited on the substrate 2560.
  • Ga and Zn each of which has a smaller relative atom mass than In
  • In is segregated on the surfaces of the targets 2500a and 2500b.
  • the In segregated on the surfaces of the targets 2500a and 2500b are sputtered from the targets 2500a and 2500b to be deposited on the substrate 2560.
  • FIGS. 13A and 13B, FIGS. 14A and 14B, FIGS. 15A and 15B, or FIGS. 16A and 16B, in which Region A and Region B are mixed, is presumed to be formed after the above-described deposition model.
  • Examples of a factor affecting the carrier density of an oxide semiconductor film include oxygen vacancies (Vo) and impurities in the oxide semiconductor film.
  • the density of defect states increases when hydrogen is bonded to the oxygen vacancy (this state is also referred to as VoH).
  • the density of defect states also increases with an increase in the amount of impurities in the oxide semiconductor film.
  • the carrier density of an oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.
  • a transistor using the oxide semiconductor film in a channel region will be described below.
  • the carrier density of the oxide semiconductor film is preferably reduced in order to inhibit the negative shift of the threshold voltage of the transistor or reduce the off-state current of the transistor.
  • the impurity concentration in the oxide semiconductor film is reduced so that the density of defect states can be reduced.
  • a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state.
  • the carrier density of a highly purified intrinsic oxide semiconductor film is lower than 8 x 10 15 cm -3 , preferably lower than 1 x 10 11 cm -3 , and further preferably lower than 1 x 10 10 cm -3 and is higher than or equal to 1 x 10 ⁇ 9 cm -3 .
  • the carrier density of the oxide semiconductor film is preferably increased in order to improve the on-state current of the transistor or improve the field-effect mobility of the transistor.
  • the impurity concentration or the density of defect states in the oxide semiconductor film is slightly increased.
  • the bandgap of the oxide semiconductor film is preferably narrowed.
  • an oxide semiconductor film that has a slightly high impurity concentration or a slightly high density of defect states in the range where a favorable on/off ratio is obtained in the Id-Vg characteristics of the transistor can be regarded as substantially intrinsic.
  • an oxide semiconductor film that has a high electron affinity and thus has a narrow bandgap so as to increase the density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that a transistor using an oxide semiconductor film with higher electron affinity has lower threshold voltage.
  • the carrier density of a substantially intrinsic oxide semiconductor film is preferably higher than or equal to 1 x 10 5 cm -3 and lower than 1 x 10 18 cm -3 , further preferably higher than or equal to 1 x 10 7 cm -3 and lower than or equal to 1 x 10 17 cm -3 , still further preferably higher than or equal to 1 x 10 9 cm -3 and lower than or equal to 5 x 10 16 cm -3 , yet further preferably higher than or equal to 1 x 10 10 cm -3 and lower than or equal to 1 x 10 16 cm -3 , and yet still preferably higher than or equal to 1 x 10 11 cm -3 and lower than or equal to 1 x 10 15 cm -3 .
  • FIG. 19 is an energy band diagram of the transistor including the oxide semiconductor film in its channel region.
  • GE, GI, OS, and SD refer to a gate electrode, a gate insulating film, an oxide semiconductor film, and a source/drain electrode, respectively.
  • FIG. 19 shows an example of energy bands of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source/drain electrode in contact with the oxide semiconductor film.
  • a silicon oxide film and an In-Ga-Zn oxide are used as the gate insulating film and the oxide semiconductor film, respectively.
  • the transition level (sf) of a defect that might be formed in the silicon oxide film is assumed to be formed at a position approximately 3.1 eV away from the conduction band minimum of the gate insulating film.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film when the gate voltage (V g ) is 30 V is assumed to be formed at a position approximately 3.6 eV away from the conduction band minimum of the gate insulating film. Note that the Fermi level of the silicon oxide film changes depending on the gate voltage.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered as the gate voltage is increased.
  • a white circle and X in FIG. 19 represent an electron (carrier) and a defect state in the silicon oxide film, respectively.
  • the Fermi level of the interface between the gate insulating film and the oxide semiconductor film might be changed.
  • the conduction band minimum of the gate insulating film becomes relatively high at the interface between the gate insulating film and the oxide semiconductor film or in the vicinity of the interface.
  • the defect state (X in FIG. 19) which might be formed in the gate insulating film also becomes relatively high, so that the energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film is increased.
  • the increase in energy difference leads to a reduction in the amount of charge trapped in the gate insulating film. For example, a change in the charge state of the defect states which might be formed in the silicon oxide film becomes smaller, so that a change in the threshold voltage of the transistor by gate bias temperature (GBT) stress can be reduced.
  • GBT gate bias temperature
  • the oxide semiconductor film when used for a channel region of a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.
  • the transistor in which a channel region is formed in the oxide semiconductor film having a high density of defect states might have unstable electrical characteristics.
  • the concentration of impurities in the oxide semiconductor film is effective to reduce the concentration of impurities in the oxide semiconductor film.
  • concentration of impurities in a film which is adjacent to the oxide semiconductor film is preferably reduced.
  • the impurities hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given.
  • the concentration of silicon or carbon in the oxide semiconductor film and around an interface with the oxide semiconductor film is set lower than or equal to 2 x 10 18 atoms/cm 3 , and preferably lower than or equal to 2 x 10 17 atoms/cm 3 .
  • the oxide semiconductor film contains alkali metal or alkaline earth metal
  • defect states are formed and carriers are generated, in some cases.
  • a transistor including an oxide semiconductor film that contains alkali metal or alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film measured by SIMS is set lower than or equal to 1 x 10 18 atoms/cm 3 , and preferably lower than or equal to 2 x 10 16 atoms/cm 3 .
  • Hydrogen contained in an oxide semiconductor film reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor film that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible.
  • the hydrogen concentration of the oxide semiconductor film measured by SIMS is set lower than 1 x 10 20 atoms/cm 3 , preferably lower than 1 x 1019 atoms/cm 3 , further preferably lower than 5 x 10 18 atoms/cm 3 , and still further preferably lower than 1 x 1018 atoms/cm 3.
  • the transistor When an oxide semiconductor film with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.
  • the energy gap of the oxide semiconductor film is preferably 2 eV or more or 2.5 eV or more.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • nc-OS nanocrystalline oxide semiconductor
  • a-like OS amorphous-like oxide semiconductor
  • an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor.
  • the crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and have no fixed atomic arrangement, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.
  • a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic e.g., an oxide semiconductor that has a periodic structure in a microscopic region
  • an a-like OS which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.
  • a CAAC-OS is one of oxide semiconductors and has a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has few impurities and defects (e.g., oxygen vacancies).
  • an impurity means an element other than the main components of an oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element specifically, silicon or the like
  • a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • nc-OS Analysis of an nc-OS by XRD is described.
  • a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.
  • the nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor.
  • the nc-OS has a lower density of defect states than the a-like OS and the amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS in some cases.
  • An a-like OS has a structure between the structure of an nc-OS and the structure of an amorphous oxide semiconductor.
  • the a-like OS contains a void or a low-density region.
  • the a-like OS has an unstable structure because it contains a void.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void.
  • the density of the a-like OS is higher than or equal to 78.6 % and lower than 92.3 % of the density of the single crystal oxide semiconductor having the same composition.
  • the density of the nc-OS and the density of the CAAC-OS are each higher than or equal to 92.3 % and lower than 100 % of the density of the single crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor having a density lower than 78 % of the density of the single crystal oxide semiconductor.
  • the density of single crystal InGaZn0 4 with a rhombohedral crystal structure is 6.357 g/cm 3 . Accordingly, in the case of the oxide semiconductor whose atomic ratio of In to Ga to Zn is 1 : 1 : 1, the density of the a-like OS is higher than or equal to 5.0 g/cm 3 and lower than 5.9 g/cm 3 , for example. In the case of the oxide semiconductor whose atomic ratio of In to Ga to Zn is 1 : 1 : 1, the density of the nc-OS and the density of the CAAC-OS are each higher than or equal to 5.9 g/cm 3 and lower than 6.3 g/cm 3 , for example.
  • an oxide semiconductor having a certain composition does not exist in a single crystal state
  • single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate a density equivalent to that of a single crystal oxide semiconductor with the desired composition.
  • the density of a single crystal oxide semiconductor having the desired composition may be calculated using a weighted average with respect to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.
  • oxide semiconductors have various structures and various properties.
  • two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS may be mixed. An example of such a case is described below.
  • the oxide semiconductor film of one embodiment of the present invention can include two kinds of crystal parts. That is, two kinds of crystal parts are mixed in the oxide semiconductor film.
  • One is a crystal part (also referred to as a first crystal part) having orientation in the thickness direction (also referred to as a film-plane direction, or a direction perpendicular to a formation surface or a film surface), i.e., a crystal part having c-axis alignment.
  • the other is a crystal part (also referred to as a second crystal part) which does not have c-axis alignment and has random orientation.
  • crystal parts are divided into the two categories for simplicity: the first crystal part having c-axis alignment and the second crystal part having no c-axis alignment, the first crystal part and the second crystal part cannot be distinguished from each other in some cases because there is not much difference in crystallinity, crystal size, and the like. That is, the oxide semiconductor film of one embodiment of the present invention can be described without a distinction between the first crystal part and the second crystal part.
  • the oxide semiconductor film of one embodiment of the present invention includes a plurality of crystal parts, and at least one of the crystal parts may have c-axis alignment. Furthermore, in the crystal parts existing in the film, the proportion of crystal parts having no c-axis alignment may be higher than that of crystal parts having c-axis alignment. For example, in a transmission electron microscope image of a cross section of the oxide semiconductor film which is one embodiment of the present invention in the thickness direction, a plurality of crystal parts are observed and the second crystal parts having no c-axis alignment are observed at a higher proportion than the first crystal parts having c-axis alignment in some cases. In other words, the oxide semiconductor film of one embodiment of the present invention has a high proportion of second crystal parts having no c-axis alignment.
  • the oxide semiconductor film has a high proportion of second crystal parts having no c-axis alignment, the following effects can be obtained.
  • the second crystal part having no c-axis alignment can serve as an oxygen diffusion path.
  • oxygen can be supplied from the source to the first crystal part having c-axis alignment through the second crystal part having no c-axis alignment. Accordingly, the amount of oxygen vacancies in the oxide semiconductor film can be reduced.
  • particular crystal planes are aligned in the thickness direction.
  • a diffraction peak derived from the first crystal parts is observed at a predetermined diffraction angle (2 ⁇ ).
  • a diffraction peak is not sufficiently observed in some cases because of x-rays scattering or increase in background due to a support substrate. Note that the higher the proportion of the first crystal parts in the oxide semiconductor film is, the higher the diffraction peak becomes; thus, the height (intensity) of the diffraction peak can be an indicator of crystallinity of the oxide semiconductor film.
  • electron diffraction can be given.
  • first regions including diffraction spots derived from the first crystal parts and second regions including diffraction spots derived from the second crystal parts are observed.
  • the first regions including diffraction spots derived from the first crystal parts are derived from crystal parts having c-axis alignment.
  • the second regions including diffraction spots derived from the second crystal parts are derived from crystal parts having no orientation or crystal parts having random orientation. Therefore, different patterns are observed in accordance with the diameter of an electron beam, i.e., the area of an observed region in some cases. Note that in this specification and the like, electron diffraction with an electron beam having a diameter of 1 ⁇ to 100 ⁇ inclusive is referred to as nanobeam electron diffraction (NBED).
  • NBED nanobeam electron diffraction
  • the crystallinity of the oxide semiconductor film of one embodiment of the present invention may be evaluated by a method different from NBED.
  • a method for evaluating crystallinity of the oxide semiconductor film electron diffraction, x-ray diffraction, neutron diffraction, and the like can be given.
  • the electron diffractions transmission electron microscopy (TEM), scanning electron microscopy (SEM), convergent beam electron diffraction (CBED), selected-area electron diffraction (SAED), and the like can be favorably used in addition to the above NBED.
  • a ring-like pattern is observed in a nanobeam electron diffraction pattern obtained by using an electron beam having a large diameter (e.g., greater than or equal to 25 ⁇ and less than or equal to 100 ⁇ , or greater than or equal to 50 ⁇ and less than or equal to 100 ⁇ ).
  • the ring-like pattern has luminance distribution in a radial direction in some cases.
  • an electron diffraction pattern of NBED obtained by using an electron beam having a sufficiently small diameter e.g., greater than or equal to 1 ⁇ and less than or equal to 10 ⁇
  • a plurality of spots distributed in a circumferential direction also referred to as ⁇ direction
  • the ring-like pattern obtained by using an electron beam having a large diameter is formed from an aggregate of the plurality of spots.
  • Samples XI to X3 Three samples (Samples XI to X3) each including an oxide semiconductor film were fabricated and the crystallinity of each of the samples was evaluated. Three kinds of oxide semiconductor films were formed in different conditions. First, methods for fabricating Samples XI to X3 are described. [0315]
  • Sample XI is a sample in which an approximately 100-nm-thick oxide semiconductor film is formed over a glass substrate.
  • the oxide semiconductor film contains indium, gallium, and zinc.
  • Sample X2 is a sample in which an approximately 100-nm-thick oxide semiconductor film is formed over a glass substrate.
  • the oxide semiconductor film of Sample X2 was formed under the following conditions: the substrate temperature was 130 °C; and an argon gas with a flow rate of 180 seem and an oxygen gas with a flow rate of 20 seem were introduced into a chamber of a sputtering apparatus.
  • the percentage of oxygen flow rate under the formation conditions for Sample X2 was 10 %. Note that the conditions other than the substrate temperature and the percentage of oxygen flow rate are the same as those for Sample XI .
  • Sample X3 is a sample in which an approximately 100-nm-thick oxide semiconductor film is formed over a glass substrate.
  • the oxide semiconductor film of Sample X3 was formed under the following conditions: the substrate temperature was room temperature; an argon gas with a flow rate of 180 seem and an oxygen gas with a flow rate of 20 seem were introduced into a chamber of a sputtering apparatus.
  • the percentage of oxygen flow rate under the formation conditions for Sample X3 was 10 %. Note that the conditions other than the substrate temperature and the percentage of oxygen flow rate are the same as those for Sample XI .
  • FIGS. 20A to 20C, FIGS. 21 A to 21C, and FIGS. 22A to 22C show cross-sectional TEM observation results of Samples XI to X3.
  • FIGS. 20A and 20B are cross-sectional TEM images of Sample XI .
  • FIGS. 21 A and 21B are cross-sectional TEM images of Sample X2.
  • FIGS. 22A and 22B are cross-sectional TEM images of Sample X3.
  • FIG. 20C, FIG. 21C, and FIG. 22C are cross-sectional high resolution transmission electron microscope (HR-TEM) images of Sample XI, Sample X2, and Sample X3, respectively.
  • the cross-sectional HR-TEM images may be obtained with a spherical aberration corrector function.
  • the high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 23A, FIG. 24A, and FIG. 25A show XRD measurement results of Sample XI
  • the XRD measurement was conducted by a powder method (also referred to as a ⁇ -2 ⁇ method) which is a kind of an out-of-plane method.
  • a powder method also referred to as a ⁇ -2 ⁇ method
  • X-ray diffraction intensity is measured while an incident angle of an X-ray is changed and the angle of a detector facing an X-ray source is equal to the incident angle.
  • a grazing-incidence XRD (GIXRD) method also referred to as a thin film method or a Seemann-Bohlin method
  • GIXRD grazing-incidence XRD
  • the GIXRD method is a kind of an out-of-plane method for measuring X-ray diffraction intensity in which X-ray is incident at an angle approximately 0.40° from a film surface with use of a variable-angle detector.
  • the vertical axis represents the diffraction intensity in arbitrary unit and the horizontal axis represents the angle 2 ⁇ .
  • each of Samples XI and X2 includes a crystal part where the c-axes are aligned in the thickness direction (hereinafter also referred to as a crystal part having c-axis alignment or a first crystal part). Note that it is difficult to determine, by XRD measurement, whether a crystal part having c-axis alignment is included in Sample X3.
  • an electron diffraction pattern obtained when a crystal exists in the submicroscopic region is similar to an electron diffraction pattern of a single crystal in some cases.
  • the thickness of the sample in the depth direction is preferably greater than or equal to 10 nm and less than or equal to 100 nm, typically greater than or equal to 10 nm and less than or equal to 50 nm.
  • FIGS. 23B and 23C show electron diffraction patterns of Sample XI .
  • FIGS. 24B and 24C show electron diffraction patterns of Sample X2.
  • FIGS. 25B and 25C show electron diffraction patterns of Sample X3.
  • FIGS. 23B and 23 C, FIGS. 24B and 24C, and FIGS. 25B and 25C The contrast of the electron diffraction patterns shown in FIGS. 23B and 23 C, FIGS. 24B and 24C, and FIGS. 25B and 25C is adjusted for clarity.
  • the brightest luminescent spot at the center of the pattern is derived from the incident electron beam and is the center of the electron diffraction pattern (also referred to as a direct spot or a transmitted wave).
  • FIG. 23B when the diameter of the incident electron beam is set to 1 ⁇ , a plurality of spots circumferentially distributed can be observed. This indicates that the oxide semiconductor film contains a plurality of submicroscopic crystal parts having random surface orientation.
  • FIG. 23C when the diameter of the incident electron beam is set to 100 ⁇ , the luminances of a sequence of a plurality of diffraction spots derived from these plurality of crystal parts are averaged to be a ring-like diffraction pattern.
  • Two ring-like diffraction patterns with different radii are observed in FIG. 23C.
  • the rings are referred to as a first ring and a second ring in ascending order of radius. It is observed that the luminance of the first ring is higher than that of the second ring.
  • two spots (referred to as first regions) with high luminance are observed at a position overlapping with the first ring.
  • the distance from the center to the first ring in a radial direction substantially corresponds to the distance from the center to a diffraction spot on the (009) plane of the structure model of single crystal InGaZn0 4 in a radical direction.
  • the first regions are diffraction spots derived from c-axis alignment.
  • the observations of the ring-like diffraction patterns indicate that crystal parts having random orientation (hereinafter also referred to as crystal parts having no c-axis alignment or second crystal parts) exist in the oxide semiconductor film.
  • two first regions are presumed to have two-hold symmetry because the regions are disposed symmetrically with respect to the center point of the electron diffraction pattern and the luminances of the regions are substantially equal to each other.
  • the two first regions are diffraction spots which are derived from the c-axis alignment, the orientation of a straight line which passes through the two first regions and the center is aligned with that of the c-axis of the crystal part.
  • the thickness direction is the vertical direction of FIG. 23C, which suggests the presence of crystal part in which the c-axis is aligned in the thickness direction in the oxide semiconductor film.
  • the oxide semiconductor film of Sample XI is confirmed to be a film including both crystal parts having c-axis alignment and crystal parts having no c-axis alignment.
  • the results of the electron diffraction patterns shown in FIGS. 24B and 24C and FIGS. 25B and 25C are substantially the same as those of the electron diffraction patterns shown in FIGS. 23B and 23C.
  • the luminance of the two spots (first regions) derived from c-axis alignment is high in the order of Sample XI, Sample X2 and Sample X3. This indicates that the proportion of crystal parts having c-axis alignment is high in that order.
  • FIGS. 26A and 26B, FIG. 27, and FIG. 28 An example of a quantification method of crystallinity of an oxide semiconductor film is described with reference to FIGS. 26A and 26B, FIG. 27, and FIG. 28.
  • FIG. 26 A shows an electron diffraction pattern obtained by measuring a 100-nm-thick oxide semiconductor film using an electron beam with a diameter of 100 ⁇ .
  • FIG. 26B shows an electron diffraction pattern obtained by adjusting contrast of the electron diffraction pattern shown in FIG. 26A.
  • two clear spots are observed over and under a direct spot.
  • the two spots (first regions) are derived from diffraction spots corresponding to (001) in a structure model of InGaZn0 4 , that is, crystal parts having c-axis alignment.
  • a ring-like pattern (second regions) with a low luminance positioned on an approximately concentric circle of the first region is observed.
  • the ring-like pattern is obtained when the luminances of spots derived from structures of crystal parts having no c-axis alignment (second crystal parts) are averaged by using the electron beam with a diameter of 100 ⁇ .
  • the first regions including diffraction spots derived from the crystal parts having c-axis alignment and the second regions including diffraction spots derived from the second crystal parts are observed to overlap with each other.
  • a line profile including the first regions and line profiles including the second regions are obtained and compared with each other, whereby the crystallinity of the oxide semiconductor film can be quantified.
  • the line profile including the first regions and the line profiles including the second regions are described with reference to FIG. 27.
  • FIG. 27 shows a simulation pattern of electron diffraction that is obtained when an electron beam is emitted to the (100) plane of the structure model of InGaZn0 4 .
  • auxiliary lines of a region A- A', a region B-B', and a region C-C are drawn.
  • the region A-A in FIG. 27 includes a straight line passing through two diffraction spots derived from the first crystal parts having c-axis alignment and a direct spot.
  • the regions B-B' and C-C in FIG. 27 each include a straight line passing through a region where no diffraction spot derived from the first crystal part having c-axis alignment is observed and the direct spot.
  • An angle between the region A-A' and the region B-B' or C-C is approximately 34°, specifically, larger than or equal to 30° and smaller than or equal to 38°, preferably larger than or equal to 32° and smaller than or equal to 36°, further preferably larger than or equal to 33° and smaller than or equal to 35°.
  • FIG. 28 illustrates line profiles and shows relative luminance R and a full width at half maximum (FWHM) of each line profile.
  • Relative luminance R in FIG. 28 is obtained by dividing the integrated intensity of luminance of the region A-A' by the integrated intensity of luminance of the region B-B' or the integrated intensity of luminance of the region C-C. Note that the integrated intensity of the luminance of each of the regions A-A, B-B', and C-C is obtained by removing the luminance of background derived from the direct spot which appears at the center.
  • the intensity of c-axis alignment can be quantitatively defined.
  • the peak intensity of diffraction spots derived from the first crystal parts having c-axis alignment in the region A-A' is high and there is no diffraction spot derived from the first crystal part having c-axis alignment in the regions B-B' and C-C; thus, the relative luminance R is much larger than 1.
  • the relative luminance R decreases in the order of single crystal, CAAC alone (details of CAAC will be described later), CAAC+nanocrystal, nanocrystal, and amorphous. In particular, in nanocrystal and amorphous, which have no particular orientation, the relative luminance R is equal to 1.
  • the full width at half maximum of single crystal is the smallest, and the full width at half maximum is increased in the order of CAAC alone, CAAC+nanocrystal, and nanocrystal.
  • the full width at half maximum of amorphous is extremely large and the profile thereof is called a "halo".
  • the ratio of the integrated intensity of luminance of the first regions to the integrated intensity of luminance of the second regions is important information to presume the proportion of crystal parts having orientation.
  • FIGS. 29A1 and 29A2 show results of analysis with line profiles of Sample XI .
  • FIGS. 29B1 and 29B2 show results of analysis with line profiles of Sample X2.
  • FIGS. 29C1 and 29C2 show results of analysis with line profiles of Sample X3.
  • FIG. 29A1 shows the electron diffraction pattern in FIG. 23C in which the regions A-A', B-B', and C-C are drawn.
  • FIG. 29B 1 shows the electron diffraction pattern in FIG. 24C in which the regions A-A, B-B', and C-C are drawn.
  • FIG. 29C1 shows the electron diffraction pattern in FIG. 25C in which the regions A-A, B-B', and C-C are drawn.
  • the regions A-A, B-B', and C-C can each be obtained by normalizing line profiles using the luminance of the direct spot as a reference. Note that the direct spot appears at the center of an electron diffraction pattern. With the regions, Samples XI to X3 can be relatively compared.
  • the profile of the luminance is calculated, a component of the luminance derived from inelastic scatterings and the like from the sample is subtracted as the background, whereby comparison with higher accuracy can be performed.
  • the component of the luminance derived from inelastic scatterings shows an extremely broad profile in a radial direction
  • the luminance of the background may be obtained by a linear approximation. For example, a straight line is drawn along the tails of a target peak, and a region positioned on the lower luminance side than the straight line can be subtracted as the background.
  • the integrated intensity of the luminance of each of the regions A-A', B-B', and C-C is calculated from data in which the background is subtracted by the method described above. Then, the relative luminance R is obtained by dividing the integrated intensity of the luminance of the region A-A' by the integrated intensity of the luminance of the region B-B' or the integrated intensity of the luminance of the region C-C.
  • FIG. 30 shows the relative luminance R of Samples XI to X3.
  • a value obtained by dividing the integrated intensity of the luminance of the region A-A' by the integrated intensity of the luminance of the region B-B' and a value obtained by dividing the integrated intensity of the luminance of the region A-A' by the integrated intensity of the luminance of the region C-C are calculated.
  • the relative luminance of Samples XI to X3 is as follows.
  • the relative luminance R of Sample XI is 25.00.
  • the relative luminance R of Sample X2 is 3.04.
  • the relative luminance R of Sample X3 is 1.05. Note that the relative luminance R is an average value of relative luminances at four points. As described above, the relative luminance R is high in the order of Sample XI, Sample X2, and Sample X3.
  • the relative luminance R is preferably greater than 1 and less than or equal to 40, further preferably greater than 1 and less than or equal to 10, still further preferably greater than 1 and less than or equal to 3.
  • the proportion of crystal parts in an oxide semiconductor film can be estimated by analyzing its cross-sectional TEM image.
  • a method for analyzing the image is described.
  • An image is analyzed as follows. First, a high-resolution TEM image is subjected to two-dimensional fast Fourier transform (FFT), whereby an FFT image is obtained. The obtained FFT image is subjected to a mask processing so that a region other than a region having a periodic structure is removed. After the mask processing, the FFT image is subjected to two-dimensional inverse fast Fourier transform (IFFT), whereby an FFT filtering image is obtained.
  • FFT fast Fourier transform
  • IFFT two-dimensional inverse fast Fourier transform
  • the proportion of crystal parts can be estimated from the proportion of the area of the remaining image.
  • the proportion of the area other than the crystal parts can be estimated by subtracting the remaining region from the area of the region used for calculation (also referred to as the area of an original image).
  • FIG. 31A1 shows a cross-sectional TEM image of Sample XI .
  • FIG. 31A2 shows an image obtained through the analysis of the cross-sectional TEM image of Sample XI .
  • FIG. 31B1 shows a cross-sectional TEM image of Sample X2.
  • FIG. 31B2 shows an image obtained through the analysis of the cross-sectional TEM image of Sample X2.
  • FIG. 31C1 shows a cross-sectional TEM image of Sample X3.
  • FIG. 31C2 shows an image obtained through the analysis of the cross-sectional TEM image of Sample X3.
  • White regions in the oxide semiconductor film in the images obtained through the analysis correspond to regions including crystal parts having orientation.
  • Black regions correspond to regions including crystal parts having no orientation or crystal parts with random orientation.
  • the proportion of the area other than the region including crystal parts having orientation is approximately 43.1 % in Sample XI .
  • the proportion of the area other than the region including crystal parts having orientation is approximately 61.7 % in Sample X2.
  • the proportion of the area other than the region including crystal parts having orientation is approximately 89.5 % in Sample X3.
  • the proportion of the region other than crystal parts having orientation in an oxide semiconductor film is preferably greater than or equal to 5 % and less than 40 % because the oxide semiconductor film has extremely high crystallinity and extremely high stability of electrical characteristics and hardly generates oxygen vacancies.
  • the proportion of the region other than crystal parts having orientation in an oxide semiconductor film is higher than or equal to 40 % and lower than 100 %, preferably higher than or equal to 60 % and lower than or equal to 90 %, the oxide semiconductor film includes both the crystal parts having orientation and the crystal parts having no orientation at an appropriate ratio and thus can achieve both high stability of electrical characteristics and high mobility.
  • LGBR lateral growth buffer region
  • an approximately 50-nm-thick oxide semiconductor film was formed over a glass substrate in a manner similar to that of Sample XI .
  • an approximately 30-nm-thick silicon oxynitride film, an approximately 100-nm-thick silicon oxynitride film, and an approximately 20-nm-thick silicon oxynitride film were stacked over the oxide semiconductor film by a PECVD method.
  • an oxide semiconductor film and a silicon oxynitride film are referred to as OS and GI, respectively, in some cases.
  • oxygen was added to the silicon oxynitride film.
  • the oxygen addition treatment was performed with an ashing apparatus under the conditions where the substrate temperature was 40 °C, an oxygen gas ( 16 0) at a flow rate of 150 seem and an oxygen gas ( 18 0) at a flow rate of 100 seem were introduced into a chamber, the pressure was 15 Pa, and an RF power of 4500 W was supplied for 600 sec. between parallel-plate electrodes provided in the ashing apparatus so that a bias would be applied to the substrate side. Since the silicon oxynitride film contained oxygen ( 16 0) at a main component level, an oxygen gas ( 18 0) was used to exactly measure the amount of oxygen added by the oxygen addition treatment.
  • Sample Y2 is a sample whose oxide semiconductor film was formed in different conditions from those of Sample Yl .
  • an approximately 50-nm-thick oxide semiconductor film was formed in a manner similar to that of Sample X2.
  • Sample Y3 is a sample whose oxide semiconductor film was formed in different conditions from those of Sample Yl .
  • an approximately 50-nm-thick oxide semiconductor film was formed in a manner similar to that of Sample X3.
  • SIMS analysis The concentration of 18 0 in Samples Yl to Y3 was measured by secondary ion mass spectrometry (SIMS) analysis.
  • the SIMS analysis was performed under three conditions: a condition in which Samples Yl to Y3 were not subjected to heat treatment; a condition in which Samples Yl to Y3 were subjected to heat treatment at 350 °C in a nitrogen atmosphere for one hour; and a condition in which Samples Yl to Y3 were subjected to heat treatment at 450 °C in a nitrogen atmosphere for one hour.
  • FIGS. 32A to 32C show SIMS measurement results.
  • FIG. 32A, FIG. 32B, and FIG. 32C show SIMS measurement results of Sample Yl, Sample Y2, and Sample Y3, respectively.
  • FIGS. 32A to 32C show the analysis results of a region including GI and OS. Note that FIGS. 32A to 32C show results of SIMS (also referred to as substrate side depth profile (SSDP)-SIMS) analysis performed from the substrate side.
  • SIMS also referred to as substrate side depth profile (SSDP)-SIMS
  • a gray dashed line indicates a profile of the sample in which heat treatment was not performed
  • a black dashed line indicates a profile of the sample in which heat treatment was performed at 350 °C
  • a black solid line indicates a profile of the sample in which heat treatment was performed at 450 °C.
  • an oxide semiconductor film including both crystal parts having orientation and crystal parts having no orientation and a low proportion of crystal parts having orientation is a film which easily transmits oxygen, in other words, a film in which oxygen is easily diffused.
  • oxygen in a GI film is diffused to OS.
  • a region other than the crystal parts which can be obviously observed in a cross-sectional observation image can be a region in which oxygen is easily diffused, that is, can serve as an oxygen diffusion path.
  • an oxide film which easily releases oxygen is formed to be in contact with the oxide semiconductor film and heat treatment is performed, so that oxygen released from the oxide film is diffused to the oxide semiconductor film in the thickness direction through the LGBR.
  • oxygen can be supplied laterally to crystal parts having orientation. Accordingly, oxygen is easily supplied sufficiently to the crystal parts having orientation and a region other than the crystal parts in the oxide semiconductor film, which leads to an effective reduction of oxygen vacancy in the film.
  • an oxygen atom is bonded to the hydrogen atom, and then OH is formed and fixed in some cases.
  • a certain amount e.g., approximately 1 x 10 17 cm -3
  • VoH oxygen vacancy
  • a certain amount of carriers exists in the oxide semiconductor film because VoH generates a carrier.
  • the oxide semiconductor film with an increased carrier density can be formed.
  • an oxygen vacancy is formed concurrently with the deposition, the oxygen vacancy can be reduced by introducing oxygen through the LGBR as described above. In this manner, the oxide semiconductor film with a relatively high carrier density and a sufficiently reduced amount of oxygen vacancies can be formed.
  • a clear grain boundary cannot be observed in the oxide semiconductor film because submicroscopic crystal parts having no orientation at the time of the deposition is formed in a region other than crystal parts having orientation.
  • the submicroscopic crystal part is positioned between a plurality of crystal parts having orientation.
  • the submicroscopic crystal part is bonded to an adjacent crystal part having orientation by growing in the lateral direction with heat at the time of the deposition.
  • the submicroscopic crystal part functions as a region where a carrier is generated.
  • the oxide semiconductor film with such a structure is expected to improve field-effect mobility considerably when used in a transistor.
  • plasma treatment in an oxygen atmosphere is preferably performed after the oxide semiconductor film is formed and an oxide insulating film such as a silicon oxide film is formed over the oxide semiconductor film.
  • the treatment can supply oxygen to the film and reduce the hydrogen concentration.
  • fluorine which remains in the chamber is doped at the same time to the oxide semiconductor film in some cases. Fluorine exists as a fluorine atom with negative charges and is bonded to a hydrogen atom with positive charges by Coulomb force, and then FIF is generated. FIF is released to the outside of the oxide semiconductor film during the plasma treatment, and as a result, the hydrogen concentration in the oxide semiconductor film can be reduced.
  • H 2 0 in which an oxygen atom and hydrogen atoms are bonded is released to the outside of the film in some cases.
  • a structure in which a silicon oxide film (or a silicon oxynitride film) is stacked over the oxide semiconductor film is considered.
  • Fluorine in the silicon oxide film does not affect electrical characteristics of the oxide semiconductor film because fluorine is bonded to hydrogen in the film and can exist as HF which is electrically neutral. Note that Si-F bond is generated in some cases, which is also electrically neutral. Furthermore, HF in the silicon oxide film does not affect the diffusion of oxygen.
  • oxygen vacancies in the oxide semiconductor film can be reduced and hydrogen which is not bonded to a metal atom in the film can be reduced, which leads to the improvement of reliability.
  • the electrical characteristics are expected to be improved because the carrier density of the oxide semiconductor film is greater than or equal to a certain amount.
  • the oxide semiconductor film of one embodiment of the present invention can be formed by a sputtering method under an atmosphere containing oxygen.
  • An oxide target that can be used for forming the oxide semiconductor film is not limited to an In-Ga-Zn-based oxide; for example, an In-M-Zn-based oxide (Mis Al, Ga, Y, or Sn) can be used.
  • an In-M-Zn-based oxide Mo Al, Ga, Y, or Sn
  • an oxide semiconductor film containing crystal parts is formed as the oxide semiconductor film using a sputtering target containing a polycrystalline oxide having a plurality of crystal grains, an oxide semiconductor film with crystallinity is more likely to be obtained than in the case of using a sputtering target not containing a polycrystalline oxide.
  • a sputtering target contains a plurality of crystal grains each of which has a layered structure and an interface at which the crystal grain is easily cleaved
  • ion collision with the sputtering target might cleave crystal grains to make plate-like or pellet-like sputtering particles.
  • the obtained plate-like or pellet-like sputtering particles are deposited on a substrate, which probably results in formation of an oxide semiconductor film containing nanocrystals.
  • An oxide semiconductor film containing crystal parts having orientation is likely to be formed when the substrate is heated because the nanocrystals are then bonded to each other or rearranged at a substrate surface.
  • a sputtering method is particularly preferable because the crystallinity can be easily adjusted.
  • a pulsed laser deposition (PLD) method a plasma-enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a vacuum evaporation method, or the like may be used.
  • a thermal CVD method a metal organic chemical vapor deposition (MOCVD) method can be given.
  • FIG. 33 is a top view illustrating an example of a display device.
  • a display device 700 in FIG. 33 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 that are provided over the first substrate 701, a sealant 712 provided to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided to face the first substrate 701.
  • the first substrate 701 and the second substrate 705 are sealed with the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are enclosed by the first substrate 701, the sealant 712, and the second substrate 705.
  • a display element is provided between the first substrate 701 and the second substrate 705.
  • a flexible printed circuit (FPC) terminal portion 708 that is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region different from the region that is over the first substrate 701 and surrounded by the sealant 712.
  • an FPC 716 is connected to the FPC terminal portion 708, and a variety of signals and the like are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.
  • a signal line 710 is connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Through the signal line 710, a variety of signals and the like are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.
  • a plurality of gate driver circuit portions 706 may be provided in the display device 700.
  • the structure of the display device 700 is not limited to the example shown here, in which the source driver circuit portion 704 and the gate driver circuit portion 706 as well as the pixel portion 702 are formed over the first substrate 701.
  • the gate driver circuit portion 706 may be formed over the first substrate 701, or only the source driver circuit portion 704 may be formed over the first substrate 701.
  • a substrate over which a source driver circuit, a gate driver circuit, or the like is formed e.g., a driver circuit board formed using a single-crystal semiconductor film or a polycrystalline semiconductor film
  • COG chip on glass
  • the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.
  • the display device 700 can include a variety of elements.
  • electroluminescent (EL) element e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED
  • a light-emitting transistor element a transistor that emits light depending on current
  • a piezoelectric ceramic display e.g., a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS) element, or an interferometric modulator display (EVIOD) element
  • An example of a display device including an EL element is an EL display.
  • Examples of a display device including an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display).
  • An example of a display device including a liquid crystal element is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct- view liquid crystal display, or a projection liquid crystal display).
  • An example of a display device including an electronic ink display or an electrophoretic element is electronic paper.
  • some or all of pixel electrodes may function as reflective electrodes.
  • some or all of pixel electrodes may contain aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.
  • a progressive system, an interlace system, or the like can be employed.
  • color elements controlled in pixels at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively).
  • R, G, and B correspond to red, green, and blue, respectively.
  • four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel may be used.
  • a color element may be composed of two colors of R, G, and B as in PenTile layout. The two colors may differ depending on the color elements.
  • one or more colors of yellow, cyan, magenta, and the like may be added to RGB.
  • the size of a display region may differ between dots of color elements.
  • One embodiment of the disclosed invention is not limited to a color display device; the disclosed invention can also be applied to a monochrome display device.
  • a coloring layer may be used to obtain a full-color display device in which white light (W) is used for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp).
  • a backlight e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp.
  • a red (R) coloring layer, a green (G) coloring layer, a blue (B) coloring layer, and a yellow (Y) coloring layer can be combined as appropriate.
  • RGB red
  • G green
  • B blue
  • Y yellow
  • the coloring layer high color reproducibility can be obtained as compared with the case without the coloring layer.
  • white light in the region without the coloring layer may be directly utilized for display.
  • a decrease in the luminance of a bright image due to the coloring layer can be suppressed, and approximately 20 % to 30 % of power consumption can be reduced in some cases.
  • a self-luminous element such as an organic EL element or an inorganic EL element
  • elements may emit light in their respective colors R, G, B, Y, and W.
  • power consumption may be further reduced as compared with the case of using a coloring layer.
  • any of the following systems may be used: the above-described color filter system in which part of white light is converted into red light, green light, and blue light through color filters; a three-color system in which red light, green light, and blue light are used; and a color conversion system or a quantum dot system in which part of blue light is converted into red light or green light.
  • FIGS. 34 to 36 a structure including a liquid crystal element as a display element and a structure including an EL element as a display element are described with reference to FIGS. 34 to 36.
  • FIG. 34 and FIG. 35 are each a cross-sectional view taken along a dashed-dotted line Q-R in FIG. 33 and illustrate the structure including a liquid crystal element as a display element.
  • FIG. 36 is a cross-sectional view taken along the dashed-dotted line Q-R in FIG. 33 and illustrates the structure including an EL element as a display element.
  • FIG. 34 Portions common to FIG. 34, FIG. 35, and FIG. 36 will be described first, and then, different portions will be described.
  • the display device 700 in FIG. 34, FIG. 35, and FIG. 36 includes a lead wiring portion 711, the pixel portion 702, the source driver circuit portion 704, and the FPC terminal portion 708.
  • the lead wiring portion 711 includes the signal line 710.
  • the pixel portion 702 includes a transistor 750 and a capacitor 790.
  • the source driver circuit portion 704 includes a transistor 752.
  • the transistor 750 and the transistor 752 each have a structure similar to that of the transistor 150A. Note that the transistor 750 and the transistor 752 may each have the structure of any of the other transistors described in the above embodiments.
  • the transistor used in this embodiment includes an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies are suppressed.
  • the transistor can have low off-state current. Accordingly, an electrical signal such as an image signal can be held for a long time, and a long writing interval can be set in an on state. Accordingly, the frequency of refresh operation can be reduced, which suppresses power consumption.
  • the transistor used in this embodiment can have relatively high field-effect mobility and thus is capable of high-speed operation.
  • a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. That is, no additional semiconductor device formed using a silicon wafer or the like is needed as a driver circuit; therefore, the number of components of the semiconductor device can be reduced.
  • the transistor capable of high-speed operation in the pixel portion a high-quality image can be provided.
  • the capacitor 790 includes a lower electrode and an upper electrode.
  • the lower electrode is formed through a step of processing a conductive film to be a conductive film functioning as a first gate electrode of the transistor 750.
  • the upper electrode is formed through a step of processing a conductive film to be a conductive film functioning as source and drain electrodes or a second gate electrode of the transistor 750.
  • an insulating film formed through a step of forming an insulating film to be an insulating film functioning as a first gate insulating film of the transistor 750 and insulating films formed through a step of forming insulating films to be insulating films functioning as protective insulating films over the transistor 750 are provided. That is, the capacitor 790 has a stacked-layer structure in which an insulating film functioning as a dielectric film is positioned between the pair of electrodes.
  • a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
  • FIG. 34, FIG. 35, and FIG. 36 each illustrate an example in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 have the same structure
  • the pixel portion 702 and the source driver circuit portion 704 may include different transistors.
  • a structure in which a top-gate transistor is used in the pixel portion 702 and a bottom-gate transistor is used in the source driver circuit portion 704, or a structure in which a bottom-gate transistor is used in the pixel portion 702 and a top-gate transistor is used in the source driver circuit portion 704 may be employed.
  • the term "source driver circuit portion 704" can be replaced by the term "gate driver circuit portion.”
  • the signal line 710 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752. In the case where the signal line 710 is formed using a material containing a copper, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen.
  • the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and the FPC 716.
  • the connection electrode 760 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752.
  • the connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.
  • glass substrates can be used as the first substrate 701 and the second substrate 705.
  • flexible substrates may also be used.
  • An example of the flexible substrate is a plastic substrate.
  • a structure 778 is provided between the first substrate 701 and the second substrate 705.
  • the structure 778 is a columnar spacer obtained by selective etching of an insulating film and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705.
  • a spherical spacer may also be used as the structure 778.
  • a light-blocking film 738 functioning as a black matrix, a coloring film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the coloring film 736 are provided on the second substrate 705 side.
  • the display device 700 in FIG. 34 includes a liquid crystal element 775.
  • the liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776.
  • the conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode.
  • the display device 700 in FIG. 34 can display an image in such a manner that transmission or non-transmission of light is controlled by the alignment state in the liquid crystal layer 776 that is changed depending on the voltage applied between the conductive film 772 and the conductive film 774.
  • the conductive film 772 is electrically connected to the conductive film functioning as the source electrode or the drain electrode of the transistor 750.
  • the conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element.
  • a conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film 772.
  • a material containing an element selected from indium (In), zinc (Zn), and tin (Sn) may be used for the conductive film that transmits visible light.
  • a material containing aluminum or silver may be used for the conductive film that reflects visible light.
  • the display device 700 is a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used as the conductive film 772, the display device 700 is a transmissive liquid crystal display device.
  • the method for driving the liquid crystal element can be changed by changing the structure over the conductive film 772, an example of this case is illustrated in FIG. 35.
  • the display device 700 illustrated in FIG. 35 is an example of employing a horizontal electric field mode (e.g., an FFS mode) as a driving mode of the liquid crystal element.
  • a horizontal electric field mode e.g., an FFS mode
  • an insulating film 773 is provided over the conductive film 772
  • the conductive film 774 is provided over the insulating film 773.
  • the conductive film 774 functions as a common electrode, and an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 can control the alignment state in the liquid crystal layer 776.
  • the conductive film 772 and/or the conductive film 774 may be provided with an alignment film on a side in contact with the liquid crystal layer 776.
  • an optical member (optical substrate) or the like such as a polarizing member, a retardation member, or an anti -reflection member, may be provided as appropriate.
  • circular polarization may be obtained by using a polarizing substrate and a retardation substrate.
  • a backlight, a sidelight, or the like may be used as a light source.
  • thermotropic liquid crystal In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.
  • a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used.
  • the blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase when the temperature of a cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight percent or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range.
  • the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral material has a short response time and optical isotropy, which eliminates the need for an alignment process.
  • An alignment film does not need to be provided, and thus, rubbing treatment is not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented, and defects and damage of a liquid crystal display device in the manufacturing process can be reduced. Moreover, the liquid crystal material that exhibits a blue phase has small viewing angle dependence.
  • a liquid crystal element In the case where a liquid crystal element is used as a display element, a twisted nematic (TN) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti -ferroelectric liquid crystal (AFLC) mode, or the like can be used.
  • TN twisted nematic
  • IPS in-plane switching
  • FFS fringe field switching
  • ASM axially symmetric aligned micro-cell
  • OBC optical compensated birefringence
  • FLC ferroelectric liquid crystal
  • AFLC anti -ferroelectric liquid crystal
  • a normally black liquid crystal display device such as a vertical alignment (VA) mode transmissive liquid crystal display device may also be used.
  • VA vertical alignment
  • a vertical alignment mode for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an ASV mode, or the like can be employed.
  • MVA multi-domain vertical alignment
  • PVA patterned vertical alignment
  • ASV ASV mode
  • the display device 700 illustrated in FIG. 36 includes a light-emitting element 782.
  • the light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788.
  • the display device 700 illustrated in FIG. 36 can display an image by utilizing light emission from the EL layer 786 of the light-emitting element 782.
  • the EL layer 786 contains an organic compound or an inorganic compound such as a quantum dot.
  • Examples of materials that can be used for an organic compound include a fluorescent material and a phosphorescent material.
  • Examples of materials that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material.
  • a material containing elements belonging to Groups 12 and 16, elements belonging to Groups 13 and 15, or elements belonging to Groups 14 and 16, may be used.
  • a quantum dot material containing an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used.
  • an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used.
  • the above-described organic compound and the inorganic compound can be deposited by a method such as an evaporation method (including a vacuum evaporation method), a droplet discharge method (also referred to as an ink-jet method), a coating method, or a gravure printing method.
  • a method such as an evaporation method (including a vacuum evaporation method), a droplet discharge method (also referred to as an ink-jet method), a coating method, or a gravure printing method.
  • a low molecular material, a middle molecular material (including an oligomer and a dendrimer), or a high molecular material may be included in the EL layer 786.
  • FIGS. 39A to 39D are cross-sectional views illustrating the method for forming the EL layer 786.
  • the conductive film 772 is formed over the planarization insulating film 770, and an insulating film 730 is formed to cover part of the conductive film 772 (see FIG. 39A).
  • a droplet 784 is discharged to an exposed portion of the conductive film 772, which is an opening of the insulating film 730, from a droplet discharge apparatus 783, so that a layer 785 containing a composition is formed.
  • the droplet 784 is a composition containing a solvent and is attached to the conductive film 772 (see FIG. 39B).
  • step of discharging the droplet 784 may be performed under reduced pressure.
  • the solvent is removed from the layer 785 containing the composition, and the resulting layer is solidified to form the EL layer 786 (see FIG. 39C).
  • the solvent may be removed by drying or heating.
  • the conductive film 788 is formed over the EL layer 786; thus, the light-emitting element 782 is formed (see FIG. 39D).
  • the composition can be selectively discharged; accordingly, waste of material can be reduced. Furthermore, a lithography process or the like for shaping is not needed, and thus, the process can be simplified and cost reduction can be achieved.
  • the droplet discharge method described above is a general term for a means including a nozzle equipped with a composition discharge opening or a means to discharge droplets such as a head having one or a plurality of nozzles.
  • FIG. 40 is a conceptual diagram illustrating a droplet discharge apparatus 1400.
  • the droplet discharge apparatus 1400 includes a droplet discharge means 1403.
  • the droplet discharge means 1403 is equipped with a head 1405 and a head 1412.
  • the heads 1405 and 1412 are connected to a control means 1407, and this control means 1407 is controlled by a computer 1410; thus, a preprogrammed pattern can be drawn.
  • the drawing may be conducted at a timing, for example, based on a marker 1411 formed over a substrate 1402.
  • the reference point may be determined on the basis of an outer edge of the substrate 1402.
  • the marker 1411 is detected by an imaging means 1404 and converted into a digital signal by an image processing means 1409. Then, the digital signal is recognized by the computer 1410, and then, a control signal is generated and transmitted to the control means 1407.
  • An image sensor or the like using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used as the imaging means 1404.
  • CCD charge coupled device
  • CMOS complementary metal oxide semiconductor
  • information about a pattern to be formed over the substrate 1402 is stored in a storage medium 1408, and a control signal is transmitted to the control means 1407 based on the information, so that each of the heads 1405 and 1412 of the droplet discharge means 1403 can be individually controlled.
  • the heads 1405 and 1412 are supplied with a material to be discharged from material supply sources 1413 and 1414 through pipes, respectively.
  • a space as indicated by a dotted line 1406 to be filled with a liquid material and a nozzle which is a discharge outlet are provided inside the head 1405.
  • an inside structure of the head 1412 is similar to that of the head 1405.
  • the nozzle sizes of the heads 1405 and 1412 are different from each other, different materials with different widths can be discharged simultaneously.
  • Each head can discharge and draw a plurality of light emitting materials.
  • the same material can be simultaneously discharged to be drawn from a plurality of nozzles in order to improve throughput.
  • the heads 1405 and 1412 can freely scan the substrate in directions indicated by arrows X, Y, and Z in FIG. 40, and a region in which a pattern is drawn can be freely set.
  • a plurality of the same patterns can be drawn over one substrate.
  • a step of discharging the composition may be performed under reduced pressure.
  • a substrate may be heated when the composition is discharged.
  • either drying or baking or both of them are performed. Both the drying and baking are heat treatments but different in purpose, temperature, and time period.
  • the steps of drying and baking are performed under normal pressure or under reduced pressure by laser irradiation, rapid thermal annealing, heating using a heating furnace, or the like. Note that there is no particular limitation on the timing of the heat treatment and the number of times of the heat treatment.
  • the temperature for performing each of the steps of drying and baking in a favorable manner depends on the materials of the substrate and the properties of the composition.
  • the EL layer 786 can be formed with the droplet discharge apparatus.
  • the insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772.
  • the insulating film 730 covers part of the conductive film 772.
  • the light-emitting element 782 has a top-emission structure.
  • the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786.
  • the top-emission structure is described as an example in this embodiment, the structure is not limited thereto.
  • a bottom-emission structure in which light is emitted to the conductive film 772 side or a dual-emission structure in which light is emitted to both the conductive film 772 side and the conductive film 788 side may also be employed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/IB2017/051280 2016-03-11 2017-03-06 Semiconductor device, manufacturing method thereof, and display device including the semiconductor device WO2017153882A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020187025833A KR20180123028A (ko) 2016-03-11 2017-03-06 반도체 장비, 상기 반도체 장치의 제작 방법, 및 상기 반도체 장치를 포함하는 표시 장치

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2016-048704 2016-03-11
JP2016048704 2016-03-11
JP2016125378 2016-06-24
JP2016-125378 2016-06-24

Publications (1)

Publication Number Publication Date
WO2017153882A1 true WO2017153882A1 (en) 2017-09-14

Family

ID=59788022

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2017/051280 WO2017153882A1 (en) 2016-03-11 2017-03-06 Semiconductor device, manufacturing method thereof, and display device including the semiconductor device

Country Status (4)

Country Link
US (3) US10134914B2 (ko)
JP (2) JP6971593B2 (ko)
KR (1) KR20180123028A (ko)
WO (1) WO2017153882A1 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11482626B2 (en) 2018-03-29 2022-10-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
US11552111B2 (en) 2018-04-20 2023-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
EP4075516A4 (en) * 2020-06-24 2023-08-16 BOE Technology Group Co., Ltd. METHOD FOR MAKING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768254B2 (en) 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
WO2021035415A1 (zh) 2019-08-23 2021-03-04 京东方科技集团股份有限公司 显示装置及其制备方法
WO2017149428A1 (en) 2016-03-04 2017-09-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
KR102513161B1 (ko) 2016-03-11 2023-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 복합체 및 트랜지스터
WO2017153882A1 (en) * 2016-03-11 2017-09-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
JP6668455B2 (ja) 2016-04-01 2020-03-18 株式会社半導体エネルギー研究所 酸化物半導体膜の作製方法
CN109791949B (zh) * 2016-09-27 2022-02-25 夏普株式会社 半导体装置及其制造方法
US11545581B2 (en) * 2019-08-02 2023-01-03 South China University Of Technology Metal oxide (MO) semiconductor and thin-film transistor and application thereof
JP6887307B2 (ja) * 2017-05-19 2021-06-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN107611085B (zh) * 2017-10-24 2019-12-24 深圳市华星光电半导体显示技术有限公司 Oled背板的制作方法
US11545580B2 (en) * 2017-11-15 2023-01-03 South China University Of Technology Metal oxide (MO semiconductor and thin-film transistor and application thereof
US10593807B2 (en) * 2017-12-26 2020-03-17 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and fabricating method thereof
KR102639769B1 (ko) * 2018-11-22 2024-02-26 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN110034178B (zh) * 2019-04-19 2022-12-06 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN110190066A (zh) 2019-05-14 2019-08-30 深圳市华星光电技术有限公司 阵列基板和阵列基板的制备方法
KR102658007B1 (ko) 2019-07-30 2024-04-17 삼성디스플레이 주식회사 표시패널, 이에 포함되는 박막 트랜지스터, 및 이의 제조 방법
CN112740421A (zh) * 2019-08-23 2021-04-30 京东方科技集团股份有限公司 显示装置及其制备方法
CN113809163B (zh) * 2021-09-17 2023-11-24 武汉天马微电子有限公司 金属氧化物晶体管、显示面板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010226101A (ja) * 2009-02-27 2010-10-07 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2015053477A (ja) * 2013-08-05 2015-03-19 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法
US20150243738A1 (en) * 2014-02-21 2015-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, transistor, semiconductor device, display device, and electronic appliance

Family Cites Families (173)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459347A (en) * 1991-12-30 1995-10-17 Nippon Telegraph And Telephone Corporation Method of making field-effect semiconductor device on SOI
JP3921363B2 (ja) * 2001-08-20 2007-05-30 松下電器産業株式会社 不揮発性半導体記憶装置の製造方法
KR20080094300A (ko) * 2007-04-19 2008-10-23 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법과 박막 트랜지스터를포함하는 평판 디스플레이
JP5213422B2 (ja) * 2007-12-04 2013-06-19 キヤノン株式会社 絶縁層を有する酸化物半導体素子およびそれを用いた表示装置
KR20090124527A (ko) * 2008-05-30 2009-12-03 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
TWI567829B (zh) 2008-10-31 2017-01-21 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JPWO2010058528A1 (ja) * 2008-11-20 2012-04-19 シャープ株式会社 半導体層およびその形成方法
TWI506795B (zh) 2008-11-28 2015-11-01 Semiconductor Energy Lab 半導體裝置和其製造方法
US8441007B2 (en) 2008-12-25 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
KR101648927B1 (ko) * 2009-01-16 2016-08-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
CN103972246B (zh) * 2009-07-27 2017-05-31 株式会社神户制钢所 布线结构以及具备布线结构的显示装置
CN102473734B (zh) 2009-07-31 2015-08-12 株式会社半导体能源研究所 半导体装置及其制造方法
WO2011065244A1 (en) 2009-11-28 2011-06-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
WO2011074409A1 (en) 2009-12-18 2011-06-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
WO2011081009A1 (en) 2009-12-28 2011-07-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
WO2011122363A1 (en) 2010-04-02 2011-10-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101706081B1 (ko) * 2010-04-06 2017-02-15 삼성디스플레이 주식회사 박막 트랜지스터, 그 제조 방법 및 이를 포함하는 액정 표시 장치
US9209314B2 (en) 2010-06-16 2015-12-08 Semiconductor Energy Laboratory Co., Ltd. Field effect transistor
TWI525818B (zh) * 2010-11-30 2016-03-11 半導體能源研究所股份有限公司 半導體裝置及半導體裝置之製造方法
US9214474B2 (en) 2011-07-08 2015-12-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US8748886B2 (en) 2011-07-08 2014-06-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US8952377B2 (en) 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
TWI580047B (zh) 2011-12-23 2017-04-21 半導體能源研究所股份有限公司 半導體裝置
JP5917385B2 (ja) 2011-12-27 2016-05-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI604609B (zh) 2012-02-02 2017-11-01 半導體能源研究所股份有限公司 半導體裝置
WO2013154195A1 (en) 2012-04-13 2013-10-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP5946318B2 (ja) 2012-05-02 2016-07-06 株式会社半導体エネルギー研究所 半導体装置
WO2013168748A1 (ja) 2012-05-09 2013-11-14 株式会社神戸製鋼所 薄膜トランジスタおよび表示装置
KR102164990B1 (ko) 2012-05-25 2020-10-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 기억 소자의 구동 방법
KR102119914B1 (ko) 2012-05-31 2020-06-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
CN104380473B (zh) 2012-05-31 2017-10-13 株式会社半导体能源研究所 半导体装置
US8785928B2 (en) 2012-05-31 2014-07-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2014027263A (ja) 2012-06-15 2014-02-06 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US8901557B2 (en) 2012-06-15 2014-12-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9059219B2 (en) 2012-06-27 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR102161077B1 (ko) 2012-06-29 2020-09-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9190525B2 (en) 2012-07-06 2015-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including oxide semiconductor layer
KR20140009023A (ko) 2012-07-13 2014-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN104488016B (zh) 2012-07-20 2018-08-10 株式会社半导体能源研究所 显示装置及具有该显示装置的电子设备
US20140027762A1 (en) 2012-07-27 2014-01-30 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device
JP6134598B2 (ja) 2012-08-02 2017-05-24 株式会社半導体エネルギー研究所 半導体装置
SG11201505225TA (en) 2012-08-03 2015-08-28 Semiconductor Energy Lab Oxide semiconductor stacked film and semiconductor device
KR102171650B1 (ko) 2012-08-10 2020-10-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
JP6211843B2 (ja) 2012-08-10 2017-10-11 株式会社半導体エネルギー研究所 半導体装置
US9929276B2 (en) 2012-08-10 2018-03-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9245958B2 (en) * 2012-08-10 2016-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN104584229B (zh) 2012-08-10 2018-05-15 株式会社半导体能源研究所 半导体装置及其制造方法
JP6220597B2 (ja) 2012-08-10 2017-10-25 株式会社半導体エネルギー研究所 半導体装置
US8981372B2 (en) 2012-09-13 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic appliance
US9018624B2 (en) 2012-09-13 2015-04-28 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic appliance
TWI595659B (zh) 2012-09-14 2017-08-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
TWI627750B (zh) 2012-09-24 2018-06-21 半導體能源研究所股份有限公司 半導體裝置
WO2014046222A1 (en) 2012-09-24 2014-03-27 Semiconductor Energy Laboratory Co., Ltd. Display device
WO2014061567A1 (en) 2012-10-17 2014-04-24 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
JP6059501B2 (ja) 2012-10-17 2017-01-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR102168987B1 (ko) 2012-10-17 2020-10-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 마이크로컨트롤러 및 그 제조 방법
JP5951442B2 (ja) 2012-10-17 2016-07-13 株式会社半導体エネルギー研究所 半導体装置
JP6283191B2 (ja) 2012-10-17 2018-02-21 株式会社半導体エネルギー研究所 半導体装置
US9166021B2 (en) 2012-10-17 2015-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR102220279B1 (ko) 2012-10-19 2021-02-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 산화물 반도체막을 포함하는 다층막 및 반도체 장치의 제작 방법
JP6204145B2 (ja) 2012-10-23 2017-09-27 株式会社半導体エネルギー研究所 半導体装置
JP6300489B2 (ja) 2012-10-24 2018-03-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
WO2014065343A1 (en) 2012-10-24 2014-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2014065301A1 (en) 2012-10-24 2014-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR102279459B1 (ko) 2012-10-24 2021-07-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
TWI637517B (zh) 2012-10-24 2018-10-01 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP6220641B2 (ja) 2012-11-15 2017-10-25 株式会社半導体エネルギー研究所 半導体装置
TWI620323B (zh) 2012-11-16 2018-04-01 半導體能源研究所股份有限公司 半導體裝置
KR20230062659A (ko) 2012-11-30 2023-05-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9153649B2 (en) 2012-11-30 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for evaluating semiconductor device
US9246011B2 (en) 2012-11-30 2016-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR102207028B1 (ko) 2012-12-03 2021-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6320009B2 (ja) 2012-12-03 2018-05-09 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
US20150325439A1 (en) * 2012-12-14 2015-11-12 Board Of Regents, The University Of Texas System Growing crystalline semiconductor oxide thin films on a substrate at a low temperature using microwave radiation
WO2014103901A1 (en) 2012-12-25 2014-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR102211596B1 (ko) 2012-12-28 2021-02-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9391096B2 (en) 2013-01-18 2016-07-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
EP2955744A4 (en) * 2013-02-06 2016-08-03 Pvg Solutions Inc METHOD FOR FORMING BORON DIFFUSION LAYER AND METHOD FOR MANUFACTURING SOLAR BATTERY CELL
TWI618252B (zh) 2013-02-12 2018-03-11 半導體能源研究所股份有限公司 半導體裝置
US9231111B2 (en) 2013-02-13 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9190527B2 (en) 2013-02-13 2015-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
US9373711B2 (en) 2013-02-27 2016-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR102238682B1 (ko) 2013-02-28 2021-04-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치와 그 제작 방법
KR102153110B1 (ko) 2013-03-06 2020-09-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체막 및 반도체 장치
TWI644433B (zh) 2013-03-13 2018-12-11 半導體能源研究所股份有限公司 半導體裝置
US9368636B2 (en) 2013-04-01 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device comprising a plurality of oxide semiconductor layers
US10304859B2 (en) 2013-04-12 2019-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an oxide film on an oxide semiconductor film
TWI620324B (zh) 2013-04-12 2018-04-01 半導體能源研究所股份有限公司 半導體裝置
US9893192B2 (en) 2013-04-24 2018-02-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6401483B2 (ja) 2013-04-26 2018-10-10 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN105190902B (zh) 2013-05-09 2019-01-29 株式会社半导体能源研究所 半导体装置及其制造方法
DE102014208859B4 (de) 2013-05-20 2021-03-11 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung
KR102657220B1 (ko) 2013-05-20 2024-04-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
SG10201601511RA (en) 2013-05-20 2016-03-30 Semiconductor Energy Lab Semiconductor device
US9343579B2 (en) 2013-05-20 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6400336B2 (ja) 2013-06-05 2018-10-03 株式会社半導体エネルギー研究所 半導体装置
US20150001533A1 (en) 2013-06-28 2015-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20150008428A1 (en) 2013-07-08 2015-01-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US9666697B2 (en) 2013-07-08 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device including an electron trap layer
JP6322503B2 (ja) 2013-07-16 2018-05-09 株式会社半導体エネルギー研究所 半導体装置
TWI621130B (zh) 2013-07-18 2018-04-11 半導體能源研究所股份有限公司 半導體裝置及用於製造半導體裝置之方法
TWI632688B (zh) 2013-07-25 2018-08-11 半導體能源研究所股份有限公司 半導體裝置以及半導體裝置的製造方法
JP6410496B2 (ja) 2013-07-31 2018-10-24 株式会社半導体エネルギー研究所 マルチゲート構造のトランジスタ
JP6345544B2 (ja) 2013-09-05 2018-06-20 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR102294507B1 (ko) 2013-09-06 2021-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6401977B2 (ja) 2013-09-06 2018-10-10 株式会社半導体エネルギー研究所 半導体装置
JP6429540B2 (ja) 2013-09-13 2018-11-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2015079946A (ja) 2013-09-13 2015-04-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP6467171B2 (ja) 2013-09-17 2019-02-06 株式会社半導体エネルギー研究所 半導体装置
TWI677989B (zh) 2013-09-19 2019-11-21 日商半導體能源研究所股份有限公司 半導體裝置及其製造方法
US9397153B2 (en) 2013-09-23 2016-07-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6386323B2 (ja) 2013-10-04 2018-09-05 株式会社半導体エネルギー研究所 半導体装置
US9293592B2 (en) 2013-10-11 2016-03-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US9455349B2 (en) 2013-10-22 2016-09-27 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor with reduced impurity diffusion
JP2015109422A (ja) 2013-10-22 2015-06-11 株式会社半導体エネルギー研究所 半導体装置の評価方法
KR20160091968A (ko) 2013-11-29 2016-08-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 반도체 장치를 제작하는 방법, 및 표시 장치
JP6537264B2 (ja) 2013-12-12 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
US9349751B2 (en) 2013-12-12 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI642186B (zh) 2013-12-18 2018-11-21 日商半導體能源研究所股份有限公司 半導體裝置
TWI721409B (zh) 2013-12-19 2021-03-11 日商半導體能源研究所股份有限公司 半導體裝置
KR20160102295A (ko) 2013-12-26 2016-08-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2015097596A1 (en) 2013-12-26 2015-07-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9397149B2 (en) 2013-12-27 2016-07-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6446258B2 (ja) 2013-12-27 2018-12-26 株式会社半導体エネルギー研究所 トランジスタ
JP6488124B2 (ja) 2013-12-27 2019-03-20 株式会社半導体エネルギー研究所 半導体装置
US9401432B2 (en) 2014-01-16 2016-07-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
JP2015188062A (ja) 2014-02-07 2015-10-29 株式会社半導体エネルギー研究所 半導体装置
TWI685116B (zh) 2014-02-07 2020-02-11 日商半導體能源研究所股份有限公司 半導體裝置
US10096489B2 (en) 2014-03-06 2018-10-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
TWI695502B (zh) 2014-05-09 2020-06-01 日商半導體能源研究所股份有限公司 半導體裝置
TWI672804B (zh) 2014-05-23 2019-09-21 日商半導體能源研究所股份有限公司 半導體裝置的製造方法
TWI663726B (zh) 2014-05-30 2019-06-21 Semiconductor Energy Laboratory Co., Ltd. 半導體裝置、模組及電子裝置
WO2015182000A1 (en) 2014-05-30 2015-12-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and electronic device
WO2015181997A1 (en) 2014-05-30 2015-12-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR102437450B1 (ko) 2014-06-13 2022-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 반도체 장치를 포함하는 전자 기기
US9461179B2 (en) 2014-07-11 2016-10-04 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor device (TFT) comprising stacked oxide semiconductor layers and having a surrounded channel structure
WO2016009310A1 (en) 2014-07-15 2016-01-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
US9722091B2 (en) 2014-09-12 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9991393B2 (en) 2014-10-16 2018-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, module, and electronic device
WO2016063159A1 (en) 2014-10-20 2016-04-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof, module, and electronic device
WO2016063160A1 (en) 2014-10-20 2016-04-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, display device, and display module
TW201624708A (zh) 2014-11-21 2016-07-01 半導體能源研究所股份有限公司 半導體裝置及記憶體裝置
US20160155759A1 (en) 2014-11-28 2016-06-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the same
JP6647846B2 (ja) 2014-12-08 2020-02-14 株式会社半導体エネルギー研究所 半導体装置
CN113793872A (zh) 2014-12-10 2021-12-14 株式会社半导体能源研究所 半导体装置及其制造方法
US10396210B2 (en) 2014-12-26 2019-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with stacked metal oxide and oxide semiconductor layers and display device including the semiconductor device
TWI686874B (zh) 2014-12-26 2020-03-01 日商半導體能源研究所股份有限公司 半導體裝置、顯示裝置、顯示模組、電子裝置、氧化物及氧化物的製造方法
US9954112B2 (en) 2015-01-26 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9660100B2 (en) 2015-02-06 2017-05-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9954113B2 (en) 2015-02-09 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Transistor including oxide semiconductor, semiconductor device including the transistor, and electronic device including the transistor
US9818880B2 (en) 2015-02-12 2017-11-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
JP2016154225A (ja) 2015-02-12 2016-08-25 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US10403646B2 (en) 2015-02-20 2019-09-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9991394B2 (en) 2015-02-20 2018-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
JP6711642B2 (ja) 2015-02-25 2020-06-17 株式会社半導体エネルギー研究所 半導体装置
US9653613B2 (en) 2015-02-27 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6744108B2 (ja) 2015-03-02 2020-08-19 株式会社半導体エネルギー研究所 トランジスタ、トランジスタの作製方法、半導体装置および電子機器
DE112016001033T5 (de) 2015-03-03 2017-12-21 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung, Verfahren zum Herstellen derselben oder Anzeigevorrichtung mit derselben
TWI718125B (zh) 2015-03-03 2021-02-11 日商半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP6705663B2 (ja) 2015-03-06 2020-06-03 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US10147823B2 (en) 2015-03-19 2018-12-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9842938B2 (en) 2015-03-24 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including semiconductor device
KR20160114511A (ko) 2015-03-24 2016-10-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
US10096715B2 (en) 2015-03-26 2018-10-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for manufacturing the same, and electronic device
US9806200B2 (en) 2015-03-27 2017-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN107710392B (zh) 2015-04-13 2021-09-03 株式会社半导体能源研究所 半导体装置及其制造方法
JP6803682B2 (ja) 2015-05-22 2020-12-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP6986831B2 (ja) 2015-07-17 2021-12-22 株式会社半導体エネルギー研究所 半導体装置及び電子機器
US11189736B2 (en) 2015-07-24 2021-11-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9825177B2 (en) 2015-07-30 2017-11-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of a semiconductor device using multiple etching mask
WO2017037564A1 (en) 2015-08-28 2017-03-09 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor, transistor, and semiconductor device
WO2017149428A1 (en) * 2016-03-04 2017-09-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
WO2017153882A1 (en) * 2016-03-11 2017-09-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010226101A (ja) * 2009-02-27 2010-10-07 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2015053477A (ja) * 2013-08-05 2015-03-19 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法
US20150243738A1 (en) * 2014-02-21 2015-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, transistor, semiconductor device, display device, and electronic appliance

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11482626B2 (en) 2018-03-29 2022-10-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
US11552111B2 (en) 2018-04-20 2023-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
EP4075516A4 (en) * 2020-06-24 2023-08-16 BOE Technology Group Co., Ltd. METHOD FOR MAKING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE

Also Published As

Publication number Publication date
JP2022022213A (ja) 2022-02-03
US20190103497A1 (en) 2019-04-04
US20170263783A1 (en) 2017-09-14
JP2018006734A (ja) 2018-01-11
US11557612B2 (en) 2023-01-17
US10134914B2 (en) 2018-11-20
US20210028014A1 (en) 2021-01-28
US10796903B2 (en) 2020-10-06
KR20180123028A (ko) 2018-11-14
JP6971593B2 (ja) 2021-11-24

Similar Documents

Publication Publication Date Title
US11557612B2 (en) Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
US11869981B2 (en) Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
US11862454B2 (en) Semiconductor device and display device including the same
US11764309B2 (en) Semiconductor device and display device
US9496412B2 (en) Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
US11682733B2 (en) Semiconductor device, manufacturing method of the semiconductor device, or display device including the semiconductor device
US10263114B2 (en) Semiconductor device, method for manufacturing the same, or display device including the same
WO2016063160A1 (en) Semiconductor device, manufacturing method thereof, display device, and display module
US10205008B2 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20187025833

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17762612

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17762612

Country of ref document: EP

Kind code of ref document: A1