WO2011070928A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2011070928A1
WO2011070928A1 PCT/JP2010/071191 JP2010071191W WO2011070928A1 WO 2011070928 A1 WO2011070928 A1 WO 2011070928A1 JP 2010071191 W JP2010071191 W JP 2010071191W WO 2011070928 A1 WO2011070928 A1 WO 2011070928A1
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Prior art keywords
oxide semiconductor
terminal
semiconductor layer
layer
semiconductor device
Prior art date
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PCT/JP2010/071191
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English (en)
French (fr)
Inventor
Shunpei Yamazaki
Original Assignee
Semiconductor Energy Laboratory Co., Ltd.
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Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co., Ltd. filed Critical Semiconductor Energy Laboratory Co., Ltd.
Priority to KR1020177022155A priority Critical patent/KR101894821B1/ko
Priority to KR1020127017765A priority patent/KR101770976B1/ko
Priority to KR1020187024867A priority patent/KR102046308B1/ko
Priority to CN201080056245.6A priority patent/CN102656683B/zh
Publication of WO2011070928A1 publication Critical patent/WO2011070928A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the technical field of the disclosed invention relates to a semiconductor device using an oxide semiconductor.
  • the semiconductor device in this specification indicates all the devices that operate by utilizing semiconductor characteristics.
  • a semiconductor device widely includes the following elements: a semiconductor element (including a so-called power device) such as a transistor, a diode and a thyristor, an integrated circuit such as an image sensor, a memory and a converter, an integrated circuit including the above elements and a display device and the like typified by a liquid crystal display device.
  • a CMOS circuit is a necessary component for a semiconductor integrated circuit because a CMOS circuit has low power consumption and can operate at high speed and can be highly integrated.
  • an increase of power consumption at the time when an increase of power consumption in a non operating state (power consumption in a standby period, hereinafter also referred to as standby power) due to an increase of leakage current (also referred to as off state current, subthreshold current or the like) has been a problem.
  • the value of drain current cannot be made zero when a potential between a gate and a source is set to threshold voltage or less.
  • Patent Document 1 To prevent an increase of the standby power due to the leakage current, a technique using a switching transistor has been proposed (for example, see Patent Document 1).
  • the technique disclosed in Patent Document 1 is as follows: a switching transistor having small leakage current compared to a CMOS circuit is provided between a power supply and the CMOS circuit; the switching transistor is turned off when the CMOS circuit is not in operation so that standby power is decreased.
  • Patent Document 1 Japanese Published Patent Application No. H5-210976
  • Standby power depends on the leakage current of the switching transistor in the technique disclosed in Patent Document 1. That is, standby power can be sufficiently reduced by sufficiently reducing the leakage current of the switching transistor.
  • the channel width of the switching transistor needs to be equivalent to or more than that of a transistor included in a CMOS circuit, in order to supply sufficient current to a CMOS circuit and secure operation of a CMOS circuit.
  • one object of the present invention is to provide a new semiconductor device whose standby power is sufficiently reduced.
  • a semiconductor device for example, a transistor
  • a highly purified oxide semiconductor is formed using a highly purified oxide semiconductor.
  • the leakage current of the transistor formed using a highly purified oxide semiconductor is extremely small, so that on/off ratio can be sufficiently increased. In other words, the leakage current of the transistor can be kept at extremely low level even when current drive capability of the transistor is sufficiently secured.
  • the above-described oxide semiconductor is used for the following structure, whereby standby power of a semiconductor device can be sufficiently suppressed.
  • one embodiment of the disclosed invention is a semiconductor device including a first power supply terminal, a second power supply terminal, a switching transistor including an oxide semiconductor material and an integrated circuit.
  • the first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor.
  • the other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit.
  • the other terminal of the integrated circuit is electrically connected to the second power supply terminal.
  • another embodiment of the disclosed invention is a semiconductor device including a first power supply terminal, a second power supply terminal, a switching transistor including an oxide semiconductor material and having a first control terminal and a second control terminal and an integrated circuit.
  • the first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor.
  • the other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit.
  • the other terminal of the integrated circuit is electrically connected to the second power supply terminal.
  • the switching transistor may include an oxide semiconductor layer including an oxide semiconductor material, a gate electrode for applying an electric field to the oxide semiconductor layer, a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer.
  • a gate electrode for controlling the threshold voltage of the switching transistor may also be included in the switching transistor.
  • the gate electrode corresponds to a control terminal
  • the source electrode corresponds to a source terminal
  • the drain electrode corresponds to a drain terminal. Note that each electrode does not need to be the same as each terminal unless circuit operation is prevented.
  • some kind of element (such as a wiring, a switching element, a resistor, an inductor, a capacitor, an element having other various functions) is connected between an electrode (for example, a source electrode) and a terminal (for example, a source terminal) in some cases.
  • an electrode for example, a source electrode
  • a terminal for example, a source terminal
  • the oxide semiconductor material may be an In-Ga-Zn-O-based oxide semiconductor material.
  • leakage current of the switching transistor can be 1 ⁇ lO "13 A or less.
  • the integrated circuit can be formed using a semiconductor material other than an oxide semiconductor material.
  • the semiconductor material other than an oxide semiconductor material can be silicon.
  • the integrated circuit includes a CMOS circuit.
  • the terms “over” and “below” do not necessarily mean “directly on” and “directly under”, respectively, in the description of a physical relationship between components.
  • the expression of “a gate electrode over a gate insulating layer” may refer to the case where another component is interposed between the gate insulating layer and the gate electrode.
  • the terms “above” and “below” are just used for convenience of explanations and they can be interchanged unless otherwise specified.
  • electrode and “wiring” does not limit the function of components.
  • an “electrode” can be used as a part of “wiring”
  • the “wiring” can be used as a part of the “electrode”.
  • the terms “electrode” and “wiring” can also mean a combination of a plurality of “electrodes” and “wirings”, for example.
  • a "source” and a “drain” might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification.
  • a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having several functions, are included, as well as electrodes and wirings.
  • a highly purified oxide semiconductor is used for a semiconductor device.
  • “Highly purified” is a concept including at least one of the following: to remove hydrogen in an oxide semiconductor from the oxide semiconductor layer as much as possible; or to supply oxygen, which is in short supply in an oxide semiconductor, into the oxide semiconductor so that defect level in energy gap due to oxygen deficiency in the oxide semiconductor is reduced.
  • An oxide semiconductor layer is highly purified as described above to be an intrinsic (i-type) oxide semiconductor.
  • An oxide semiconductor is an n-type semiconductor in general, whereby the leakage current of a transistor using an oxide semiconductor is increased.
  • an oxide semiconductor is highly purified to be an i-type oxide semiconductor or close to an i-type oxide semiconductor in order to reduce leakage current sufficiently.
  • a semiconductor device including the highly purified oxide semiconductor as described above, so that a semiconductor device whose standby power is sufficiently reduced can be realized. It can be said that effect of the suppression of standby power increases as a circuit becomes complicated.
  • FIGS. 1A and IB are circuit diagrams relating to an example of a semiconductor device
  • FIG. 2 A is a cross-sectional view and FIG. 2B is a plan view each relating to an example of a semiconductor device
  • FIGS. 3A to 3H are cross-sectional views relating to manufacturing steps of a semiconductor device
  • FIGS. 4 A to 4G are cross-sectional views relating to manufacturing steps of a semiconductor device
  • FIGS. 5A to 5D are cross-sectional views relating to manufacturing steps of a semiconductor device
  • FIGS. 6 A and 6B are circuit diagrams relating to an example of a semiconductor device
  • FIG 7 is a cross-sectional view relating to an example of a semiconductor device
  • FIG. 8 is a block diagram relating to an example of a semiconductor device
  • FIGS. 9 A to 9E are cross-sectional views relating to manufacturing steps of a semiconductor device
  • FIGS. 1 OA to 10E are cross-sectional views relating to manufacturing steps of a semiconductor device.
  • FIGS. 11 A to 1 IF are diagrams for explaining electronic appliances. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIGS. 1 A and IB a structure and a manufacturing method of a semiconductor device according to one embodiment of the present invention disclosed will be described with reference to FIGS. 1 A and IB, FIGS. 2A and 2B, FIGS. 3A to 3H, FIGS. 4A to 4G and FIGS. 5A to 5D.
  • OS is written beside a transistor in order to indicate that the transistor includes an oxide semiconductor.
  • FIGS. 1A and I B show an example of a circuit configuration of a semiconductor device.
  • FIG. 1 A is an example of a semiconductor device using a CMOS inverter circuit which is the simplest CMOS circuit.
  • FIG. IB is an example of a semiconductor device having a plurality of CMOS inverter circuits.
  • a semiconductor device shown in FIG. 1A includes a power supply terminal VH, a power supply terminal VL, a switching transistor SI using an oxide semiconductor material and a CMOS inverter circuit CI .
  • the switching transistor SI is typically an n-channel transistor using an oxide semiconductor.
  • a high potential is supplied to the power supply terminal VH and a low potential is supplied to the power supply terminal VL.
  • the power supply terminal VH is electrically connected to a source terminal of a p-channel transistor in the CMOS inverter circuit CI.
  • a drain terminal of the p-channel transistor in the CMOS inverter circuit CI and a drain terminal of an n-channel transistor in the CMOS inverter circuit CI are electrically connected to each other and are connected to an output terminal OUT of the CMOS inverter circuit CI .
  • a source terminal of the n-channel transistor in the CMOS inverter circuit CI is electrically connected to a drain terminal of the switching transistor SI.
  • a source terminal of the switching transistor SI is electrically connected to the power supply terminal VL.
  • a gate terminal of the p-channel transistor in the CMOS inverter circuit CI and a gate terminal of the n-channel transistor in the CMOS inverter circuit CI are electrically connected to each other and are connected to an input terminal IN of the CMOS inverter circuit C 1.
  • a high potential is input to a control terminal S_IN of the switching transistor SI and the switching transistor SI turns on.
  • a high potential or a low potential is input to the input terminal IN
  • a high potential or a low potential corresponding to the potential is output from the output terminal OUT.
  • the p-channel transistor in the CMOS inverter circuit CI turns off and the n-channel transistor in the CMOS inverter circuit C 1 turns on, so that the CMOS inverter circuit CI outputs a low potential corresponding to the potential supplied to the power supply terminal VL.
  • the p-channel transistor in the CMOS inverter circuit CI turns on and the n-channel transistor in the CMOS inverter circuit CI turns off, so that the CMOS inverter circuit CI outputs a high potential corresponding to the potential supplied to the power supply terminal VH.
  • CMOS inverter circuit CI When the semiconductor device does not operate, a low potential is input to the control terminal S IN of the switching transistor SI and the switching transistor SI turns off.
  • Current which flows in the CMOS inverter circuit CI (leakage current) is controlled by the combined resistance of the CMOS inverter circuit CI and the switching transistor SI, whereby power consumption (power consumption in a standby period, hereinafter also referred to as standby power) can be sufficiently reduced by sufficiently increasing the off state resistance of the switching transistor SI and sufficiently reducing the leakage current of the switching transistor S 1.
  • a transistor using an oxide semiconductor material has a characteristic of a significantly small off state current.
  • the carrier density of a sufficiently intrinsic oxide semiconductor is less than 1 x 10 12 /cm 3 , preferably less than 1.45 x 10 10 /cm .
  • the off state current of a transistor is 1x10 A or less for example, in the case where the drain voltage Vd is +1 V or +10 V and the gate voltage Vg is in the range of -5 V to -20 V. Therefore, by forming the switching transistor SI using an oxide semiconductor, the leakage current of the semiconductor device can be sufficiently reduced.
  • leakage current at room temperature can be reduced from approximately 1 x lO -20 A (10 zA (zeptoampere)) to 1 x 10 " 19 A ( ⁇ ). That is, leakage current can even be reduced to substantially zero.
  • the amount of the leakage current does not change even in the case where the channel width of the switching transistor SI is relatively large. In other words, by a transistor using an oxide semiconductor, sufficient current drive capability can be secured and the leakage current can be reduced by reducing the power consumption of the semiconductor device.
  • a semiconductor device shown in FIG. IB corresponds to the semiconductor device shown in FIG. 1A in which the CMOS inverter circuit CI is replaced with a plurality of CMOS inverter circuits CI to Cn.
  • the semiconductor device shown in FIG. IB includes a power supply terminal VH, a power supply terminal VL, a switching transistor SI using an oxide semiconductor material and CMOS inverter circuits CI to Cn (also simply referred to as an integrated circuit).
  • each of the CMOS inverter circuits includes input terminals II to In and output terminals Ol to On.
  • the connection relations of each element are the same as that of FIG. 1 A.
  • a difference between FIGS. 1A and IB is that the plurality of CMOS inverter circuits CI to Cn is connected to each other in parallel and each of the CMOS inverter circuits is connected to the power supply terminal VH and the switching transistor SI in FIG IB.
  • the operation of the circuits is also the same as that of FIG. 1 A. Note that a potential is input to each of the input terminals and a potential corresponding to the input potential is output from each of the output terminals in FIG IB, which is different from that of FIG. 1A.
  • a semiconductor device whose standby power is sufficiently reduced is realized by using an oxide semiconductor, particularly, a highly purified oxide semiconductor for at least as a part of the semiconductor device.
  • an oxide semiconductor particularly, a highly purified oxide semiconductor for at least as a part of the semiconductor device.
  • the present invention can realize this.
  • the present invention is excellent. Specifically, in a circuit in which a number of circuits is integrated and is complicated, the total amount of standby power is large even if the amount of standby power of each circuit is slight. Therefore, effect of reducing the value of standby power to substantially zero is more noticeable as a circuit is integrated and complicated.
  • CMOS inverter circuit Note that an example of a semiconductor device using a CMOS inverter circuit is described here, but the disclosed invention is not limited thereto.
  • One embodiment of the disclosed invention can be used for any circuit (an integrated circuit) which has a problem with power consumption when a circuit is not in operation.
  • the switching transistor SI is electrically connected to the p-channel transistor in the CMOS inverter circuit, for example.
  • FIGS. 2A and 2B are an example of a structure of the semiconductor device shown in FIG 1 A.
  • FIG. 2 A shows a cross section of the semiconductor device and
  • FIG 2B shows a plan of the semiconductor device.
  • FIG 2 A corresponds to a cross section taken along line A1-A2-A3 in FIG 2B.
  • the semiconductor device shown in FIGS. 2 A and 2B includes a transistor 160 (a transistor included in a CMOS inverter circuit CI) using a material other than oxide semiconductor in a lower portion, and a transistor 162 (a transistor functioning as the switching transistor SI) using an oxide semiconductor in an upper portion. Note that the transistors 160 and 162 are both described as n-channel transistors.
  • CMOS inverter circuit both a p-channel transistor and an n-channel transistor are used in a CMOS inverter circuit.
  • a technical idea of the disclosed invention is to use a transistor using oxide semiconductor as a switching transistor in order to reduce power consumption; thus, a specific structure of the semiconductor device is not limited to the structure described here.
  • the transistor 160 includes a channel formation region 116 provided in a substrate 100 including a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (these regions can be collectively referred to simply as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108 provided over the channel formation region 116, a gate electrode 110 provided over the gate insulating layer 108 and a source electrode or drain electrode 130a and a source or drain electrode 130b both of which are electrically connected to the impurity regions 114.
  • Sidewall insulating layers 118 are provided on side surfaces of the gate electrode 110. Moreover, as shown in the plan view, the high-concentration impurity regions 120 are provided in a region of the substrate 100 which does not overlap with the side wall insulating layers 118, and metal compound regions 124 are present over the high-concentration impurity regions 120.
  • An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160.
  • An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160.
  • the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the metal compound regions 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the high-concentration impurity regions 120 and the impurity regions 114 through the metal compound regions 124.
  • the transistor 162 includes a gate electrode 136c provided over the interlayer insulating layer 128, a gate insulating layer 138 provided over the gate electrode 136c, an oxide semiconductor layer 140 provided over the gate insulating layer 138 and a source or drain electrode 142a and a source or drain electrode 142b both of which are provided over the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140.
  • the gate electrode 136c is formed so as to be embedded in an insulating layer 132 provided over the interlayer insulating layer 128. Like the gate electrode 136c, an electrode 136a and an electrode 136b are formed in contact with the source or drain electrode 130a and the source or drain electrode 130b, respectively.
  • a protective insulating layer 144 is provided over the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140.
  • An interlayer insulating layer 146 is provided over the protective insulating layer 144.
  • the protective insulating layer 144 and the interlayer insulating layer 146 are provided with openings reaching the source or drain electrode 142a and the source or drain electrode 142b.
  • An electrode 150c and an electrode 150d are in contact with the source or drain electrode 142a and the source or drain electrode 142b through the openings.
  • an electrode 150a and an electrode 150b are formed in contact with the electrode 136a and the electrode 136b, respectively, through openings in the gate insulating layer 138, the protective insulating layer 144 and the interlayer insulating layer 146.
  • the oxide semiconductor layer 140 is preferably a highly purified oxide semiconductor layer by sufficiently removing impurities such as hydrogen or sufficiently supplying oxygen.
  • the hydrogen concentration of the oxide semiconductor layer 140 is 5 x 10 19 atoms/cm 3 or less, preferably 5 x 10 18 atoms/cm 3 or less, and more preferably 5 10 atoms/cm or less.
  • the carrier concentration of the oxide semiconductor layer 140 which is highly purified and the hydrogen concentration of which is sufficiently reduced and defect level in energy gap due to oxygen deficiency is reduced by sufficiently supplying oxygen is as follows: less than 1 10 12 /cm 3 , preferably less than 1 x 10 11 /cm 3 , more preferably less than 1.45 ⁇ 10 10 /cm 3 .
  • the off state current is 1 x 10 ⁇ 13 A or less.
  • the off state resistivity is 1 ⁇ 10 9 ⁇ -m or more, preferably 1 x 10 10 ⁇ •m or more.
  • the transistor 162 with very excellent off current characteristics can be obtained with the use of such an oxide semiconductor that is highly purified to be intrinsic (i-type) or substantially intrinsic (i-type).
  • the hydrogen concentration in the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS).
  • the insulating layer 152 is provided over the interlayer insulating layer 146.
  • the electrode 154a, the electrode 154b and the electrode 154c are provided so as to be embedded in the insulating layer 152.
  • the electrode 154a is in contact with the electrode 150a
  • the electrode 154b is in contact with the electrodes 150b and 150c
  • the electrode 154c is in contact with the electrode 150d.
  • the source or drain electrode 130b of the transistor 160 is electrically connected to the source or drain electrode 142a of the transistor 162 through the electrode 136b, the electrode 150b, the electrode 154b and the electrode 150c.
  • the substrate 100 containing a semiconductor material is prepared (see
  • the substrate 100 containing a semiconductor material a single crystal semiconductor substrate or a polycrystalline semiconductor substrate containing silicon, silicon carbide or the like, a compound semiconductor substrate containing silicon germanium or the like, an SOI substrate or the like can be used.
  • a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material.
  • the term "SOI substrate” means a substrate having a silicon semiconductor layer over an insulating surface.
  • the term "SOI substrate” also means a substrate having a semiconductor layer using a material other than silicon over an insulating surface. That is, a semiconductor layer included in the "SOI substrate” is not limited to a silicon semiconductor layer.
  • the SOI substrate includes a substrate having a semiconductor layer over its insulating substrate such as a glass substrate, with an insulating layer between the semiconductor layer and the insulating substrate.
  • a protective layer 102 which functions as a mask for forming an element isolation insulating layer is formed (see FIG. 3A).
  • the protective layer 102 for example, an insulating layer formed using silicon oxide, silicon nitride, silicon oxynitride or the like can be used.
  • an impurity element giving n-type conductivity or an impurity element giving p-type conductivity may be added to the substrate 100 before or after the above step to control the threshold voltage of the transistor.
  • the impurity giving n-type conductivity phosphorus, arsenic or the like can be used when the semiconductor is silicon.
  • the impurity giving p-type conductivity boron, aluminum, gallium, or the like can be used, for example.
  • part of the substrate 100 in a region which is not covered with the protective layer 102 is removed by etching with the use of the protective layer 102 as a mask.
  • a semiconductor region 104 which is separated is formed (see FIG 3B).
  • dry etching is preferably performed, but wet etching may also be performed.
  • An etching gas and an etchant can be selected as appropriate depending on a material of the object to be etched.
  • an insulating layer is formed so as to cover the semiconductor region 104 and is selectively removed in a region which overlaps with the semiconductor region 104, whereby the element isolation insulating layer 106 is formed (see FIG. 3B).
  • the insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride or the like.
  • etching treatment and polishing treatment such as CMP, and any of them can be employed.
  • the protective layer 102 is removed either after the semiconductor region 104 is formed or after the element isolation insulating layer 106 is formed.
  • an insulating layer is formed over the semiconductor region 104 and a layer containing a conductive material is formed over the insulating layer.
  • the insulating layer serves as a gate insulating layer later and preferably has a single-layer structure or a stacked-layer structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide or the like obtained by using a CVD method, a sputtering method or the like.
  • the above insulating layer may be obtained by oxidizing or nitriding a surface of the semiconductor region 104 by high-density plasma treatment or thermal oxidation treatment.
  • the high-density plasma treatment can be performed using, for example, a mixed gas of a rare gas such as He, Ar, Kr or Xe and oxygen, nitrogen oxide, ammonia, nitrogen or hydrogen.
  • the thickness of the insulating layer can be 1 nra or more and 100 ran or less, for example.
  • the layer containing a conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten.
  • the layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon containing a conductive material.
  • a method for forming the layer containing a conductive material and any of a variety of film formation methods such as an evaporation method, a CVD method, a sputtering method and a spin coating method is applicable. Note that in this embodiment, an example of the case where the layer containing a conductive material is formed using a metal material is described.
  • the gate insulating layer 108 and the gate electrode 110 are formed (see FIG 3C).
  • Phosphorus (P), arsenic (As) or the like is then added to the semiconductor region 104, whereby the impurity regions 114 with a shallow junction depth in the substrate 100 are formed (see FIG. 3C).
  • an impurity element such as boron (B) or aluminum (Al) may be added in the case of forming a p-channel transistor.
  • the channel formation region 116 is formed in the semiconductor region 104 below the gate insulating layer 108 by formation of the impurity regions 114 (see FIG. 3C).
  • the concentration of the added impurity can be set as appropriate; in the case where a semiconductor element is highly miniaturized, the concentration is preferably set to be high. Further, a process in which the insulating layer 112 is formed after formation of the impurity regions 114 may be employed instead of the process employed here in which the impurity regions 114 are formed after formation of the insulating layer 112.
  • the sidewall insulating layers 118 are formed (see FIG. 3D).
  • An insulating layer is formed so as to cover the insulating layer 112 and then is subjected to highly anisotropic etching treatment, whereby the sidewall insulating layers 118 can be formed in a self-aligned manner. It is preferable that the insulating layer 112 be partly etched at this time so that a top surface of the gate electrode 110 and top surfaces of the impurity regions 114 are exposed.
  • an insulating layer is formed so as to cover the gate electrode 110, the impurity regions 114, the side wall insulating layers 118 and the like.
  • Phosphorus (P), arsenic (As), or the like is then added to regions where the gate insulating layer is in contact with the impurity regions 114, whereby the high-concentration impurity regions 120 are formed (see FIG. 3E).
  • the above insulating layer is removed and a metal layer 122 is formed so as to cover the gate electrode 110, the sidewall insulating layers 118, the high-concentration impurity regions 120 and the like (see FIG. 3E).
  • the metal layer 122 be formed using a metal material that reacts with a semiconductor material included in the semiconductor region 104 so as to form a metal compound having low resistance.
  • a metal material include titanium, tantalum, tungsten, nickel, cobalt and platinum.
  • a portion of the gate electrode 110 which is in contact with the metal layer 122 also has the metal compound region.
  • irradiation with a flash lamp can be used.
  • a method by which heat treatment for an extremely short time can be achieved is preferably used in order to improve the controllability of chemical reaction in formation of the metal compound.
  • the above described metal compound regions are formed through reaction of the metal material with the semiconductor material and have sufficiently high conductivity. By formation of the metal compound regions, electric resistance can be sufficiently reduced and element characteristics can be improved.
  • the metal layer 122 is removed after formation of the metal compound regions 124.
  • the interlayer insulating layers 126 and 128 are formed so as to cover the components formed in the above steps (see FIG 3G).
  • the interlayer insulating layers 126 and 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide.
  • an organic insulating material such as polyimide or acrylic can be used. Note that although a two-layer structure has been employed with the interlayer insulating layer 126 and the interlayer insulating layer 128 here, the structure of the interlayer insulating layers is not limited to this.
  • a surface of the interlayer insulating layer 128 is preferably subjected to CMP, etching treatment or the like so as to be flattened after the interlayer insulating layer 128 is formed.
  • the source or drain electrode 130a and the source or drain electrode 130b are formed in the openings (see FIG. 3H).
  • the source or drain electrode 130a and the source or drain electrode 130b can be formed as follows: a conductive layer is formed in a region including the openings by a PVD method, a CVD method or the like; and then, part of the conductive layer is removed by etching treatment, CMP or the like.
  • surfaces thereof are preferably processed to be flat.
  • a titanium film, a titanium nitride film or the like is formed to have a small thickness in the region including the openings and a tungsten film is then formed so as to fill the openings, CMP which is performed after that can remove an unnecessary portion of the tungsten film, titanium film, titanium nitride film or the like, and improve the flatness of the surfaces.
  • source or drain electrode 130a and the source or drain electrode 130b which are in contact with the metal compound regions 124 are described, an electrode which is in contact with the gate electrode 110 and the like can be formed in the same step.
  • a material used for the source or drain electrode 130a and the source or drain electrode 130b can be used.
  • a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium or scandium can be used.
  • the transistor 160 including the substrate 100 containing a semiconductor material is formed.
  • electrodes, wirings, insulating layers or the like may be formed as well after the above process is performed.
  • a multilayer wiring structure in which an interlayer insulating layer and a conductive layer are stacked is employed as a wiring structure, a highly-integrated semiconductor device can be provided.
  • FIGS. 4A to 4G and FIGS. 5 A to 5D a process through which the transistor 162 is manufactured over the interlayer insulating layer 128 is described with reference to FIGS. 4A to 4G and FIGS. 5 A to 5D. Note that the transistor 160 and the like below the transistor 162 are omitted in FIGS. 4A to 4G and FIGS. 5 A to 5D, which illustrate a manufacturing process of a variety of electrodes over the interlayer insulating layer 128, the transistor 162 and the like.
  • the insulating layer 132 is formed over the interlayer insulating layer 128, the source or drain electrode 130a and the source or drain electrode 130b (see FIG. 4A).
  • the insulating layer 132 can be formed by a PVD method, a CVD method or the like.
  • a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide can be used for the insulating layer 132.
  • openings reaching the source or drain electrode 130a and the source or drain electrode 130b are formed in the insulating layer 132. At this time, another opening is formed in a region where the gate electrode 136c is to be formed.
  • a conductive layer 134 is formed so as to fill the openings (see FIG. 4B).
  • the above openings can be formed by etching with the use of a mask, for example.
  • the mask can be formed by exposure using a photomask, for example.
  • etching either wet etching or dry etching may be performed but dry etching is preferable in view of the fine patterning.
  • the conductive layer 134 can be formed by a film formation method such as a PVD method or a CVD method.
  • Examples of a material for the conductive layer 134 include a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, an alloy of any of these, and a compound containing any of these (e.g., nitride of any of these).
  • a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, an alloy of any of these, and a compound containing any of these (e.g., nitride of any of these).
  • the conductive layer 134 can be formed as follows: a titanium film is formed to have a small thickness by a PVD method in a region including the openings and a titanium nitride film is then formed to have a small thickness by a CVD method; and then, a tungsten film is formed so as to fill the openings.
  • the titanium film formed by a PVD method has a function of reducing an oxide film (e.g., a natural oxide film) formed on a surface over which the titanium film is formed, to decrease the contact resistance with the lower electrodes (here, the source or drain electrode 130a, the source or drain electrode 130b or the like).
  • the subsequently formed titanium nitride film has a barrier property such that diffusion of a conductive material is prevented.
  • a barrier film is formed using titanium, titanium nitride or the like, a copper film may be formed by a plating method.
  • part of the conductive layer 134 is removed by etching treatment, CMP or the like so that the insulating layer 132 is exposed and the electrodes 136a, 136b and the gate electrode 136c are formed (see FIG. 4C).
  • processing is preferably performed so that flattened surfaces are obtained.
  • the gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrodes 136a, 136b and the gate electrode 136c (see FIG 4D).
  • the gate insulating layer 138 can be formed by a sputtering method, a CVD method or the like.
  • the gate insulating layer 138 preferably contains silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide or the like. Note that the gate insulating layer 138 may have a single-layer structure or a stacked-layer structure. There is no particular limitation on the thickness of the gate insulating layer 138, but the thickness can be 10 nm or more and 500 nm or less, for example.
  • the gate insulating layer 138 is preferably formed by stacking a first gate insulating layer with a thickness 50 nm or more and 200 nm or less and a second gate insulating layer with a thickness 5 nm or more and 300 nm or less over the first gate insulating layer.
  • an oxide semiconductor which is made to be an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor by removing an impurity is extremely sensitive to an interface energy levels or to the electric charges trapping at the interface; therefore, when such an oxide semiconductor is used for an oxide semiconductor layer, an interface between the oxide semiconductor layer and a gate insulating layer is important. Therefore, the gate insulating layer 138 which is to be in contact with the highly purified oxide semiconductor layer needs to be of high quality.
  • a high-density plasma CVD method using microwave (2.45 GHz) is favorable because a dense and high-quality gate insulating layer 138 having high withstand voltage can be formed thereby.
  • the interface state can be reduced and interface characteristics can be favorable when the highly purified oxide semiconductor layer and the high quality gate insulating layer are in contact with each other.
  • the gate insulating layer 138 which is of good quality and which is capable of reducing interface state with the oxide semiconductor layer may be formed.
  • an oxide semiconductor layer is formed over the gate insulating layer 138 and processed by a method such as etching using a mask so that the oxide semiconductor layer 140 having an island-shape is formed (see FIG 4E).
  • the oxide semiconductor layer is preferably formed using a sputtering method.
  • an In-Sn-Ga-Zn-O-based oxide semiconductor layer which is a four-component metal oxide
  • an In-Ga-Zn-O-based oxide semiconductor layer an In-Sn-Zn-O-based oxide semiconductor layer, an In-Al-Zn-O-based oxide semiconductor layer, a Sn-Ga-Zn-O-based oxide semiconductor layer, an Al-Ga-Zn-O-based oxide semiconductor layer or a Sn-Al-Zn-O-based oxide semiconductor layer which are three-component metal oxide
  • an In-Ga-Zn-O-based metal oxide when used, a semiconductor device having sufficiently high resistance and sufficiently reduced off state current when there is no electric field, or a semiconductor device having high field effect mobility can be formed. Therefore, an In-Ga-Zn-O-based metal oxide is preferable for a semiconductor material used for a semiconductor device.
  • InGa0 3 (ZnO) OT m>0
  • InM0 3 (ZnO) m M instead of Ga
  • M denotes one or more of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co) and the like.
  • M can be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co or the like. Note that the above described composition is derived from a crystal structure and is just an example.
  • the oxide semiconductor layer is formed by a sputtering method using a target for forming an In-Ga-Zn-O-based oxide semiconductor.
  • a substrate is set in a chamber at reduced pressure and the substrate temperature is preferably set 100 °C or higher and 600 °C or lower, more preferably 200 °C or higher and 400 °C or lower.
  • the substrate temperature is preferably set 100 °C or higher and 600 °C or lower, more preferably 200 °C or higher and 400 °C or lower.
  • An atmosphere for film formation of the oxide semiconductor layer is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen.
  • a high-purity gas atmosphere is preferable in which the concentration of impurities such as hydrogen, water, hydroxyl and hydride is reduced to a concentration of approximately several parts per million (preferably several parts per billion).
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump can be used.
  • the evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0) (and also preferably a compound containing a carbon atom) or the like is removed from a deposition chamber which is evacuated with the cryopump, so that the concentration of impurities contained in the oxide semiconductor layer formed in the deposition chamber can be reduced.
  • the oxide semiconductor layer is formed to have a thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that an appropriate thickness depends on an applied oxide semiconductor material, and the thickness of the oxide semiconductor layer may be set as appropriate depending on the material.
  • powder substances also referred to as particles or dust
  • the film thickness can be uniform.
  • the oxide semiconductor layer can be formed using a sputtering method under the following conditions, for example: the distance between the substrate and the target is 170 mm; the pressure is 0.4 Pa; the direct current (DC) power supply is 0.5 kW; and the atmosphere is oxygen (the flow rate ratio of oxygen is 100 %).
  • the reverse sputtering means a method for improving the quality of a surface of the object to be processed by ions striking on the surface, while general sputtering is achieved by ions striking on a sputtering target.
  • Methods for making ions strike the surface of the object to be processed include a method in which a high frequency voltage is applied on the surface in an argon atmosphere and plasma is generated in the vicinity of the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere or the like may be used instead of the argon atmosphere.
  • etching of the oxide semiconductor layer either dry etching or wet etching may be used. Needless to say, a combination of dry etching and wet etching may be employed.
  • the etching conditions an etching gas, etching solution, etching time, temperature or the like
  • the etching conditions may be set as appropriate, depending on the material so that the oxide semiconductor layer can be etched into a desired shape.
  • etching gas for dry etching examples include a gas containing chlorine (a chlorine-based gas such as chlorine (Cl 2 ), boron trichloride (BC1 3 ), silicon tetrachloride (SiCl 4 ) or carbon tetrachloride (CC1 4 )) and the like.
  • a chlorine-based gas such as chlorine (Cl 2 ), boron trichloride (BC1 3 ), silicon tetrachloride (SiCl 4 ) or carbon tetrachloride (CC1 4 )
  • chlorine chlorine
  • BC1 3 boron trichloride
  • SiCl 4 silicon tetrachloride
  • CC1 4 carbon tetrachloride
  • a gas containing fluorine a fluorine-based gas such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ) or trifluoromethane (CHF 3 )); hydrogen bromide (HBr); oxygen (0 2 ); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like may be used.
  • a fluorine-based gas such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ) or trifluoromethane (CHF 3 )
  • hydrogen bromide HBr
  • oxygen (0 2 ); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like may be used.
  • a parallel plate reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method can be used.
  • the etching conditions (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side or the like) are set as appropriate.
  • etchant used for wet etching a mixed solution of phosphoric acid, acetic acid and nitric acid or the like can be used.
  • An etchant such as ITO07N (produced by KANTO CHEMICAL CO., INC.) may also be used.
  • the oxide semiconductor layer is preferably subjected to first heat treatment.
  • the oxide semiconductor layer can be dehydrated or dehydrogenated.
  • the first heat treatment is performed at a temperature 300 °C or higher and 750 °C or lower, preferably 400 °C or higher and 700 °C or lower.
  • the substrate is introduced into an electric furnace using a resistance heating element or the like and the oxide semiconductor layer 140 is subjected to heat treatment in a nitrogen atmosphere at a temperature of 450 °C for an hour. During this time, the oxide semiconductor layer 140 is prevented from being exposed to the air so that entry of hydrogen (including water and the like) is prevented.
  • a heat treatment apparatus is not limited to an electrical furnace, and may include a device for heating an object to be processed by heat conduction or heat radiation given by a medium such as a heated gas or the like.
  • a rapid thermal anneal (RTA) apparatus such as a lamp rapid thermal anneal (LRTA) apparatus or a gas rapid thermal anneal (GRTA) apparatus can be used.
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus for heat treatment using a high-temperature gas.
  • the gas an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used.
  • GRTA treatment may be performed as follows.
  • the substrate is placed in an inert gas which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and taken out from the inert gas.
  • GRTA treatment enables high-temperature heat treatment for a short time.
  • a substrate having low heat resistance such as a glass substrate or the like is used, such heat treatment is applicable even when a temperature exceeds the strain point of the substrate because it takes only short time.
  • the first heat treatment is preferably performed in an atmosphere which contains nitrogen or a rare gas (such as helium, neon or argon) as its main component and does not contain water, hydrogen or the like.
  • nitrogen or a rare gas such as helium, neon or argon
  • the purity of nitrogen or a rare gas (such as helium, neon or argon) introduced into the heat treatment apparatus is 6N (99.9999 %) or more, preferably 7N (99.99999 %) or more (that is, the concentration of impurities is 1 ppm or less, preferably 0.1 ppm or less).
  • the oxide semiconductor layer might be crystallized to be an oxide semiconductor layer including a crystal depending on the condition of the first heat treatment or the material of the oxide semiconductor layer. Further, depending on the condition of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become an amorphous oxide semiconductor layer containing no crystalline component.
  • electric characteristics of the oxide semiconductor layer can be changed by providing a crystal layer over the amorphous surface.
  • the electric characteristics of the oxide semiconductor layer can be changed by forming a crystal layer in which a crystal grain having electrical anisotropy is aligned.
  • Such a crystal layer may be referred to as a plate-like crystal according to its shape.
  • the first heat treatment performed on the oxide semiconductor layer 140 can be performed on the oxide semiconductor layer which has not yet been processed into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography step is performed.
  • the first heat treatment can dehydrogenate (dehydrate) the oxide semiconductor layer 140 and thus can be called dehydrogenation treatment (dehydration treatment). It is possible to perform such treatment at any timing, for example, after the oxide semiconductor layer is formed, after the source electrode or the drain electrode is stacked over the oxide semiconductor layer 140 or after a protective insulating layer is formed over the source and drain electrodes. Such treatment may be performed more than once.
  • the first heat treatment can be omitted.
  • the source or drain electrode 142a and the source or drain electrode 142b are formed in contact with the oxide semiconductor layer 140 (see FIG. 4F).
  • the source or drain electrode 142a and the source or drain electrode 142b can be formed in such a manner that a conductive layer is formed so as to cover the oxide semiconductor layer 140 and then selectively etched. Note that in some cases, the oxide semiconductor layer 140 is partly etched in this step and thus has a groove portion (a recessed portion) depending on the materials and the etching conditions.
  • the conductive layer can be formed by a PVD method such as a sputtering method, a CVD method such as a plasma CVD method.
  • a material of the conductive layer an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum and tungsten, an alloy containing any of the above elements as its component or the like can be used. Further, a material containing one or more elements selected from manganese, magnesium, zirconium, beryllium and thorium as a component may be used.
  • a material in which aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium and scandium are combined is also applicable to the material of the conductive layer.
  • the conductive layer may have either a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure of an aluminum film and a titanium film stacked thereover, a three-layer structure in which a titanium film, an aluminum film and a titanium film are stacked in this order and the like can be given.
  • the conductive layer may be formed using conductive metal oxide.
  • conductive metal oxide indium oxide (ln 2 0 3 ), tin oxide (Sn0 2 ), zinc oxide (ZnO), indium oxide-tin oxide alloy (In 2 0 3 -Sn0 2 , which is abbreviated to ITO in some cases), indium oxide-zinc oxide alloy (In 2 0 3 -ZnO) or any of these metal oxide materials in which silicon or silicon oxide is contained can be used.
  • the channel length (L) of the transistor is determined by a distance between a lower edge portion of the source or drain electrode 142a and a lower edge portion of the source or drain electrode 142b.
  • exposure to make a mask for etching may be performed in the extreme ultraviolet range of several nanometers to several tens of nanometers which is extremely short wavelength.
  • the resolution is high and the focus depth is large. Therefore, the channel length (L) of the transistor to be formed can be 10 nm or more and 1000 nm or less, whereby operation speed of a circuit can be increased and power consumption can be reduced.
  • plasma treatment using a gas such as N 2 0, N 2 or Ar is preferably performed after the above step.
  • a gas containing oxygen such as a mixed gas of oxygen and argon. In this manner, the oxide semiconductor layer is supplied with oxygen and defect level in energy gap due to oxygen deficiency can be reduced.
  • the protective insulating layer 144 which is in contact with part of the oxide semiconductor layer 140 is formed without exposure to the air (see FIG 4G).
  • the protective insulating layer 144 can be formed by appropriately employing a method such as a sputtering method, by which an impurity such as hydrogen or water is prevented from entering the protective insulating layer 144.
  • the protective insulating layer 144 is formed to have a thickness 1 nm or more.
  • As a material which can be used for the protective insulating layer 144 there are silicon oxide, silicon nitride, silicon oxynitride and the like.
  • the protective insulating layer 144 may have a single-layer structure or a stacked-layer structure.
  • the substrate temperature for formation of the protective insulating layer 144 is preferably room temperature or higher and 300 °C or lower, preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen.
  • a rare gas typically argon
  • oxygen atmosphere typically a mixed atmosphere of a rare gas (typically argon) and oxygen.
  • the protective insulating layer 144 When hydrogen is contained in the protective insulating layer 144, entry of the hydrogen to the oxide semiconductor layer 140, extraction of oxygen in the oxide semiconductor layer 140 by the hydrogen or the like is caused, and the resistance of the backchannel side of the oxide semiconductor layer 140 is made low, which may form a parasitic channel. Therefore, it is preferable that a formation method in which hydrogen is not used be employed so that the protective insulating layer 144 contains hydrogen as less as possible.
  • the protective layer 144 is formed by a sputtering method
  • a sputtering gas a high-purity gas from which a concentration of an impurity such as hydrogen, water, hydroxyl or hydride is reduced to approximately several parts per million (preferably several parts per billion) is used.
  • moisture remaining in a treatment chamber is preferably removed.
  • an insulating layer containing silicon oxide is formed by a sputtering method.
  • second heat treatment (preferably at a temperature 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) in an inert gas atmosphere or an oxygen atmosphere is preferably performed.
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for an hour.
  • the second heat treatment can reduce variation in the electric characteristics of the transistor.
  • oxygen is supplied from an insulating layer containing oxygen to the oxide semiconductor layer and defect level in energy gap due to oxygen deficiency can be reduced.
  • an atmosphere of the second heat treatment is not limited to the above described atmosphere and may be an air atmosphere or the like. In this case, hydrogen, water and the like may be preferably removed from the atmosphere so that hydrogen is not included in the oxide semiconductor layer.
  • the second heat treatment is not an absolutely necessary step, whereby the second heat treatment can be omitted.
  • the interlayer insulating layer 146 is formed over the protective insulating layer 144 (see FIG 5 A).
  • the interlayer insulating layer 146 can be formed by a PVD method, a CVD method or the like.
  • a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide can be used for the interlayer insulating layer 146.
  • a surface of the interlayer insulating layer 146 is preferably subjected to CMP, etching or the like so as to be flattened after the interlayer insulating layer 146 is formed.
  • openings reaching the electrodes 136a and 136b, the source or drain electrode 142a and the source or drain electrode 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138; then, a conductive layer 148 is formed so as to fill the openings (see FIG. 5B).
  • the above openings can be formed by etching with the use of a mask, for example.
  • the mask can be formed by exposure using a photomask, for example.
  • For the etching either wet etching or dry etching may be performed but dry etching is preferable in view of the fine patterning.
  • Materials used for the conductive layer 148, a method for forming the conductive layer 148 and the like is the same as that of the conductive layer 134, so that description about the conductive layer 134 can be referred to for the details.
  • the conductive layer 148 After the conductive layer 148 is formed, part of the conductive layer 148 is removed by etching, CMP or the like so that the interlayer insulating layer 146 is exposed and the electrodes 150a, 150b, 150c and 150d are formed (see FIG 5C). Note that when the electrodes 150a, 150b, 150c and 150d are formed by removing part of the above conductive layer 148, processing is preferably performed to obtain flattened surfaces. By flattening surfaces of the interlayer insulating layer 146 and the electrodes 150a, 150b, 150c and 150d, favorable electrodes, wirings, insulating layers, semiconductor layers, and the like can be formed in a subsequent step.
  • the insulating layer 152 is formed.
  • openings reaching the electrodes 150a, 150b, 150c and 150d are formed.
  • a conductive layer is formed so as to be embedded in the openings.
  • part of the conductive layer is removed by etching, CMP or the like so that the insulating layer 152 is exposed and the electrodes 154a, 154b and 154c are formed (see FIG. 5D). This step is similar to that of the electrode 136a, the electrode 150a and the like; therefore, detailed description is omitted here.
  • the hydrogen concentration of the oxide semiconductor layer 140 is 5 x 10 19 atoms/cm 3 or less, preferably 5 x 10 18 atoms/cm 3 or less, more preferably 5 x 10 17 atoms/cm 3 or less.
  • the off state current of the transistor 162 is 1 ⁇ 10 ⁇ 13 A or less and the off resistivity is 1 x 10 9 ⁇ •m or more (alternatively, 1 x 10 10 ⁇ -m or more).
  • the transistor 162 having excellent characteristics can be obtained by employing the highly purified oxide semiconductor layer in which the hydrogen concentration is sufficiently reduced and defect level in energy gap due to oxygen deficiency are reduced.
  • a semiconductor device related to a stacked-layer structure of a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor is not limited to the stacked-layer structure.
  • a single-layer structure, a stacked-layer structure of two or more layers may be used.
  • a semiconductor device can have a single-layer structure or a stacked-layer structure using only an oxide semiconductor as a semiconductor material.
  • field effect mobility ⁇ can be ⁇ > 100 cm 2 /V s and a semiconductor device using only an oxide semiconductor can be realized.
  • a semiconductor device can be formed using a substrate such as a glass substrate or the like.
  • an arrangement and a connection relation of an electrode (a wiring), an insulating layer, a semiconductor layer and the like, various parameters such as a width of a wiring, a channel width, a channel length and the other conditions can be changed as appropriate in accordance with a function required for a semiconductor integrated circuit.
  • a structure of an electrode, a wiring and the like of a semiconductor device having a single-layer structure is greatly different from that of a semiconductor device having a stacked-layer structure.
  • FIGS. 6 A and 6B show an example of a circuit configuration of a semiconductor device according to this embodiment.
  • FIG 6A is an example of a semiconductor device using a CMOS inverter circuit which is the simplest CMOS circuit.
  • FIG. 6B is an example of a semiconductor device having a plurality of CMOS inverter circuits.
  • a difference between the semiconductor devices shown in FIGS. 6A and 6B and the semiconductor devices shown in FIGS. 1A and IB is whether the switching transistor SI using an oxide semiconductor has a back gate or not.
  • the switching transistor SI has a back gate, so that the threshold voltage of the switching transistor SI can be controlled by controlling a potential of the back gate. Consequently, an off state leakage current can be easily reduced to the value which can be considered substantially zero.
  • control terminal S IN l since the switching transistor SI has the back gate as described above, there are two control terminals: control terminal S IN l and control terminal S IN 2. Similar to the foregoing embodiment, a high potential or a low potential is input to the control terminal S IN l, whereby the switching transistor SI is switched on and off.
  • the value of a potential input to the control terminal S IN 2 is not particularly limited as long as it is a potential to make a threshold voltage of the switching transistor SI be a desired value.
  • a constant potential or a fluctuating potential may be input to the control terminal S_IN_2.
  • a potential like a ground potential may be employed.
  • FIG 7 is an example of a structure (a cross-section) of the semiconductor device shown in FIG 6A.
  • the semiconductor device shown in FIG. 7 includes a transistor 160 using a material other than oxide semiconductor in a lower portion (a transistor included in a CMOS inverter circuit CI), and a transistor 162 using an oxide semiconductor in an upper portion (a transistor functioning as the switching transistor SI).
  • the semiconductor device shown in FIG. 7 is in common with the semiconductor device shown in FIG. 2A.
  • a difference between the semiconductor device shown in FIG 2A and the semiconductor device shown in FIG. 7 is whether a gate electrode 145 is provided or not in addition to the gate electrode 136c.
  • the details of each component are the same as those of the semiconductor device shown in the foregoing embodiment.
  • the gate electrode 145 provided in the region over the protective insulating layer 144 which overlaps with the oxide semiconductor layer 140 has a function of generating an electric field which controls the threshold voltage of the transistor 162.
  • the off state leakage current of the transistor 162 be easily suppressed to the value which can be considered substantially zero.
  • the protective insulating layer 144 also has a function of a gate insulating layer.
  • An integrated semiconductor device 170 which is a modification example of the semiconductor device shown in the foregoing embodiment (for example, Embodiment 1) is shown in FIG. 8.
  • Specific examples of the integrated semiconductor device 170 are a CPU, an MPU and the like.
  • the semiconductor device 170 includes a plurality of circuit blocks such as circuit blocks 171 to 174 and the like.
  • the circuit blocks are electrically connected to each other through an element using an oxide semiconductor at least in a part thereof such as a switching element 181, a switching element 182 and the like.
  • circuit blocks 171 to 174 an integrated circuit including the CMOS inverter circuits CI to Cn and the like can be used, for example.
  • a memory circuit or the like typified by DRAM may also be applied.
  • Each circuit blocks needs to have an appropriate function depending on the required properties.
  • the switching transistor SI can be used, for example. At least a part of the switching element 181 and the switching element 182 are preferably formed using an oxide semiconductor, particularly, a highly purified oxide semiconductor.
  • the semiconductor device 170 shown in FIG 8 is only an example in which the configuration is simplified, and an actual semiconductor device may have various configurations depending on the uses.
  • At least a part of the semiconductor device 170 is formed using an oxide semiconductor, particularly, a highly purified oxide semiconductor and standby power thereof is sufficiently suppressed. As described in the foregoing embodiment, an effect of suppressing standby power in an integrated and complicated semiconductor device is extremely large.
  • FIGS. 9A to 9E Another example of a method for manufacturing a transistor using an oxide semiconductor which can be used as the switching transistor SI in the foregoing embodiment (such as Embodiment 1) is described with reference to FIGS. 9A to 9E.
  • top-gate transistor is described as an example but a structure of the transistor is not necessarily limited to a top-gate transistor.
  • an insulating layer 202 is formed over a lower layer substrate 200. Then an oxide semiconductor layer 206 is formed over the insulating layer 202 (see FIG. 9A).
  • the lower layer substrate 200 can be a structure body in a portion lower than the interlayer insulating layer 128 in the semiconductor device of the foregoing embodiment (the semiconductor device shown in FIG 2A and the like).
  • the foregoing embodiment can be referred to for the details.
  • the insulating layer 202 functions as a base and is formed in the same manner as the gate insulating layer 138, the protective insulating layer 144 and the like in the foregoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • the insulating layer 202 is preferably formed containing as little hydrogen or water as possible.
  • an In-Sn-Ga-Zn-O-based oxide semiconductor layer which is a four-component metal oxide; an In-Ga-Zn-O-based oxide semiconductor layer, an In-Sn-Zn-O-based oxide semiconductor layer, an In-Al-Zn-O-based oxide semiconductor layer, a Sn-Ga-Zn-O-based oxide semiconductor layer, an Al-Ga-Zn-O-based oxide semiconductor layer or a Sn-Al-Zn-O-based oxide semiconductor layer which are three-component metal oxide; an In-Zn-O-based oxide semiconductor layer, a Sn-Zn-O-based oxide semiconductor layer, an Al-Zn-O-based oxide semiconductor layer, a Zn-Mg-O-based oxide semiconductor layer, a Sn-Mg-O-based oxide semiconductor layer or an In-Mg-O-based oxide semiconductor layer which are two-component metal oxide; or an In-O-based oxide semiconductor layer, a Sn-O-O-
  • an In-Ga-Zn-O-based oxide semiconductor material has sufficiently high resistance when there is no electric field and thus off state current can be sufficiently reduced.
  • the In-Ga-Zn-O-based oxide semiconductor material is suitable for a semiconductor device.
  • a thin film represented by InM0 3 (ZnO) m (m > 0 and m is not a natural number) can be used.
  • M is one or more metal elements selected from Ga, Al, Mn and Co.
  • M Ga, Ga and Al, Ga and Mn, and Ga and Co are given.
  • a material represented by can also be used.
  • x, y and z are given numbers.
  • x, y, and z do not necessarily be integers and may be non-integers. Note that x may be zero but y is preferably not zero.
  • the expression includes In-Zn-0 in which x is zero.
  • the oxide semiconductor material represented by In-Ga-Zn-O described in this specification is InGa0 3 (ZnO) m (m > 0 and m is not a natural number).
  • m is not a natural number can be confirmed by analysis using ICP-MS or RBS.
  • the oxide semiconductor layer 206 having an amorphous structure is formed by a sputtering method using a target for forming an In-Ga-Zn-O-based oxide semiconductor.
  • a metal oxide semiconductor contained in the oxide semiconductor target for film formation has a relative density of 80 % or more, preferably 95 % or more, more preferably 99.9 % or more. With use of a target for forming an oxide semiconductor with high relative density, the oxide semiconductor layer 206 having a dense structure can be formed.
  • An atmosphere for formation of the oxide semiconductor layer 206 is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen.
  • a rare gas typically argon
  • an atmosphere of a high-purity gas is preferable in which the concentration of impurities such as hydrogen, water, hydroxyl and hydride is reduced to a concentration of approximately several parts per million (preferably several parts per billion).
  • the substrate is fixed in a treatment chamber which is kept in a reduced-pressure state and heated so that the substrate temperature is 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower.
  • a sputtering gas from which hydrogen, moisture and the like are removed is introduced, and the oxide semiconductor layer 206 is formed with use of the target.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump or a titanium sublimation pump can be used.
  • the evacuation unit may be a turbo pump provided with a cold trap. Hydrogen, water and the like are removed from the deposition chamber by evacuating with the cryopump, so that the concentration of impurities contained in the oxide semiconductor layer 206 can be reduced.
  • the film formation conditions of the oxide semiconductor layer 206 can be set as follows: the distance between a substrate and a target is 170 mm; the pressure is 0.4 Pa; the direct-current (DC) power is 0.5 kW; and the atmosphere is an oxygen atmosphere (the flow rate ratio of oxygen is 100 %) or an argon atmosphere (the flow rate ratio of argon is 100 %). It is preferable that a pulsed direct-current (DC) power supply be used because powder substances (also referred to as particles or dust) can be reduced and a variation of the film thickness can be decreased.
  • the thickness of the oxide semiconductor layer 206 is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that an appropriate thickness depends on an oxide semiconductor material to be applied, the intended use of the semiconductor device or the like, and thus the thickness of the oxide semiconductor layer may be set as appropriate depending on the material to be used, the intended use or the like.
  • the oxide semiconductor layer 206 is formed by a sputtering method
  • a material attached to a surface of the insulating layer 202 is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated.
  • the reverse sputtering means a method for improving the quality of a surface of the object to be processed by ions striking on the surface, while general sputtering is achieved by ions striking on a sputtering target.
  • Methods for making ions strike the surface of the object to be processed include a method in which a high frequency voltage is applied on the surface in an argon atmosphere and plasma is generated in the vicinity of the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere or the like may be used instead of the argon atmosphere.
  • an island-shaped oxide semiconductor layer 206a is formed by processing the oxide semiconductor layer 206 by an etching or the like with use of a mask.
  • etching of the oxide semiconductor layer 206 either dry etching or wet etching may be used. Needless to say, a combination of dry etching and wet etching may be employed.
  • the etching conditions an etching gas, etching solution, etching time, temperature or the like
  • the etching of the oxide semiconductor layer 206 can be performed in the same manner as the etching of the semiconductor layer in the foregoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • the oxide semiconductor layer 206a is desirably subjected to heat treatment (first heat treatment).
  • first heat treatment Excessive hydrogen (including water and hydroxyl group) in the oxide semiconductor layer 206a is removed by the first heat treatment and a structure of the oxide semiconductor is improved, so that defect level in energy gap of the oxide semiconductor layer 206a can be reduced.
  • the first heat treatment is performed for example, at a temperature 300 °C or higher and 750 °C or lower, preferably 400 °C or higher and 700 °C or lower.
  • the first heat treatment can be performed in such a way that, for example, the lower layer substrate 200 is introduced into an electric furnace using a resistance heating element or the like and heated, under a nitrogen atmosphere at 450 °C for an hour. During the first heat treatment, the oxide semiconductor layer 206a is not exposed to the air to prevent the entry of water and hydrogen.
  • a heat treatment apparatus is not necessary limited to an electrical furnace, and may include a device for heating an object to be processed by heat conduction or heat radiation given by a medium such as a heated gas or the like.
  • a rapid thermal anneal (RTA) apparatus such as a lamp rapid thermal anneal (LRTA) apparatus or a gas rapid thermal anneal (GRTA) apparatus can be used.
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus for heat treatment using a high-temperature gas.
  • the gas an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used.
  • GRTA treatment may be performed as follows.
  • the substrate is placed in an inert gas atmosphere which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and taken out from the inert gas atmosphere.
  • GRTA treatment enables high-temperature heat treatment for a short time.
  • the GRTA treatment can be employed even when the temperature exceeds the upper temperature limit of the substrate because the heat treatment can be achieved in a short time.
  • the inert gas may be switched to a gas including oxygen during the process. This is because defect level in energy gap due to oxygen deficiency can be reduced by performing the first heat treatment in an atmosphere including oxygen.
  • the inert gas atmosphere is preferably an atmosphere which contains nitrogen or a rare gas (such as helium, neon or argon) as its main component and does not contain water, hydrogen or the like.
  • nitrogen or a rare gas such as helium, neon or argon
  • the purity of nitrogen or a rare gas such as helium, neon or argon introduced into a heat treatment apparatus is 6N (99.9999 %) or more, preferably 7N (99.99999 %) or more (that is, the concentration of the impurities is 1 ppm or less, preferably 0.1 ppm or less).
  • impurities are reduced by the first heat treatment and an i-type or substantially i-type oxide semiconductor layer 206a is formed, so that a transistor having excellent characteristics can be realized.
  • the first heat treatment may be performed on the oxide semiconductor layer 206 which has not yet been processed into the island-shaped oxide semiconductor layer 206a. In that case, after the first heat treatment, the lower layer substrate 200 is taken out of the heating apparatus and subjected to a photolithography step.
  • the first heat treatment has an effect of removing hydrogen, water and the like and can be referred to as dehydration treatment, dehydrogenation treatment or the like.
  • the dehydration treatment or the dehydrogenation treatment can be performed after a source electrode and a drain electrode are stacked over the oxide semiconductor layer 206a. Further, such dehydration treatment or dehydrogenation treatment may be conducted once or plural times.
  • a conductive layer is formed to be in contact with the oxide semiconductor layer 206a.
  • the conductive layer is selectively etched, whereby a source or drain electrode 208a and a source or drain electrode 208b are formed (see FIG. 9B).
  • the step is the same as the step relating to the source or drain electrode 142a and the like.
  • the foregoing embodiment can be referred to for a detailed description.
  • a gate insulating layer 212 which is in contact with part of the oxide semiconductor layer 206a is formed (see FIG. 9C).
  • the description regarding the gate insulating layer 138 of the foregoing embodiment can be referred to for a detailed description.
  • the formed gate insulating layer 212 is desirably subjected to second heat treatment in an inert gas atmosphere or an oxygen atmosphere.
  • the second heat treatment is performed at a temperature 200 °C or higher and 450 °C or lower, preferably 250 °C or higher and 350 °C or lower.
  • the second heat treatment is performed at 250 °C for an hour in a nitrogen atmosphere.
  • the second heat treatment can reduce variation in electric characteristics of the transistor.
  • oxygen is supplied to the oxide semiconductor layer 206a and oxygen deficiency of the oxide semiconductor layer 206a is filled, whereby an i-type oxide semiconductor layer (an intrinsic semiconductor) or an oxide semiconductor layer which is extremely close to an i-type can be formed.
  • the second heat treatment is performed after the gate insulating layer 212 is formed; however, timing of the second heat treatment is not limited thereto.
  • a gate electrode 214 is formed in a region over the gate insulating layer 212 which overlaps with the oxide semiconductor layer 206a (see FIG 9D).
  • the gate electrode 214 can be formed after a conductive layer is formed over the gate insulating layer 212 and then selectively patterned.
  • the description regarding the gate electrode 136c and the gate electrode 145 of the foregoing embodiment can be referred to for a detailed description.
  • an interlayer insulating layer 216 and an interlayer insulating layer 218 are formed over the gate insulating layer 212 and the gate electrode 214 (see FIG. 9E).
  • the interlayer insulating layer 216 and the interlayer insulating layer 218 can be formed using a PVD method, a CVD method or the like.
  • a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide can be used for the interlayer insulating layer 216 and the interlayer insulating layer 218.
  • a stacked-layer structure of the interlayer insulating layer 216 and the interlayer insulating layer 218 is employed but the disclosed invention is not limited thereto.
  • a single-layer structure, a stacked layer structure of two layers may also be used.
  • the interlayer insulating layer 218 is desirably formed so as to have a planarized surface. This is because an electrode, a wiring or the like can be favorably formed over the interlayer insulating layer 218 by forming the interlayer insulating layer 218 to have a planarized surface.
  • the transistor 250 shown in FIG 9E includes the following components: the oxide semiconductor layer 206a provided over the lower layer substrate 200 with the insulating layer 202 interposed therebetween; the source or drain electrode 208a and the source or drain electrode 208b both of which are electrically connected to the oxide semiconductor layer 206a; the gate insulating layer 212 covering the oxide semiconductor layer 206a, the source or drain electrode 208a and the source or drain electrode 208b; the gate electrode 214 over the gate insulating layer 212; the interlayer insulating layer 216 over the gate insulating layer 212 and the gate electrode 214; and the interlayer insulating layer 218 over the interlayer insulating layer 216.
  • the hydrogen concentration of the transistor 250 shown in this embodiment is 5 x 10 19 atoms/cm 3 or less, preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 5 x 10 17 atoms/cm 3 or less.
  • the carrier density of the oxide semiconductor layer 206a (for example, less than 1 x 10 12 /cm 3 , preferably less than 1.45 x 10 10 /cm 3 ) is sufficiently less than that of general silicon wafer (approximately 1 x 10 14 /cm 3 ). Because of this, the off state current is sufficiently reduced.
  • the off state current (drain current of when a voltage between a gate and a source is 0 V or less) is 1 x 10 ⁇ 13 A or less.
  • an off state current density (the value obtained by dividing the off state current with the channel width) at a room temperature is 100 aA (1 aA (attoampere) is 10 A (ampere))
  • / ⁇ or less preferably 10 aA/ ⁇ or less, more preferably, 1 aA/ ⁇ or less.
  • off state resistance resistance value when the transistor is turned off
  • off state resistivity resistivity when the transistor is turned off
  • off state resistance R can be obtained by Ohm' s law using off state current and drain voltage.
  • the off state current of the transistor can be sufficiently reduced.
  • the disclosed invention is not necessarily construed as being limited thereto.
  • an oxide semiconductor can be used for all transistors including a transistor included in an integrated circuit by the electric characteristics being sufficiently increased. In such a case, the transistors do not need to be a stacked-layer structure as described in the foregoing embodiment.
  • field effect mobility ⁇ of a transistor including an oxide semiconductor is preferably ⁇ > 100 cm 2 /V-s in order to realize favorable circuit operation.
  • the semiconductor device can be formed using a glass substrate or the like.
  • a top-gate transistor is described as an example but a structure of the transistor is not necessary limited to a top-gate transistor.
  • an insulating layer 302 is formed over a lower layer substrate 300.
  • a first oxide semiconductor layer is formed over the insulating layer 302 and first heat treatment is performed to crystallize at least a region including a surface of the first oxide semiconductor layer, so that a first oxide semiconductor layer 304 is formed (see FIG 1 OA).
  • the lower layer substrate 300 can be a structure body in a portion lower than the interlayer insulating layer 128 in the semiconductor device of the foregoing embodiment (the semiconductor device shown in FIG. 2A and the like).
  • the foregoing embodiment can be referred to for the details.
  • the insulating layer 302 functions as a base and is formed in the same manner as the insulating layer 138, the protective insulating layer 144 or the like in the foregoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • the insulating layer 302 is preferably formed containing as little hydrogen or water as possible.
  • the first oxide semiconductor layer 304 can be formed in the same manner as the oxide semiconductor layer 206 in the foregoing embodiment.
  • the foregoing embodiment may be referred to for the details of the first oxide semiconductor layer 304 and the film formation method thereof.
  • the first oxide semiconductor layer 304 is intentionally crystallized by the first heat treatment; thus, a target for film formation of an oxide semiconductor which can be easily crystallized is preferably used to form the first oxide semiconductor layer 304.
  • the thickness of the first oxide semiconductor layer 304 is preferably 3 nm or more and 15 nm or less.
  • the first oxide semiconductor layer 304 has a thickness of 5 nm as an example. Note that an appropriate thickness differs depending on an oxide semiconductor material to be applied, the intended use of the semiconductor device or the like, and thus the thickness is set as appropriate depending on the material to be used, the intended use or the like.
  • the first heat treatment is performed at a temperature of 450 °C or higher and 850 °C or lower, preferably 550 °C or higher and 750 °C or lower.
  • the heat treatment is preferably performed for one minute or more and 24 hours or less.
  • the atmosphere of the first heat treatment is preferably an atmosphere in which hydrogen, water and the like are not included.
  • the atmosphere can be a nitrogen atmosphere, an oxygen atmosphere, an atmosphere of a rare gas (such as helium, neon, and argon) or the like from which water is sufficiently removed.
  • a device for heating an object to be processed by heat conduction or heat radiation given by a medium such as a heated gas or the like can be used besides an electrical furnace.
  • a rapid thermal anneal (RTA) apparatus such as a lamp rapid thermal anneal (LRTA) apparatus or a gas rapid thermal anneal (GRTA) apparatus can be used.
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus for heat treatment using a high-temperature gas.
  • the gas an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon is used.
  • At least the region including the surface of the first oxide semiconductor layer 304 is crystallized by the first heat treatment.
  • the crystal grows from the surface of the first oxide semiconductor layer 304 to the inside of the first oxide semiconductor layer 304, whereby the crystal region is formed.
  • the crystal region contains a plate-like crystal whose average thickness is 2 nm or more and 10 nm or less, in some cases.
  • the crystal region contains a crystal whose c-axis is aligned a direction perpendicular to the surface of the oxide semiconductor layer, in some cases.
  • the first heat treatment may be performed in an atmosphere such as a nitrogen atmosphere, an oxygen atmosphere and an atmosphere of a rare gas (such as helium, neon and argon) with a purity of 6N (99.9999 %) or more (that is, the concentration of the impurities is 1 ppm or less). More preferably, an atmosphere with a purity of 7N (99.99999 %) or more (that is, the concentration of the impurities is 0.1 ppm or less) may be used. Furthermore, the first heat treatment may be performed in ultra-dry air with an H 2 0 concentration of 20 ppm or lower, preferably 1 ppm or lower.
  • oxygen be supplied to the first oxide semiconductor layer 304 while the crystal region be formed by the first heat treatment.
  • oxygen can be supplied to the first oxide semiconductor layer 304 by changing the atmosphere of the heat treatment to an oxygen atmosphere or the like.
  • a heat treatment is performed at 700 °C for an hour under a nitrogen atmosphere as the first heat treatment and hydrogen and the like are removed from the oxide semiconductor layer.
  • oxygen is supplied to inside of the first oxide semiconductor layer 304 by changing the atmosphere to an oxygen atmosphere.
  • a main object of the first heat treatment is a formation of the crystal region, so that another treatment whose object is removal of hydrogen and the like and supply of oxygen can be additionally performed.
  • a heat treatment for crystallization can be performed after a heat treatment for removing hydrogen and the like and treatment for supplying oxygen are performed.
  • the first oxide semiconductor layer 304 which has the crystal region and from which hydrogen (including water and hydroxyl group) and the like are removed and to which oxygen is supplied can be obtained by such first heat treatment.
  • the second oxide semiconductor layer 306 is formed over the first oxide semiconductor layer 304 having the crystal region at least in the region including the surface (see, FIG 10B).
  • the second oxide semiconductor layer 306 can be formed in the same manner as the oxide semiconductor layer 206 in the foregoing embodiment.
  • the foregoing embodiment may be referred to for the details of the second oxide semiconductor layer 306 and the film formation method thereof.
  • the second oxide semiconductor layer 306 is preferably formed to have a thickness larger than that of the first oxide semiconductor layer 304. Further, it is preferable that the second oxide semiconductor layer 306 be formed so that the sum of the thicknesses of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is 3 nm or more and 50 nm or less. Note that an appropriate thickness differs depending on an oxide semiconductor material, the intended use or the like, and thus the thickness is set as appropriate depending on the material, the intended use or the like.
  • a material having the same main component as that of the first oxide semiconductor layer 304 for example, a material whose lattice constant after crystallization is close to that of the first oxide semiconductor layer 304 (lattice mismatch is 1 % or less) is preferably used. This is because, in the case where the material having the same main component is used, a crystal can be easily grown in crystallization of the second oxide semiconductor layer 306 by using the crystal region of the first oxide semiconductor layer 304 as a seed. Moreover, in the case where the material having the same main component is used, physical properties of an interface and electrical characteristics between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are favorable.
  • a material having a different main component may be used to form the second oxide semiconductor layer 306.
  • a second heat treatment is performed to the second oxide semiconductor layer 306, so that the crystal is grown by using the crystal region of the first oxide semiconductor layer 304 as a seed to form a second oxide semiconductor layer 306a (see FIG IOC).
  • the temperature of the second heat treatment is 450 °C or higher and 850 °C or lower, preferably 600 °C or higher and 700 °C or lower.
  • the second heat treatment is performed for one minute or more and 100 hours or less, preferably 5 hours or more and 20 hours or less and typically, for 10 hours. Note that it is preferable that also in the second heat treatment, hydrogen, water and the like be not contained in the treatment atmosphere.
  • a heat treatment apparatus which can be used is the same as that of the first heat treatment.
  • an atmosphere inside a furnace is set to a nitrogen atmosphere and at the time of performing cooling, the atmosphere of the furnace is set to an oxygen atmosphere. Consequently, hydrogen and the like can be removed under a nitrogen atmosphere and oxygen can be supplied under an oxygen atmosphere.
  • the second heat treatment as described the above is performed, whereby the crystal is grown from the crystal region formed in the first oxide semiconductor layer 304 to the whole area of the second oxide semiconductor layer 306; thus, the second oxide semiconductor layer 306a can be formed. Further, the second oxide semiconductor layer 306a from which hydrogen (including water and hydroxyl group) is removed and to which oxygen is supplied can be formed. Furthermore, orientation of the crystal region of the first oxide semiconductor layer 304 can be increased by performing second heat treatment.
  • InGa0 3 (ZnO) OT m > 0 and m is not a natural number
  • Such crystals are aligned so that its c-axis is perpendicular to a surface of a second oxide semiconductor layer 306b by the second heat treatment.
  • the crystals include any of In, Ga and Zn, and can be considered to have a stacked-layer structure of layers parallel to a-axis and b-axis. Specifically, the crystals have a structure in which a layer containing In and a layer which does not containing In (a layer containing Ga or Zn) are stacked in a direction of c-axis.
  • conductivity in a direction parallel to a-axis and b-axis of a layer containing In is favorable. This is due to the fact that electrical conductivity is mainly controlled by In in an In-Ga-Zn-O-based oxide semiconductor crystal and the fact that the 5 s orbital of one In atom overlaps with the 5s orbital of an adjacent In atom and thereby a carrier path is formed.
  • the crystal grows from the crystal region formed at the surface of the first oxide semiconductor layer 304 toward a bottom portion of the first oxide semiconductor layer 304 by the second heat treatment, whereby the amorphous region is crystallized in some cases.
  • the amorphous region remains in some cases depending on a material included in the insulating layer 302, a condition of the second heat treatment or the like.
  • the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a have the same crystal structure in some cases, as shown in FIG IOC. Therefore, although boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a is indicated by a dotted line in FIG IOC, the boundary cannot be found, therefore the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a can be regarded as the same layer in some cases.
  • the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a are processed by a method such as an etching using a mask, so that an island-shaped first oxide semiconductor layer 304a and an island-shaped second oxide semiconductor layer 306b are formed (see FIG. 10D).
  • the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a either dry etching or wet etching may be used. Needless to say, a combination of dry etching and wet etching may be employed.
  • the etching conditions an etching gas, etching solution, etching time, temperature or the like
  • the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306a can be performed in the same manner as the etching of the semiconductor layer in the foregoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • a region to be a channel formation region preferably has a flat surface.
  • a difference in height of the surface of the second oxide semiconductor layer 306b is preferably 1 nm or less (more preferably, 0.2 nm or less).
  • a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306b.
  • the conductive layer is selectively etched, whereby a source or drain electrode 308a and a source or drain electrode 308b are formed (see, FIG 10D).
  • the source or drain electrodes 308a and 308b can be formed in the same manner as that of the source or drain electrodes 142a and 142b in the foregoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • a crystal layer contacting with the source or drain electrode 308a and the source or drain electrode 308b becomes an amorphous state at the side surface of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306b. Therefore, the whole region of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306b does not always have a crystal structure.
  • a gate insulating layer 312 contacting with part of the second oxide semiconductor layer 306b is formed.
  • the gate insulating layer 312 can be formed using a CVD method, sputtering method or the like.
  • a gate electrode 314 is formed in a region over the gate insulating layer 312 which overlaps with the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306b.
  • An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed over the gate insulating layer 312 and the gate electrode 314 (see FIG 10E).
  • the gate insulating layer 312, the gate electrode 314 and the interlayer insulating layers 316 and 318 can be formed in the same manner as the gate insulating layer 138, the gate electrode 136c, the gate electrode 145 and the interlayer insulating layers 216 and 218 in the forgoing embodiment.
  • the foregoing embodiment may be referred to for a detailed description.
  • the formed gate insulating layer 312 is desirably subjected to third heat treatment in an inert gas atmosphere or an oxygen atmosphere.
  • the third heat treatment is performed at a temperature 200 °C or higher and 450 °C or lower, preferably 250 °C or higher and 350 °C or lower.
  • the heat treatment is performed at 250 °C for an hour in an atmosphere containing oxygen.
  • the third heat treatment can reduce variation in electric characteristics of the transistor.
  • the gate insulating layer 312 contains oxygen
  • oxygen is supplied to the second oxide semiconductor layer 306b and oxygen deficiency of the second oxide semiconductor layer 306b is filled, whereby an i-type (an intrinsic semiconductor) oxide semiconductor layer or an oxide semiconductor layer which is extremely close to an i-type can be formed.
  • the third heat treatment is performed after the gate insulating layer 312 is formed; however, timing of the third heat treatment is not limited thereto.
  • the third heat treatment may be omitted.
  • the transistor 350 shown in FIG. 10E includes the following components: the first oxide semiconductor layer 304a provided over the lower layer substrate 300 with the insulating layer 302 interposed therebetween; the second oxide semiconductor layer 306b provided over the first oxide semiconductor layer 304a; the source or drain electrode 308a and the source or drain electrode 308b are electrically connected to the second oxide semiconductor layer 306b; the gate insulating layer 312 covering the second oxide semiconductor layer 306b, the source or drain electrode 308a and the source or drain electrode 308b; the gate electrode 314 over the gate insulating layer 312; the interlayer insulating layer 316 over the gate insulating layer 312 and the gate electrode 314; and the interlayer insulating layer 318 over the interlayer insulating layer 316.
  • the hydrogen concentration is 5 x 10 19 atoms/cm 3 or less, preferably 5 x 10 18 atoms/cm 3 or less, and more preferably 5 x 10 17 atoms/cm 3 or less.
  • the carrier density of the oxide semiconductor layer 206a (for example, less than 1 x 10 /cm 3 , preferably less than 1.45 x 10 10 /cm 3 ) is sufficiently less than that of general silicon wafer (approximately 1 x 10 14 /cm 3 ). Because of this, the off state current is sufficiently reduced.
  • the off state current (drain current of when a voltage between a gate and a source is 0 V or less) is 1 x 10 "13 A or less.
  • an off state current density (the value obtained by dividing the off state current with the channel width) at a room temperature is 100 aA (1 aA (attoampere) is 10 — 18 A (ampere))
  • / ⁇ or less preferably 10 aA/ ⁇ or less, more preferably, 1 aA/ ⁇ or less.
  • off state resistance resistance value when the transistor is turned off
  • off state resistivity resistivity when the transistor is turned off
  • off state resistance R can be obtained by Ohm' s law using off state current and drain voltage.
  • the off state current of the transistor can be sufficiently reduced.
  • the first oxide semiconductor layer 304a including the crystal region and the second oxide semiconductor layer 306b obtained by crystal growth from the crystal region of the first oxide semiconductor layer 304a are used as an oxide semiconductor layer, whereby field effect mobility can be increased and a transistor having favorable electric characteristics can be realized.
  • the transistor 350 is used instead of the transistor
  • the transistor 350 shown in this embodiment uses the first oxide semiconductor layer 304a including the crystal region and the second oxide semiconductor layer 306b obtained by crystal growth from the crystal region of the first oxide semiconductor layer 304a, so that the transistor 350 has favorable field effect mobility. Therefore, an oxide semiconductor can be used for all transistors including a transistor included in an integrated circuit. In such a case, the transistor does not need to be a stacked-layer structure as described in the foregoing embodiment.
  • field effect mobility ⁇ of a transistor including an oxide semiconductor is preferably ⁇ > 100 cm /V-s in order to realize favorable circuit operation.
  • the semiconductor device can be formed using a glass substrate or the like.
  • the case where the semiconductor device described in the above embodiments is applied to electronic appliances is described with reference to FIGS. 11 A to 1 IF.
  • the case where the above described semiconductor device is applied to electronic appliances such as a computer, a mobile phone set (also referred to as a mobile phone or a mobile phone device), a personal digital assistant (including a portable game machine, an audio reproducing device and the like), a digital camera, a digital video camera, electronic paper, a television set (also referred to as a television or a television receiver) and the like is described.
  • FIG. 11 A shows a notebook personal computer including a housing 401, a housing 402, a display portion 403, a keyboard 404 and the like.
  • the semiconductor device shown in the foregoing embodiment is provided in the housing 401 and the housing 402.
  • a notebook PC with sufficiently low power consumption can be realized.
  • FIG. 11B shows a personal digital assistant (PDA) including a main body 411 provided with a display portion 413, an external interface 415, operation button 414 and the like.
  • a stylus 412 and the like operating the personal digital assistant are also provided.
  • the semiconductor device shown in the foregoing embodiment is provided in the main body 411. Therefore, a personal digital assistant with sufficiently low power consumption can be realized.
  • FIG llC shows an e-book reader 420 with electronic paper attached including two housings 421 and 423.
  • the housings 421 and 423 are connected by a hinge portion 437 and can be opened or closed with the hinge portion 437. With such a structure, the e-book reader can be handled like a paper book.
  • the housing 421 is provided with a power switch 431, operation keys 433, a speaker 435 and the like.
  • the semiconductor device shown in the foregoing embodiment is provided at least in one of the housings 421 and 423. Therefore, an e-book reader with sufficiently low power consumption can be realized.
  • FIG. 11D is a mobile phone set including two housings 440 and 441. Moreover, the housings 440 and 441 which are shown unfolded in FIG. 1 ID can overlap with each other by sliding. Thus, the mobile phone can be in a suitable size for portable use.
  • the housing 441 includes a display panel 442, a speaker 443, a microphone 444, a pointing device 446, a camera lens 447, an external connection terminal 448 and the like.
  • the housing 440 is provided with a solar cell 449 for charging the mobile phone, an external memory slot 450 and the like.
  • an antenna is incorporated in the housing 441.
  • the semiconductor device shown in the foregoing embodiment is provided at least in one of the housings 440 and 441. Thus, a mobile phone set with sufficiently low power consumption can be realized.
  • FIG. HE is a digital camera including a main body 461, a display portion 467, an eyepiece portion 463, an operation switch 464, a display portion 465, a battery 466 and the like.
  • the semiconductor device shown in the foregoing embodiment is provided in the main body 461. Therefore, a digital camera with sufficiently low power consumption can be realized.
  • FIG 1 IF is a television set 470 including a housing 471, a display portion 473, a stand 475 and the like.
  • the television set 470 can be operated by an operation switch of the housing 471 and a separate remote controller 480.
  • the semiconductor device shown in the foregoing embodiment is mounted in the housing 471 and the separate remote controller 480.
  • a television set with sufficiently low power consumption can be realized.
  • an integrated circuit related to the foregoing embodiment is mounted in the electronic appliances shown in this embodiment. Therefore, an electronic appliance whose standby power is sufficiently reduced and power consumption is sufficiently reduced can be realized.

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JP2017085185A (ja) 2017-05-18
KR102046308B1 (ko) 2019-11-19
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TW201138026A (en) 2011-11-01
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CN102656683A (zh) 2012-09-05
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