WO2005029581A1 - インターポーザ、多層プリント配線板 - Google Patents
インターポーザ、多層プリント配線板 Download PDFInfo
- Publication number
- WO2005029581A1 WO2005029581A1 PCT/JP2004/013831 JP2004013831W WO2005029581A1 WO 2005029581 A1 WO2005029581 A1 WO 2005029581A1 JP 2004013831 W JP2004013831 W JP 2004013831W WO 2005029581 A1 WO2005029581 A1 WO 2005029581A1
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- WO
- WIPO (PCT)
- Prior art keywords
- interposer
- thickness
- substrate
- hole
- young
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- 239000000758 substrate Substances 0.000 claims abstract description 195
- 239000011347 resin Substances 0.000 claims description 75
- 229920005989 resin Polymers 0.000 claims description 75
- 239000004020 conductor Substances 0.000 claims description 70
- 239000000463 material Substances 0.000 claims description 62
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 84
- 239000002585 base Substances 0.000 description 53
- 239000007858 starting material Substances 0.000 description 45
- 239000011521 glass Substances 0.000 description 27
- 230000035882 stress Effects 0.000 description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 25
- 238000007747 plating Methods 0.000 description 25
- 238000011049 filling Methods 0.000 description 23
- 239000011162 core material Substances 0.000 description 20
- 230000000052 comparative effect Effects 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 15
- 238000005498 polishing Methods 0.000 description 13
- 238000005488 sandblasting Methods 0.000 description 13
- 239000006258 conductive agent Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000012360 testing method Methods 0.000 description 12
- 239000000919 ceramic Substances 0.000 description 10
- 239000011889 copper foil Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 238000005259 measurement Methods 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 238000013001 point bending Methods 0.000 description 8
- 238000005245 sintering Methods 0.000 description 8
- 239000000565 sealant Substances 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 239000004576 sand Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- 229920002799 BoPET Polymers 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 238000010304 firing Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 241000287127 Passeridae Species 0.000 description 3
- 229920005822 acrylic binder Polymers 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 3
- 229910000365 copper sulfate Inorganic materials 0.000 description 3
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000000704 physical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 2
- 229930185605 Bisphenol Natural products 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 2
- 239000002202 Polyethylene glycol Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 229910052878 cordierite Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 229910052839 forsterite Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 244000062645 predators Species 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- NLJMYIDDQXHKNR-UHFFFAOYSA-K sodium citrate Chemical compound O.O.[Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O NLJMYIDDQXHKNR-UHFFFAOYSA-K 0.000 description 2
- 239000001509 sodium citrate Substances 0.000 description 2
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 2
- 238000003756 stirring Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910001374 Invar Inorganic materials 0.000 description 1
- 240000008415 Lactuca sativa Species 0.000 description 1
- 235000003228 Lactuca sativa Nutrition 0.000 description 1
- 244000061456 Solanum tuberosum Species 0.000 description 1
- 235000002595 Solanum tuberosum Nutrition 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 238000001354 calcination Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- NNFCIKHAZHQZJG-UHFFFAOYSA-N potassium cyanide Chemical compound [K+].N#[C-] NNFCIKHAZHQZJG-UHFFFAOYSA-N 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 159000000000 sodium salts Chemical class 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- FAKFSJNVVCGEEI-UHFFFAOYSA-J tin(4+);disulfate Chemical compound [Sn+4].[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O FAKFSJNVVCGEEI-UHFFFAOYSA-J 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Definitions
- the present invention relates to an interposer and a multilayer printed wiring board, and more particularly to an interposer interposed between a package substrate made of a resin and an IC chip that also has a ceramic force, and an interposer for connecting an Ic chip.
- the present invention relates to a multilayer printed wiring board having:
- a package substrate is used to connect a fine-pitch IC chip to an external substrate such as a daughter board.
- Ceramic or resin is used as a material for the knockout substrate.
- the resistance value is high, and it is difficult to mount a high-frequency, high-performance IC with a high dielectric constant of ceramic.
- resin package boards can use copper wiring by plating, so wiring resistance can be reduced, and the resin has a low dielectric constant, making it relatively easy to mount high-frequency, high-performance ICs. It is.
- Patent Document 2 JP-A-2002-373962
- Patent Document 3 JP-A-2002-261204
- Patent document 4 JP-A-2000-332168
- the present invention has been made to solve the above-described problems, and an object of the present invention is to prevent the occurrence of cracks due to thermal expansion and thermal shrinkage, and to provide electronic components such as IC chips.
- An object of the present invention is to provide an interposer capable of supplying electricity stably to a multi-layer printed wiring board including the interposer.
- the inventors of the present invention have conducted intensive studies for realizing the above object, and as a result, have found an idea that an interposer for electrically connecting a package substrate made of resin and an IC chip having ceramic power is interposed. .
- the package substrate refers to a resin package substrate in which an interlayer insulating layer and a conductive circuit are laminated on one or both sides of a core substrate described later.
- the interposer by interposing an interposer having a Young's modulus in the above range between the IC and the resin package substrate, the interposer can be operated even if the resin package has a larger deformation amount than the IC deformation amount. Since it is difficult to deform, thermal stress caused by the difference in thermal expansion between the IC and the resin package is transmitted to the resin layer of the IC. Therefore, it is effective to interpose a high Young's modulus interposer between the IC and the package substrate in order to prevent the destruction of the resin of the IC.
- the Young's modulus of the insulating base material that composes the interposer is less than 55 GPa, the Young's modulus is low, so even if the interposer is interposed between the package substrate and the IC chip, the amount of deformation of the interposer increases, and the IC wiring The stress reaches the resin in the layer. On the other hand, if it exceeds 440 GPa, stress concentrates on the solder bumps between the interposer and the package substrate, which causes cracks and disconnections.
- the interposer has a structure in which the external electrodes of the IC and the connection pads of the resin package substrate are electrically connected by straight through-hole conductors.
- the through-hole conductor is formed of a conductive material having a lower Young's modulus than the insulating base material forming the interposer. For this reason, the insulating base material constituting the interposer has different Young's modulus and thermal expansion coefficient immediately below the IC and at a portion other than immediately below the IC. Therefore, the insulating base material constituting the interposer is likely to be warped starting immediately below the periphery of the IC.
- the amount of warpage also depends on the thickness, even if the Young's modulus of the insulating base material forming the interposer is within the range of 55 to 440 GPa, the thickness of the insulating base material forming the interposer is reduced.
- the substrate thickness is less than XO.05, the thickness is small, so that the amount of deformation and warpage increases.
- the IC receives a pulling force or a bending force in the outward direction, and cracks and disconnections occur in the resin of the IC wiring layer.
- the Young's modulus of the insulating base material that composes the interposer is in the range of 55 to 440 GPa, and the thickness exceeds the resin package substrate thickness X O.05 or more, the insulation material that composes the interposer becomes thicker.
- the rigid substrate has increased rigidity. Therefore, deformation and warpage caused by the difference in physical properties between the portion immediately below the IC and the other portion of the insulating base material constituting the interposer are reduced. Therefore, the amount of deformation and warping together with the IC force S interposer is reduced, so that cracks and disconnections do not occur in the resin of the wiring layer of the IC.
- the thickness of the insulating material constituting the interposer is equal to or greater than the thickness of the core of the knockout substrate X 0.08 or more. This is because the core / cage substrate is mainly used for the die / cage substrate, and the deformation of the knockage substrate depends on the core substrate.
- the interposer does not warp. For this reason, the stress caused by the difference in the thermal expansion coefficient between the IC and the interposer concentrates in the XY direction without relaxing in the Z direction (where the XY direction is This means a direction parallel to the surface), and cracks and disconnections occur in the resin of the wiring layer of the IC. Further, since the entire semiconductor device becomes thick, it cannot meet the demand for thinning. As another reason, when the insulating base material is thick, it is difficult to form a small-diameter through-hole, which is not suitable for fine shading.
- the material of the insulating base material constituting the interposer is not particularly limited as long as the Young's modulus is 55 to 440 GPa, and examples thereof include Pyrex (registered trademark) glass and SF glass.
- Glass substrate such as stainless steel, BK7 glass, MGF glass, zirconia, aluminum nitride, nitride
- Silicone substrate such as silicon, silicon carbide, alumina, mullite, cordierite, steatite, LTCC substrate (low-temperature firing ceramic substrate), and forsterite, resin, epoxy resin, polyimide resin, phenol resin, and BT.
- a fired ceramic substrate or a glass substrate as a starting material of the interposer. Since there is no high-temperature treatment that causes shrinkage or dimensional change after the formation of the through-hole, the positional accuracy of the through-hole can be improved.
- a ceramic substrate containing a glass component such as Nirex (registered trademark) glass, mullite, cordierite, steatite, forsterite, or the like is used for the interposer, the dielectric constant is low, which is advantageous when transmitting a high-speed signal. .
- a solder material used for a joint between an electronic component such as an IC and an interposer and between an interposer and a package is not particularly limited.
- the size of the insulating base material forming the interposer preferably has the following relationship.
- the area of the insulating base material constituting the interposer is smaller than the projected area of the electronic component, This is because electronic components cannot be mounted on the interposer. If the area of the insulating base material that composes the interposer exceeds the projected area of the electronic component X 1.2 or more, a step is created between the interposer and the electronic component, so it is possible to fill the mold resin between them. It becomes. The mold resin can also relieve the stress, further extending the life of the joint and the electronic component against thermal shock. If the area of the insulating base material that composes the interposer is less than 0.8 times the projected area of the knock package substrate, a step will be created between the interposer and the package body. Can be.
- the reliability of the semiconductor device as a whole against thermal shock is improved. If the size of the insulating base material constituting the interposer exceeds the projected area of the package substrate, the entire substrate becomes large, and the demand for miniaturization cannot be met. When the interposer is large, the amount of deformation increases with temperature change, so that the insulating star of the IC is easily broken.
- the insulating base material constituting the interposer has a Young's modulus of 55 to 440 GPa, and the thickness thereof is 0.05 to 1.5 times the package substrate thickness. It has a through-hole with a through-hole conductor that electrically connects the back, and the arrangement of the through-holes connected to the power and ground terminals of the IC must be in a grid or staggered arrangement. preferable.
- the pitch is preferably 60-250 m force S. It is more preferably 180 m or less.
- the through-hole may be filled with a conductive substance, or a structure in which the through-hole is covered with plating or the like and an unfilled portion is filled with an insulating agent or a conductive substance.
- the conductive substance to be filled in the through-hole is not particularly limited, but is, for example, a single metal such as copper, gold, silver, and nickel, or a metal having two or more forces, rather than a conductive paste or a metal paste. It is preferably filled with. This is because the resistance is lower than that of the conductive paste, so that the power supply to the IC becomes smoother and the calorific value decreases. Another reason is that since the through holes are completely filled with metal, stress can be absorbed by plastic deformation of the metal.
- the through-hole conductor connected to the power supply terminal of the IC it is preferable to arrange the through-hole conductor connected to the ground terminal of the IC at an adjacent position. It is preferable that a through-hole conductor connected to the ground terminal of the IC has a through-hole conductor connected to the power supply terminal of the IC at an adjacent position.
- the pitch between the through holes is preferably 250 m or less is also the force that reduces the diameter of the through holes when trying to reduce the pitch of the through holes.
- the diameter is preferably 30 to 150 / zm or less. If it is less than 30 / zm, the strength of the conductive material in the through hole will be lost, and the conductive material will be damaged by fatigue.
- the diameter of the through-hole becomes 125 / zm or less, it is effective to connect the power supply terminal and the ground terminal of the IC and arrange the through-holes in a staggered or lattice-like manner. This is because the conductor resistance increases, and the amount of heat generated in the through holes connected to the power and ground terminals of the IC increases. If the arrangement of the through-holes is lattice-like or staggered, they are evenly arranged.
- the temperature distribution of the interposer at the time of use becomes uniform, so that stress is not concentrated at a specific location, and the insulating layer of the IC chip is not damaged. Further, since the through-holes are formed uniformly, the physical properties (thermal expansion coefficient, Young's modulus, etc.) of the insulating base material immediately below the IC chip become similar.
- the opening diameter of at least one end face of the interposer is larger than the hole diameter at the center of the through hole. Further, it is preferable that the opening diameter of both end surfaces is larger than the opening diameter of the central portion.
- the minimum diameter of the opening diameter Z through hole at one end face exceeds 5
- the land diameter increases or the opening diameter at the center decreases.
- the strength toward the fine dagger and the interposer become large.
- the stress increases accordingly, and the insulating layer of the IC is easily broken.
- the conductive material is easily broken at the portion having the smallest diameter.
- the reason why the diameter of the opening at the one end face is larger than the diameter of the hole at the center of the through hole is to reduce the number of laser shots, for example, as compared with the case where the opening is straight.
- the conductor layers 34P and 34E of the surface layer of the core substrate 30 are formed to have a thickness of 5 to 35 ⁇ m, and the inner conductor layers 16P and 16E are formed to have a thickness of 5 to 250 m.
- the conductor circuit 42 on the resin insulation layer 40 and the conductor circuit 52 on the interlayer resin insulation layer 50 are formed to have a length of 5 to 25 m.
- the resin package substrate used in the present embodiment includes a power supply layer (conductor layer) 34P, a conductor layer 34, an inner power supply layer (conductor layer) 16P, a conductor layer 16E, and a metal plate of the surface layer of the core substrate 30. 12 was thickened. This increases the strength of the core substrate. Therefore, even if the core substrate itself is thinned The warpage and the generated stress can be reduced by the substrate itself.
- FIG. 5A shows an example of a partial plan view of the interposer 70.
- a part of a through hole connected to a power supply terminal and a dull terminal of the IC is shown.
- the lands 74 (through holes 81) of the interposer are arranged in a lattice pattern, and the pitch P1 is set to, for example, 175 m.
- FIG. 5B shows a plan view of an interposer according to another example.
- the lands 74 (through holes 81) of the interposer are arranged in a staggered manner, and the pitch P2 is set to, for example, 120 m.
- “+” Is a through hole connected to the power terminal of the IC
- “ ⁇ ” is a through hole connected to the ground terminal of the IC.
- the interposer 70 since the interposer 70 is interposed to join the IC chip 110 and the package substrate 10, stress is applied to the joint (solder 114) between the IC chip 110 and the interposer 70 and the interposer 110. And the package board 10 (signal bumps 64S, power supply bumps 64P, ground bumps 64E). Further, by interposing the interposer 70 having a Young's modulus of 55 GPa and a package substrate thickness of 0.05, the stress due to the difference in thermal expansion between the ceramic IC chip 110 and the resin package substrate 10 is reduced. The interposer 70 does not transmit the stress to the resin of the wiring layer of the IC chip 110 by receiving it. As a result, cracks and disconnections do not occur in the resin of the wiring layer of the IC chip.
- the manufacturing process of the interposer of the first embodiment will be described with reference to FIG. (1) 100 parts by weight of bisphenol A-type epoxy resin, 5 parts by weight of imidazole-type curing agent and 60 parts by weight of alumina filament are mixed, and the resin is impregnated into a glass cloth, dried and dried.
- a cured single-sided copper-clad laminate 80A obtained by laminating a pre-predator 80 and a copper foil 78 and pressing the laminate under heat and pressure is used (FIG. 6 (A)).
- the thickness of the insulating base material 80 is 50 ⁇ m
- the thickness of the copper foil 78 is 12 ⁇ m.
- the Young's modulus of the insulating substrate constituting the interposer was 55 GPa as measured by a three-point bending method according to JIS. In addition, a 1 mm thick insulating base material was used for the measurement of the Young's modulus.
- Example 2 carbon dioxide laser irradiation is performed from the insulating material side under the conditions shown in Table 1 to form a through-hole forming opening 81 that penetrates the insulating base material 80 and reaches the copper foil 78. Then, the inside of the opening 81 was subjected to desmear treatment by ultraviolet laser irradiation (FIG. 6 (B)).
- a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Mitsubishi Electric was used to form an opening for forming a via hole, and a glass cloth epoxy resin base material having a base material thickness of 50 m was used.
- the insulating material side was irradiated with a laser beam by a mask image method to form an opening for forming a via hole of 125 m at a speed of 100 holes / sec.
- the arrangement was made at a pitch of 180 m at a position corresponding to the external electrodes of the IC in a 1: 1 ratio.
- the power and ground terminals of the IC are in a grid.
- a desmear treatment was performed.
- the UV laser irradiation device using YAG 3rd harmonic for desmear processing uses GT605LDX manufactured by Mitsubishi Electric Corporation.
- the laser irradiation conditions for the desmear processing are a transmission frequency of 5 KHz and a pulse energy of 0. 8iuJ and 10 shots.
- an electroless nickel plating solution having a pH of 5 consisting of 30 gZl of nickel salt, 10 gZl of sodium hypophosphite, and 10 g of sodium citrate was applied on the copper plating 84 for 20 minutes.
- a nickel plating layer 86 of 5 / zm was formed.
- the substrate is immersed in an electroless plating solution composed of 2 g Zl of potassium cyanide, 75 g of sodium salt, 50 g of sodium citrate, and 10 g of sodium hypophosphite at 93 ° C. for 23 seconds.
- a gold plating layer 87 having a thickness of 0.03 m was formed on the nickel plating layer.
- the interposer of the second embodiment differs from the first embodiment in that the substrate thickness of the starting material is 64 m. did. Accordingly, the laser conditions for forming the through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Other than that
- the substrate thickness of the starting material in the first embodiment was 1500 m. Accordingly, the laser conditions for forming the through holes were changed to the conditions shown in the table below. The time required for filling the through holes with the conductive agent was changed according to the thickness of the substrate. Other than that is the same as Example 1.
- a method of manufacturing the interposer according to the seventh embodiment will be described with reference to FIGS. (1)
- a fired zirconia substrate (manufactured by Nippon Fine Ceramics Co., Ltd.) 80B having a size of 32 mm X 32 mm X thickness 50 ⁇ m was used as a starting material (FIG. 7A).
- the Young's modulus of the insulating substrate was 200 GPa when measured by a three-point bending method according to JIS. For the measurement of the Young's modulus, an insulating substrate having a thickness of 1 mm was used.
- a urethane-based resist 79 was attached to one surface of the substrate 80B, and an opening 8 la having a diameter of 125 / zm was formed at a position corresponding to the external electrode of the IC by a normal photographic method (FIG. 7 (B)). .
- the chromium and nickel coatings are represented as coatings 82) were deposited (FIG. 7 (D)).
- the PET film 85 was peeled off, a dry film was adhered to the electrolytic copper 84 under the PET film 85, and after exposure and development, the electrolytic copper plating layer and the electroless copper plating layer were alkali-etched.
- the lands 76P, 76S and 76E were formed by etching with a chilling liquid (Fig. 8 (D)).
- Example 8 differs from Example 7 in that the substrate thickness of the starting material is 64 m. did. Accordingly, the sandblasting conditions for forming the through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Otherwise, the configuration is the same as that of the seventh embodiment.
- the substrate thickness of the starting material in the seventh embodiment was set to 100 m. Accordingly, the sandblasting conditions for forming the through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Otherwise, the configuration is the same as that of the seventh embodiment.
- the substrate thickness of the starting material in the seventh embodiment was 400 m. Accordingly, the conditions for sandblasting for forming through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Otherwise, the configuration is the same as that of the seventh embodiment.
- the substrate thickness of the starting material in the seventh embodiment was set to 1000 / zm. Accordingly, the conditions for sandblasting to form through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Otherwise, it is the same as Example 7.
- the substrate thickness of the starting material in the seventh embodiment was set to 1500 / zm. Accordingly, the conditions for sandblasting to form through holes were changed to the conditions shown in the table below. The time required for filling the through hole with the conductive agent was changed according to the thickness of the substrate. Otherwise, it is the same as Example 7.
- Example 13 The green sheet thickness in (b) was changed to 67-72 ⁇ m, and then the step (c) was performed to obtain a SiC substrate having a thickness of 64 ⁇ m.
- Example 8 the starting material was changed to the one prepared in (1) above. Otherwise, it is the same as Example 8.
- Example 13 The green sheet thickness in (b) was changed to 103-113 m, and then the process (c) was performed. A 100 m thick SiC substrate was obtained.
- Example 13 The thickness of the green sheet in (b) was changed to 1030 to 1150 ⁇ m, and then the step (c) was performed to obtain a 1000 m thick SiC substrate.
- the interposer of the nineteenth embodiment is the same as the ninth embodiment except that the size of the outer shape is set to 24 mm ⁇ 24 mm in the ninth embodiment.
- Example 7 (1) In the interposer of Example 23, in Example 7, the starting material was changed to a sintered ALN substrate having an outer size of 32 ⁇ 32 mm and a thickness of 50 ⁇ m. This ALN substrate was manufactured by the steps (1), (2), (6) and (7) in Example 22. The thickness of the green sheet in (2) was 52-57 m. After sintering, the thickness of the insulating substrate may be adjusted by polishing. Otherwise, it is the same as Example 7.
- Example 8 (1) In the interposer of Example 24, in Example 8, the starting material was changed to a sintered ALN substrate having an outer size of 32 ⁇ 32 mm and a thickness of 64 ⁇ m. This ALN substrate was manufactured by the steps (1), (2), (6) and (7) in Example 22. The thickness of the green sheet in (2) was 67-72 m. After sintering, the thickness of the insulating substrate may be adjusted by polishing. Otherwise, it is the same as Example 8.
- the starting material was changed to a sintered ALN substrate having an outer size of 32 ⁇ 32 mm and a thickness of 100 ⁇ m.
- This ALN substrate was manufactured by the steps (1), (2), (6) and (7) in Example 22.
- the thickness of the green sheet in (2) was 103-113 m. After sintering, the thickness of the insulating base material may be adjusted by polishing. Otherwise, it is the same as Example 9.
- Example 11 the starting material was changed to a sintered ALN substrate having an outer size of 32 ⁇ 32 mm and a thickness of 1000 ⁇ m.
- This ALN substrate was manufactured by the steps (1), (2), (6) and (7) in Example 22.
- the thickness of the green sheet in (2) was set to 1030 to 1150 m. After sintering, the thickness of the insulating substrate may be adjusted by polishing. Otherwise, the configuration is the same as that of the eleventh embodiment.
- Example 11 (1) In the interposer of Example 33, in Example 11, the starting material was changed to an SF2 glass substrate (Schott, glass cord; 64 8339) having a size of 32 x 32 mm and a thickness of 1000 ⁇ m. did. The thickness was adjusted by polishing. Other than that, it is the same as Example 11.
- SF2 glass substrate Schott, glass cord; 64 8339
- the through-hole formation area of the interposer and the number of through-holes were the same as in Example 9, and the positions of the through-holes connected to the power and ground terminals of the IC were staggered. Except for the arrangement position of the through holes, it is the same as the ninth embodiment.
- the ICs that match the arrangement of the through holes of the interposer were used.
- a Pyrek glass substrate (manufactured by Corning) 80Z was used as a starting material (FIG. 10 (A)).
- a urethane-based resist 79 was attached to both sides of the substrate 80 (FIG. 10 (B)), and an opening 79a at a position of 125 m corresponding to the external electrode of the IC was formed by a normal photographic method (FIG. 10B). (C)).
- the interposer of Comparative Example 5 is the same as Example 1 except that the size of the external force was set to 15 mm X 15 mm in Example 1.
- Example 9 the number of terminals was the same, and the pitch of the through hole connected to the power and ground terminals of the IC was 120 ⁇ m. (The diameter of the through hole is ⁇ 60 m.) The electrode pitch of the IC chip to be connected in the subsequent process was 120 ⁇ m.
- Experimental Example 4 is an example in which the arrangement of the through holes in Experimental Example 3 is staggered.
- a sealant (underfill) 69 was filled between the interposer 70 and the IC chip 110, and cured at 80 ° C. for 15 minutes, and then at 150 ° C. for 2 hours (FIG. 3).
- the various semiconductor devices fabricated in step 3 are subjected to a heat cycle test (-55 ° C * 30 minutes 120 ° C * 30 minutes), and the wiring including via holes and through holes in the package substrate from the measurement terminals on the back of the package ⁇ Through hole conductor of interposer ⁇ IC chip wiring ⁇ Snorehole conductor of interposer ⁇ Wiring including viahole and snorehole in package substrate ⁇ Resistance value of wiring to measurement terminal on the back of package before heat cycle test (Initial value) Measured after 500, 1000, 1500 and 2000 cycles. The results are shown in the charts of FIGS. 12, 13, and 14. Pass means that the resistance shift is within ⁇ 10%.
- the insulating base material constituting the interposer preferably has a Young's modulus of 55 to 440 GPa.
- the present inventor has analyzed the thermal stress when the semiconductor device is mounted on the substrate.
- the Young's modulus of the interposer is within the above-mentioned range, the thermal stress of the IC chip, the interposer and the resin package, etc.
- the amount of deformation depends on the IC interposer and the package substrate. In such a relationship, the interposer receives the stress due to the difference in thermal expansion between the ceramic IC and the resin package substrate, and does not transmit the stress to the resin of the wiring layer of the IC. As a result, it was found that cracks and disconnections did not occur in the resin of the wiring layer of the IC.
- the Young's modulus of the interposer decreases, the amount of deformation of the interposer due to stress increases.
- the Young's modulus of the interposer is less than 55 GPa, the difference between the deformation of the IC and the interposer increases. Then, it was found that the resin of the wiring layer of the IC could not withstand the stress generated due to the difference, and cracks and disconnections occurred in the resin of the wiring layer of the IC. Beyond 440 GPa, the rigidity of the interposer was too high, and cracks and breaks in the resin of the IC's insulating layer contributed.
- Example 1-143 The comparison between Example 1-143 and Comparative Example 1-1-4 after 500 heat cycles showed that In Example 114-43, all of them are ⁇ or more, whereas in Comparative Examples 1-4, all are X. From this, if the Young's modulus of the insulating base material of the interposer is 55-440 GPa and the thickness is in the range of 0.05 times to 1.5 times the thickness of the package substrate, the heat-stress resistance of the IC mounting substrate It can be seen that is improved.
- the size of the insulating base material is preferably larger than the IC chip and smaller than the package substrate.
- Example 9 shows that the heat cycle resistance of the IC mounting substrate differs depending on the arrangement of the through holes. It is preferable to arrange them in a lattice or staggered pattern.
- the semiconductor devices of Examples 9, 19, 20, and 21 were planarly polished from the IC side to a thickness of about 1Z2 of the sealant to remove voids in the sealant.
- the incidence was measured (the number of semiconductor devices with voids Z100 x 100).
- the cross-sectional shape of the through-hole affects the filling property of the conductive material.
- the cross-sectional shape of the through hole of the interposer be at least one opening diameter of the end face or more than the diameter of the center of the through hole.
- the relationship between the opening diameter Z of the one end surface and the minimum hole diameter of the through hole is preferably 1.02 to 5.0. If it is less than 1, it is difficult to fill the through hole with a conductive material without filling it. When the value is 1.02 or more, the opening diameter of the end surface of the through-hole becomes larger than that of the other through-hole portions, so that the filling of the conductive material is easily performed. As a result, voids are eliminated.
- Example 35 The semiconductor package of Example 35 and Comparative Example 7 after a heat cycle of 2,000 cycles was polished in cross section to confirm the direction of cracks at the joint.
- Evaluation test 1 The Young's modulus on the BB line (Fig. 16-1) calculated by simulation (3D strip simulation) using the insulating substrate (interposer) 70 shown in Fig. 16 (A) as a target It is shown in 16 (B).
- the through-hole 74 in the part 75 immediately below the IC chip is 77 X 77 columns are arranged.
- the physical properties of the insulating base material change in Young's modulus with the boundary immediately below the periphery of the IC as a boundary.
- the thermal expansion coefficient of the insulating base material (interposer) has the same tendency.
- Evaluation test 2 The same material was used for the interposer, conductor, IC chip, package board solder, etc., and their Young's modulus, Poisson's ratio, and coefficient of thermal expansion were input, and the insulation calculated by 3D strip simulation.
- FIG. 15 shows the relationship between the thickness of the base material (interposer) and the stress applied to the resin in the wiring layer of the IC.
- the Young's modulus of the insulating substrate was set to 200 GPa. As can be seen from this figure, when the thickness of the insulating base material (interposer) becomes 0.05 to 1.5 times the thickness of the package substrate, the stress applied to the resin in the IC wiring layer decreases. . Therefore, if the thickness of the insulating base material (interposer) is 0.05 to 1.5 times the thickness of the package substrate, the resin of the wiring layer of the IC is not easily broken.
- Example 22 using the baked substrate as the starting material was negative, whereas Example 22 was X.
- Example 26 since the through-hole was formed in the fired substrate, it is estimated that the positioning accuracy of the through-hole conductor with the terminal of the IC chip and the terminal of the package substrate is good.
- Example 22 since the firing process at a high temperature is performed after the formation of the through-hole conductor, the position of the through-hole conductor is reduced with respect to the IC chip terminals and the terminal positions of the package substrate due to shrinkage and warpage. It is presumed that the contact area with the terminal of the IC chip and the terminal of the package substrate is reduced. It is thought that this difference caused a difference between the two.
- FIG. 1 is a cross-sectional view of a resin package substrate according to Embodiment 1 of the present invention.
- FIG. 2 A cross-sectional view of the resin package board shown in FIG. 1 with an interposer attached. It is.
- FIG. 3 is a cross-sectional view showing a state where an IC chip is mounted on the resin package substrate shown in FIG. 2 and attached to a daughter board.
- FIG. 4 is a plan view of the IC chip, the interposer, and the resin package substrate shown in FIG. 3.
- FIG. 5 (A) is a plan view of an interposer according to the first embodiment
- FIG. 5 (B) is a plan view of an interposer according to another example of the first embodiment.
- FIG. 6 is a manufacturing process diagram of the interposer according to the first embodiment.
- FIG. 7 is a manufacturing process diagram of the interposer according to the seventh embodiment.
- FIG. 8 is a manufacturing process diagram of the interposer according to the seventh embodiment.
- FIG. 9 is a view showing a manufacturing process of an interposer according to Example 22.
- FIG. 10 is a manufacturing process diagram of the interposer according to Example 41.
- FIG. 11 is a view showing a manufacturing process of an interposer according to Example 41.
- FIG. 12 is a chart showing the results of a heat cycle test.
- FIG. 13 is a chart showing the results of a heat cycle test.
- FIG. 14 is a table showing the results of a heat cycle test.
- FIG. 15 is a chart showing stress applied to a resin of a wiring layer of an IC.
- FIG. 16 is a schematic diagram of an insulating base material (interposer), and FIG. 16 (B) is a chart showing Young's moduli of the insulating base material (interposer) immediately below an IC and other parts. It is. Explanation of symbols
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04788014A EP1667225A4 (en) | 2003-09-24 | 2004-09-22 | INTERMEDIATE MEMBER AND MULTILAYER CONDUCTOR PLATE |
JP2005514107A JP4771808B2 (ja) | 2003-09-24 | 2004-09-22 | 半導体装置 |
US10/564,200 US20060202322A1 (en) | 2003-09-24 | 2004-09-22 | Interposer, and multilayer printed wiring board |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2003331360 | 2003-09-24 | ||
JP2003-331360 | 2003-09-24 | ||
JP2003381048 | 2003-11-11 | ||
JP2003-381048 | 2003-11-11 |
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WO2005029581A1 true WO2005029581A1 (ja) | 2005-03-31 |
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PCT/JP2004/013831 WO2005029581A1 (ja) | 2003-09-24 | 2004-09-22 | インターポーザ、多層プリント配線板 |
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US (1) | US20060202322A1 (ja) |
EP (1) | EP1667225A4 (ja) |
JP (1) | JP4771808B2 (ja) |
KR (1) | KR20060111449A (ja) |
TW (1) | TW200522833A (ja) |
WO (1) | WO2005029581A1 (ja) |
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TWI814582B (zh) * | 2022-09-19 | 2023-09-01 | 大陸商芯愛科技(南京)有限公司 | 封裝基板 |
Also Published As
Publication number | Publication date |
---|---|
EP1667225A1 (en) | 2006-06-07 |
KR20060111449A (ko) | 2006-10-27 |
JP4771808B2 (ja) | 2011-09-14 |
EP1667225A4 (en) | 2009-04-01 |
TW200522833A (en) | 2005-07-01 |
TWI299970B (ja) | 2008-08-11 |
US20060202322A1 (en) | 2006-09-14 |
JPWO2005029581A1 (ja) | 2007-11-15 |
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