WO2002011200A1 - Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung - Google Patents
Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung Download PDFInfo
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- WO2002011200A1 WO2002011200A1 PCT/DE2001/002798 DE0102798W WO0211200A1 WO 2002011200 A1 WO2002011200 A1 WO 2002011200A1 DE 0102798 W DE0102798 W DE 0102798W WO 0211200 A1 WO0211200 A1 WO 0211200A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000003990 capacitor Substances 0.000 claims abstract description 101
- 230000015654 memory Effects 0.000 claims abstract description 39
- 239000011159 matrix material Substances 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 61
- 125000006850 spacer group Chemical group 0.000 claims description 28
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- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
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- 238000001465 metallisation Methods 0.000 description 1
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
Definitions
- the invention relates to a semiconductor memory cell arrangement with dynamic memory cells, DRAMs for short, which each have a selection transistor and a storage capacitor.
- DRAMs dynamic memory cells
- the information is stored in the memory cell in the form of electrical charges, the memory states "0" and "1" corresponding to a positively or negatively charged storage capacitor.
- the selection transistor and the storage capacitor of the memory cell are connected to one another in such a way that when the selection transistor is activated via a word line, the charge of the capacitor can be read in and out via a bit line.
- the main effort in technology development of DRAM cell arrays is to reliably operate DRAMs with a high packing density, i. H. to create a small space requirement per memory cell.
- the storage capacitor has a storage capacity which ensures a sufficient read signal and is also insensitive to ⁇ -particles.
- storage capacitors have been developed that use the third dimension.
- Such three-dimensional storage capacitors are primarily designed in the form of trench capacitors which are produced in such a way that a trench is etched into the semiconductor substrate and is filled with a dielectric layer and a first storage electrode, the semiconductor substrate serving as a second storage electrode.
- the selection transistor of the DRAM cell is usually formed on the planar semiconductor surface next to the trench capacitor.
- Such a cell arrangement with a trench capacitor and a planar selection transistor requires at least a chip area of 8F 2 , where F is the minimum technology used in the represents structure size producible by lithography.
- F is the minimum technology used in the represents structure size producible by lithography.
- the structure size F is reduced from memory generation to memory generation on the one hand and the entire chip area is enlarged on the other hand.
- One possibility of reducing the cell size of the DRAM is to design the selection transistor three-dimensionally, similarly to the storage capacitor.
- Various DRAM cell concepts are already known in which a trench capacitor is connected to a selection transistor which is configured essentially vertically as an MISFET.
- MISFET magnetic field-effect transistor
- the active area between the source electrode and the drain electrode of a word or bit line adjacent to the DRAM cell, which is not used to control the relevant DRAM cell is used is affected. With the small structure sizes of the DRAMs in particular, this can lead to a leakage current through the active region of the MISFET and thus to a loss of information in the memory cell.
- US Pat. No. 5,519,236 proposes a semiconductor memory cell arrangement in which the active region between the source electrode and the drain electrode of the vertical selection transistor is completely covered by one Gate structure is enclosed, whereby the active area is shielded from adjacent word or bit lines.
- the known cell arrangement is constructed in such a way that trenches and columns in a checkerboard pattern in the semiconductor substrate. arrangement are carried out, the storage capacitor in a trench and the associated selection transistor are carried out vertically in an adjacent column and a gate electrode layer completely surrounds the active layer of the selection transistor.
- the gate electrode layer can
- a bit line of the DRAM cell is further arranged in such a way that it runs vertically offset against the trench capacitor above the column of the associated vertical selection transistor and is connected to its source electrode.
- the checkerboard pattern used in US Pat. No. 5,519,236 for arranging the DRAM cells requires a large amount of space, so that the maximum packing density of the DRAM cells on the semiconductor substrate remains limited. Furthermore, when designing the DRAM cell according to US Pat. No.
- the matrix-like arrangement of the DRAM cells also results in a maximum It is possible to expand the cross section of the trench capacitors in relation to the cell area of the individual DRAM cells, as a result of which improved capacitance values of the trench capacitors can be achieved.
- this cubic closest packing of the individual DRAM cells is achieved in that the trench capacitor and the associated vertical selection transistor of the dynamic memory cells are formed essentially under an associated bit line. This enables the individual DRAM cells to be formed closely next to one another and, at the same time, to reliably shield the active areas of the selection transistors from adjacent word and bit lines by enclosing these active areas with the aid of the gate electrode structure.
- the spacer technology is used to define the areas with the vertical selection transistors and their connection to the associated trench capacitors, which enables a self-adjusting definition of these areas and thus minimum structure sizes in the DRAM cells.
- spacers with differently doped regions are used in particular to define the vertical selection transistors, so that a self-adjusting definition of the vertical selection transistors results with the aid of selective etching processes for the different doping. Furthermore, this enables a connection region between the lower electrode of the selection transistor and the inner electrode of the trench capacitor to be reliably and precisely defined.
- the lower electrodes of the selection transistors are produced by doping implantation and diffusion, the conductive Tending connection to the inner electrode of the trench capacitor with doped and thus a self-adjusting connection is made.
- the structuring of the upper electrode of the selection transistors takes place with the aid of the trench isolation technology, which ensures reliable insulation with at the same time minimal process expenditure.
- the gate electrode layer sequence is introduced around the active region of the selection transistors with the aid of spacer technology, so that self-adjusting and space-saving generation of the word line regions is possible without lithographic processes.
- a support structure is formed between the selection transistors in order to produce, in particular, an entangled bit line interconnection, each of which belongs to successive bit lines, but to the same word line.
- FIGS. 1 to 11 show a first embodiment of a semiconductor memory cell arrangement according to the invention, with FIGS. 1 to 11 representing method steps for producing this semiconductor memory cell arrangement, and partial figure B is a plan view, partial figure
- A a cross section along the AA line and partial Figure C represents a cross section along the CC line;
- Figure 13 shows a second embodiment of the semiconductor memory cell arrangement according to the invention, partial figure
- partial figure A shows a cross section along the AA line
- partial figure C shows a cross section along the CC line
- FIG. 14 shows a top view of a third embodiment after the process step for producing the trench capacitors
- FIG. 15 shows a plan view of a fourth embodiment after the process step for producing the trench capacitors.
- Figure 16 is a circuit diagram of a dynamic read / write memory.
- So-called 1-transistor cells are predominantly used in dynamic read / write memories (DRAMs). These 1-transistor cells consist of a storage capacitor 1 and a selection transistor 2.
- the selection transistor 2 is preferably designed as a field effect transistor. This field effect transistor has a first electrode 21 and a second electrode 23, between which an active region 22 is arranged, in which a current-conducting channel can be formed between the first electrode 21 and the second electrode 23.
- An insulator layer 24 and a gate electrode 25 are arranged above the active region 22 and act like a plate capacitor with which the charge carrier density in the active region 22 can be influenced.
- the field effect transistor 2 hereinafter also abbreviated to MISFET, is of the enhancement type, ie a current flow between the first electronic device only occurs when a threshold voltage is applied to the gate electrode 25. de 21 and the second electrode 23 via the active region 22.
- the second electrode 23 of the MISFET 2 is connected to a first electrode 11 of the storage capacitor 1 via a connecting line 4.
- the second electrode 12 of the storage capacitor 1 is in turn connected to a capacitor plate 5, which is preferably common to all storage capacitors of the DRAM cell arrangement.
- the first electrode 21 of the MISFET 2 is connected to a bit line 6 in order to be able to read in and read out the information stored in the storage capacitor 1 in the form of charges.
- the read-in and read-out process is controlled via a word line 7, which is connected to the gate electrode 24 of the MISFET 2, in order to produce a current-conducting channel in the active region 22 between the first electrode 21 and the second electrode 23 by applying a voltage.
- the minimum structure size F that can be produced using the described lithography technique is 0.1 ⁇ m. This means that the bit and word lines and the contact holes generally have a width of approximately 0.1 ⁇ m. It should be noted, however, that the figures shown are not to scale. The invention is also not limited to the structure sizes mentioned.
- the dashed line defines a DRAM cell 10. These DRAM cells are essentially arranged longitudinally below bit lines 6, which are equidistantly spaced on the memory arrangement in the x direction.
- FIG. 12A shows a cross section through the semiconductor cell arrangement along a A bit line 6
- FIG. 12C shows the cross section through the semiconductor cell arrangement along a word line 7.
- the DRAM cells, which are essentially aligned along the bit line 6, are composed of columns 101 in which the MISFET selection is essentially Transistors 2 are formed and trenches 102, in which essentially the storage capacitors 1 are formed, together.
- the cell arrangement shown is produced using silicon semiconductor technology, a weakly doped p-substrate serving as the basis.
- a buried plate (not shown) is embodied in this p-type semiconductor substrate 103 in the form of a strong n-doping, which serves as a common second outer electrode 12 for all trench capacitors of the cell arrangement.
- the semiconductor substrate in contact with the buried n-doped plate, as shown in FIG. 12A, equally spaced trenches are formed, which can have any shape, but are preferably oval or rectangular. These trenches are lined with a dielectric layer 13 in their lower part and filled with n-doped polysilicon in this area. This n-doped poly-silicon filling represents the first inner electrode 11 of the storage capacitor 1.
- SiO 2 is preferably used as the dielectric layer 13 in the trench for insulating the electrodes.
- the MISFET selection capacitors 2 are each formed in the semiconductor columns 101 between the trenches, which, as the cross section according to FIG. 12A shows, extend under the bit line 6.
- This MISFET transistor has, in the region of the upper end of the poly-silicon layer 11 in the trench, ie the inner electrode of the trench capacitor, the second electrode 23 in the form of a highly doped n-layer.
- the active region 22, which is weakly p-doped, is then formed on this n-layer.
- the first electrode 21 is in turn applied to this active region 24 as a highly doped n-layer.
- an Si0 2 layer (not shown) with a thickness of approx. 8 nm is deposited from this starting material after several cleaning steps.
- An Si 3 N 4 layer S2 with a thickness of approximately 200 nm is then produced on this oxide layer.
- An SiO 2 layer with a thickness of approximately 800 nm is in turn applied to this nitride layer.
- This layer sequence serves as a masking layer for the following trench etching. With the help of a mask, photolithography is then carried out to define the trench capacitors. After this photolithography process, an anisotropic etching of the masking layer takes place.
- B. C 2 F S and 0 2 can be used.
- the resist mask for the photolithography is removed.
- the silicon layer in the exposed areas of the etching mask is then anisotropically etched to about 10 ⁇ m deep with HBr and HF in order to expose the trenches for the storage capacitors.
- a buried plate for the common second electrode of the storage capacitors is then formed in the silicon substrate, an arsenic glass preferably being used.
- an arsenic glass layer is preferably produced in a thickness of approximately 2 nm.
- a polymer photoresist, preferably PMMA, with a thickness of approximately 500 nm is then produced on this arsenic glass layer and fills the etched trenches.
- This polymer photoresist layer is then outside of the trenches to a thickness of approximately 2 ⁇ m z. B. etched back with 0 2 . Then the arsenic glass above the polymer photoresist in the trenches z. B. etched away with HF and then the polymer photoresist layer in the trenches z. B. removed with 0 2 .
- arsenic is diffused out of the arsenic glass into the p-doped silicon. The remaining arsenic glass is then removed using HF etching.
- an ONO deposition (oxide nitride oxide) is carried out, a layer thickness S3 of approximately 3 nm being selected.
- highly n-doped polysilicon S4 with a thickness of approximately 200 nm is deposited in order to fill up the trenches.
- the protruding polysilicon outside the trenches is then etched back.
- the ONO dielectric, which protrudes over the trenches, is removed with HF.
- An approximately 20 nm thick SiO 2 layer is then preferably produced using the TEOS process and is anisotropically etched away with CHF 3 and 0 2 in the region of the trenches.
- FIG. 1A shows a cross section along the AA line through the trenches for the storage capacitors.
- trenches for the storage capacitors shown in FIG. 1B there is also the possibility of producing trenches for the storage capacitors with a different shape, such as that shown in FIG. B. are shown in Figures 14 and 15.
- trench shapes can be selected that allow a larger surface area of the side wall and thus an increased storage capacity of the capacitor.
- the shape of the trenches in which the vertical selection transistors are arranged can be determined via the shape of the trenches of the trench capacitors. If the lines are formed with a rectangular shape, the spaces between the webs with the selection transistors are smaller, for example in the direction of the word line than in the direction of the bit lines, as a result of which continuous and separate word lines are formed by means of a spacer deposition.
- amorphous silicon spacer S7 After the removal of the oxide mask, thermal activation of the dopants is carried out in the amorphous silicon spacer S7 on one side of the trench, the amorphous silicon spacers S6, S7 recrystallizing.
- the undoped silicon spacer S6 is then removed in a further photolithography step.
- a polymer photoresist S9 preferably PMMA, is spun on with a thickness of approximately 500 nm. This polymer layer is then completely outside the trenches z. B. etched back with 0 2 .
- the undoped silicon spacer is then selectively removed from the doped silicon spacer, which is either heavily p- or n-doped.
- the ONO layer is isotropically etched back by approx. 40 nm with HF.
- Figure 4A shows a cross section along the AA line.
- this contact point is then filled.
- the PMMA layer S9 with z. B. 0 2 completely removed.
- the remaining doped polysilicon spacer S7 is then etched away and then on the semiconductor Structure undoped amorphous silicon Sll deposited with a layer thickness of about 15nm.
- This amorphous silicon is then etched back isotropically with C 2 F 6 and 0 2 , so that the amorphous silicon is completely removed, except at the contact point in the trench.
- the silicon wafer after this process step is shown in the top view in FIG. 5B and in cross section along the AA line in FIG. 5A.
- oxide S12 is first deposited with a thickness of approximately 80 nm, preferably according to the TE0S method.
- This Si0 2 layer is then etched back by approx. 130 nm with CHF 6 and 0 2 , so that the columns between the trenches in the area of the upper Si 3 N 4 layer are exposed.
- This Si 3 N 4 layer is then z. B. completely removed with H 3 P0 4 .
- the Si0 2 layer is then etched back by approximately 10 nm with 0 2 .
- the silicon wafer after this process step is shown in the top view of FIG. 6B and in cross section along the AA line in FIG. 6A.
- the vertical selection is then formed - transistors to the side of the storage capacitors arranged in the trenches.
- the vertical selection is then formed - transistors to the side of the storage capacitors arranged in the trenches.
- a high n-doping preferably by arsenic doping, which after diffusion extends to a depth of approximately 100 nm with a doping of 5 ⁇ 10 19 / cm 3 .
- This upper n-doping layer S13 defines the first electrode of the transistor.
- a buried layer S14 is formed in the cell field, in which the depth of the maximum is preferably in the range of approximately 400 nm, with a vertical layer thickness of approximately 200 nm diffuses out.
- the silicon wafer after completion of this process step is shown in the top view in FIG. 8B, in cross section along the AA line in FIG. 8A and in cross section along the CC line in FIG. 8C.
- the selected trench isolation technology achieves simple structuring and isolation of the selection transistors in the y direction, so that isolation is possible with little process effort.
- a spacer structure is then generated between the selection transistors in the vertical direction in order to produce a semiconductor memory cell arrangement with an entangled bit line structure, as is shown in the embodiment in FIG.
- an Si0 2 layer with a thickness of approximately 50 nm is first deposited using the TEOS process.
- a spacer etching of the oxide layer S12 with C 2 F 6 and 0 2 then takes place, an overetching of approximately 80 nm being carried out. Then in the uncovered trenches between the
- FIG. 9A shows a cross section along the AA line
- FIG. 9C shows a cross section along the CC line.
- an open bit line interconnection as shown in the embodiment according to FIG. 13
- no support structure is required, so that the process sequence which is based on the Process image of Figure 8 leads to the process image of Figure 9, can be omitted.
- a top oxide is generated on the storage capacitors for their insulation.
- the Si 3 N 4 layer is completely removed in a first step with H 3 P0 4 .
- the remaining Si0 2 layer is then etched back to a depth of approximately 380 nm with CHF 3 and 0 2 , the etching process being not selective for Si 3 N. This ensures that the columns with the transistor structures and the support structures are completely exposed.
- a trench top oxide S18 for insulating the storage capacitors is then then then produced with a thickness of preferably 40 nm.
- the silicon wafer after this process step is shown in perspective in Figure 10B, in cross-section along the AA line in Figure 10A and in cross-section along the CC line in Figure IOC.
- a gate dielectric S19 is preferably grown as a thermal oxide with a thickness of approximately 4 nm in a first process step. Then an approximately 20 nm thick polysilicon layer S20 is deposited, which is highly n-doped. This polysilicon layer S20 serves as a gate electrode for the selection transistors. Then the word lines connecting the individual gate electrodes are generated. For this purpose, an approximately 2 nm thick barrier layer (not shown) made of tungsten nitride is first produced, on which tungsten is then deposited with a layer thickness S21 of approximately 20 nm.
- the polysilicon layer S20, the barrier layer and the tungsten layer S21 are then anisotropically etched away by approximately 50 nm by means of C 2 F 6 and 0 2 , so that the columns with the Selection transistors around the spacer from the gate electrode structure and the Form word line structure, the active areas between the upper and lower electrodes in the columns are completely covered with the selection transistors.
- a thin approx. 20 nm thick SI 3 N 4 layer S22 is deposited in a further process step, on which an approx. 200 nm thick SiO 2 is then preferably deposited using the TEOS method 2 layer S23 is generated.
- This oxide layer S23 is then preferably ground flat with the aid of chemical mechanical polishing up to the upper edge of the nitride layer S22.
- the nitride is then selectively etched off with C 2 F 6 and 0 2 .
- the oxide has been etched back, preferably with HF by approx. 40 nm, there is a structure in the silicon wafer as shown in the top view in FIG. 11B, in cross section along the AA line in FIG. ILA and in cross section along the CC line in FIG Figure 11C is shown.
- the polysilicon contacts for the upper electrodes of the selection transistors and the tungsten metallization for forming the bit lines are then produced in a further lithography process sequence, so that a DRAM memory cell arrangement as shown in FIGS. 12A to C results is shown.
- a DRAM memory cell arrangement results, as is shown in FIGS. 13A to C.
- the process flow according to the invention makes it possible to produce a DRAM memory cell arrangement with trench capacitors and vertical selection transistors, in which the active area of the selection transistors is completely enclosed by the gate and word line structure and which is characterized by a minimal space requirement.
- the maximum packing density of the DRAM cells is achieved in particular by using a self-aligning memory structure for the word lines, as explained above.
- the specified dimensions, concentrations, materials and processes in a suitable manner beyond the exemplary embodiments described above in order to produce the DRAM memory cell arrangement according to the invention.
- known process sequences for forming the selection transistors, especially the source / drain regions can be used.
- the conductivity type of the doped regions in the semiconductor structure in a complementary manner.
- the specified dielectrics can also be replaced by other known dielectrics.
- silicon oxide for.
- silicon nitride aluminum oxide, zirconium oxide, oxide-nitride mixtures and low-k materials can be used.
- ONO intermediate layer in the storage capacitors other known dielectrics with a high dielectric constant such as e.g. As aluminum oxide, zirconium oxide, tantalum oxide, hafnium oxide, perovskite, in particular BST, can be used.
- tungsten to form the spacer structures for the word lines, z. B. silicides such. B. tungsten silicide or silicides made of titanium and goblin or doped polysilicon can be used.
- further layer sequences, in particular to form barriers in order to avoid undesired diffusions can be introduced into the semiconductor structure.
- the selectivities and mask sequences in a suitable manner the structuring processes shown are modified without leaving the scope of the invention.
- the vertical selection transistor 2 of the DRAM memory cell comprises an upper electrode 21 which is n + -doped, an active intermediate layer 22 which is weakly p-doped and a lower electrode 23 which is likewise n + - is endowed.
- an out-diffusion D is introduced in the lower electrode 23, the dopant of which is diffused out of the inner electrode 11 of the trench capacitor 1 through the conductive connection 4 into the lower electrode 23.
- the vertical selection transistor 2 is formed in a web which has the width B.
- the width B is chosen to be so small that the active intermediate layer 22, in which the channel of the transistor 2 is arranged, is completely depleted. This is achieved, for example, in that adjacent intermediate layers in adjacent webs in one
- the width B of the webs is substantially smaller than the spaces between the webs, so that the spaces between the webs in which the trench capacitors are arranged have a width between 1F and 2F and the webs have the width B, which is made up of 2F minus the width B of the trenches results.
- the webs thus have a width B that is sublithographic.
- FIG. 13B The plan view of a memory cell array according to the invention is shown with reference to FIG. 13B.
- PJ ⁇ d ⁇ Di ⁇ ⁇ d ⁇ i tr dd et ⁇ - d CQ ⁇ ⁇ tr ⁇ rt ⁇ ⁇ ii td ⁇ - d ⁇ d ü rt d et ⁇ et tr d ⁇ Pf rt Di td CQ CD 0 LQ d CQ tr d D.
- ⁇ - PJ ⁇ CQ ii et LQ ⁇ - et LQ ⁇ et td H Di ü o-- ⁇ ⁇ - CD ⁇ ⁇ ⁇ .
- the position and the thickness of the layer 23, from which the lower electrodes 23 are subsequently formed can be set very precisely.
- the upper electrode 21 can subsequently be formed both before and after the formation of the trenches for the trench capacitors 1 by means of an implantation.
- the gate electrode and the word line are formed using spacer technology.
- a layer is deposited conformally (isotropically), which is also reflected in the bars of the selection transistors.
- the previously deposited layer is etched back with directed (anisotropic) etching, so that a gate electrode forms around the webs.
- the individual gate electrodes around the webs are connected in the direction of the word line, since the distance between the webs in the direction of the word lines is so small that a connected word line is formed.
- the active intermediate layer 22, in which a channel of the vertical selection transistor 2 can be formed, is essentially arranged between the trenches 1 of adjacent memory cells.
- the current flow which can be controlled in the selection transistors essentially takes place between the trenches.
- the trench capacitor 1 and the associated vertical selection transistor 2 of the dynamic memory cell 10 can essentially be arranged under an associated bit line 6.
- the minimum distance between two adjacent word lines can be formed twice as large as the minimum structure size of the lithography technique with which the memory cells are produced.
- the minimum distance between two adjacent bit lines can also be formed twice as large as the minimum structure size of the lithography technology with which the memory cells are manufactured, this enables memory cells that require a substrate surface of 4 F 2 .
- memory cells are made possible which require a substrate surface of 6 F 2 .
- the larger space requirement can be used, for example, to implement a folded bitline concept in which a sense amplifier compares an active bit line with an inactive bit line.
- the word line for the 4 F 2 memory cell as well as for the 6 F 2 memory cell can be formed in a self-aligned manner without a mask, which saves an additional space requirement for adjustment tolerances for masks.
- an area of the inner electrode of the trench capacitors 1 can be exposed.
- the upper electrode 21 of the selection transistor 2 can be defined by a trench isolation process and can be formed by means of a subsequent implantation.
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Abstract
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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EP01956376A EP1305827A1 (de) | 2000-07-31 | 2001-07-23 | Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung |
JP2002516826A JP4004949B2 (ja) | 2000-07-31 | 2001-07-23 | 半導体メモリーセル構造 |
KR10-2003-7001413A KR100506336B1 (ko) | 2000-07-31 | 2001-07-23 | 반도체 메모리 셀 배열 및 그 제조 방법 |
US10/356,780 US6853023B2 (en) | 2000-07-31 | 2003-01-31 | Semiconductor memory cell configuration and a method for producing the configuration |
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DE10038728.4 | 2000-07-31 | ||
DE10038728A DE10038728A1 (de) | 2000-07-31 | 2000-07-31 | Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/356,780 Continuation US6853023B2 (en) | 2000-07-31 | 2003-01-31 | Semiconductor memory cell configuration and a method for producing the configuration |
US10/356,780 Continuation-In-Part US6853023B2 (en) | 2000-07-31 | 2003-01-31 | Semiconductor memory cell configuration and a method for producing the configuration |
Publications (2)
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WO2002011200A1 true WO2002011200A1 (de) | 2002-02-07 |
WO2002011200A8 WO2002011200A8 (de) | 2002-04-11 |
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PCT/DE2001/002798 WO2002011200A1 (de) | 2000-07-31 | 2001-07-23 | Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung |
Country Status (7)
Country | Link |
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US (1) | US6853023B2 (de) |
EP (1) | EP1305827A1 (de) |
JP (1) | JP4004949B2 (de) |
KR (1) | KR100506336B1 (de) |
DE (1) | DE10038728A1 (de) |
TW (1) | TW513801B (de) |
WO (1) | WO2002011200A1 (de) |
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- 2001-07-23 KR KR10-2003-7001413A patent/KR100506336B1/ko not_active IP Right Cessation
- 2001-07-23 EP EP01956376A patent/EP1305827A1/de not_active Withdrawn
- 2001-07-23 JP JP2002516826A patent/JP4004949B2/ja not_active Expired - Fee Related
- 2001-07-31 TW TW090118615A patent/TW513801B/zh not_active IP Right Cessation
-
2003
- 2003-01-31 US US10/356,780 patent/US6853023B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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KR100506336B1 (ko) | 2005-08-05 |
JP4004949B2 (ja) | 2007-11-07 |
JP2004505466A (ja) | 2004-02-19 |
EP1305827A1 (de) | 2003-05-02 |
US20030169629A1 (en) | 2003-09-11 |
WO2002011200A8 (de) | 2002-04-11 |
DE10038728A1 (de) | 2002-02-21 |
KR20030019639A (ko) | 2003-03-06 |
TW513801B (en) | 2002-12-11 |
US6853023B2 (en) | 2005-02-08 |
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