WO2002011200A8 - Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung - Google Patents

Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung Download PDF

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Publication number
WO2002011200A8
WO2002011200A8 PCT/DE2001/002798 DE0102798W WO0211200A8 WO 2002011200 A8 WO2002011200 A8 WO 2002011200A8 DE 0102798 W DE0102798 W DE 0102798W WO 0211200 A8 WO0211200 A8 WO 0211200A8
Authority
WO
WIPO (PCT)
Prior art keywords
trench capacitor
memory cell
semiconductor memory
cell arrangement
memory cells
Prior art date
Application number
PCT/DE2001/002798
Other languages
English (en)
French (fr)
Other versions
WO2002011200A1 (de
Inventor
Bernd Goebel
Joern Luetzen
Martin Popp
Harald Seidl
Original Assignee
Infineon Technologies Ag
Bernd Goebel
Joern Luetzen
Martin Popp
Harald Seidl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Bernd Goebel, Joern Luetzen, Martin Popp, Harald Seidl filed Critical Infineon Technologies Ag
Priority to EP01956376A priority Critical patent/EP1305827A1/de
Priority to KR10-2003-7001413A priority patent/KR100506336B1/ko
Priority to JP2002516826A priority patent/JP4004949B2/ja
Publication of WO2002011200A1 publication Critical patent/WO2002011200A1/de
Publication of WO2002011200A8 publication Critical patent/WO2002011200A8/de
Priority to US10/356,780 priority patent/US6853023B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Halbleiter-Speicherzellenanordnung mit dynamischen Speicherzellen (10), die jeweils einen Grabenkondensator (1) und einen verikalen Auswahltransistor (2) aufweisen, wobei der vertikale Auswahltransistor (2) im wesentlichen oberhalb wom Grabenkondensators (1) angeordnet ist und eine gegenüber der inneren Elektrode des Grabenkondensators (1) versetzt angeordnete Schichtenfolge die mit inneren Elektrode (11) des Grabekondensators (1) verbunden ist, wobei eine aktive Zwischenschicht (22) von einer Isolatorschicht (24) und einer Gate-Elektrodenschicht (25) vollständing umschlossen ist, die mit einer Worleitung (7) verbunden ist, wobei die dynamisch Speicherzellen (10) matrixförmig angeordnet sind, und die Grabenkondensatoren (1) und zugehörigen vertikalen Auswahltransistore (2) der dynamischen speicherzellen (10) jeweils zeilen-und/oder spaltenförmig aufeinanderfolgen.
PCT/DE2001/002798 2000-07-31 2001-07-23 Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung WO2002011200A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01956376A EP1305827A1 (de) 2000-07-31 2001-07-23 Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung
KR10-2003-7001413A KR100506336B1 (ko) 2000-07-31 2001-07-23 반도체 메모리 셀 배열 및 그 제조 방법
JP2002516826A JP4004949B2 (ja) 2000-07-31 2001-07-23 半導体メモリーセル構造
US10/356,780 US6853023B2 (en) 2000-07-31 2003-01-31 Semiconductor memory cell configuration and a method for producing the configuration

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10038728.4 2000-07-31
DE10038728A DE10038728A1 (de) 2000-07-31 2000-07-31 Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10/356,780 Continuation US6853023B2 (en) 2000-07-31 2003-01-31 Semiconductor memory cell configuration and a method for producing the configuration
US10/356,780 Continuation-In-Part US6853023B2 (en) 2000-07-31 2003-01-31 Semiconductor memory cell configuration and a method for producing the configuration

Publications (2)

Publication Number Publication Date
WO2002011200A1 WO2002011200A1 (de) 2002-02-07
WO2002011200A8 true WO2002011200A8 (de) 2002-04-11

Family

ID=7651755

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/002798 WO2002011200A1 (de) 2000-07-31 2001-07-23 Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung

Country Status (7)

Country Link
US (1) US6853023B2 (de)
EP (1) EP1305827A1 (de)
JP (1) JP4004949B2 (de)
KR (1) KR100506336B1 (de)
DE (1) DE10038728A1 (de)
TW (1) TW513801B (de)
WO (1) WO2002011200A1 (de)

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Also Published As

Publication number Publication date
KR100506336B1 (ko) 2005-08-05
KR20030019639A (ko) 2003-03-06
JP2004505466A (ja) 2004-02-19
US20030169629A1 (en) 2003-09-11
JP4004949B2 (ja) 2007-11-07
EP1305827A1 (de) 2003-05-02
TW513801B (en) 2002-12-11
DE10038728A1 (de) 2002-02-21
US6853023B2 (en) 2005-02-08
WO2002011200A1 (de) 2002-02-07

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