TW333709B - DRAM cell arrangement and method for its production - Google Patents

DRAM cell arrangement and method for its production

Info

Publication number
TW333709B
TW333709B TW086106647A TW86106647A TW333709B TW 333709 B TW333709 B TW 333709B TW 086106647 A TW086106647 A TW 086106647A TW 86106647 A TW86106647 A TW 86106647A TW 333709 B TW333709 B TW 333709B
Authority
TW
Taiwan
Prior art keywords
trenches
storage capacitors
neighbored
flank
polar
Prior art date
Application number
TW086106647A
Other languages
Chinese (zh)
Inventor
Risch Lothar
Hofmann Franz
Rosner Wolfgang
Augle Thomas
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW333709B publication Critical patent/TW333709B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A kind of DRAM cell arrangement whose features are: - multiple memory cells comprising of storage capacitors and selected transistors are allocated on the main region of the semiconductor substrate - selected transistors are arranged on top of the storage capacitors in the trenches in rows and columns within the main region - the storage capacitors are produced in the trenches and form the capacitor polar board in the neighboring region on the substrate - each two neighbored trenches in a row are formed a pair of trenches that surrounded by an insulation structure - semiconductor island is arranged in main region between the neighboring trench to the pair of trenches - semiconductors of neighbored rows are arranged offset each other; selected transistors are produced vertical transistors on a flank of the semiconductor island and the dielectric and polar gates are arranged on the flank - the storage nodes of storage capacitors are neighbored to the flank of the semiconductor island and the polar gates connect to the word lines.
TW086106647A 1996-05-22 1997-05-19 DRAM cell arrangement and method for its production TW333709B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19620625A DE19620625C1 (en) 1996-05-22 1996-05-22 High packing density DRAM cell array

Publications (1)

Publication Number Publication Date
TW333709B true TW333709B (en) 1998-06-11

Family

ID=7795030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086106647A TW333709B (en) 1996-05-22 1997-05-19 DRAM cell arrangement and method for its production

Country Status (3)

Country Link
DE (1) DE19620625C1 (en)
TW (1) TW333709B (en)
WO (1) WO1997044826A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1213182A (en) * 1997-09-30 1999-04-07 西门子公司 Memory cell for dynamic random access memory (DRAM)
US6383864B2 (en) * 1997-09-30 2002-05-07 Siemens Aktiengesellschaft Memory cell for dynamic random access memory (DRAM)
DE19800340A1 (en) * 1998-01-07 1999-07-15 Siemens Ag Semiconductor memory device and method for its production
US6093614A (en) * 1998-03-04 2000-07-25 Siemens Aktiengesellschaft Memory cell structure and fabrication
DE19811882A1 (en) * 1998-03-18 1999-09-23 Siemens Ag DRAM cell arrangement
KR100631092B1 (en) 2001-03-09 2006-10-02 인피니언 테크놀로지스 아게 Semiconductor memory location and method for the production thereof
JP2003101025A (en) * 2001-09-26 2003-04-04 Toshiba Corp Semiconductor device
EP1302982A1 (en) * 2001-10-12 2003-04-16 Infineon Technologies AG Method of producing a vertical field effect transistor device
US7473596B2 (en) 2003-12-19 2009-01-06 Micron Technology, Inc. Methods of forming memory cells
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
CN113078116B (en) * 2021-03-29 2024-01-23 长鑫存储技术有限公司 Method for preparing semiconductor structure and semiconductor structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4737829A (en) * 1985-03-28 1988-04-12 Nec Corporation Dynamic random access memory device having a plurality of one-transistor type memory cells
JPS62298156A (en) * 1986-06-18 1987-12-25 Matsushita Electric Ind Co Ltd Semiconductor memory
US4959698A (en) * 1986-10-08 1990-09-25 Mitsubishi Denki Kabushiki Kaisha Memory cell of a semiconductor memory device
US4763180A (en) * 1986-12-22 1988-08-09 International Business Machines Corporation Method and structure for a high density VMOS dynamic ram array
JPS63170955A (en) * 1987-01-09 1988-07-14 Sony Corp Semiconductor storage device
JPS63245954A (en) * 1987-04-01 1988-10-13 Hitachi Ltd Semiconductor memory
JPH0815208B2 (en) * 1987-07-01 1996-02-14 三菱電機株式会社 Semiconductor memory device
DE3741186A1 (en) * 1987-12-04 1989-06-15 Siemens Ag Three-dimensional single-transistor cell, and arrangement of single-transistor cells for dynamic semiconductor memories, and method for producing them
KR910000246B1 (en) * 1988-02-15 1991-01-23 삼성전자 주식회사 Semiconductor memory device
JPH07109875B2 (en) * 1988-08-31 1995-11-22 株式会社東芝 Dynamic memory
US4894697A (en) * 1988-10-31 1990-01-16 International Business Machines Corporation Ultra dense dram cell and its method of fabrication
JPH0379073A (en) * 1989-08-22 1991-04-04 Toshiba Corp Semiconductor memory
TW313677B (en) * 1991-08-14 1997-08-21 Gold Star Electronics

Also Published As

Publication number Publication date
WO1997044826A1 (en) 1997-11-27
DE19620625C1 (en) 1997-10-23

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees