JPS63170955A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To arrange a region in contact with a bit line, a memory element and an element-isolation region highly densely and to prevent a harmful influence due to alpha rays from occurring by a method wherein the region in contact with the bit line, the memory device and the element-isolation region are arranged in succession in the direction of the bit line while a word line of other adjacent memory elements is formed in the direction of the word line in the device-isolation region. CONSTITUTION:At a semiconductor storage device, a region 15 in contact with an Al layer 41 acting as a bit line, a memory element composed of a transistor 13 and of a capacitor 12 and a element-isolation region 16 are arranged in succession in the direction of the bit line. A polycrystalline silicon layer 33 acting as a word line to control the adjacent memory element is formed on the element-isolation region 16; by the polycrystalline silicon layer 33 constructed in this manner, the positional relation of the memory element in the direction of the word line is inclined; as a result, it is possible to prevent a punch-through effectively. By this method, a highly dense element is realized; it is possible to prevent alpha rays or the like effectively; the element can be structured uniformly.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C8 Prior art (Figs. 5 to 8) D0 Problems to be solved by the invention E0 Means for solving the problems F0 Effects G, Examples G- ■ Example of the structure of the semiconductor memory device of the embodiment (FIGS. 1 and 2) G-■ Example of its process (FIGS. 3a to 3n) G-■ Examples of other processes (FIG. 4a) ~Figure 4 d) G-■ Characteristics of the semiconductor memory device of the embodiment H0 Effects of the invention A, Industrial field of application The present invention is based on a matrix of memory elements having one transistor and one capacitor in the vertical direction. Arranged so-called DRAM (Guinaminok Random Access
(memory) and other semiconductor storage devices.

B0 Summary of the Invention The present invention provides a semiconductor device tα12 in which memory elements including one transistor and one capacitor are vertically arranged in a matrix, and a contact region with a bit line, the memory element, and an inter-element By sequentially arranging isolation regions in each bit line direction, and arranging the word lines of other memory elements adjacent in the word line direction on the inter-element isolation regions, each memory element can be arranged with high density. Moreover, interference between memory elements can be effectively prevented.

C1 Prior Art In the past, a large number of DRAM cell structures have been devised.

Here, a representative example of a conventional general RAM will be briefly described with reference to FIGS. 5 to 8.

FIG. 5 is a sectional view of the first conventional example, and FIG. 6 is a plan view thereof. As shown in FIG. 5, the first conventional DRA
The structure of M is a trench type capacitor 10 on a semiconductor substrate 101.
2 is formed, and the lower electrode 103 of the capacitor 102
extend to the surface of the substrate and form the source/drain regions of the transistor 104. As shown in FIG. 6, each memory element consisting of one transistor 104 and one capacitor 102 is wired with a pin line 105 and a word line 107, and is connected in the bit line direction (X in the figure).
A pair of memory cell elements are arranged symmetrically with respect to a contact portion 106 with a bit line 105 as the center.

Further, FIG. 7 is a sectional view of the second conventional example, and FIG. 8 is a plan view thereof. As shown in FIG. 7, the structure of the second conventional DRAM consists of a transistor 121 and a capacitor 1.
22 are arranged in the vertical direction, and the P half-type semiconductor substrate 1
An N half-type high concentration impurity region 124 formed at the boundary between the transistor 120 and the P- type epitaxial growth layer 123 serves as the source/drain region of the transistor 121 and is connected to the electrode portion of the capacitor 122 . The bit line is an N-type high concentration impurity region 125 formed on the surface,
The word line is the gate electrode 126 of transistor 121. FIG. 8 shows a planar layout of this second conventional example, in which memory elements in which transistors 121 and capacitors 122 are arranged vertically are arranged in a matrix.

Problems to be Solved by the D0 Invention However, in the conventional examples as described above, the following problems may occur.

First, in the first conventional semiconductor memory device shown in FIGS. 5 and 6, the charge that becomes the memory content is accumulated in the lower electrode 103 of the capacitor 102, and in this way, the charge is accumulated on the substrate side. Therefore, it is vulnerable to alpha rays. Furthermore, since a pair of memory elements are arranged facing each other, the distance d between the lower electrodes 103 of adjacent capacitors is short, and punch-through between them becomes a problem. Further, the gate electrode of the transistor 104 is a second polycrystalline silicon layer (2nd Polyst), and the channel length is not easy to control due to steps etc., and variations are likely to occur.
Furthermore, although the groove portion is formed by the element #region and the self-alignment line, the capacitance value of the capacitor 102 of each memory element varies depending on the accuracy of mask alignment during manufacturing.

Next, in the second conventional semiconductor memory device shown in FIGS. 7 and 8, the charge is stored inside the capacitor 122, and the structure is resistant to alpha rays. N+ type high concentration impurity region 125, which is a bit line, is
If the distance between the bit lines is shortened, punch-through becomes a problem, and since the bit line is an N-type high concentration impurity region 125, C (capacitance) and R (
resistance) cannot be made small, which is disadvantageous to speeding up. Further, it is difficult to use a folded pinot structure, and it is not easy to compensate for variations in elements, which increases the burden on sense amplifiers and the like.

Therefore, in view of the above-mentioned problems, the present invention arranges each memory element at high density without interference between adjacent memory elements,
Another object of the present invention is to provide a semiconductor memory device that prevents the harmful effects of α rays and has less variation between memory elements.

Means for Solving Problem E1 The present invention provides a semiconductor memory device in which memory elements each consisting of one transistor and one capacitor are arranged in a matrix in the vertical direction of a semiconductor substrate.
A contact region with a focus line, the memory element, and an inter-element isolation region are sequentially arranged in the bit line direction, and
The above problem is solved by a semiconductor memory device characterized in that word lines of other memory elements adjacent in the word line direction are provided on the element isolation region.

F0 Effect The semiconductor memory device of the present invention is an improved type of the second conventional example (FIGS. 7 and 8), in which one transistor and one capacitor are arranged vertically. Therefore, the storage node (one side of the opposing electrode) side of the capacitor can be placed inside the groove, resulting in a structure that is strong against alpha rays. Since the contact region with the focus line, the memory element, and the element isolation region 9I are arranged in sequence in the bit line direction, the channel of the transistor constituting the memory element can be connected in the bit line direction. It can be provided only on the side of the contact region with the bit line, and since the contact GW region etc. are sequentially and continuously arranged along the bit line direction, the memory element is adjacent to the inter-element isolation region, The contact region is also adjacent to the next successive element isolation region, and the contact region and its memory element are completely isolated from each other while corresponding to each other. Furthermore, in the present invention, a word line is formed on the element isolation region, but with such a structure, memory elements adjacent to each other in the word line direction are arranged diagonally. The distance is large enough to operate satisfactorily even when the elements are arranged in a particularly high density.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

G-■ Structural example of the semiconductor memory device of the embodiment (FIGS. 1 and 2) The semiconductor memory device of the present embodiment has the structure shown in FIGS. 1 and 2. This allows memory elements to be arranged at high density.

First, in the semiconductor memory device of this embodiment, as shown in FIG. is formed.

The groove-type capacitor 12 has a structure in which charges serving as memory contents are accumulated in the groove internal electrode 21 inside the groove.
A dielectric film 22 such as an oxide film is formed on the outside of the groove internal electrode 21, and a P-type impurity jJ is formed on the outside of the dielectric film 22.
A capacitor lower electrode 23 consisting of a region is formed.

A portion of the groove internal electrode 21 directly below the gate electrode 31 of the transistor 13 is taken out to form an N-half type high concentration impurity region 24, which is used as the source/drain region of the transistor 13. There is.

In this way, the semiconductor memory device of this embodiment has one vertical direction.
Two capacitors 12 and one transistor 13 are arranged to form a memory element, and an N-half type high concentration impurity region 24 for electrically connecting the capacitor 12 and transistor 13 is connected to a bit line as described later. It is formed only in one direction. Therefore, in the semiconductor memory device of this embodiment, the distance between the N-type high-concentration impurity regions 24 can be particularly large, effectively preventing the punch-through phenomenon, and allowing memory elements to be arranged at high density. be able to.

The transistor 13 controls the movement of charge to the capantor 12 by a switching operation, and in this embodiment is formed above the carrier bank 12, with its channel directed vertically. One of the source/drain regions is an N-type high concentration impurity region 24 taken out from the capacitor 12 and formed only in one direction in the bit line direction, while the other source/drain region is a P- type. This is an N-half type high concentration impurity region 31 formed on the surface of the same P- type epitaxially grown N14 layered on the semiconductor substrate 11, and this N half type high concentration impurity region 31 simultaneously serves as a bit line A1. It is connected to layer 41 through contact hole 42 . The gate electrode of this transistor 13 is a polycrystalline silicon layer 32 which is a word line, and this polycrystalline silicon layer 32 is formed in a direction perpendicular to the Aa layer 41 which is a bit line. A polycrystalline silicon layer 32 serving as a gate electrode of the transistor 13 is formed by digging a groove in a part of the upper part of the capacitor 12 and filling the groove. As will be described later, this polycrystalline silicon layer 32 is formed so as to pass over the # region by the amount of memory elements adjacent in the word line direction.

The semiconductor memory device of this embodiment having such a memory element has bit lines A and N as shown in FIG.
contact region 15 with layer 41 and said transistor 1
3 and a capacitor 12, and an element isolation region 16 are arranged in sequence in the bit line direction. That is, in the bit line direction, the contact region 15°, the memory element 9, the inter-element isolation region 16. Contact area 15. Memory element, inter-element isolation region 16.・・・
・They are formed sequentially and sequentially. By adopting such an arrangement, the semiconductor memory device of this embodiment has the high concentration impurity region 24 formed only in one direction in the bit line direction, and the distance between the impurity regions can be increased. The punch-through phenomenon can be effectively prevented, and memory elements can be arranged at high density. Further, the distance between the contact Hff region 15 itself and other impurity regions can be increased, and the punch-through phenomenon can be similarly effectively prevented, and memory elements can be arranged at high density.

Here, the contact region 15 adjacent to the memory element is
In this case, the A1 layer 41 as a bit line is connected to the transistor 1.
This is a region for connecting to the N-type high concentration impurity region 31 which is the source/drain region of No. 3.

Further, the inter-element isolation regions 16 are formed sequentially in the bit line direction as described above, but in terms of planar layout, as will be described later, the regions other than the memory element and the contact sJl region 15 are This becomes the inter-element isolation region 16, and effective isolation between elements is performed. and,
A polycrystalline silicon layer 33 serving as a word line for controlling adjacent memory elements is formed on this inter-element isolation region 16, and due to the structure of such polycrystalline silicon I'i33, The positional relationship of the memory elements is diagonal, and punch-through is effectively prevented. Note that these word lines are polycrystalline silicon FM.
i32 and 33 are each covered with an interlayer insulating layer.

Next, regarding the planar layout of this embodiment,
This will be explained with reference to FIG.

In the planar layout of this embodiment, as shown in FIG. 2, the memory elements 17 are arranged vertically and horizontally, that is, in a matrix, and in the bit line direction indicated by the X direction in the figure, the contact regions 15 and , the memory element 17;
Inter-element isolation regions 16 are sequentially arranged. and,
In the word line direction indicated by the Y direction in the figure, each memory element 17 connected to an adjacent bit line is shifted by half of the area of one memory cell in the X direction in the figure. , the word line 18 that is used as the gate electrode of every other transistor and passes through the memory cells that are not used as the gate electrode is
It is arranged so that it passes over 6. Note that the bit line 19 is commonly used by memory elements 17 adjacent in the X direction in the figure.

The features of this embodiment having such a planar layout are as follows:
Each memory element 17 is formed independently, which is different from the above-described first conventional example in which a pair of memory elements are combined and arranged. The N-type high-concentration impurity region of the transistor, where punch-through is a problem, is formed only in one direction in the bit line direction of the capacitor 12 as described above, and is formed in each memory element 1.
This corresponds to the area between the contact area 7 and the contact area 16.

Therefore, the N+ type high concentration impurity regions where punch-through is a problem are arranged at the most dispersed positions on the planar layout, punch-through is effectively prevented, and elements can be arranged at high density. becomes possible.

G-■ Example of process (FIGS. 3a to 3n) Next, an example of the process of the semiconductor memory device of this embodiment will be described with reference to FIGS. 3a to 3n.

(a) As shown in FIG. 3a, an oxide film 51 is formed on the entire surface of a P-type semiconductor substrate 50, for example, and then a groove 52 is formed by anisotropic etching. This groove 5
Part 2 will later become a capacitor.

After the trench 52 is formed, a P+ type impurity region 53 that will become the capacitor lower electrode is formed. The concentration is, for example, 10”~
The concentration is about 101101e.

(bl After forming the P+ type impurity region 53 that will become the capacitor lower electrode, sacrificial oxidation, etching, etc. are performed,
Oxide film 51 is removed. A dielectric layer 54 is then formed as shown in FIG. The film thickness is, for example, 100
It is about the size of a person. This dielectric layer 54 is formed by forming an oxide film on the surface of the groove 52, but a nitride film may also be formed to improve the dielectric constant. and,
After forming the dielectric N54, the /1I52 is filled with polycrystalline silicon N55 containing impurities such as phosphorus. This polycrystalline silicon Ji 55 becomes one of the opposing electrodes of a capacitor in which charge is accumulated and the charge becomes the memory content.

Note that this polycrystalline silicon layer 55 is etched back to have a predetermined size and a flat surface.

fcl Next, as shown in FIG. 3C, a photoresist 56 is formed to form a window 57 for forming a high concentration impurity region for taking out the capacitor. In this embodiment, this window 57 is important because it is formed only in one portion of the capacitor and the high concentration impurity region is formed only in one direction along the bit line direction. After forming the window 57 of this photoresist 56, a portion of the dielectric film 54 on the semiconductor substrate 50 exposed through the window 57 exists between the polycrystalline silicon layer 55 and the semiconductor substrate 5.0. A portion of the dielectric film 54 is removed. By removing a portion of the dielectric 1!54 on the top and side surfaces of the semiconductor substrate 50, a portion of the semiconductor substrate 50 is exposed.

(d) After exposing a part of the semiconductor substrate in this way, the photoresist 56 is removed, and a polycrystalline silicon layer 58 containing phosphorus is formed on the entire surface as shown in FIG. 3d. . The thickness of this polycrystalline silicon layer 58 can be approximately 0.1 μm.

By removing the oxide film 54 through the window 57, the phosphorus-containing polycrystalline silicon layer 58 adheres to the exposed part of the semiconductor substrate, and further covers the removed part of the dielectric film 54. Fill. Then, using this polycrystalline silicon IW 58 as a diffusion source, an N-type high concentration impurity region 59 is formed in a part of the exposed semiconductor substrate. This N-type high concentration impurity region 59 functions as a lead-out portion of the capacitor and becomes one of the source and drain regions of the transistor. Here, the N-type high concentration impurity region 59 is formed only on one side especially when viewed from the capacitor, and punch-through can be effectively prevented later.

te+ Next, as shown in FIG. 3e, the phosphorus-containing polycrystalline silicon layer 58 is removed except for the portion filled with a portion of the removed dielectric film 54. Then, as shown in FIG. By forming the N-type high-concentration impurity region 59 as described above and partially remaining the polycrystalline silicon layer 58, the portion taken out from the polycrystalline silicon [55] which becomes the capacitor upper electrode is formed. Become. The extracted portions of the N-type high concentration impurity region 59 and the like are formed only in one direction in the bit line direction of the capacitor, which is suitable for high density.

(fl Next, as shown in FIG. 3f, the semiconductor substrate 5
The dielectric layer 54 on top of the dielectric layer 54 is removed and the surface is planarized. In the figure, the extracted portions of the N-type high concentration impurity region 59 and the like are shown integrally with the polycrystalline silicon layer 55.

(g+ After flattening the surface, as shown in FIG. 3g, the surfaces of the polycrystalline silicon layer 55 and the semiconductor substrate 50 are oxidized to form an oxide film 60. The thickness of the upper oxide film 60 is the same as that of the semiconductor substrate 5.
It is approximately four to five times thicker than the thickness of the oxide film 60 on the top surface.

(h) A thick oxide film 60 is formed on the polycrystalline silicon layer 55 (
Taking advantage of this fact, the interlayer insulating layer remains only on the polycrystalline silicon layer 55. That is, as shown in the third diagram, by removing the oxide film 11a60 on the entire surface, the oxide film 60 is left only on the polycrystalline silicon layer 55 due to the thickness of each part.

This oxide film 60 becomes part of the insulating film between the capacitor and the transistor.

++1 Next, as shown in FIG. 3i, a P- type epitaxial growth layer 61 is grown over the entire surface. The impurity concentration of this P-type epitaxial growth layer 61 can be approximately the same as that of the P-type semiconductor substrate 50, and therefore its crystallinity can be made good. Subsequently, a bad oxide film 62 is formed, and CVD
Silicon nitride 11963 is formed by the method.

fil Next, as shown in FIG. 3J, a field oxide film (so-called LOGO3 film) 64 is formed, and a portion of this field oxide film 64 will function as an inter-element isolation region. In addition, silicon nitride film 6 as an oxidation-resistant film
The region below 3 is not oxidized and will later form transistor and contact regions. Note that when forming the field oxide film 64, ions such as boron are implanted for channel stop.

(kl) Next, as shown in FIG. 3k, the silicon nitride 11163, the pad oxide film 62, and the epitaxial growth layer 61 are etched, and 'a65' is formed in a part of the epitaxial growth layer 61. The groove 65 is a groove for forming a control transistor of the memory element, and is a groove for burying a gate electrode.

(11) After forming the trench 65 for burying the gate electrode, the silicon nitride film 63 that remains partially
is removed to form an oxide film 66 that will become the gate of the transistor. With this oxide film 66, the inner wall of the groove 65 is covered with an oxide film.

Then, as shown in FIG. 3, a polycrystalline silicon layer 67 containing phosphorus or the like is formed over the entire surface.

By forming the polycrystalline silicon layer 67 over the entire surface, the groove 65 is filled with the polycrystalline silicon layer 67 . By filling the trench 65 with the polycrystalline silicon layer 67 in this way, the gate electrode of the transistor is formed, and the structure of the memory element of the semiconductor storage device is such that the capacitor and the transistor are arranged vertically. become something that

(E) As shown in FIG. 3m, after forming the polycrystalline silicon layer 67, this polycrystalline silicon layer 67 is buttered,
It is shaped into a word line and a gate Th pole of a transistor. At this time, when comparing the word line pattern shapes of two adjacent memory elements in the word line direction (that is, the normal direction of the cross section in the figure), it was found that one element was used as a gate electrode. The polycrystalline silicon layer 67 exists on the field oxide film 64 in the other element, and the polycrystalline silicon layer 67 that existed on the field oxide film 64 in one element is wired to become a gate electrode in the other element. That will happen. Further, the plane pattern becomes a slightly meandering pattern as shown in FIG. 2 for one word line.

After forming the polycrystalline silicon layer 67 used as the word line, the surface of the polycrystalline silicon N67 is oxidized and covered with the oxide film. Then, ions of arsenic, for example, are implanted into the entire surface to form N-type high concentration impurity regions 68 which function as contacts and source/drain regions of transistors of the memory element. Due to the formation of this N-type high-concentration impurity region 68, the channel direction of the transistor of the memory element becomes vertical. The impurity regions 59 function as source and drain regions of the transistor, respectively.

+n1 Next, a reflow film such as BPSG is formed on the entire surface including the N-type high concentration impurity region 68 serving as a contact region, and this reflow film is reflowed. Then, a contact hole 69 is opened above the N-type high concentration impurity region 68, and the N half-type high concentration impurity region 68 is exposed. Then, as shown in FIG. 3n, an A1 layer 70 as a bit line is formed, and a predetermined semiconductor memory device is completed.

G-■ Examples of other processes (FIGS. 4a to 4d) The semiconductor memory device of this embodiment can also be manufactured by the processes shown in FIGS. 4a to 4d. can.

(a) First, a field oxide film 81 is formed in advance on the surface of the semiconductor substrate 80, which will become the gI region by the amount of elements, by using a selective oxidation method or the like, and after an oxide film 82 is further formed on the surface, the capacitors and transistors are removed. A trench 83 is formed in a region where a memory element is to be formed. In this groove 83,
For example, a BSG film 84 is filled and etched to a predetermined height. Then, as shown in Figure 4a,
Using this BSG film 84 as a diffusion source, a P-type high-concentration impurity region 85 which becomes a cavacic lower electrode is formed on the side wall of the groove 83.

Next, as shown in FIG. 4, the BSG film 84 is removed, a capacitor dielectric film 86 is formed on the inner wall of the trench 83, and a capacitor upper trench is formed inside the dielectric film 86. Functional phosphorus-containing polycrystalline silicon layer 87
is formed. This polycrystalline silicon layer 87 is etched back to predetermined dimensions. Then, the surface portion of the polycrystalline silicon layer 87 is oxidized.

(C1 Next, a portion where a high concentration impurity region will be formed is opened. At the time of this opening, a portion of the dielectric film 86 between the polycrystalline silicon layer 87 and the semiconductor substrate 80 is also removed. Then, this opening portion a phosphorus-containing polycrystalline silicon layer with a thickness of approximately 0.1 μm is deposited through the
This polycrystalline silicon layer containing phosphorus is approximately 0.1μ
m Have sex back. Then, the polycrystalline silicon layer remains in the portion of the dielectric film 86 that has been partially removed, and by performing impurity diffusion using this remaining polycrystalline silicon layer, the process shown in FIG. 4C is performed. As shown,
N serves as an extraction part for the upper electrode of the capacitor.
A green high concentration impurity region 88 is formed.

Here, this N-type high concentration impurity region 88 is formed only on one side of the capacitor, and therefore punch-through between memory elements is effectively prevented. next,
Remove unnecessary silicon oxide film, perform gate oxidation,
An oxide film 89 is formed on the inner wall of the groove 83.

+dl Next, a polycrystalline silicon layer 90 containing phosphorus, which will become a word line, is formed and selectively removed to form a predetermined pattern. After patterning this word line,
An oxide film is formed on the polycrystalline silicon layer 90, and then,
As shown in FIG. 4d, for example, by implanting arsenic ions,
An N-type high concentration impurity region 91 is formed. This N-type high concentration impurity region 91 becomes a contact region and also functions as a source/drain region of the transistor.

After forming a glue flow film such as a BPSG film, the reflow film is reflowed to form the N-type high concentration impurity region 91.
The upper insulating film is removed and an A4 layer serving as a bit line is formed to complete the semiconductor memory device.

G-■ Characteristics of the semiconductor memory device of the embodiment The semiconductor memory device as described above first has a structure in which a contact region with a bit line, the memory element, and an isolation region between elements are sequentially arranged in the bit line direction. Due to this structure, the N-type high concentration impurity region 24 shown in FIG. 1 (not shown in FIG. This corresponds to the N type high concentration impurity region 88.

) can be formed only on one side of the capacitor. Since the N-type high-concentration impurity regions 24 and the like are formed only in one direction in the bit line direction, the high-4 degree impurity regions are also dispersed in the layout shed, resulting in interference with adjacent elements. Punch-through between the elements can be effectively prevented, and therefore there is no problem even if the elements are arranged in a highly dense manner. Furthermore, this structure can also suppress variations between memory elements.

Furthermore, memory elements adjacent in the word line direction (Y direction in FIG. 2) have a structure in which one gate electrode is disposed over the other element's area t='tJ Tii,
Therefore, the memory elements are arranged diagonally between adjacent memory elements with respect to the word line direction, and a distance relative to the density of the memory elements can be increased.

Furthermore, by minimizing the trenches of the transistor formed in the epitaxial growth layer 61, the size of the transistor itself can be reduced, and the density of the semiconductor device can be further increased. can.

Further, as described above, the storage side of the capacitor 12 is connected to the inside of the groove W.
i21, and therefore has a structure that is resistant to α rays and the like.

Further, even when the epitaxially grown layers 61 described above are stacked, the impurity concentration of the epitaxially grown Fi 61 can be made approximately the same as that of the semiconductor substrate, and misfit can be prevented and crystallinity can be improved. .

In addition, it is easy to configure a hold bit line,
Another feature is that the A4 layer can be used for the bit line.

H3 Effects of the Invention The semiconductor memory device of the present invention, having the above-described structure, can effectively prevent punch-through and the like and achieve higher density of elements. Furthermore, it can effectively prevent alpha rays, etc., and has a structure that is resistant to variations in elements.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an example of the semiconductor memory device of the present invention, and FIG.
The figure is a plan view, FIGS. 3a to 3n are cross-sectional views for explaining an example of the semiconductor memory device of the present invention according to the process, and FIGS. 4a to 4d are semiconductor memory devices of the present invention. FIGS. 3A and 3B are cross-sectional views for explaining an example of the apparatus according to another process. FIGS. 5 is a sectional view of the first conventional example, FIG. 6 is a plan view thereof, FIG. 7 is a sectional view of the second conventional example, and FIG. 8 is a plan view thereof. 11... Semiconductor substrate 12... Capacitor 13... Transistor 14... Epitaxial growth layer 15... Contact region 16... Inter-element isolation region 21... In-groove electrode 22... Dielectric film 23...Capacitor lower electrode 24...High concentration impurity region 31...High concentration impurity region 32...Polycrystalline silicon N (word line) 41...A
1st layer (bit line) Patent agent Sony Corporation agent Patent attorney Koike Mima Sakae Tamura - Figure 3 a Figure 3 C Figure 3 - Figure 3 d Figure 3 e Figure 3 9 Figure 3 Fig. f Fig. 3 h Swamp 8 Fig. 4 a Fig. 4 S Fig. 4 C Fig. 4 d Example of secondary channel of sacrifice 1 Fig. 5 v Figure 1: 1 distortion; Le 2's Ishiba Takami 4 Crits Figure 8

Claims (1)

[Scope of Claims] A semiconductor memory device in which memory elements each consisting of one transistor and one capacitor arranged in the vertical direction of a semiconductor substrate are arranged in a matrix, comprising: a contact region with a bit line, and the memory element; and an inter-element isolation region are arranged sequentially in the bit line direction, and
A semiconductor memory device characterized in that a word line of another memory element adjacent in the word line direction is provided on the element isolation region.