JPS5667959A - Mos dynamic random access memory - Google Patents
Mos dynamic random access memoryInfo
- Publication number
- JPS5667959A JPS5667959A JP14347679A JP14347679A JPS5667959A JP S5667959 A JPS5667959 A JP S5667959A JP 14347679 A JP14347679 A JP 14347679A JP 14347679 A JP14347679 A JP 14347679A JP S5667959 A JPS5667959 A JP S5667959A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- mos
- capacitance
- layer polysilicon
- constituting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To prevent unequality of a cell capacitance by a method wherein a separating gate is used to separate a word line of an MOS dynamic RAM from a memory cell and an MOS capacitance is constituted with the 2nd layer polysilicon gate. CONSTITUTION:An 1-transistor 1-capacitor type memory cell consists of an N<+> diffusion area 11 constituting a bit line, the 1st layer polysilicon gate 12 constituting a word line, a separating gate 16 wherein a VSS voltage is applied to separate each memory cell one another, the 2nd layer polysilicon gate 13 constituting an MOS capacitor and a gate oxide film 14. And during the 1st layer polysilicon gate being formed, each of the gate are of a transfer transistor, the area of an MOS capacitor and the area of an N<+> diffusion layer is decided and they are equal without depending upon an error of a mask matching, thus, resulting in each equal cell capacitance and each equal bit line capacitance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14347679A JPS5667959A (en) | 1979-11-05 | 1979-11-05 | Mos dynamic random access memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14347679A JPS5667959A (en) | 1979-11-05 | 1979-11-05 | Mos dynamic random access memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5667959A true JPS5667959A (en) | 1981-06-08 |
Family
ID=15339578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14347679A Pending JPS5667959A (en) | 1979-11-05 | 1979-11-05 | Mos dynamic random access memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5667959A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH022666A (en) * | 1987-12-23 | 1990-01-08 | Texas Instr Inc <Ti> | Mos transistor having improved resolution |
JPH02153565A (en) * | 1988-07-08 | 1990-06-13 | Mitsubishi Electric Corp | Semiconductor memory device |
JP2001036034A (en) * | 1999-07-19 | 2001-02-09 | Hitachi Ltd | Semiconductor device and its manufacture |
-
1979
- 1979-11-05 JP JP14347679A patent/JPS5667959A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH022666A (en) * | 1987-12-23 | 1990-01-08 | Texas Instr Inc <Ti> | Mos transistor having improved resolution |
JPH02153565A (en) * | 1988-07-08 | 1990-06-13 | Mitsubishi Electric Corp | Semiconductor memory device |
JP2001036034A (en) * | 1999-07-19 | 2001-02-09 | Hitachi Ltd | Semiconductor device and its manufacture |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Shah et al. | A 4-Mbit DRAM with trench-transistor cell | |
ATE222403T1 (en) | DRAM MEMORY CELL HAVING A VERTICAL TRANSISTOR AND METHOD FOR PRODUCING THE SAME | |
JPS5723261A (en) | Semiconductor memory | |
US5572461A (en) | Static random access memory cell having a capacitor and a capacitor charge maintenance circuit | |
KR920008929A (en) | Semiconductor Memory and Manufacturing Method | |
KR840000083A (en) | Semiconductor memory | |
JPS5718356A (en) | Semiconductor memory storage | |
US4388121A (en) | Reduced field implant for dynamic memory cell array | |
JPS5667959A (en) | Mos dynamic random access memory | |
JPS5519820A (en) | Semiconductor device | |
HK125595A (en) | Memory cell design for dynamic semiconductor memories | |
JPS5451429A (en) | Semiconductor memory device | |
US5960278A (en) | Method of manufacturing SRAM cell | |
JPS561559A (en) | One-transistor type dynamic memory cell | |
JPS59104161A (en) | 1-transistor type semiconductor memory | |
GB1530056A (en) | Semiconductor data storage matrices | |
JPS5491083A (en) | Integrated-circuit device | |
JPS6480066A (en) | Semiconductor integrated circuit device | |
KR100207287B1 (en) | Semiconductor device and fabrication method thereof | |
JPS55150267A (en) | Semiconductor memory cell | |
JPS5667958A (en) | Semiconductor memory system | |
JPS5667960A (en) | Mos dynamic random access memory | |
JPS583270A (en) | Semiconductor memory | |
JPS62107496A (en) | Semiconductor memory cell | |
JPS6425461A (en) | Semiconductor memory cell and manufacture thereof |