JPS5667958A - Semiconductor memory system - Google Patents

Semiconductor memory system

Info

Publication number
JPS5667958A
JPS5667958A JP14347579A JP14347579A JPS5667958A JP S5667958 A JPS5667958 A JP S5667958A JP 14347579 A JP14347579 A JP 14347579A JP 14347579 A JP14347579 A JP 14347579A JP S5667958 A JPS5667958 A JP S5667958A
Authority
JP
Japan
Prior art keywords
source
capacitor
capacitance
layer
proportional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14347579A
Other languages
Japanese (ja)
Other versions
JPS6349390B2 (en
Inventor
Koichiro Masuko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14347579A priority Critical patent/JPS5667958A/en
Publication of JPS5667958A publication Critical patent/JPS5667958A/en
Publication of JPS6349390B2 publication Critical patent/JPS6349390B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To prevent a software error by making a capacitance of a capacitor great by a method wherein a peripheral length of an inversion layer or a diffusion layer of an 1-transistor 1-capacitor type MOS dynamic RAM is made long. CONSTITUTION:The magnitude of charge stored at an MOS dynamic RAM is proportional to the sum of each capacitance of a capacitor formed with an MOS transistor source and a power source wire, a capacitor which is formed with a depletion layer between a source and a substrate, and a capacitor which is formed with a depletion layer between a source and a channel stopper layer. And further, a capacitance between a source and a channel stopper layer is proportional to the peripheral length of a source, as a result, if the peripheral pattern of a source 6 is made mutually to enter retaining the minimum allowable intervals prescribed by a design standard, the capacitance of a capacitor for the information memory use can be increased without changing the dimension of a chip.
JP14347579A 1979-11-05 1979-11-05 Semiconductor memory system Granted JPS5667958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14347579A JPS5667958A (en) 1979-11-05 1979-11-05 Semiconductor memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14347579A JPS5667958A (en) 1979-11-05 1979-11-05 Semiconductor memory system

Publications (2)

Publication Number Publication Date
JPS5667958A true JPS5667958A (en) 1981-06-08
JPS6349390B2 JPS6349390B2 (en) 1988-10-04

Family

ID=15339556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14347579A Granted JPS5667958A (en) 1979-11-05 1979-11-05 Semiconductor memory system

Country Status (1)

Country Link
JP (1) JPS5667958A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2577338A1 (en) * 1985-02-12 1986-08-14 Eurotechnique Sa METHOD FOR MANUFACTURING A DYNAMIC MEMORY IN INTEGRATED CIRCUIT AND MEMORY OBTAINED BY THIS METHOD
US10455875B2 (en) 2007-06-06 2019-10-29 Higher Dimension Materials, Inc. Cut, abrasion and/or puncture resistant knitted gloves

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2577338A1 (en) * 1985-02-12 1986-08-14 Eurotechnique Sa METHOD FOR MANUFACTURING A DYNAMIC MEMORY IN INTEGRATED CIRCUIT AND MEMORY OBTAINED BY THIS METHOD
US4888628A (en) * 1985-02-12 1989-12-19 Eurotechnique Dynamic memory in integrated circuit form
US10455875B2 (en) 2007-06-06 2019-10-29 Higher Dimension Materials, Inc. Cut, abrasion and/or puncture resistant knitted gloves

Also Published As

Publication number Publication date
JPS6349390B2 (en) 1988-10-04

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