KR100207287B1 - Semiconductor device and fabrication method thereof - Google Patents

Abstract

An object of the present invention is to provide a ram cell having four transistors. One RAM cell includes a write pass transistor, a storage transistor, a read pass transistor, and a charge transistor. In the write pass transistor, a gate electrode is connected to a write word line, a drain electrode is connected to a write bit line, and a source positive electrode is connected to a gate electrode of a storage transistor. It is also connected to the electrode. In the read pass transistor, the gate electrode is connected to the read word line, the drain electrode is connected to the read bit line, and the source electrode is connected to the drain electrode of the storage transistor. In the storage transistor, the source electrode is connected to Vss, the charge transistor is connected to the source electrode of the write transistor and the gate electrode of the storage transistor, while the gate electrode is also connected to the source electrode of the charge transistor, and the drain electrode of the charge transistor. Is connected to a constant power line.

Description

Semiconductor device and manufacturing method

1 is a circuit diagram of a DRAM cell having three transistors according to a conventional embodiment.

2 is a circuit diagram of a DRAM cell having four transistors according to an embodiment of the present invention.

3 is a plan view of a DRAM cell having four transistors of FIG.

(A) and (b) of FIG. 4 show a method of manufacturing the DRAM cell shown in the plan view of FIG. 3, which is taken along a cut line X-X '.

* Explanation of symbols for main parts of the drawings

M1: Write pass transistor M2: Storage transistor

a1 4a: gate electrode of the write pass transistor

a2,5a2: Drain electrode of write pass transistor

a3,5a3: source electrode of the write pass transistor

b1,4b: gate electrode of the storage transistor

b2,5b2: Drain electrode of storage transistor

b3,5b3: source electrode of the storage transistor

M3: read-pass transistor P: charge transistor

c1, 4c: gate electrode of the read pass transistor

c2,5c2: Drain electrode of read pass transistor

c3,5c3: source electrode of read pass transistor

f1,4f; Gate electrode of charge transistor

f2,5f2: Drain electrode of charging transistor

f3,5f3 Source electrode A of charge transistor A: Active mask

G: gate mask 1: semiconductor substrate

2 device isolation insulating film 3 gate oxide film

6: interlayer insulating film 7a2,7a3,7b3,7c2: wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory semiconductor devices, and more particularly, to a memory semiconductor device having four transistors and a method of manufacturing the same.

Memory semiconductor devices are classified into static random access memory (SRAM) and dynamic random access memory (DRAM) according to memory protection. A DRAM is composed of one transistor and one capacitor, and is a memory in which information is stored by discharging charges on the capacitors, and the charges discharge over time. Therefore, in order to maintain data in DRAM, it must be refreshed within a certain time.

SRAM, on the other hand, uses flip-flops as a memory device, and its contents are preserved unless the power is turned off.

SRAM has two driver transistors, pull-down, two access transistors, two pull-up transistors, and two pull-up transistors. Consists of a high speed characteristic. SRAM's structure is divided into three types: full CMOS cell, high load resistor (HLR) cell, and thin film transistor (TFT) cell.

In general, a full CMOS RAM (six transistor cells) is widely used as a memory device used in a logic semiconductor device.

The full CMOS cell uses a P-channel bulk MOSFET as a pull-up device, the load resistor cell uses polysilicon with high resistance as a pull-up device, and the TFT cell is a pull-up device. As a cell, a P-channel polysilicon thin film transistor (TFT) is used.

Each of these cells has advantages and disadvantages of each other and can be selected and used depending on the intended use. In other words, a full CMOS SRAM cell has the best device characteristics and a simple process, but is used when a small amount of memory device is used in a logic semiconductor device due to its large cell size. Load resistors (HRL) and RAM SRAM cells are used in semiconductor memory devices, which are used exclusively for memory devices, because the device characteristics are weak and the process is complicated, while the cell size can be significantly reduced.

However, the full CMOS SRAM cell is the biggest disadvantage in ultra-high integration because the cell size is relatively large. On the other hand, 3T DRAMs with three transistors use separate read and write access ports, which can achieve high speed while reducing cell size to less than half compared to full CMOS SRAMs. Has an advantage.

In addition, the 3T DRAM cell is more than twice as large as a 1T DRAM cell, but the process is simple by using a single poly structure as in logic technology, and the signal transmission can be accelerated, and the read and write access is possible. The ports can be used separately, which makes them ideal for use in logic semiconductor devices.

1 is a circuit diagram of a conventional DRAM cell (3T DRAM CELL) having three transistors, where M1 represents a write pass transistor, M2 represents a storage transistor, and M3 represents a read pass transistor.

In the write pass transistor M1, the gate electrode al is connected to the write word line, the drain electrode a2 is connected to the write bit line, and the source electrode a3 is connected to the gate electrode b1 of the storage transistor. do.

In the read pass transistor M3, the gate electrode cl is connected to the read-only word line, the drain electrode c2 is connected to the read bit line, and the source electrode c3 is connected to the drain electrode b2 of the storage transistor M2. Connected.

The source electrode b3 of the storage transistor M is connected to Vss.

In the above-described 3T DRAM cell, when writing data to the cell, the write word line is accessed to turn on the pass transistor M1, and when the desired data is input through the write bit line, the data is stored by the cell node capacitance. . When reading the data of the cell, accessing the read word line and turning on the pass transistor M3 causes the gate of the storage transistor to be turned on or off depending on the cell node capacitance to read the data of the cell through the read bit line. Can be.

In such a 3T DRAM cell, the amount of charge stored in the cell node is reduced by a certain amount of leakage current after a certain amount of time, and the data is lost. To prevent this, the data is refreshed every predetermined time. do.

That is, the amount of charge stored in the cell node decreases after a certain period of time due to various types of leakage currents, so that the correct data cannot be read and is refreshed every several msec to tens of msec. Can not.

Accordingly, an object of the present invention is to provide a RAM cell structure capable of eliminating refresh of data used in a DRAM device by continuously supplying charges to a cell node by connecting a charging transistor to a gate electrode of the storage transistor.

Another object of the present invention is to provide a method of manufacturing a RAM cell that can minimize the area of a charging transistor added for eliminating the refresh operation.

In order to achieve the object of the present invention, a RAM cell includes one unit cell including a write pass transistor, a storage transistor, a read pass transistor, and a charge transistor.

The gate electrode of the write pass transistor is connected to the write word line, the drain electrode is connected to the write bit line, and the source electrode is connected to the gate electrode of the storage transistor while the gate electrode of the charge transistor and the charge transistor are connected. It is also connected to the source electrode.

The gate electrode of the read pass transistor is connected to the read word line, the drain electrode is connected to the read bit line, and the source electrode is connected to the drain electrode of the storage transistor.

The source electrode of the storage transistor is connected to Vss, the charge transistor is also connected to the source electrode of the write transistor and the source electrode of the storage transistor while the gate electrode is connected to the source electrode of the storage transistor. It is connected to a constant power line.

In the ram cell manufacturing method of the present invention for achieving the above-mentioned other objects, first, an element isolation insulating film is formed on a predetermined portion of a semiconductor substrate. Then, the gate electrode of the write pass transistor and the gate electrode of the charging transistor are formed in the same active region formed of the device isolation insulating film, and the gate electrode of the storage transistor and the read pass transistor are formed in the same active region formed of the adjacent device isolation insulating film. A gate electrode is formed. Subsequently, a source / drain electrode is formed, an interlayer insulating film is formed, and then a contact is formed in a predetermined region to form wiring.

Hereinafter, with reference to the accompanying drawings, a detailed description of the present invention will be described.

2 is a circuit diagram of a 4T RAM cell having four transistors in a unit cell according to an embodiment of the present invention.

One unit cell includes a write pass transistor M1, a storage transistor M2, a read pass transistor M3, and a charge transistor P.

In the write pass transistor M1, the gate electrode al is connected to the write word line, the drain electrode a2 is connected to the write bit line, and the source electrode a3 is connected to the gate electrode b1 of the storage transistor. The gate electrode f1 and the source electrode f3 of the charging transistor are also connected to each other.

In the read pass transistor M3, the gate electrode c1 is connected to the read word line, the drain electrode c2 is connected to the read bit line, and the source electrode c3 is connected to the drain electrode b2 of the storage transistor. do.

The source electrode b3 of the storage transistor M2 is connected to Vss.

The charging transistor P is also connected to the source electrode f3 of the charging transistor while the gate electrode f1 is connected to the source electrode a3 of the write pass transistor and the gate electrode b1 of the storage transistor. The drain electrode f2 of the charging transistor P is connected to a constant power line Vin. The potential applied to the drain of the charging transistor P is preferably greater than the threshold voltage of the charging transistor than the potential applied to the writing bit line.

The operation of the RAM cell configured as described above is as follows.

When writing data to a cell, the write word line is accessed to turn on the pass transistor M1, and when the desired data is input through the write bit line, the data is stored by the cell node capacitance, and at the same time, the charging transistor P is turned on. On, the charge is continuously supplied to the cell node through the power line Vin. Therefore, even when leakage current is generated in the cell node after the write pass transistor M1 is turned off, the charge is continuously supplied through the charging transistor P. Therefore, data is not lost even after a certain time, so the data need to be refreshed. There will be no.

FIG. 3 is a plan view showing a 4T ram cell according to an embodiment of the present invention, and FIGS. 4A and 4B illustrate a method of manufacturing the DRAM cell shown in the plan view of FIG. Sectional drawing cut along the line X-X '.

In FIG. 3, A is an active mask, C is a contact mask, G is a gate mask, M1 is a write pass transistor, P is a charge transistor, M2 is a storage transistor, M3 is a read pass transistor, and a2 is a write pass. Drain electrode a3 of transistor M1 represents a source electrode of M1, f1 represents a gate electrode of charging transistor P, and c2 represents a drain electrode of M3, respectively.

In the method of manufacturing a RAM cell including a 4T transistor as shown in FIG. 3, first, as shown in FIG. 4A, an element isolation insulating film 2 is formed on a predetermined portion of the semiconductor substrate 1. Thereafter, gate electrodes 4a, 4f, 4b, and 4c and source / drain electrodes 5a2, 5a3, 5f2, 5b3, 5b2, 5c3, and 5c2 are formed. Here, the gate electrode 4a of the write pass transistor M1 and the gate electrode 4f of the charge transistor P are formed in the same active region, and the gate electrode 4b of the storage transistor M2 and the gate electrode of the read pass transistor M3 ( 4c) is formed in another same active region. The drain electrode 5b2 of the storage transistor M2 and the source electrode 5c3 of the read pass transistor M3 are shared in the same region.

Next, as shown in (b), the interlayer insulating film 6 is formed on the entire surface, and contacts are formed in predetermined regions to form wirings 7a2, 7a3, 7f2, 7b3, and 7c2. The contacts formed on the source electrode 5a3 of the write pass transistor M1 and the gate electrode 4f of the charging transistor P can be shared as one contact.

As described above, the present invention increases the predetermined area to add one transistor compared to the conventional 3T DRAM cell, but the gate capacitance of the storage transistor used as the cell node may be minimized, thereby minimizing the area increase. have.

In addition, according to the present invention, the charge transistor is connected to the gate electrode of the storage transistor to continuously supply electric charges to the cell node, thereby eliminating data refresh, thereby improving the processing speed of the semiconductor device.

Although specific embodiments of the present invention have been described and illustrated herein, those skilled in the art can make modifications and variations. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (6)

A semiconductor device in which one unit cell includes four transistors, wherein the four transistors include a write pass transistor, a storage transistor, a read pass transistor, and a charge transistor, and the write pass transistor has a gate electrode written therein. A drain electrode is connected to a writing bit line, a source electrode is connected to a gate electrode of the storage transistor, and is also connected to a gate electrode of the charging transistor and a source electrode of the charging transistor, The read pass transistor has a gate electrode connected to a read word line, a drain electrode connected to a read bit line, a source electrode connected to a drain electrode of the storage transistor, and the storage transistor includes a source electrode connected to Vss. Fold The charge transistor has a gate electrode connected to a source electrode of the write pass transistor and a gate electrode of the storage transistor, and also a source electrode of the charge transistor, and a drain electrode connected to a constant power line. A semiconductor device, characterized in that. The semiconductor device according to claim 1, wherein the four transistors are N-MOS formed on a P-type semiconductor substrate. The semiconductor device according to claim 1, wherein the potential applied to the drain electrode of the charging transistor is larger than the threshold voltage of the charging transistor than the potential applied to the write bit line. Forming a device isolation insulating film on a predetermined portion of the semiconductor substrate; The gate electrode of the write pass transistor and the gate electrode of the charging transistor are formed in the same active region formed of the device isolation insulating film, and the gate electrode of the storage transistor and the gate electrode of the read pass transistor are formed in the same active region formed of the adjacent device isolation insulating film. Forming a; Forming a source / drain electrode; Forming an interlayer insulating film and forming a contact in a predetermined region to form wiring; The method of claim 4, wherein the drain electrode of the storage transistor and the source electrode of the read pass transistor are formed to be shared in the same region. The method of claim 4, wherein the contacts formed on the source electrode of the write pass transistor and the gate electrode of the charging transistor are formed to be shared as one contact.