US6261953B1 - Method of forming a copper oxide film to etch a copper surface evenly - Google Patents

Method of forming a copper oxide film to etch a copper surface evenly Download PDF

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US6261953B1
US6261953B1 US09/494,025 US49402500A US6261953B1 US 6261953 B1 US6261953 B1 US 6261953B1 US 49402500 A US49402500 A US 49402500A US 6261953 B1 US6261953 B1 US 6261953B1
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copper
film
wiring
oxide film
etching
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Yoshihiro Uozumi
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Toshiba Corp
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Toshiba Corp
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Priority to US09/865,569 priority Critical patent/US6475909B2/en
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Priority to US10/233,582 priority patent/US6818556B2/en
Priority to US10/976,758 priority patent/US7183203B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C22/00—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C22/05—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using aqueous solutions
    • C23C22/60—Chemical surface treatment of metallic material by reaction of the surface with a reactive liquid, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using aqueous solutions using alkaline aqueous solutions with pH greater than 8
    • C23C22/63—Treatment of copper or alloys based thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/0209—Cleaning of wafer backside
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation

Definitions

  • the present invention relates to a semiconductor device such as a semiconductor integrated circuit, a method of processing a copper film to be used for wiring of a semiconductor device such as a semiconductor integrated circuit and a method of producing a wiring structure for such a semiconductor device.
  • copper or a material essentially consisting of copper is used for wiring of a semiconductor device such as a semiconductor integrated circuit.
  • copper atoms can diffuse into an insulating film to enter the semiconductor substrate, which may result in malfunctioning of transistors.
  • a barrier metal layer of a titanium nitride, tantalum nitride, tungsten nitride or the like is often formed around the copper film to isolate the copper film from the insulating film.
  • FIG. 13A is a cross-sectional view showing the structure of a semiconductor substrate
  • wiring formed on a semiconductor substrate is normally buried in wiring grooves in an insulating film.
  • An inter-layer insulating film 101 is formed of silicon oxide on a semiconductor substrate 100 of silicon or the like where a semiconductor element (not shown) such as an integrated circuit is formed, and wiring grooves are formed in the surface of this inter-layer insulating film 101 .
  • a barrier metal layer 102 of TiN, TaN or the like is formed on the side wall of each wiring groove and a copper film 103 or an alloy film essentially consisting of copper is buried in the region surrounded by the barrier metal layer 102 .
  • the conventional wiring may allow copper in the wiring portion to be diffused into the inter-layer insulating film 101 from a portion where there is no barrier metal, i.e., from above, thereby adversely affecting the semiconductor element formed on the semiconductor substrate 100 .
  • the surfaces of the inter-layer insulating film 101 and the copper film 103 buried therein are planarized by CMP or the like, the pattern edges may not be detected at the time of implementing lithography, which may lead to deviation of the wiring pattern.
  • a barrier metal layer 104 may be buried in the recessed portion to cover the copper film 103 as shown in FIG. 13 C.
  • This structure has an advantage of suppressing the diffusion of copper from above the wiring. Further, forming the cap layer of a conductive material prevents copper from being placed in the etching environment at the time a via wiring (contact wiring) to the over-lying wiring is formed. This can reduce the possible occurrence of corrosion or etching-originated wiring disconnection.
  • Dry etching includes anisotropic etching called RIE (Reactive Ion Etching) and isotropic etching called CDE (Chemical Dry Etching), both of which can etch copper.
  • RIE Reactive Ion Etching
  • CDE Chemical Dry Etching
  • Copper is also soluble in an acid solution which is formed by mixing acid with aqueous hydrogen peroxide, ozone or oxygen, such as hydrochloric acid+aqueous hydrogen peroxide, hydrochloric acid+aqueous ozone or hydrofluoric acid+aqueous hydrogen peroxide.
  • copper is also etched by a material which forms a soluble complex with copper, such as ammonia, a material having an amino group (ethylene diamine or the like), cyanide (KCN or the like). Etching is often accelerated by mixing aqueous hydrogen peroxide or the like with those materials to provide an oxidizing property.
  • a mixed solution of aqueous ammonia and aqueous hydrogen peroxide and a mixed solution of hydrochloric acid and aqueous hydrogen peroxide are used as cleaning chemical solutions and are respectively called SC1 and SC2.
  • concentrations of aqueous ammonia, hydrochloric acid and aqueous hydrogen peroxide available on the market are often about 20 to 35%, and SC1 and SC2 are usually mixed with pure water in the volume ratio of about 1:1:5 to 1:1:7.
  • Jpn. Pat. Appln. KOKAI Publication No. 2-306631 proposes a method of carrying out implantation of oxygen ions in a copper film and then annealing the resultant structure or subjecting the structure to an oxygen plasma treatment to form a copper oxide, and then etching the copper oxide with diluted sulfuric acid or acetic acid.
  • Jpn. Pat. Appln. KOKAI Publication No. 2-306631 proposes a method of carrying out implantation of oxygen ions in a copper film and then annealing the resultant structure or subjecting the structure to an oxygen plasma treatment to form a copper oxide, and then etching the copper oxide with diluted sulfuric acid or acetic acid.
  • 10-233397 proposes a method of placing a copper film in the environment of oxygen (O 2 ) or ozone (O 3 ) in a diffusion furnace, an RTA furnace or an oven at room temperature or higher to thereby form a copper oxide film and then removing the copper oxide film by wet etching using diluted hydrochloric acid or diluted sulfuric acid, or dry etching or CMP.
  • Those schemes however often cause copper to have a rough surface after etching. Particularly, this tendency becomes more noticeable as the temperature is increased to make the oxide film thicker.
  • This invention is characterized in that, in forming a copper wiring, copper is placed in a mixed solution (SC1) of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10, thereby forming a copper oxide film including an ammonia complex on the surface of the copper, after which the copper oxide film is selectively etched with acid having a weak oxidizing property such as diluted hydrochloric acid or alkali such as diluted aqueous ammonia.
  • SC1 mixed solution
  • aqueous ammonia and aqueous hydrogen peroxide which has been adjusted to have pH of 8 to 10
  • acid having a weak oxidizing property such as diluted hydrochloric acid or alkali such as diluted aqueous ammonia.
  • the copper is dipped in SC1 which has been adjusted to have pH of 10 to 11 which would normally etch copper, thereby forming a thicker copper oxide film including an ammonia complex, which is then selectively etched with acid having a weak oxidizing property such as hydrochloric acid or alkali such as diluted aqueous ammonia.
  • acid having a weak oxidizing property such as hydrochloric acid or alkali such as diluted aqueous ammonia.
  • Copper oxide film can be selectively etched even with liquid which solves copper by forming complex with copper, though the liquid is neutral as an aqueous solution of neutral amino acid such as glycine or alanine.
  • Such formation of an oxide film and such etching can permit copper to be etched without roughening the copper surface which has conventionally been difficult to achieve, and can ensure quick oxidation and etching with a safe and inexpensive chemical solution. As a result, a barrier metal layer to be coated on the surface of the wiring structure is formed stably.
  • a method of forming a copper oxide film which comprises the step of forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film.
  • a method of forming a copper oxide film which comprises the steps of forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film; and exposing the copper film having the copper oxide film formed on the surface thereof to a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 10 to 11.
  • a method of forming a copper oxide film which comprises the steps of forming an oxide film on a surface of a copper film using aqueous hydrogen peroxide; and forming a copper oxide film including an ammonia complex by placing the copper film having the oxide film formed thereon in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 10 to 11.
  • pH may be varied intermittently in a multi-stage manner or continuously in the course of performing the method of forming a copper oxide film.
  • a method of etching a copper film which comprises the steps of forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method as recited in any one of the first to third aspects; and selectively removing the copper oxide film from the copper film.
  • the copper oxide film may be removed with acid or alkali.
  • a method of fabricating a semiconductor device which comprises the steps of burying a copper film (to be a wiring or a contact wiring) in a wiring groove or a contact hole formed in a surface of an insulating film formed on a semiconductor substrate, or in both the wiring groove and the contact hole; forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method as recited in any one of the first to third aspects; and selectively removing the copper oxide film from the copper film.
  • a copper film to be a wiring or a contact wiring
  • the surface of the copper film from which the copper oxide film has been removed may be etched deeper at a region closer to the wiring groove or the contact hole.
  • a barrier metal layer may be intervened between the wiring groove or the contact hole and the buried copper film or between the wiring groove and contact hole and the buried copper film.
  • the semiconductor device fabricating method may further comprise the step of forming a barrier metal layer on the copper film after removing the copper oxide film from the copper film.
  • the barrier metal layer intervening between the wiring groove or the contact hole and the buried copper film or between the wiring groove and contact hole and the buried copper film and the barrier metal layer formed on the copper film may be made of different materials.
  • the semiconductor device fabricating method may further comprise the step of placing the surface of the copper film from which the copper oxide film has been removed in aqueous ammonia.
  • the surface of the copper film may be placed in the aqueous ammonia.
  • a method of fabricating a semiconductor device comprising the steps of: filling a wiring groove or a contact hole formed in an insulating film formed on a semiconductor substrate with wiring metal by depositing the wiring metal in the wiring groove or the contact hole; exposing the insulating film by polishing the wiring metal; cleaning the semiconductor substrate; and carrying out recessing etching on a surface of the wiring metal buried in the wiring groove or the contact hole, wherein chemical solutions used in at least two steps of the polishing step, the cleaning step and the recessing etching step have the same main component.
  • a method of fabricating a semiconductor device comprising the steps of: depositing metal or metal compound on a semiconductor substrate; and etching out an unnecessary portion of the metal or metal compound by etching; wherein the step of depositing metal or metal compound includes a plating step, component in plating solution used in the plating step forming salt or complex with a component to be plated is the same as a main component of chemical solution used in the etching-out step.
  • the step of depositing the wiring metal may be a plating step and a main acidic component in plating solution used in the plating step may be the same as a main component of the chemical solution.
  • the main oxidizing agent in the chemical solution may be hydrogen peroxide or ozone.
  • the main acidic component in the chemical solution may be sulfuric acid or hydrocyanic acid.
  • the semiconductor device fabrication method may further comprise a step of removing oxidizing agent contained in the chemical solution after the step of etching-out an unnecessary portion, a step of making metal ion concentration in the chemical solution approximately equal to metal ion concentration in the plating solution, and a step of using the chemical solution where the oxidizing agent has been removed as the plating solution.
  • an apparatus of fabricating a semiconductor device used for the above method of fabricating a semiconductor device comprising means for removing oxidizing agent contained in the chemical solution; means for making metal ion concentration in the chemical solution approximately equal to metal ion concentration in the plating solution; and means for using the chemical solution where the oxidizing agent has been removed as the plating solution.
  • a semiconductor device comprising a semiconductor substrate; a metal film buried in a wiring groove, a contact hole, or the wiring groove and the contact hole formed on an insulating film formed on the semiconductor substrate; and a barrier metal layer formed on the metal film buried in the wiring groove, the contact hole, or the wiring groove and the contact hole so as to cover a surface of the metal film, wherein a surface of the metal film is etched deeper at a region closer to a side wall of the wiring groove or the contact hole.
  • the metal film may be buried in the wiring groove or the contact hole via barrier metal.
  • the barrier metal formed so as to cover the surface of the metal film may have a structure where it has been buried in the wiring groove or the contact hole. That is, the closer to the side wall of the wiring groove, the greater the etching amount of a surface of such a metal film as a copper film, and the surface of the metal film has a cross section with shoulders of the wiring dropped.
  • This shape is frequently advantageous when this invention is worked out.
  • the contact hole for forming a contact wiring is formed on the barrier metal layer, the etching area where the contact hole is to be formed partly cut into an inter-layer insulating film due to misalignment in some case.
  • the inter-layer insulating film which covers the barrier metal layer of the under-layer wiring is etched under such a situation, etching of the inter-layer insulating film progresses because the etching rate of such an inter-layer insulating film as a silicon oxide film is greater than that of such a metal film as a copper film, so that that portion is greatly etched.
  • the diameter of a deep portion is larger than that in a case of a flat surface. That is, the aspect ratio of this portion is low.
  • it is easy to deposit a barrier metal layer and deposit a seed metal film as a copper film. Forming the contact hole is not limited to a case that a barrier metal layer is buried.
  • FIGS. 1A through 1D are cross-sectional views of a semiconductor substrate for explaining the fabrication steps for a semiconductor device according to this invention
  • FIGS. 2A and 2B are cross-sectional views of the semiconductor substrate for explaining the fabrication steps for the semiconductor device according to this invention.
  • FIGS. 3A and 3B are cross-sectional views of the semiconductor substrate for explaining the fabrication steps for the semiconductor device according to this invention.
  • FIG. 4 is a cross-sectional view of a semiconductor substrate on which multilayer wirings according to this invention are formed
  • FIG. 5 is a cross-sectional view of a semiconductor substrate on which multilayer wirings according to this invention are formed
  • FIG. 6 is a characteristic diagram illustrating the amount of etched copper at the time of forming an oxide film on a copper film by dipping the copper film in a pH-adjusted mixed solution (SC1) for 1 minute and selectively etching the oxide film with diluted hydrochloric acid;
  • SC1 pH-adjusted mixed solution
  • FIGS. 7A and 7B are diagrams respectively showing the SEM image of the surface of copper before copper is processed and the SEM image of the surface of copper after an oxide film is etched with hydrochloric acid after oxidation with a mixed solution of hydrochloric acid and aqueous hydrogen peroxide with pH of 9.5 for 1 minute;
  • FIGS. 8A and 8B are diagrams respectively showing the SEM image of the surface of copper when copper is etched with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide with pH of 10.2 and the SEM image of the surface of copper when copper is etched with a mixed solution of hydrochloric acid and aqueous hydrogen peroxide;
  • FIG. 9 is a cross-sectional view of a semiconductor substrate for explaining the surface shape of a copper wiring in a wiring groove formed in an inter-layer insulating film according to this invention.
  • FIGS. 10A and 10B are exemplary cross-sectional views of a semiconductor substrate for explaining the advantage of this invention.
  • FIG. 11 is a process diagram for explaining the steps of forming copper wirings
  • FIG. 12 is a characteristic diagram for explaining the dependency of the wiring resistance of a wafer on the number of rotations of the wafer in an ammonia treatment at the time of recessing copper;
  • FIGS. 13A through 13C are cross-sectional views showing a conventional buried wiring structure
  • FIG. 14 is a diagrammatical view of a semiconductor manufacturing apparatus for performing a manufacturing method of a semiconductor device according to the present invention.
  • FIG. 15 is a diagrammatical view of a semiconductor manufacturing apparatus for performing a manufacturing method of a semiconductor device according to the present invention, and is used to explain the recycle in the apparatus.
  • This invention is adapted to, for example, a pillar process, a single damascene structure and a dual damascene structure in a multilayer wiring structure of a semiconductor device.
  • FIGS. 1A through 1D are cross-sectional views of a semiconductor substrate on which multilayer wirings are formed.
  • a pillar wiring (contact wiring) which is formed by this process connects an under-lying wiring to an over-lying wiring.
  • the under-lying wiring is buried in an inter-layer insulating film 1 .
  • the inter-layer insulating film 1 is formed of silicon oxide on a semiconductor substrate 10 of silicon or the like where a semiconductor element (not shown) such as an integrated circuit is formed, and wiring grooves are formed in the surface of this inter-layer insulating film 1 .
  • the barrier metal layer 2 is present only in the wiring groove, not on the surface of the inter-layer insulating film (FIG. 1 A).
  • the barrier metal layer may be formed over the wiring groove of the inter-layer insulating film 1 to the surface thereof.
  • a copper oxide film 5 is formed on the surface of the copper film 3 (FIG. 1 B).
  • the surface of the copper film 3 is set back from the surface of the inter-layer insulating film by etching out the oxide film 5 (FIG. 1 C).
  • Barrier metal is deposited on the upper portion of the wiring groove by sputtering, CVD or the like, and is then polished by CMP to bury a barrier metal layer 4 in the upper portion of the wiring groove (FIG. 1 D).
  • the material for the barrier metal layer 4 may be the same as that for the barrier metal layer 2 or those materials may differ from each other.
  • a barrier metal layer 6 of tungsten or the like, an aluminum film 7 and a conductive etching stopper 8 are deposited in order (FIG. 2 A), and are then patterned to form a pillar wiring 9 (FIG.
  • an inter-layer insulating film 11 of silicon oxide is formed on the inter-layer insulating film 1 so as to cover the pillar wiring 9 (FIG. 3 A).
  • the surface of the inter-layer insulating film 11 is polished by CMP to expose the top surface of the pillar wiring 9 .
  • an over-lying inter-layer insulating film 12 is deposited on the inter-layer insulating film 11 , a groove which connects to the under-lying wiring 9 is formed in the inter-layer insulating film 12 , and an over-lying wiring is formed in this groove.
  • the over-lying wiring comprises a barrier metal layer 13 formed in the wiring groove, a copper film 14 buried in the wiring groove and a barrier metal layer 15 which covers the surface of the copper film 14 (FIG. 3 B).
  • the pillar wiring 9 electrically connects the under-lying wiring to the over-lying wiring.
  • this invention is adapted to the formation of the barrier metal layers 4 and 15 . That is, for example, in the method of forming a barrier metal layer 4 (FIGS. 1A to 1 D), an exposed surface of the copper film 3 buried and formed in the insulating film 1 is oxidized to yield a copper oxide film 5 (FIG. 1 B). Then, the copper oxide film 5 formed is etched out to yield an non-roughened (whitening-free) surface, on which a barrier metal layer 4 is then formed (FIG. 1 C).
  • FIG. 4 is a cross-sectional view of a semiconductor substrate on which multilayer wirings are formed.
  • Inter-layer insulating films 21 , 25 and 29 of silicon oxide or the like are sequentially formed on a semiconductor substrate 20 .
  • Formed in the inter-layer insulating films 21 , 25 and 29 are wiring grooves and contact holes which communicate with one another and in which an under-lying wiring, a contact wiring and an over-lying wiring are respectively formed.
  • each wiring the wiring groove or contact hole is formed in the associated inter-layer insulating film, then a barrier metal layer is formed in the wiring groove and on the surface of the inter-layer insulating film, copper or an alloy essentially consisting of copper is deposited on the barrier metal layer and is polished by CMP or the like for surface planarization, thereby burying a copper film, covered with the barrier metal layer, in the wiring groove or the contact hole.
  • the surface of the copper film is oxidized and the copper oxide film formed by the oxidation is etched out to yield an non-roughened (whitening-free) surface, on which a barrier metal layer is then formed. That is, this invention is adapted to the formation of barrier metal layers 24 , 28 and 32 in the multilayer wiring structure of a semiconductor device.
  • the under-lying wiring to be buried in the inter-layer insulating film 21 comprises a barrier metal layer 22 formed on the side wall of the wiring groove, a copper film 23 covered with the barrier metal layer 22 and the barrier metal layer 24 which covers the surface of the copper film 23 .
  • the contact wiring which is electrically connected to the under-lying wiring and is buried in the inter-layer insulating film 25 comprises a barrier metal layer 26 formed on the side wall of the wiring groove, a copper film 27 buried in the wiring groove and covered with the barrier metal layer 26 and the barrier metal layer 28 which covers the surface of the copper film 27 .
  • the over-lying wiring which is electrically connected to the contact wiring and is buried in the inter-layer insulating film 29 comprises a barrier metal layer 30 formed on the side wall of the wiring groove, a copper film 31 buried in the wiring groove and covered with the barrier metal layer 30 and the barrier metal layer 32 which covers the surface of the copper film 31 .
  • the barrier metal layer 24 is formed on the surface of the copper film 23 of the under-layer wiring, diffusion of copper from an upper portion of the wiring can be suppressed. Also, as the surface of the copper film 23 is not roughened, the copper film is not affected by surface scattering or the like and increase in real resistance of the copper film is small. Also, as concentration of charges is suppressed after a contact is formed, an effect is also obtained that electro-migration is difficult unlikely to occur.
  • FIG. 5 is a cross-sectional view of a semiconductor substrate on which multilayer wirings are formed.
  • Inter-layer insulating films 41 and 45 of silicon oxide or the like are sequentially formed on a semiconductor substrate 40 .
  • Formed in the inter-layer insulating films 41 and 45 are wiring grooves and contact holes in which an under-lying wiring, a contact hole and an over-lying wiring are respectively formed.
  • the wiring groove or contact hole is formed in the associated inter-layer insulating film, then a barrier metal layer is formed in the wiring groove and on the surface of the inter-layer insulating film, copper or an alloy essentially consisting of copper is deposited on the barrier metal layer and is polished by CMP or the like for surface planarization, thereby burying a copper film, covered with the barrier metal layer, in the wiring groove or the contact hole.
  • the surface of the copper film is oxidized and the copper oxide film formed by the oxidation is etched out to yield an non-roughened (whitening-free) surface, on which a barrier metal layer is then formed. That is, this invention is adapted to the formation of barrier metal layers 44 and 48 in the multilayer wiring structure of a semiconductor device.
  • the under-lying wiring to be buried in the inter-layer insulating film 41 comprises a barrier metal layer 42 formed on the side wall of the wiring groove, a copper film 43 covered with the barrier metal layer 42 and the barrier metal layer 44 which covers the surface of the copper film 43 .
  • the over-lying wiring which is electrically connected to the under-lying wiring via a contact wiring and is buried in the inter-layer insulating film 45 comprises a barrier metal layer 46 formed in the wiring groove and on the side wall of the contact hole which is formed continuous to this groove, a copper film 47 buried in the wiring groove and the contact hole and covered with the barrier metal layer 46 , and the barrier metal layer 48 which covers the surface of the copper film 47 .
  • FIGS. 6 through 8B To begin with, a first example will be discussed referring to FIGS. 6 through 8B.
  • the feature of this invention lies in its method of etching a copper film without roughening the copper surface. That is, an oxide film including an ammonia complex is formed on the surface of the copper film and is then etched out.
  • this method forms a relatively thick oxide film on the surface of copper without etching copper by adjusting a mixed solution of aqueous ammonia and aqueous hydrogen peroxide in such a way as to have pH of 8 to 10 or pH of 9 to 10, and then etches out this oxide film using an acid having a weak oxidizing property such as diluted hydrochloric acid or alkali such as diluted aqueous ammonia.
  • the ordinary mixed solution (SC1) of aqueous ammonia and aqueous hydrogen peroxide etches copper and has pH of about 10.5 to 11.
  • the experiments conducted by the present inventor demonstrated such a property that with pH of 10 or less, an oxide film is formed on the surface of the copper film whereas with pH of greater than 10, copper is etched.
  • FIG. 6 shows the amount of etched copper at the time of forming an oxide film on a copper film by dipping the copper film in a pH-adjusted SC1 for 1 minute and selectively etching the oxide film with diluted hydrochloric acid.
  • the vertical scale represents the etching amount (nm) and the horizontal scale represents pH.
  • the etching amount was approximately 4 nm then.
  • FIG. 7A shows the SEM image of the surface of copper before copper is processed
  • FIG. 7B shows the SEM image of the surface of copper after an oxide film is etched with hydrochloric acid after oxidation with a mixed solution of hydrochloric acid and aqueous hydrogen peroxide with pH of 9.5 for 1 minute
  • FIG. 8A shows the SEM image of the surface of copper which is etched with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide with pH of 10.2
  • 8B shows the SEM image of the surface of copper when copper is etched with a mixed solution (80° C.) of hydrochloric acid and aqueous hydrogen peroxide (for the purpose of reference). It is apparent from those diagrams that the use of a pH-adjusted mixed solution of aqueous ammonia and aqueous hydrogen peroxide can etch copper without roughening the copper surface.
  • the etching thickness be 30 to 50 nm and the etching time be as short as possible. Even a treatment only with aqueous hydrogen peroxide which is considered as being capable of ensuring relatively thick oxidation takes about 12 to 13 minutes to etch copper by 50 nm. It is therefore preferable to carry out the treatment with a solution having pH of 8 to 10, desirably 9 to 10. Particularly, the use of a solution with pH of about 10 can achieve etching of 50 nm in approximately 4 minutes.
  • the desirable etching amount of copper is 30 nm to 50 nm. Even if copper is dipped in a solution whose pH has been adjusted to 10, however, copper cannot be etched more than 12 nm in 1 minute.
  • an etching method which can avoid roughening of the copper surface while increasing the etching amount will be discussed. According to this method, a copper film is temporarily dipped in a solution containing only aqueous hydrogen peroxide or SC1 with pH of 8 to 10 to thereby form an oxide film on the copper film, and this copper film is then dipped in SC1 with pH of 10 to 11. Although the concentration of pH of 10 to 11 normally causes copper to be etched, the previous formation of an oxide film on the copper surface forms a thicker oxide film.
  • an inter-layer insulating film 51 is formed on a semiconductor substrate 50 , and a wiring groove 54 having a barrier metal layer 52 deposited on its side wall is formed on this inter-layer insulating film 51 .
  • a copper film 53 is buried in this wiring groove 54 .
  • the copper wiring with the above structure is subjected to the above-described oxide-film formation and etching to yield a non-roughened surface. Thereafter, TaN or WN is deposited as second barrier metal on the non-roughened surface by sputtering or CVD method, followed by CMP to thereby form a barrier metal layer 55 .
  • This non-roughened surface of the copper film 53 has a cross section with shoulders of the wiring dropped. Therefore, the closer to the wiring groove 54 the barrier metal layer 55 formed on the copper film 53 is, the thicker the layer 55 becomes. This shape is frequently advantageous when this invention is worked out.
  • FIGS. 10A and 10B are exemplary cross-sectional views of a semiconductor substrate for explaining the advantage of this invention.
  • FIG. 10A shows the copper wiring in FIG. 9 with its shoulders dropped
  • FIG. 10B shows the copper wiring having its surface flattened up to the end thereof and formed with a nearly uniform barrier metal layer which covers the copper wiring.
  • a contact hole should be formed in the inter-layer insulating film deposited on the under-lying wiring. As shown in FIGS.
  • the diameter of the deep portion is “a” and the depth is “b”.
  • the diameter of the deep portion is “a′” and the depth is “b′”.
  • the diameter of the deep portion is larger than that in a case of the flat surface in FIG. 10B (a>a′). That is, the deep portion in FIG. 10B is shaped like a pocket so that the aspect ratio of this portion (b′/a′) is significantly greater than the aspect ratio of the deep portion (b/a) in FIG. 10 A.
  • a barrier metal layer in the contact hole in FIG. 10 B and using plating to bury copper in the contact hole therefore, it is difficult to form a seed copper film, whereas it is easy to deposit a barrier metal layer in the contact hole in FIG. 10A to thereby form a seed copper film.
  • this is not limited to copper, but it is applicable to a metal film of any wiring or contact in a semiconductor device. It is applicable to a case that a barrier layer is formed on the entire surface of a metal film or a case that an inter-layer insulating film is directly deposited on the metal film instead of burying barrier metal in a metal film.
  • a fifth example will be discussed below referring to FIG. 11 .
  • FIG. 11 is a process diagram for explaining the steps of forming copper wirings.
  • the copper wiring forming process first (1) forms a wiring groove in the inter-layer insulating film.
  • a barrier metal layer formed of a conductive nitride such as TaN, WN or TiN is deposited on the bottom and the side walls of the wiring groove by sputtering, CVD or the like.
  • copper (Cu) is so deposited as to be buried in the wiring groove by sputtering, plating, CVD or the like.
  • the solution in this invention can permit polishing of the Cu surface while protecting this surface by forming an oxide film thereon, the solution can be used as slurry for Cu-CMP.
  • the chemical solution of this invention is alkaline, it is effective to use this solution in cleaning to remove residual ground particles (alumina or silica).
  • the use of sputtering or CVD causes Cu to be deposited on the bevel portion of a wafer or the back thereof.
  • the Cu deposited on the bevel portion is utilized as an electrode, however the Cu on the bevel portion becomes unnecessary after plating.
  • the bevel or the back of the wafer is where various systems contact for transfer or chuck purposes at the time of fabricating a semiconductor device. When there is Cu contamination in such a portion, other wafers may be contaminated through the manufacturing equipment. It is therefore necessary to carry out etching and cleaning of Cu adhered to the bevel and back of a wafer after Cu-CMP.
  • this process may be executed prior to CMP, it is desirably carried out after CMP because the bevel and back of the wafer are likely to be polluted with Cu again at the time of CMP.
  • Etching in this manner may oxidize Cu in the device portion on the surface only in the vicinity of the wafer edges after treatment. This seems to have occurred by the acceleration of oxidation by gases, such as HCl, NOx and SOx vaporized from the chemical solution or generated during etching, remaining on the Cu surface.
  • a treatment with acid having a weak oxidation property such as hydrochloric acid or diluted sulfuric acid is performed, which may make the Cu film near the wafer edges oxidized by the treatment thinner.
  • acid having a weak oxidation property such as hydrochloric acid or diluted sulfuric acid
  • One way to avoid this problem is to provide a nozzle which sprays a chemical solution only on the bevel portion while letting pure water flow from the surface side while rotating the wafer, process the bevel portion using this nozzle and at the same time process the back by spraying the chemical solution also from the back.
  • This scheme requires a special nozzle, making the structure of the manufacturing equipment complicated and resulting in an increased cost from the viewpoint of hardware, and requires a step of letting pure water flow from the surface, disabling the collection and recirculation of the chemical solution as an etching solution and increasing the amount of the chemical solution in use, from the viewpoint of processes.
  • FIG. 14 is a diagrammatical view of a semiconductor fabricating apparatus where a semiconductor device is fabricated in the above same chamber. Forming steps of a copper wiring will be explained using the process shown in FIG. 11 . First, (1) a wiring groove is formed in an inter-layer insulating film. Then, (2) a barrier metal layer is deposited on a bottom surface and a side surface of the wiring groove. Next, (3) Cu is deposited so as to be buried in the wiring groove by plating.
  • This step is carried out in a Cu plating chamber 61 .
  • (4) Cu alone or Cu and the barrier metal layer are polished by CMP to form a buried Cu wiring in the inter-layer insulating film.
  • This step is carried out in a CMP chamber 62 .
  • the wafer after CMP is cleaned in a post-CMP cleaning chamber 63 .
  • (6) Cu on a bevel/back of the wafer is etched and the wafer is cleaned.
  • This step is performed in an etching chamber 64 .
  • (7) a recessing process of Cu is also performed in the etching chamber 64 .
  • the bevel/back etching process and the recessing etching process may be respectively performed in chambers different from each other, but it is preferable to perform them sequentially in the same chamber.
  • These Cu plating chamber 61 , CMP chamber 62 , post-CMP cleaning chamber 63 , etching chamber 64 and processing chamber 65 are disposed in one apparatus 60 so that the copper wiring forming step may be performed.
  • the exhaust solutions from the Cu plating chamber 61 and the etching chamber 64 of the respective chambers are collected in the processing chamber 65 where the oxidizing agent such as hydrogen peroxide or ozone is removed from the collected solution, and the concentration of copper or sulfuric acid is adjusted.
  • the solution thus adjusted is returned to the plating chamber 61 , and it is reused as the plating solution.
  • the semiconductor fabrication apparatus shown in FIG. 14 is provided with the plating chamber 61 , the etching chamber 64 and the processing chamber 65 .
  • the processing chamber 65 comprises a concentration adjusting section and a plating solution section for adjusting plating solution, where the used plating solution from the plating chamber 61 and the exhaust solution from the etching chamber 64 is adjusted while supplying pure water, components forming salt or complex or the like to the concentration adjusting section and the adjusted solution is supplied to the plating solution section to form plating solution.
  • the plating solution thus adjusted is supplied to the plating chamber 61 .
  • the semiconductor fabricating apparatus may be structured such that, when the amount of the exhaust solution from the etching chamber 64 is small relative to that of the used plating solution from the plating chamber 61 , only the exhaust solution from the etching chamber 64 is adjusted while the used plating solution is directly recovered in the plating solution section.
  • the solution which has been applied for etching copper or copper oxide has the same components as the plating solution as the solution is sulfuric acid when the plating solution used is aqueous solution of copper sulfate or it is hydrocyanic acid when the plating solution is aqueous solution of copper cyanide.
  • the components of the etching chemical solution and the components contained in plating solution which has been used are approximately equal to each other, there is an advantage that they can be exhausted and treated simultaneously. Further, a process having a very high efficiency in use of copper can be made up by carrying out plating again using the chemical solution which has been used for etching.
  • etching solution sulfuric acid having a concentration different from that of the plating solution
  • the circulation is not required to carry out necessarily.
  • the copper concentration is made equal to or more than the concentration of sulfuric acid.
  • targeted aqueous solution with 10% copper sulfate is prepared by completely decomposing hydrogen peroxide or ozone by an active carbon filter, a UV lamp irradiation or the like, and adding sulfuric acid or pure water to the etching solution or condensing the etching solution by processing using thermal treatment or a semipermeable membrane such as a reverse osmosis membrane while monitoring copper concentration or sulfuric acid concentration.
  • the aqueous solution is added with additives required for plating to be used for plating.
  • concentration adjustment may be carried out on the plating solution which has been used, and the solution which has been concentration-adjusted may be added a little by a little.
  • any other devices or mechanism than the above mentioned ones can be used as the concentration monitor, the oxidizing agent removing mechanism and the chemical solution condensing mechanism.
  • a process or apparatus where the solution which has been applied to the etching process is recycled as the plating solution can be applied not only to copper but also to any material including at least metal such as Au, Ag, Ti or the like.
  • FIG. 12 is a characteristic diagram for explaining the dependency of the wiring resistance of a wafer on the number of rotations of the wafer in an ammonia treatment at the time of recessing Cu.
  • Cu recess of about 50 nm is possible by using a rotary type single wafer system in the Cu recessing process and performing (1) a treatment with NH 4 OH:H 2 O 2 :DIW (30:100:1000) for 60 seconds at 1000 rpm, (2) a treatment with NH 4 OH:H 2 O 2 :DIW (100:100:1000) for 60 seconds at 1000 rpm and (3) HCl:DIW (30:1000) for 5 seconds at 1000 rpm.
  • the Cu surface finished with the treatment with hydrochloric acid has fast natural oxidation.
  • the effective Cu that can be used as wiring is reduced and the cross-sectional area of the wiring is decreased, thus increasing the wiring resistance.
  • the contact resistance to upper via may increase or the capacitance provided may delay the processing speed in terms of device.
  • the processing conditions were (1) NH 4 OH:H 2 O 2 :DIW (30:100:1000) for 60 seconds at 1000 rpm, (2) a treatment with NH 4 OH:H 2 O 2 :DIW (100:100:1000) for 60 seconds at 1000 rpm, (3) NC:DIW (30:1000) for 5 seconds at 1000 rpm and (4) NH 4 OH:DIW (30:1000) for 5 seconds at 1475 rpm.
  • the above-described structures can permit copper to be etched without roughening the copper surface which has conventionally been difficult to achieve, can ensure quick oxidation and etching with a safe and inexpensive chemical solution.
  • a barrier metal layer to be coated on the surface of the wiring structure is formed stably.

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US10/233,582 US6818556B2 (en) 2000-01-25 2002-09-04 Method of plating a metal or metal compound on a semiconductor substrate that includes using the same main component in both plating and etching solutions
US10/976,758 US7183203B2 (en) 2000-01-25 2004-11-01 Method of plating a metal or metal compound on a semiconductor substrate that includes using the same main component in both plating and etching solutions

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US7183203B2 (en) 2007-02-27
JP2001210630A (ja) 2001-08-03
KR20010074557A (ko) 2001-08-04
US20010034125A1 (en) 2001-10-25

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