CN103943604B - 复合铜线互连结构及形成方法 - Google Patents
复合铜线互连结构及形成方法 Download PDFInfo
- Publication number
- CN103943604B CN103943604B CN201410028901.1A CN201410028901A CN103943604B CN 103943604 B CN103943604 B CN 103943604B CN 201410028901 A CN201410028901 A CN 201410028901A CN 103943604 B CN103943604 B CN 103943604B
- Authority
- CN
- China
- Prior art keywords
- copper
- layers
- barrier layer
- grain growth
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/746,627 | 2013-01-22 | ||
US13/746,627 US8975531B2 (en) | 2013-01-22 | 2013-01-22 | Composite copper wire interconnect structures and methods of forming |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103943604A CN103943604A (zh) | 2014-07-23 |
CN103943604B true CN103943604B (zh) | 2017-03-22 |
Family
ID=51191202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410028901.1A Expired - Fee Related CN103943604B (zh) | 2013-01-22 | 2014-01-22 | 复合铜线互连结构及形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8975531B2 (zh) |
CN (1) | CN103943604B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9893009B2 (en) * | 2014-01-10 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company Limited | Duplicate layering and routing |
KR20160099381A (ko) * | 2015-02-12 | 2016-08-22 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 제조 방법 |
JP2016207893A (ja) * | 2015-04-24 | 2016-12-08 | イビデン株式会社 | プリント配線板およびその製造方法 |
JP6530298B2 (ja) * | 2015-10-09 | 2019-06-12 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
US9716063B1 (en) | 2016-08-17 | 2017-07-25 | International Business Machines Corporation | Cobalt top layer advanced metallization for interconnects |
US10115670B2 (en) | 2016-08-17 | 2018-10-30 | International Business Machines Corporation | Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer |
US9941212B2 (en) | 2016-08-17 | 2018-04-10 | International Business Machines Corporation | Nitridized ruthenium layer for formation of cobalt interconnects |
US9859215B1 (en) | 2016-08-17 | 2018-01-02 | International Business Machines Corporation | Formation of advanced interconnects |
US9852990B1 (en) | 2016-08-17 | 2017-12-26 | International Business Machines Corporation | Cobalt first layer advanced metallization for interconnects |
US10727120B2 (en) * | 2018-08-23 | 2020-07-28 | Globalfoundries Inc. | Controlling back-end-of-line dimensions of semiconductor devices |
US11664271B2 (en) * | 2019-05-02 | 2023-05-30 | International Business Machines Corporation | Dual damascene with short liner |
CN114008911A (zh) * | 2019-06-24 | 2022-02-01 | 千叶正毅 | 介电弹性体换能器 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180505B1 (en) * | 1999-01-07 | 2001-01-30 | International Business Machines Corporation | Process for forming a copper-containing film |
US6261953B1 (en) * | 2000-01-25 | 2001-07-17 | Kabushiki Kaisha Toshiba | Method of forming a copper oxide film to etch a copper surface evenly |
CN1790663A (zh) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | 半导体元件及制造铜导线的方法 |
CN101246875A (zh) * | 2007-02-15 | 2008-08-20 | 富士通株式会社 | 半导体器件及其制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6271137B1 (en) | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
US5278448A (en) | 1991-03-19 | 1994-01-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of fabricating the same |
KR970001883B1 (ko) | 1992-12-30 | 1997-02-18 | 삼성전자 주식회사 | 반도체장치 및 그 제조방법 |
US5603147A (en) * | 1995-06-07 | 1997-02-18 | Microelectronic Packaging, Inc. | Method of making a high energy multilayer ceramic capacitor |
US6126806A (en) | 1998-12-02 | 2000-10-03 | International Business Machines Corporation | Enhancing copper electromigration resistance with indium and oxygen lamination |
US6123825A (en) | 1998-12-02 | 2000-09-26 | International Business Machines Corporation | Electromigration-resistant copper microstructure and process of making |
US6359328B1 (en) | 1998-12-31 | 2002-03-19 | Intel Corporation | Methods for making interconnects and diffusion barriers in integrated circuits |
US6436787B1 (en) | 2001-07-26 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming crown-type MIM capacitor integrated with the CU damascene process |
US6548906B2 (en) | 2001-08-22 | 2003-04-15 | Agere Systems Inc. | Method for reducing a metal seam in an interconnect structure and a device manufactured thereby |
US7687917B2 (en) | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
US20040056366A1 (en) | 2002-09-25 | 2004-03-25 | Maiz Jose A. | A method of forming surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement |
US7545040B2 (en) | 2002-12-09 | 2009-06-09 | Nec Corporation | Copper alloy for wiring, semiconductor device, method for forming wiring and method for manufacturing semiconductor device |
KR100675280B1 (ko) | 2005-06-22 | 2007-01-29 | 삼성전자주식회사 | 반도체소자의 선택적 구리 합금 배선 및 그 형성방법 |
US7968967B2 (en) | 2006-07-17 | 2011-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-time-programmable anti-fuse formed using damascene process |
US7737013B2 (en) | 2007-11-06 | 2010-06-15 | Varian Semiconductor Equipment Associates, Inc. | Implantation of multiple species to address copper reliability |
US7618893B2 (en) | 2008-03-04 | 2009-11-17 | Applied Materials, Inc. | Methods of forming a layer for barrier applications in an interconnect structure |
-
2013
- 2013-01-22 US US13/746,627 patent/US8975531B2/en active Active
-
2014
- 2014-01-22 CN CN201410028901.1A patent/CN103943604B/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180505B1 (en) * | 1999-01-07 | 2001-01-30 | International Business Machines Corporation | Process for forming a copper-containing film |
US6261953B1 (en) * | 2000-01-25 | 2001-07-17 | Kabushiki Kaisha Toshiba | Method of forming a copper oxide film to etch a copper surface evenly |
CN1790663A (zh) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | 半导体元件及制造铜导线的方法 |
CN101246875A (zh) * | 2007-02-15 | 2008-08-20 | 富士通株式会社 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140202746A1 (en) | 2014-07-24 |
CN103943604A (zh) | 2014-07-23 |
US8975531B2 (en) | 2015-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103943604B (zh) | 复合铜线互连结构及形成方法 | |
KR101770455B1 (ko) | 반도체 디바이스 및 반도체 디바이스를 형성하는 방법 | |
US7417321B2 (en) | Via structure and process for forming the same | |
US7902061B2 (en) | Interconnect structures with encasing cap and methods of making thereof | |
KR20180110011A (ko) | 반도체 장치 및 그 제조방법 | |
US20100314774A1 (en) | Reliable interconnects | |
US20060163739A1 (en) | Semiconductor device and method for production thereof | |
US20060043589A1 (en) | Electronic device and method for fabricating the same | |
US9224686B1 (en) | Single damascene interconnect structure | |
US20070123029A1 (en) | Semiconductor device and method for manufacturing the same | |
US11121075B2 (en) | Hybrid metallization interconnects for power distribution and signaling | |
CN102364673A (zh) | 一种铜互连的形成方法 | |
JP2008060243A (ja) | 半導体装置およびその製造方法 | |
CN102437104B (zh) | 具有部分冗余通孔的集成电路制作方法及集成电路 | |
KR20060120413A (ko) | 배선 구조 및 그 형성 방법 | |
CN102437105B (zh) | 具有部分冗余通孔的集成电路制作方法及集成电路 | |
US20050082606A1 (en) | Low K dielectric integrated circuit interconnect structure | |
JP4646591B2 (ja) | 半導体装置及びその製造方法 | |
KR100924865B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
US7902065B2 (en) | Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same | |
KR100889555B1 (ko) | 반도체 소자의 인덕터 제조방법 | |
US6479898B1 (en) | Dielectric treatment in integrated circuit interconnects | |
JP2009146958A (ja) | 半導体装置及びその製造方法 | |
US20080265370A1 (en) | Semiconductor device | |
JP2004235620A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171115 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171115 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170322 Termination date: 20190122 |
|
CF01 | Termination of patent right due to non-payment of annual fee |