US5539911A - High-performance, superscalar-based computer system with out-of-order instruction execution - Google Patents

High-performance, superscalar-based computer system with out-of-order instruction execution Download PDF

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Publication number
US5539911A
US5539911A US07/817,810 US81781092A US5539911A US 5539911 A US5539911 A US 5539911A US 81781092 A US81781092 A US 81781092A US 5539911 A US5539911 A US 5539911A
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United States
Prior art keywords
instruction
instructions
register
unit
data
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US07/817,810
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English (en)
Inventor
Le T. Nguyen
Derek J. Lentz
Yoshiyuki Miyayama
Sanjiv Garg
Yasuaki Hagiwara
Johannes Wang
Te-Li Lau
Sze-Shun Wang
Quang H. Trang
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to US07/817,810 priority Critical patent/US5539911A/en
Assigned to S MOS SYSTEMS, INC. reassignment S MOS SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TRANG, QUANG H.
Assigned to SEIKO EPSON CORPORATION, A CORP. OF JAPAN reassignment SEIKO EPSON CORPORATION, A CORP. OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: S MOS SYSTEMS, INC.
Priority to US08/602,021 priority patent/US5689720A/en
Application granted granted Critical
Publication of US5539911A publication Critical patent/US5539911A/en
Priority to US08/946,078 priority patent/US6092181A/en
Priority to US09/150,706 priority patent/US5961629A/en
Priority to US09/309,601 priority patent/US6101594A/en
Priority to US09/309,603 priority patent/US6128723A/en
Assigned to S MOS SYSTEMS, INC. reassignment S MOS SYSTEMS, INC. INVALID ASSIGNMENT. SEE DOCUMENT AT REEL 9814 FRAME 0987. Assignors: TRANG, QUANG H.
Priority to US09/338,563 priority patent/US6038654A/en
Priority to US09/436,986 priority patent/US6256720B1/en
Priority to US09/437,601 priority patent/US6272619B1/en
Priority to US09/852,293 priority patent/US6647485B2/en
Priority to US10/282,207 priority patent/US6948052B2/en
Priority to US10/282,045 priority patent/US6959375B2/en
Priority to US10/283,177 priority patent/US6986024B2/en
Priority to US10/283,106 priority patent/US6915412B2/en
Priority to US10/660,671 priority patent/US7162610B2/en
Priority to US10/697,257 priority patent/US6934829B2/en
Priority to US10/700,520 priority patent/US6941447B2/en
Priority to US10/700,485 priority patent/US7487333B2/en
Priority to US11/642,599 priority patent/US7739482B2/en
Priority to US12/235,215 priority patent/US7721070B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Definitions

  • the present invention is generally related to the design of RISC type microprocessor architectures and, in particular, to RISC microprocessor architectures that are capable of executing multiple instructions concurrently.
  • CISC Complex Instruction Set Computer
  • RISC Reduced Instruction Set Computer
  • the CISC architectures are notable for the provision of substantial hardware to implement and support an instruction execution pipeline.
  • the typical conventional pipeline structure includes, in fixed order, instruction fetch, instruction decode, data load, instruction execute and data store stages.
  • a performance advantage is obtained by the concurrent execution of different portions of a set of instructions through the respective stages of the pipeline. The longer the pipeline, the greater the number of execution stages available and the greater number of instructions that can be concurrently executed.
  • conditional branch instructions may not be adequately evaluated until a prior condition code setting instruction has substantially completed execution through the pipeline.
  • condition codes are written to a condition code register, also referred to as a processor status register (PSR), only at completion of processing an instruction through the execution stage.
  • PSR processor status register
  • the pipeline must be stalled with the conditional branch instruction in the decode stage for multiple processor cycles pending determination of the branch condition code.
  • the stalling of the pipeline results in a substantial loss of through-put.
  • the average through-put of the computer will be substantially dependent on the mere frequency of conditional branch instructions occurring closely after the condition code setting instructions in the program instruction stream.
  • Data registers are often used as the destination or source of data in the store and load stages of successive instructions.
  • an instruction that stores data to the register file must complete processing through at least the execution stage before the load stage processing of a subsequent instruction can be allowed to access the register file. Since the execution of many instructions require multiple processor cycles in the single execution stage to produce store data, the entire pipeline is typically stalled for the duration of an execution stage operation. Consequently, the execution through-put of the computer is substantially dependent on the internal order of the instruction stream being executed.
  • Contemporary CISC microprocessor hardware sub-systems can detect the occurrence of trap conditions during the execution of instructions. Traps include hardware interrupts, software traps and exceptions. Each trap requires execution of a corresponding trap handling routines by the processor. On detection of the trap, the execution pipeline must be cleared to allow the immediate execution of the trap handling routine. Simultaneously, the state-of-the-machine must be established as of the precise point of occurrence of the trap; the precise point occurring at the conclusion of the first currently executing instruction for interrupts and traps and immediately prior to an instruction that fails due to a exception.
  • each RISC instruction executes in only three pipelined program cycles including a load cycle, an execution cycle, and a store cycle.
  • load cycle an execution cycle
  • store cycle an execution cycle
  • conventional RISC architectures can essentially execute a single instruction per cycle in the three stage pipeline.
  • RISC architectures Whenever possible, hardware support in RISC architectures is minimized in favor of software routines for performing the required functions. Consequently, the RISC architecture holds out the hope of substantial flexibility and high speed through the use of a simple load/store instruction set executed by an optimally matched pipeline. And in practice, RISC architectures have been found to benefit from the balance between a short, high-performance pipeline and the need to execute substantially greater numbers of instructions to implement all required functions.
  • the design of the RISC architecture generally avoids or minimizes the problems encountered by CISC architectures with regard to branches, register references and exceptions.
  • the pipeline involved in a RISC architecture is short and optimized for speed. The shortness of the pipeline minimizes the consequences of a pipeline stall or clear as well as minimizing the problems in restoring the state-of-the-machine to an earlier execution point.
  • a general purpose of the present invention is to provide a high-performance, RISC based, super-scaler processor architecture capable of substantial performance gains over conventional CISC and RISC architectures and that is further suited for microprocessor implementation.
  • the microprocessor architecture includes an instruction prefetch unit for fetching instruction sets from the instruction store. Each instruction set includes a plurality of fixed length instructions.
  • An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer.
  • An instruction execution unit including a register file and a plurality of functional units, is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and issuing any of these instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file as necessary for the concurrent execution of the respective instructions.
  • the register file includes an additional set of data registers used for the temporary storage of register data. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units in the out-of-order execution of instructions. The data stored in the temporary data registers is selectively held, then cleared or retired to the register file when, and if, the precise state-of-the-machine advances to the instruction's location in the instruction stream; where all prior in-order instructions have been completely executed and retired.
  • the prefetching of instruction sets from the instruction store is facilitated by multiple prefetch paths allowing for prefetching of the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream.
  • the target conditional branch prefetch path enables both possible instruction streams for a conditional branch instruction, main and target, to be simultaneously prefetched.
  • the procedural instruction prefetch path allows a supplementary instruction stream, effective for allowing execution of an extended procedures implementing a singular instruction found in the main or target instruction streams; the procedural prefetch path enables these extended procedures to be fetched and executed without clearing at least the main prefetch buffers.
  • an advantage of the present invention is that it provides an architecture that realizes extremely high performance through-put utilizing a fundamentally RISC type core architecture.
  • Another advantage of the present invention is that it provides for the execution of multiple instructions per cycle.
  • a further advantage of the present invention is that it provides for the dynamic selection and utilization of functional units necessary to optimally execute multiple instructions concurrently.
  • Still another advantage of the present invention is that it provides for a register file unit that integrally incorporates a mechanism for supporting a precise state-of-the-machine return capability.
  • Yet another advantage of the present invention is that it incorporates multiple register files within the register file unit that are generalized, typed and capable of multiple register file functions including operation as multiple independent and parallel integer register files, operation of a register file as both a floating point and integer file and operation of a dedicated boolean register file.
  • a still further advantage of the present invention is that load and store operations and the handling of exceptions and interrupts can be performed in a precise manner through the use of a precise state-of-the-machine return capability including efficient instruction cancellation mechanisms and a load/store order synchronizer.
  • a yet still further advantage of the present invention is the provision for dedicated register file unit support of trap states so as to minimize latency and enhance processing through-put.
  • Yet still another advantage of the present invention is the provision for main and target branch instruction prefetch queues whereby even incorrect target branch stream execution ahead minimally impacts the overall processing through-put obtainable by the present invention.
  • the procedural instruction prefetch queue allows an efficient manner of intervening in the execution of the main or target branch instruction streams to allow the effective implementation of new instructions through the execution of procedural routines and, significantly, the externally provided revision of procedural routines implementing built-in procedural instructions.
  • FIG. 1 is a simplified block diagram of the preferred microprocessor architecture implementing the present invention
  • FIG. 2 is a detailed block diagram of the instruction fetch unit constructed in accordance with the present invention.
  • FIG. 3 is a block diagram of the program counter logic unit constructed in accordance with the present invention.
  • FIG. 4 is a further detailed block diagram of the program counter data and control path logic
  • FIG. 5 is a simplified block diagram of the instruction execution unit of the present invention.
  • FIG. 6A is a simplified block diagram of the register file architecture utilized in a preferred embodiment of the present invention.
  • FIG. 6B is a graphic illustration of the storage register format of the temporary buffer register file and utilized in a preferred embodiment of the present invention.
  • FIG. 6C is a graphic illustration of the primary and secondary instruction sets as present in the last two stages of the instruction FIFO unit of the present invention.
  • FIGS. 7A, 7B, and 7C provide a graphic illustration of the reconfigurable states of the primary integer register set as provided in accordance with a preferred embodiment of the present invention
  • FIG. 8 is a graphic illustration of a reconfigurable floating point and secondary integer register set as provided in accordance with the preferred embodiment of the present invention.
  • FIG. 9 is a graphic illustration of a tertiary boolean register set as provided in a preferred embodiment of the present invention.
  • FIG. 10 is a detailed block diagram of the primary integer processing data path portion of the instruction execution unit constructed in accordance with the preferred embodiment of the present invention.
  • FIG. 11 is a detailed block diagram of the primary floating point data path portion of the instruction execution unit constructed in accordance with a preferred embodiment of the present invention.
  • FIG. 12 is a detailed block diagram of the boolean operation data path portion of the instruction execution unit as constructed in accordance with the preferred embodiment of the present invention.
  • FIG. 13 is a detailed block diagram of a load/store unit constructed in accordance with the preferred embodiment of the present invention.
  • FIG. 14 is a timing diagram illustrating the preferred sequence of operation of a preferred embodiment of the present invention in executing multiple instructions in accordance with the present invention
  • FIG. 15 is a simplified block diagram of the virtual memory control unit as constructed in accordance with the preferred embodiment of the present invention.
  • FIG. 16 is a graphic representation of the virtual memory control algorithm as utilized in a preferred embodiment of the present invention.
  • FIG. 17 is a simplified block diagram of the cache control unit as utilized in a preferred embodiment of the present invention.
  • the architecture 100 of the present invention is generally shown in FIG. 1.
  • An Instruction Fetch Unit (IFU) 102 and an Instruction Execution Unit (IEU) 104 are the principal operative elements of the architecture 100.
  • a Virtual Memory Unit (VMU) 108, Cache Control Unit (CCU) 106, and Memory Control Unit (MCU) 110 are provided to directly support the function of the IFU 102 and IEU 104.
  • a Memory Array Unit (MAU) 112 is also provided as a generally essential element for the operation of the architecture 100, though the MAU 112 does not directly exist as an integral component of the architecture 100.
  • the IFU 102, IEU 104, VMU 108, CCU 106, and MCU 110 are fabricated on a single silicon die utilizing a conventional 0.8 micron design rule low-power CMOS process and comprising some 1,200,000 transistors.
  • the standard processor or system clock speed of the architecture 100 is 40 MHz.
  • the internal processor clock speed is 160 MHz.
  • the IFU 102 is primarily responsible for the fetching of instructions, the buffering of instructions pending execution by the IEU 104, and, generally, the calculation of the next virtual address to be used for the fetching of next instructions.
  • instructions are each fixed at a length of 32 bits.
  • Instruction sets, or "buckets" of four instructions are fetched by the IFU 102 simultaneously from an instruction cache 132 within the CCU 106 via a 128 bit wide instruction bus 114.
  • the transfer of instruction sets is coordinated between the IFU 102 and CCU 106 by control signals provided via a control bus 116.
  • the virtual address of a instruction set to be fetched is provided by the IFU 102 via an IFU combined arbitration, control and address bus 118 onto a shared arbitration, control and address bus 120 further coupled between the IEU 104 and VMU 108.
  • Arbitration for access to the VMU 108 arises from the fact that both the IFU 102 and IEU 104 utilize the VMU 108 as a common, shared resource.
  • the low order bits defining an address within a physical page of the virtual address are transferred directly by the IFU 102 to the Cache Control Unit 106 via the control lines 116.
  • the virtualizing, high order bits of the virtual address supplied by the IFU 102 are provided by the address portion of the buses 118, 120 to the VMU 108 for translation into a corresponding physical page address.
  • this physical page address is transferred directly from the VMU 108 to the Cache Control Unit 106 via the address control lines 122 one-half internal processor cycle after the translation request is placed with the VMU 108.
  • the instruction stream fetched by the IFU 102 is, in turn, provided via an instruction stream bus 124 to the IEU 104. Control signals are exchanged between the IFU 102 and the IEU 104 via controls lines 126. In addition, certain instruction fetch addresses, typically those requiring access to the register file present within the IEU 104, are provided back to the IFU via a target address return bus within the control lines 126.
  • the IEU 104 stores and retrieves data with respect to a data cache 134 provided within the CCU 106 via an 80-bit wide bi-directional data bus 130.
  • the entire physical address for IEU data accesses is provided via an address portion of the control bus 128 to the CCU 106.
  • the control bus 128 also provides for the exchange of control signals between the IEU 104 and CCU 106 for managing data transfers.
  • the IEU 104 utilizes the VMU 108 as a resource for converting virtual data address into physical data addresses suitable for submission to the CCU 106.
  • the virtualizing portion of the data address is provided via the arbitration, control and address bus 120 to the VMU 108.
  • the VMU 108 returns the corresponding physical address via the bus 120 to the IEU 104.
  • the IEU 104 requires the physical address for use in ensuring that load/store operations occur in proper program stream order.
  • the CCU 106 performs the generally conventional high-level function of determining whether physical address defined requests for data can be satisfied from the instruction and data caches 132, 134, as appropriate. Where the access request can be properly fulfilled by access to the instruction or data caches 132, 134, the CCU 106 coordinates and performs the data transfer via the data buses 114, 128.
  • the CCU 106 provides the corresponding physical address to the MCU 110 along with sufficient control information to identify whether a read or write access of the MAU 112 is desired, the source or destination cache 132, 134 of the CCU 106 for each request, and additional identifying information to allow the request operation to be correlated with the ultimate data request as issued by the IFU 102 or IEU 104.
  • the MCU 110 preferably includes a port switch unit 142 that is coupled by a uni-directional data bus 136 with the instruction cache 132 of the CCU 106 and a bi-directional data bus 138 to the data cache 134.
  • the port switch 142 is, in essence, a large multiplexer allowing a physical address obtained from the control bus 140 to be routed to any one of a number of ports P 0 -P N 146 O-N and the bi-directional transfer of data from the ports to the data buses 136, 138.
  • Each memory access request processed by the MCU 110 is associated with one of the ports 146 O-N for purposes of arbitrating for access to the main system memory bus 162 as required for an access of the MAU 112.
  • the MCU provides control information via the control bus 140 to the CCU 106 to initiate the transfer of data between either the instruction or data cache 132, 134 and MAU 112 via the port switch 142 and the corresponding one of the ports 146 O-N .
  • the MCU 110 does not actually store or latch data in transit between the CCU 106 and MAU 112. This is done to minimize latency in the transfer and to obviate the need for tracking or managing data that may be uniquely present in the MCU 110.
  • the primary elements of the Instruction Fetch Unit 102 are shown in FIG. 2. The operation and interrelationship of these elements can best be understood by considering their participation in the IFU data and control paths.
  • the IFU data path begins with the instruction bus 114 that receives instruction sets for temporary storage in a prefetch buffer 260.
  • An instruction set from the prefetch buffer 260 is passed through an IDecode unit 262 and then to an IFIFO unit 264. Instruction sets stored in the last two stages of the instruction FIFO 264 are continuously available, via the data buses 278, 280, to the IEU 104.
  • the prefetch buffer unit 260 receives a single instruction set at a time from the instruction bus 114.
  • the full 128 bit wide instruction set is generally written in parallel to one of four 128 bit wide prefetch buffer locations in a Main Buffer (MBUF) 188 portion of the prefetch buffer 260.
  • MBUF Main Buffer
  • Up to four additional instruction sets may be similarly written into two 128 bit wide Target Buffer (TBUF) 190 prefetch buffer locations or to two 128 bit wide Procedural Buffer (EBUF) 192 prefetch buffer locations.
  • TBUF Target Buffer
  • EBUF Procedural Buffer
  • an instruction set in any one of the prefetch buffer locations within the MBUF 188, TBUF 190 or EBUF 192 may be transferred to the prefetch buffer output bus 196.
  • a direct fall through instruction set bus 194 is provided to connect the instruction bus 114 directly with the prefetch buffer output bus 196, thereby bypassing the MBUF, TBUF and
  • the MBUF 188 is utilized to buffer instruction sets in the nominal or main instruction stream.
  • the TBUF 190 is utilized to buffer instruction sets fetched from a tentative target branch instruction stream. Consequently, the prefetch buffer unit 260 allows both possible instruction streams following a conditional branch instruction to be prefetched. This facility obviates the latency for further accesses to at least the CCU 106, if not the substantially greater latency of a MAU 112, for obtaining the correct next instruction set for execution following a conditional branch instruction regardless of the particular instruction stream eventually selected upon resolution of the conditional branch instruction.
  • the provision of the MBUF 188 and TBUF 190 allow the instruction fetch unit 102 to prefetch both potential instruction streams and, as will be discussed below in relationship to the instruction execution unit 104, to further allow execution of the presumed correct instruction stream.
  • any instruction sets in the TBUF 190 may be simply invalidated.
  • the instruction prefetch buffer unit 260 provides for the direct, lateral transfer of those instruction sets from the TBUF 190 to respective buffer locations in the MBUF 188.
  • the prior MBUF 188 stored instruction sets are effectively invalidated by being overwritten by the TBUF 190 transferred instruction sets. Where there is no TBUF instruction set transferred to an MBUF location, that location is simply marked invalid.
  • the EBUF 192 is provided as another, alternate prefetch path through the prefetch buffer 260.
  • the EBUF 192 is preferably utilized in the prefetching of an alternate instruction stream that is used to implement an operation specified by a single instruction, a "procedural" instruction, encountered in the MBUF 188 instruction stream.
  • complex or extended instructions can be implemented through software routines, or procedures, and processed through the prefetch buffer unit 260 without disturbing the instruction streams already prefetched into the MBUF 188.
  • the present invention generally permits handling of procedural instructions that are first encountered in the TBUF 190, prefetching of the procedural instruction stream is held until all prior pending conditional branch instructions are resolved.
  • conditional branch instructions occurring in the procedural instruction stream to be consistently handled through the use of the TBUF 190.
  • the target instruction sets will have been prefetched into the TBUF 190 and can be simply laterally transferred to the EBUF 192.
  • each of the MBUF 188, TBUF 190 and EBUF 192 are coupled to the prefetch buffer output bus 196 so as to provide any instruction set stored by the prefetch unit onto the output bus 196.
  • a flow through bus 194 is provided to directly transfer an instruction set from the instruction bus 114 directly to the output bus 196.
  • the prefetch buffers within the MBUF 188, TBUF 190, EBUF 192 do not directly form a FIFO structure. Instead, the provision of an any buffer location to output bus 196 connectivity allows substantial freedom in the prefetch ordering of instruction sets retrieved from the instruction cache 132. That is, the instruction fetch unit 102 generally determines and requests instruction sets in the appropriate instruction stream order of instructions. However, the order in which instruction sets are returned to the IFU 102 is allowed to occur out-of-order as appropriate to match the circumstances where some requested instruction sets are available and accessible from the CCU 106 alone and others require an access of the MAU 112.
  • instruction sets may not be returned in order to the prefetch buffer unit 260, the sequence of instruction sets output on the output bus 196 must generally conform to the order of instruction set requests issued by the IFU 102; the in-order instruction stream sequence subject to, for example, tentative execution of a target branch stream.
  • the IDecode unit 262 receives the instruction sets, generally one per cycle, IFIFO unit 264 space permitting, from the prefetch buffer output bus 196. Each set of four instructions that make up a single instruction set is decoded in parallel by the IDecode unit 262. While relevant control flow information is extracted via lines 318 for the benefit of the control path portion of the IFU 102, the contents of the instruction set is not altered by the IDecode unit 262.
  • Instruction sets from the IDecode Unit 262 are provided onto a 128 bit wide input bus 198 of the IFIFO unit 264.
  • the IFIFO unit 264 consists of a sequence of master/slave registers 200, 204, 208, 212, 216, 220, 224. Each register is coupled to its successor to allow the contents of the master registers 200, 208, 216 to be transferred during a first half internal processor cycle of FIFO operation to the slave registers 204, 212, 220 and then to the next successive master register 208, 216, 224 during the succeeding half-cycle of operation.
  • the input bus 198 is connected to the input of each of the master registers 200, 208, 216, 224 to allow loading of an instruction set from the IDecode unit 262 directly in to a master register during the second half-cycle of FIFO operation.
  • loading of a master register from the input bus 198 need not occur simultaneously with a FIFO shift of data within the IFIFO unit 264. Consequently, the IFIFO unit 264 can be continuously filled from the input bus 198 regardless of the current depth of instruction sets stored within the instruction FIFO unit 264 and, further, independent of the FIFO shifting of data through the IFIFO unit 264.
  • Each of the master/slave registers 200, 204, 208, 212, 216, 220, 224 in addition to providing for the full parallel storage of a 128 bit wide instruction set, also provides for the storage of several bits of control information in the respective control registers 202, 206, 210, 214, 218, 222, 226.
  • the preferred set of control bits include exception miss and exception modify, (VMU), no memory (MCU), branch bias, stream, and offset (IFU).
  • VMU exception miss and exception modify,
  • MCU no memory
  • IFU offset
  • This control information originates from the control path portion of the IFU 102 simultaneous with the loading of an IFIFO master register with a new instruction set from the input bus 198. Thereafter, the control register information is shifted in parallel concurrently with the instruction sets through the IFIFO unit 264.
  • the output of instruction sets from the IFIFO unit 264 is obtained simultaneously from the last two master registers 216, 224 on the I -- Bucket -- 0 and I -- Bucket -- 1 instruction set output buses 278, 280.
  • the corresponding control register information is provided on the IBASV0 and IBASV1 control field buses 282, 284. These output buses 278, 282, 280, 284 are all provided as the instruction stream bus 124 to the IEU 104.
  • the control path for the IFU 102 directly supports the operation of the prefetch buffer unit 260, IDecode unit 262 and IFIFO unit 264.
  • a prefetch control logic unit 266 primarily manages the operation of the prefetch buffer unit 260.
  • the prefetch control logic unit 266 and IFU 102 in general, receives the system clock signal via the clock line 290 for synchronizing IFU operations with those of the IEU 104, CCU 106 and VMU 108. Control signals appropriate for the selection and writing of instruction sets into the MBUF 188, TBUF 190 and EBUF 192 are provided on the control lines 304.
  • a number of control signals are provided on the control lines 316 to the prefetch control logic unit 266. Specifically, a fetch request control signal is provided to initiate a prefetch operation. Other control signals provided on the control line 316 identify the intended destination of the requested prefetch operation as being the MBUF 188, TBUF 190 or EBUF 192.
  • the prefetch control logic unit 266 In response to a prefetch request, the prefetch control logic unit 266 generates an ID value and determines whether the prefetch request can be posted to the CCU 106. Generation of the ID value is accomplished through the use of a circular four-bit counter.
  • the use of a four-bit counter is significant in three regards. The first is that, typically a maximum of nine instruction sets may be active at one time in the prefetch buffer unit 260; four instruction sets in the MBUF 188, two in the TBUF 190, two in the EBUF 192 and one provided directly to the IDecode unit 262 via the flow through bus 194. Secondly, instruction sets include four instructions of four bytes each. Consequently, the least significant four bits of any address selecting an instruction set for fetching are superfluous. Finally, the prefetch request ID value can be easily associated with a prefetch request by insertion as the least significant four bits of the prefetch request address; thereby reducing the total number of address lines required to interface with the CCU 106.
  • the architecture 100 provides for the return of the ID request value with the return of instruction sets from the CCU 106.
  • the out-of-order instruction set return capability may result in exhaustion of the sixteen unique IDs.
  • a combination of conditional instructions executed out-of-order, resulting in additional prefetches and instruction sets requested but not yet returned can lead to potential re-use of an ID value. Therefore, the four-bit counter is preferably held, and no further instruction set prefetch requests issued, where the next ID value would be the same as that associated with an as yet outstanding fetch request or another instruction set then pending in the prefetch buffer 260.
  • the prefetch control logic unit 266 directly manages a prefetch status array 268 which contains status storage locations logically corresponding to each instruction set prefetch buffer location within the MBUF 188, TBUF 190 and EBUF 192.
  • the prefetch control logic unit 266, via selection and data lines 306, can scan, read and write data to the status register array 268.
  • a main buffer register 308 provides for storage of four, four-bit ID values (MB ID), four single-bit reserved flags (MB RES) and four single-bit valid flags (MB VAL), each corresponding by logical bit-position to the respective instruction set storage locations within the MBUF 180.
  • a target buffer register 310 and extended buffer register 312 each provide for the storage of two four-bit ID values (TB ID, EB ID), two single-bit reserved flags (TB RES, EB RES), and two single-bit valid flags (TB VAL, EB VAL).
  • a flow through status register 314 provides for the storage of a single four-bit ID value (FT ID), a single reserved flag bit (FT RES), and a single valid flag bit (FT VAL).
  • the status register array 268 is first scanned and, as appropriate, updated by the prefetch control logic unit 266 each time a prefetch request is placed with the CCU 106 and subsequently scanned and updated each time an instruction set is returned. Specifically, upon receipt of the prefetch request signal via the control lines 316, the prefetch control logic unit 266 increments the current circular counter generated ID value, scans the status register array 268 to determine whether the ID value is available for use and whether a prefetch buffer location of the type specified by the prefetch request signal is available, examines the state of the CCU IBUSY control line 300 to determine whether the CCU 106 can accept a prefetch request and, if so, asserts a CCU IREAD control signal on the control line 298, and places the incremented ID value on the CCU ID out bus 294 to the CCU 106.
  • a prefetch storage location is available for use where both of the corresponding reserved and valid status flags are false.
  • the prefetch request ID is written into the ID storage location within the status register array 268 corresponding to the intended storage location within the MBUF 188, TBUF 190, or EBUF 192 concurrent with the placement of the request with the CCU 106.
  • the corresponding reserved status flag is set true.
  • the CCU IREADY signal is asserted on control line 302 and the corresponding instruction set ID is provided on the CCU ID control lines 296.
  • the prefetch control logic unit 266 scans the ID values and reserved flags within the status register array 268 to identify the intended destination of the instruction set within the prefetch buffer unit 260. Only a single match is possible. Once identified, the instruction set is written via the bus 114 into the appropriate location within the prefetch buffer Unit 260 or, if identified as a flow through request, provided directly to the IDecode unit 262. In either case, the valid status flag in the corresponding status register array is set true.
  • the PC logic unit 270 tracks the virtual address of the MBUF 188, TBUF 190 and EBUF 192 instruction streams through the entirety of the IFU 102. In performing this function, the PC logic block 270 both controls and operates from the IDecode unit 262. Specifically, portions of the instructions decoded by the IDecode unit 262 potentially relevant to a change in the program instruction stream flow are provided on the bus 318 to a control flow detection unit 274 and directly to the PC logic block 270.
  • the control flow detection unit 274 identifies each instruction in the decoded instruction set that constitutes a control flow instruction including conditional and unconditional branch instructions, call type instructions, software traps procedural instructions and various return instructions.
  • the control flow detection unit 274 provides a control signal, via lines 322, to the PC logic unit 270 to identify the location and specific nature of the control flow instructions within the instruction set present in the IDecode unit 262.
  • the PC logic unit 270 determines the target address of the control flow instruction, typically from data provided within the instruction and transferred to the PC logic unit via lines 318. Where, for example, a branch logic bias has been selected to execute ahead for conditional branch instructions, the PC logic unit 270 will begin to direct and separately track the prefetching of instruction sets from the conditional branch instruction target address.
  • the PC logic unit 270 will further assert a control signal, via lines 316, selecting the destination of the prefetch to be the TBUF 190, assuming that prior prefetch instruction sets were directed to the MBUF 188 or EBUF 192.
  • the prefetch control logic unit 266 determines that a prefetch request can be supplied to the CCU 106, the prefetch control logic unit 266 provides an enabling signal, again via lines 316, to the PC logic unit 270 to enable the provision of a page offset portion of the target address (CCU PADDR [13:4]) via the address lines 324 directly to the CCU 106.
  • the PC logic unit 270 where a new virtual to physical page translation is required further provides a VMU request signal via control line 328 and the virtualizing portion of the target address (VMU VADDR [31:14]) via the address lines 326 to the VMU 108 for translation into a physical address.
  • VMU VADDR [31:14] virtualizing portion of the target address
  • the previous translation result is maintained in an output latch coupled to the bus 122 for immediate use by the CCU 106.
  • VMU exception and VMU miss control lines 332, 334 Operational errors in the VMU 108 in performing the virtual to physical translation requested by the PC logic unit 270 are reported via the VMU exception and VMU miss control lines 332, 334.
  • the VMU miss control line 334 reports a translation lookaside buffer (TLB) miss.
  • TLB translation lookaside buffer
  • the VMU exception control signal, on VMU exception line 332, is raised for all other exceptions.
  • the PC logic unit handles the error condition by storing the current execution point in the instruction stream and then prefetching, as if in response to an unconditional branch, a dedicated exception handling routine instruction stream for diagnosing and handling the error condition.
  • the VMU exception and miss control signals identify the general nature of the exception encountered, thereby allowing the PC logic unit 270 to identify the prefetch address of a corresponding exception handling routine.
  • the IFIFO control logic unit 272 is provided to directly support the IFIFO unit 264. Specifically, the PC logic unit 270 provides a control signal via the control lines 336 to signal the IFIFO control logic unit 272 that an instruction set is available on the input bus 198 from the IDecode unit 262. The IFIFO control unit 272 is responsible for selecting the deepest available master register 200,208,216, 224 for receipt of the instruction set. The output of each of the master control registers 202,210,218, 226 is provided to the IFIFO control unit 272 via the control bus 338.
  • the control bits stored by each master control register includes a two-bit buffer address (IF -- Bx -- ADR), a single stream indicator bit (IF -- Bx -- STRM), and a single valid bit (IF -- Bx -- VLD).
  • the two bit buffer address identifies the first valid instruction within the corresponding instruction set. That is, instruction sets returned by the CCU 106 may not be aligned such that the target instruction of a branch operation, for example, is located in the initial instruction location within the instruction set. Thus, the buffer address value is provided to uniquely identify the initial instruction within an instruction set that is to be considered for execution.
  • the stream bit is used essentially as a marker to identify the location of instruction sets containing conditional control flow instructions, and giving rise to potential control flow changes, in the stream of instructions through the IFIFO unit 264.
  • the main instruction stream is processed through the MBUF 188 generally with a stream bit value of 0.
  • the corresponding instruction set is marked with a stream bit value of 1.
  • the conditional branch instruction is detected by the IDecode unit 262. Up to four conditional control flow instructions may be present in the instruction set.
  • the instruction set is then stored in the deepest available master register of the IFIFO unit 264.
  • the current IEU 104 execution point address (DPC), the relative location of the conditional instruction containing instruction set as identified by the stream bit, and the conditional instruction location offset in the instruction set, as provided by the control flow detector 274, are combined with the relative branch offset value as obtained from a corresponding branch instruction field via control lines 318.
  • the result is a branch target virtual address that is stored by the PC logic unit 270.
  • the initial instruction sets of the target instruction stream may then be prefetched into the TBUF 190 utilizing this address.
  • the IFIFO unit 264 will continue to be loaded from either the MBUF 188 or TBUF 190. If a second instruction set containing one or more conditional flow instructions is encountered, the instruction set is marked with a stream bit value of 0. Since a second target stream cannot be fetched, the target address is calculated and stored by the PC logic unit 270, but no prefetch is performed. In addition, no further instruction sets can be processed through the IDecode unit 262, or at least none that are found to contain a conditional flow control instruction.
  • the PC logic unit 270 in the preferred embodiments of the present invention, can manage up to eight conditional flow instructions occurring in up to two instruction sets.
  • the target addresses for each of the two instruction sets marked by stream bit changes are stored in an array of four address registers with each target address positioned logically with respect to the location of the corresponding conditional flow instruction in the instruction set.
  • the PC logic unit 270 will direct the prefetch control unit 260, via control signals on lines 316, to transfer the contents of the TBUF 190 to the MBUF 188, if the branch is taken, and to mark invalid the contents of the TBUF 190. Any instruction sets in the IFIFO unit 264 from the incorrect instruction stream, target stream if the branch is not taken and main stream if the branch is taken, are cleared from the IFIFO unit 264.
  • the target addresses of the second stream bit marked instruction set are promoted to the first array of address registers.
  • a next instruction set containing conditional flow instructions can then be evaluated through the IDecode unit 262.
  • the toggle usage of the stream bit allows potential control flow changes to be marked and tracked through the IFIFO unit 264 for purposes of calculating branch target addresses and for marking the instruction set location above which to clear where the branch bias is subsequently determined to have been incorrect for a particular conditional flow control instruction.
  • the IFIFO control logic unit 272 simply resets the valid bit flag in the control registers of the corresponding master registers of the IFIFO unit 264.
  • the clear operation is instigated by the PC logic unit 270 in a control signal provided on lines 336.
  • the inputs of each of the master control registers 202, 210, 218, 226 are directly accessible by the IFIFO control logic unit 272 via the status bus 230.
  • the bits within these master control registers. 202, 210, 218, 226 may be set by the IFIFO control unit 272 concurrent with or independent of a data shift operation by the IFIFO unit 264.
  • This capability allows an instruction set to be written into any of the master registers 200,208, 216, 224, and the corresponding status information to be written into the master control registers 202, 210, 218, 226 asynchronously with respect to the operation of the IEU 104.
  • an additional control line on the control and status bus 230 enables and directs the FIFO operation of the IFIFO unit 264.
  • An IFIFO shift is performed by the IFIFO control logic unit 272 in response to the shift request control signal provided by the PC logic unit 270 via the control lines 336.
  • the IFIFO control unit 272, based on the availability of a master register 200, 208, 216, 224 to receive an instruction set provides a control signal, via lines 316, to the prefetch control unit 266 to request the transfer of a next appropriate instruction set from the prefetch buffers 260. On transfer of the instruction set, the corresponding valid bit in the array 268 is reset.
  • the control interface between the IFU 102 and IEU 104 is provided by the control bus 126.
  • This control bus 126 is coupled to the PC logic unit 270 and consists of a number of control, address and specialized data lines.
  • Interrupt request and acknowledge control signals allow the IFU 102 to signal and synchronize interrupt operations with the IEU 104.
  • An externally generated interrupt signal is provided on a line 292 to the logic unit 270.
  • an interrupt request control signal provided on lines 340, causes the IEU 104 to cancel tentatively executed instructions. Information regarding the nature of an interrupt is exchanged via interrupt information lines 341.
  • the IEU 104 When the IEU 104 is ready to begin receiving instruction sets prefetched from the interrupt service routine address determined by the PC logic unit 270, the IEU 104 asserts an interrupt acknowledge control signal on the lines 340. Execution of the interrupt service routine, as prefetched by the IFU 102, will then commence.
  • IFIFO read (IFIFO RD) control signal is provided by the IEU 104 to signal that the instruction set present in the deepest master register 224 has been completely executed and that a next instruction set is desired.
  • the PC logic unit 270 directs the IFIFO control logic unit 272 to perform a IFIFO shift operation on the IFIFO unit 264.
  • PC INC/SIZE PC increment request and size value
  • DPC point of execution program counter
  • a target address (TARGET ADDR) is returned on the address lines 346 to the PC logic unit 270.
  • the target address is the virtual target address of a branch instruction that depends on data stored within the register file of the IEU 104. Operation of the IEU 104 is therefore required to calculate the target address.
  • Control flow result (CF RESULT) control signals are provided on the control lines 348 to the PC logic unit 270 to identify whether any currently pending conditional branch instruction has been resolved and whether the result is either a branch taken or not taken. Based on these control signals, the PC logic unit 270 can determine which of the instruction sets in the prefetch buffer 260 and IFIFO unit 264 must be cancelled, if at all, as a consequence of the execution of the conditional flow instruction.
  • IEU Return IEU instruction return type control signals
  • IEU Return IEU instruction return type control signals
  • These instructions include a return from procedural instruction, return from trap, and return from subroutine call.
  • the return from trap instruction is used equally in hardware interrupt and software trap handling routines.
  • the subroutine call return is also used in conjunction with jump-and-link type calls.
  • the return control signals are provided to alert the IFU 102 to resume its instruction fetching operation with respect to the previously interrupted instruction stream. Origination of the signals from the IEU 104 allows the precise operation of the system 100 to be maintained; the resumption of an "interrupted" instruction stream is performed at the point of execution of the return instruction.
  • a current instruction execution PC address (Current IF -- PC) is provided on an address bus 352 to the IEU 104.
  • This address value, the DPC identifies the precise instruction being executed by the IEU 104. That is, while the IEU 104 may tentatively execute ahead instructions past the current IF -- PC address, this address must be maintained for purposes of precise control of the architecture 100 with respect to the occurrence of interrupts, exceptions, and any other events that would require knowing the precise state-of-the-machine.
  • the PC Inc/Size signal is provided to the IFU 102 and immediately reflected back in the current IF -- PC address value.
  • an address and bi-directional data bus 354 is provided for the transfer of special register data. This data may be programmed into or read from special registers within the IFU 102 by the IEU 104. Special register data is generally loaded or calculated by the IEU 104 for use by the IFU 102.
  • FIG. 3 A detailed diagram of the PC Logic unit 270 including a PC control unit 362, interrupt control unit 363, prefetch PC control unit 364 and execution PC control unit 366, is shown in FIG. 3.
  • the PC control unit 362 provides timing control over the prefetch and execution PC control units 364, 366 in response to control signals from the prefetch control logic unit 266, IFIFO control logic unit 272, and the IEU 104, via the interface bus 126.
  • the Interrupt Control Unit 363 is responsible for managing the precise processing of interrupts and exceptions, including the determination of a prefetch trap address offset that selects an appropriate handling routine to process a respective type of trap.
  • the prefetch PC control unit 364 is, in particular, responsible for managing program counters necessary to support the prefetch buffers 188, 190, 192, including storing return addresses for traps handling and procedural routine instruction flows. In support of this operation, the prefetch PC control unit 364 is responsible for generating the prefetch virtual address including the CCU PADDR address on the physical address bus lines 324 and the VMU VMADDR address on the address lines 326. Consequently, the prefetch PC control unit 364 is responsible for maintaining the current prefetch PC virtual address value.
  • the prefetch operation is generally initiated by the IFIFO control logic unit 272 via a control signal provided on the control lines 316.
  • the PC control unit 362 generates a number of control signals provided on the control lines 372 to operate the prefetch PC control unit 364 to generate the PADDR and, as needed, the VMADDR addresses on the address lines 324, 326.
  • An increment signal having a value of 0 to four, may be also provided on the control lines 374 depending on whether the PC control unit 362 is re-executing an instruction set fetch at the present prefetch address, aligning for the second in a series of prefetch requests, or selecting the next full sequential instruction set for prefetch.
  • the current prefetch address PF -- PC is provided on the bus 370 to the execution PC control unit 366.
  • New prefetch addresses originate from a number of sources.
  • a primary source of addresses is the current IF -- PC address provided from the execution PC control unit 366 via bus 352. Principally, the IF -- PC address provides a return address .for subsequent use by the prefetch PC control unit 364 when an initial call, trap or procedural instruction occurs.
  • the IF -- PC address is stored in registers in the prefetch PC control unit 364 upon each occurrence of these instructions. In this manner, the PC control unit 362, on receipt of a IEU return signal, via control lines 350, need merely select the corresponding return address register within the prefetch PC control unit 364 to source a new prefetch virtual address, thereby resuming the original program instruction stream.
  • Another source of prefetch addresses is the target address value provided on the relative target address bus 382 from the execution PC control unit 366 or on the absolute target of address bus 346 provided from the IEU 104.
  • Relative target addresses are those that can be calculated by the execution PC control unit 366 directly. Absolute target addresses must be generated by the IEU 104, since such target addresses are dependant on data contained in the IEU register file.
  • the target address is routed over the target address bus 384 to the prefetch PC control unit 364 for use as a prefetch virtual address.
  • an operand portion of the corresponding branch instruction is also provided on the operand displacement portion of the bus 318 from the IDecode unit 262.
  • a return address bus 352' is provided to transfer the current IF -- PC value (DPC) to the prefetch PC control unit 364. This address is utilized as a return address where an interrupt, trap or other control flow instruction such as a call has occurred within the instruction stream.
  • the prefetch PC control unit 364 is then free to prefetch a new instruction stream.
  • the PC control unit 362 receives an IEU return signal, via lines 350, from the IEU 104 once the corresponding interrupt or trap handling routine or subroutine has been executed.
  • the PC control unit 362 selects, via one of the PFPC control signals on line 372 and based on an identification of the return instruction executed as provided via lines 350, a register containing the current return virtual address. This address is then used to continue the prefetch operation by the PC logic unit 270.
  • Another source of prefetch virtual addresses is from the special register address and data bus 354.
  • An address value, or at least a base address value, calculated or loaded by the IEU 104 is transferred as data via the bus 354 to the prefetch PC control unit 364.
  • the base addresses include the base addresses for the trap address table, a fast trap table, and a base procedural instruction dispatch table.
  • the bus 354 also allows many of the registers in the prefetch and execution PC control units 364, 366 to be read to allow corresponding aspects of the state-of-the-machine to be manipulated through the IEU 104.
  • the execution PC control unit 366 subject to the control of the PC control unit 362 is primarily responsible for calculating the current IF -- PC address value. In this role, the execution PC control unit 366 responds to control signals provided by the PC control unit 362 on the ExPC control lines 378 and increment/size control signals provided on the control lines 380 to adjust the IF -- PC address. These control signals are generated primarily in response to the IFIFO read control signal provided on line 342 and the PC increment/size value provided on the control lines 344 from the IEU 104.
  • FIG. 4 provides a detailed block diagram of the prefetch and execution PC control units 364, 366. These units primarily consist of registers, incrementors and the like, selectors and adder blocks. Control for managing the transfer of data between these blocks is provided by the PC Control Unit 362 via the PFPC control lines 372, the ExPC control lines 378 and the Increment Control lines 374, 380. For purposes of clarity, those specific control lines are not shown in the block diagram of FIG. 4. However, it should be understood that these control signals are provided to the blocks shown as described herein.
  • a prefetch selector (PF -- PC SEL) 390 that operates as a central selector of the current prefetch virtual address.
  • This current prefetch address is provided on the output bus 392 from the prefetch selector to an incrementor unit 394 to generate a next prefetch address.
  • This next prefetch address is provided on the incrementor output bus 396 to a parallel array of registers MBUF PFnPC 398, TBUF PFnPC 400, and EBUF PFnPC 402. These registers 398, 400, 402 effectively store the next instruction prefetch address.
  • prefetch addresses are held for the MBUF 188, TBUF 190, and EBUF 192.
  • the prefetch addresses, as stored by the MBUF, TBUF and EBUF PFnPC registers 398, 400, 402 are respectively provided by the address buses 404, 408, 410 to the prefetch selector 390.
  • the PC control unit 362 can direct an immediate switch of the prefetch instruction stream merely by directing the selection, by the prefetch selector 390, of another one of the prefetch registers 398, 400, 402.
  • the register block 412 includes a trap return address register, a procedural instruction return address register, a procedural instruction dispatch table base address register, a trap routine dispatch table base address register, and a fast trap routine table base address register. Under the control of the PC control unit 362, these return address registers may receive the current IF -- PC execution address via the bus 352'.
  • the address values stored by the return and base address registers within the register block 412 may be both read and written independently by the IEU 104.
  • the register are selected and values transferred via the special register address and data bus 354.
  • a selector within the special register block 412 allows the addresses stored by the registers of the register block 412 to be put on the special register output bus 416 to the prefetch selector 390. Return addresses are provided directly to the prefetch selector 390. Base address values are combined with the offset value provided on the interrupt offset bus 373 from the interrupt control unit 363. Once sourced to the prefetch selector 390 via the bus 373', a special address can be used as the initial address for a new prefetch instruction stream by thereafter continuing the incremental loop of the address through the incrementor 394 and one of the prefetch registers 398, 400, 402.
  • Another source of addresses to the prefetch selector 390 is an array of registers within the target address register block 414.
  • the target registers within the block 414 provide for storage of, in the preferred embodiment, eight potential branch target addresses. These eight storage locations logically correspond to the eight potentially executable instructions held in the lowest two master registers 216, 224 of the IFIFO unit 264. Since any, and potentially all of the those instructions could be conditional branch instructions, the target register block 414 allows for their precalculated target addresses to be stored awaiting use for fetching of a target instruction stream through the TBUF 190.
  • a conditional branch bias is set such that the PC Control Unit 362 immediately begins prefetching of a target instruction stream
  • the target address is immediately fed through the target register block 414 via the address bus 418 to the prefetch selector 390. Once incremented by the incrementor 394, the address is stored back to the TBUF PFnPC 400 for use in subsequent prefetch operations of the target instruction stream. If additional branch instructions occur within the target instruction stream, the target addresses of such secondary branches are calculated and stored in the target register array 414 pending use upon resolution of the first conditional branch instruction.
  • a calculated target address as stored by the target register block 414 is transferred from a target address calculation unit within the execution PC control unit 366 via the address lines 382 or from the IEU 104 via the absolute target address bus 346.
  • the Address value transferred through the prefetch PF -- PC selector 390 is a full thirty-two bit virtual address value.
  • the page size, in the preferred embodiment of the present invention is fixed at 16 KBytes, corresponding to the maximum page offset address value [13:0]. Therefore, a VMU page translation is not required unless there is a change in the current prefetch virtual page address [27:14].
  • a comparator in the prefetch selector 390 detects this circumstance.
  • a VMU translation request signal (VMXLAT) is provided via line 372' to the PC control unit 362 when there is a change in the virtual page address, either due incrementing across a page boundary or a control flow branch to another page address.
  • the PC control unit 362 directs the placement of the VMU VMADDR address on lines 326, in addition to the CCU PADDR on lines 324, both via a buffer unit 420, and the appropriate control signals on the VMU control lines 326, 328, 330 to obtain a VMU virtual to physical page translation. Where a page translation is not required, the current physical page address [31:14] is maintained by a latch at the output of the VMU unit 108 on the bus 122.
  • the virtual address provided onto the bus 370 is incremented by the incrementor 394 in response to a signal provided on the increment control line 374.
  • the incrementor 394 increments by a value representing an instruction set (four instructions or sixteen bytes) in order to select a next instruction set.
  • the low-order four bits of a prefetch address as provided to the CCU unit 106 are zero. Therefore the actual target address instruction in a first branch target instruction set may not be located in the first instruction location. However, the low-order four bits of the address are provided to the PC control unit 362 to allow the proper first branch instruction location to be known by the IFU 102.
  • the detection and handling by returning the low order bits [3:2] of a target address as the two-bit buffer address, to select the proper first instruction for execution in a non-aligned target instruction set, is performed only for the first prefetch of a new instruction stream, i.e., any first non-sequential instruction set address in an instruction stream.
  • the non-aligned relationship between the address of the first instruction in an instruction set and the prefetch address used in prefetching the instruction set can and is thereafter ignored for the duration of the current sequential instruction stream.
  • the remainder of the functional blocks shown in FIG. 4 comprise the execution PC control unit 366.
  • the execution PC control unit 366 incorporates its own independently functioning program counter incrementor. Central to this function is an execution selector (DPC SEL) 430.
  • This execution address is provided to an adder unit 434.
  • the increment/size control signals provided on the lines 380 specify an instruction increment value of from one to four that the adder unit 434 adds to the address obtained from the selector 430.
  • the adder 432 additionally performs an output latch function, the incremented next execution address is provided on the address lines 436 directly back to the execution selector 430 for use in the next execution increment cycle.
  • the initial execution address and all subsequent new stream addresses are obtained through a new stream register unit 438 via the address lines 440.
  • the new stream register unit 438 allows the new current prefetch address, as provided on the PFPC address bus 370 from the prefetch selector 390 to be passed on to the address bus 440 directly or stored for subsequent use. That is, where the prefetch PC control unit 364 determines to begin prefetching at a new virtual address, the new stream address is temporarily stored by the new stream register unit 438.
  • the PC control unit 362 by its participation in both the prefetch and execution increment cycles, holds the new stream address in the new stream register 438 unit until the execution address has reached the program execution point corresponding to the control flow instruction that instigated the new instruction stream.
  • the new stream address is then output from the new stream register unit 438 to the execution selector 430 to initiate the independent generation of execution addresses in the new instruction stream.
  • the new stream register unit 438 provides for the buffering of two control flow instruction target addresses.
  • the new stream address By the immediate availability of the new stream address, there is essentially no-latency in the switching of the execution PC control unit 366 from the generation of a current sequence of execution addresses to a new stream sequence of execution addresses.
  • an IF -- PC selector (IF -- PC SEL) 442 is provided to ultimately issue the current IF -- PC address on the address bus 352 to the IEU 104.
  • the inputs to the IF -- PC selector 442 are the output addresses obtained from either the execution selector 430 or new stream register unit 438.
  • the IF -- PC selector 442 is directed by the PC control unit 362 to select the execution address output by the execution selector 430.
  • the selected address provided from the new stream register unit 438 can be bypassed via bus 440 directly to the IF -- PC selector 442 for provision as the current IF -- PC execution address.
  • the execution PC control unit 366 is capable of calculating all relative branch target addresses.
  • the current execution point address and the new stream register unit 438 provided address are received by a control flow selector (CF -- PC) 446 via the address buses 352', 440. Consequently, the PC control unit 362 has substantial flexibility in selecting the exact initial address from which to calculate a target address.
  • This initial, or base, address is provided via address bus 454 to a target address ALU 450.
  • a second input value to the target ALU 450 is provided from a control flow displacement calculation unit 452 via bus 458.
  • Relative branch instructions in accordance with the preferred architecture 100, incorporate a displacement value in the form of an immediate mode constant that specifies a relative new-target address.
  • the control flow displacement calculation unit 452 receives the operand displacement value initially obtained via the IDecode unit operand output bus 318. Finally, an offset register value is provided to the target address ALU 450 via the lines 456. The offset register 448 receives an offset value via the control lines 378' from the PC control unit 362. The magnitude of the offset value is determined by the PC control unit 362 based on the address offset between the base address provided on the address lines 454 and the address of the current branch instruction for which the relative target address is being calculated.
  • the PC control unit 362 through its control of the IFIFO control logic unit 272 tracks the number of instructions separating the instruction at the current execution point address (requested by CP -- PC) and the instruction that is currently being processed by the IDecode unit 262 and, therefore, being processed by the PC logic unit 270 to determine the target address for that instruction.
  • the target address is written into a corresponding one of the target registers 414 via the address bus 382.
  • a 32 bit incrementor adjusts the address value in the MBUF PFnPC by sixteen bytes ( ⁇ 16) with each prefetch cycle.
  • the target address of a relative unconditional control flow is calculated by the IFU from register data maintained by the IFU and from operand data following the control flow instruction.
  • the target address of an absolute unconditional control flow instruction is eventually calculated by the IEU from a register reference, a base register value, and an index register value.
  • a procedural instruction may be prefetched in the main or branch target instruction stream. If fetched in a target stream, stall prefetching of the procedural stream until the conditional control flow instruction resolves and the procedural instruction is transferred to the MBUF. This allows the TBUF to be used in handling of conditional control flows that occur in the procedural instruction stream.
  • a procedural instruction should not appear in a procedural instruction stream, i.e., procedural instructions should not be nested: a return from procedural instruction will return execution to the main instruction flow. In order to allow nesting, an additional, dedicated return from nested procedural instruction would be required. While the architecture can readily support such an instruction, the need for a nested procedural instruction capability will not likely improve the performance of the architecture.
  • a procedural instruction stream that, in turn, includes first and second conditional control flow instruction containing instruction sets will stall prefetching with respect to the second conditional control flow instruction set until any conditional control flow instructions in the first such instruction set are resolved and the second conditional control flow instruction set has been transferred to the MBUF.
  • procedural instructions provide a relative offset, included as an immediate mode operand field of the instruction, to identify the procedural routine starting address:
  • the offset value provided by the procedural instruction is combined with a value contained in a procedural base address (PBR) register maintained in the IFU.
  • PBR procedural base address
  • the starting address of the procedural stream is simultaneously provided to the new stream register unit and to the incrementor for incrementing ( ⁇ 16); the incremented address is then stored in the EBUF PFnPC.
  • a 32 bit incrementor adjusts address value ( ⁇ 16) in the EBUF PFnPC with each procedural instruction prefetch cycle.
  • the target address of a relative unconditional control flow instruction is calculated by the IFU from IFU maintained register data and from the operand data provided within an immediate mode operand field of the control flow instruction.
  • the target address of an absolute unconditional branch is calculated by the IEU from a register reference, a base register value, and an index register value.
  • prefetching continues from the address stored in the uPC register, which is then incremented ( ⁇ 16) and returned to the MBUF PFnPC register for subsequent prefetches.
  • Branch Instruction Stream Processing TBUF PFnPC
  • the target address is determined by the IFU if the target address is relative to the current address or by the IEU for absolute addresses.
  • 3.2.3 target instruction stream instructions are prefetched into the TBUF and then routed into the IFIFO for subsequent execution; if the IFIFO and TBUF becomes full, stall prefetching.
  • the 32 bit incrementor adjusts ( ⁇ 16) the address value in the TBUF PFnPC with each prefetch cycle.
  • conditional control flow instruction in the first conditional instruction set is relative, calculate the target address and store in the target registers.
  • conditional control flow instructions in the first conditional instruction set is absolute, wait for the IEU to calculate the target address and return the address to the target registers.
  • 3.3.3.3 transfer the prefetched TBUF instructions to the MBUF or EBUF, as determined from the state of the procedure-in-progress bit.
  • the starting address of an interrupt handler is determined as the vector number offset into a predefined table of trap handler entry points.
  • the starting address of the trap handler is determined from the trap number offset combined with a base address value stored in the TBR or FTB register.
  • the starting address of the exception handler is determined from the trap number offset into a predefined table of trap handler entry point.
  • Traps may nest, provided the trap handling routine saves the xPC address prior to a next allowed trap--failure to do so will corrupt the state of the machine if a trap occurs prior to completion of the current trap operation.
  • the trap handling routine may provide for the xPC address to be saved to a predefined location and interrupts re-enabled; the xPC register is read/write via a special register move instruction and the special register address and data bus.
  • the xPC address is returned to the current instruction stream register MBUF or EBUF PFnPC, as determined from the state of the procedure-in-progress bit, and prefetching continues from that address.
  • Interrupts and exceptions will be processed, as long as they are enabled, regardless of whether the processor is executing from the main instruction stream or a procedural instruction stream. Interrupts and exceptions are serviced in priority order, and persist until cleared.
  • the starting address of a trap handler is determined as the vector number offset into a predefined table of trap handler addresses as described below.
  • Interrupts and exceptions are of two basic types in the present embodiment, those which occur synchronously with particular instructions in the instruction stream, and those which occur asynchronously with particular instructions in the instruction stream.
  • the terms interrupt, exception, trap and fault are used interchangeably herein.
  • Asynchronous interrupts are generated by hardware, either on-chip or off-chip, which does not operate synchronously with the instruction stream.
  • interrupts generated by an on-chip timer/counter are asynchronous, as are hardware interrupts and non-maskable interrupts (NMI) provided from off-chip.
  • NMI non-maskable interrupts
  • Synchronous exceptions are those that occur synchronously with instructions in the instruction stream. These exceptions occur in relation to particular instructions, and are held until the relevant instruction is to be executed.
  • synchronous exceptions arise during prefetch, during instruction decode, or during instruction execution.
  • Prefetch exceptions include, for example, TLB miss or other VMU exceptions.
  • Decode exceptions arise, for example, if the instruction being decoded is an illegal instruction or does not match the current privilege level of the processor.
  • Execution exceptions arise due to arithmetic errors, for example, such as divide by zero. Whenever these exceptions occur, the preferred embodiments maintain them in correspondence with the particular instruction which caused the exception, until the time at which that instruction is to be retired. At that time, all prior completed instructions are retired, any tentative results from the instruction which caused the exception are flushed, as are the tentative results of any following tentatively executed instructions. Control is then transferred to an exception handler corresponding to the highest priority exception which occurred for that instruction.
  • Asynchronous interrupts are signaled to the PC logic unit 270 over interrupt lines 292. As shown in FIG. 3, these lines are provided to the interrupt logic unit 363 in the PC logic unit 270, and comprise an NMI line, an IRQ line and a set of interrupt level lines (LVL).
  • the NMI line signals a non-maskable interrupt, and derives from an external source. It is the highest priority interrupt except for hardware reset.
  • the IRQ line also derives from an external source, and indicates when an external device is requesting a hardware interrupt.
  • the preferred embodiments permit up to 32 user-defined externally supplied hardware interrupts and the particular external device requesting the interrupt provides the number of the interrupt (0-31) on the interrupt level lines (LVL).
  • the memory error line is activated by the MCU 110 to signal various kinds of memory errors.
  • Other asynchronous interrupt lines are also provided to the interrupt logic unit 363, including lines for requesting a timer/counter interrupt, a memory I/O error interrupt, a machine check interrupt and a performance monitor interrupt.
  • Each of the asynchronous interrupts, as well as the synchronous exceptions described below, have a corresponding predetermined trap number associated with them, 32 of these trap numbers being associated with the 32 available hardware interrupt levels.
  • a table of these trap numbers is maintained in the interrupt logic unit 363. The higher the trap number, in general, the higher the priority of the trap.
  • interrupt control unit 363 When one of the asynchronous interrupts is signaled to the interrupt logic unit 363, the interrupt control unit 363 sends out an interrupt request to the IEU 104 over INT REQ/ACK lines 340. Interrupt control unit 363 also sends a suspend prefetch signal to PC control unit 362 over lines 343, causing the PC control unit 262 to stop prefetching instructions. The IEU 104 either cancels all then-executing instructions, and flushing all tentative results, or it may allow some or all instructions to complete. In the preferred embodiments, any then-executing instructions are canceled, thereby permitting the fastest response to asynchronous interrupts. In any event, the DPC in the execution PC control unit 366 is updated to correspond to the last instruction which has been completed and retired, before the IEU 104 acknowledges the interrupt. All other prefetched instructions in MBUF, EBUF, TBUF and IFIFO 264 are also cancelled.
  • the interrupt control unit 363 maintains a set of four internal exception bits (not shown) for each instruction set, one bit corresponding to each instruction in the set.
  • the interrupt control unit 363 also maintains an indication of the particular trap numbers, if any detected for each instruction.
  • VMU If the VMU signals a TLB miss or another VMU exception while a particular instruction set is being prefetched, this information is transmitted to the PC logic unit 270, and in particular to the interrupt control unit 363, over the VMU control lines 332 and 334.
  • the interrupt control unit 363 When the interrupt control unit 363 receives such a signal, it signals the PC control unit 362 over line 343 to suspend further prefetches. At the same time, the interrupt control Unit 363 sets the VM -- Miss or VM -- Excp bit, as appropriate, associated the prefetch buffer to which the instruction set was destined.
  • the interrupt control unit 363 sets all four internal exception indicator bits corresponding to that instruction set, since none of the instructions in the set are valid, and stores the trap number for the particular exception received in correspondence with each of the four instructions in the faulty instruction set.
  • the shifting and executing of instructions prior to the faulty instruction set then continues as usual until the faulty set reaches the lowest level in the IFIFO 264.
  • this information is also transmitted to the interrupt control unit 363 which sets the internal exception indicator bit corresponding to the instruction generating the exception and stores the trap number in correspondence with that exception.
  • the shifting and executing of instructions prior to the faulty instruction then continues as usual until the faulty set reaches the lowest level in the IFIFO 264.
  • the only type of exception which is detected during the shifting of an instruction through the prefetch buffers 260, the IDecode unit 262 or the IFIFO 264 is a software trap instruction.
  • Software trap instructions are detected at the IDecode stage by CF -- DET unit 274. While in some embodiments other forms of synchronous exceptions may be detected in the IDecode unit 262, it is preferred that the detection of any other synchronous exceptions wait until the instruction reaches the execution unit 104. This avoids the possibility that certain exceptions, such as arising from the handling of privileged instruction, might be signaled on the basis of a processor state which could change before the effective in-order-execution of the instruction.
  • software trap instructions are detected at the IDecode stage by the CF -- DET unit 274.
  • the internal exception indicator bit corresponding to that instruction in the interrupt logic unit 363 is set and the software trap number, which can be any number from 0 to 127 and which is specified in an immediate mode operand field of the software trap instruction, is stored in correspondence with the trap instruction.
  • the interrupt control unit 363 does not signal PC control unit 362 to suspend prefetches when a software trap instruction is detected. Rather, at the same time the instruction is shifting through the IFIFO 264, the IFU 102 prefetches the trap handler into the MBUF instruction stream buffer.
  • the interrupt logic unit 363 transmits the exception indicator bits for that instruction set as a 4-bit vector to the IEU 104 over the SYNCH -- INT -- INFO lines 341 to indicate which, if any, of the instructions in the instruction set have already been determined to be the source of a synchronous exception.
  • the IEU 104 does not respond immediately, but rather permits all the instructions in the instruction set to be scheduled in the normal course. Further exceptions, such as integer arithmetic exceptions, may be generated during execution.
  • the IEU 104 retires all instructions which have been tentatively executed and which occur in the instruction stream prior to the first instruction which has a synchronous exception, and flushes the tentative results from any tentatively executed instructions which occur subsequently in the instruction stream. The particular instruction that caused the exception is also flushed since that instruction will typically be re-executed upon return from trap.
  • the IF -- PC in the execution PC control unit 366 is then updated to correspond to the last instruction actually retired, and the before any exception is signaled to the interrupt control unit 363.
  • the IEU 104 When the instruction that is the source of an exception is retired, the IEU 104 returns to the interrupt logic unit 363, over the SYNCH -- INT -- INFO lines 341, both a new 4-bit vector indicating which, if any, instructions in the retiring instruction set (register 224) had a synchronous exception, as well as information indicating the source of the first exception in the instruction set.
  • the information in the 4-bit exception vector returned by IEU 104 is an accumulation of the 4-bit exception vectors provided to the IEU 104 by the interrupt logic unit 363, as well as exceptions generated in the IEU 104.
  • interrupt control unit 363 determines the nature of the highest priority synchronous exception and its trap number.
  • the current DPC is temporarily stored as a return address in an xPC register, which is one of the special registers 412 (FIG. 4).
  • the current processor status register (PSR) is also stored in a previous PSR (PPSR) register, and the current compare state register (CSR) is saved in a prior compare state register (PCSR) in the special registers 412.
  • the address of a trap handler is calculated as a trap base register address plus an offset.
  • the PC logic unit 270 maintains two base registers for traps, both of which are part of the special registers 412 (FIG. 4), and both of which are initialized by special move instructions executed previously. For most traps, the base register used to calculate the address of the handler is a trap base register TBR.
  • the interrupt control unit 363 determines the highest priority interrupt or exception currently pending and, through a look-up table, determines the trap number associated therewith. This is provided over a set of INT -- OFFSET lines 373 to the prefetch PC control unit 364 as an offset to the selected base register.
  • the vector address is calculated by merely concatenating the offset bits as low-order bits to the higher order bits obtained from the TBR register. This avoids any need for the delays of an adder.
  • the handler address may be calculated by concatenating the 8 bit trap number to the end of a 22-bit TBR stored value. Two low-order zero bits may be appended to the trap number to ensure that the trap handler address always occurs on a word boundary.
  • the concatenated handler address thus constructed is provided as one of the inputs, 373; to the prefetch selector PF -- PC Sel 390 (FIG. 4), and is selected as the next address from which instructions are to be prefetched.
  • the vector handler address for traps using the TBR register are all only one word apart. Thus, the instruction at the trap handler address must be a preliminary branch instruction to a longer trap handling routine. Certain traps require very careful handling, however, to prevent degradation of system performance. TLB traps, for example, must be executed very quickly. For this reason, the preferred embodiments include a fast trap mechanism designed to allow the calling of small trap handlers without the cost of this preliminary branch. In addition, fast trap handlers can be located independently in memory, in on-clip ROM, for example, to eliminate memory system penalties associated with RAM locations.
  • the only traps which result in fast traps are the VMU exceptions mentioned above.
  • Fast traps are numbered separately from other traps, and have a range from 0 to 7. However, they have the same priority as MMU exceptions.
  • the interrupt control unit 363 recognizes a fast trap as the highest priority trap then pending, it causes a fast trap base register (FTB) to be selected from the special registers 412 and provided on the lines 416 to be combined with the trap offset.
  • FTB fast trap base register
  • the resulting vector address provided to the prefetch selector PF -- PC Sel 390, via lines 373', is then a concatenation of the high-order 22 bits from the FTB register, followed by three bits representing the fast trap number, followed by seven bits of 0's.
  • each fast trap address is 128 bytes, or 32 words apart.
  • the processor branches to the starting word and may execute programs within the block or branch out of it. Execution of small programs, such as standard TLB handling routines which may be implemented in 32 instructions or less, is faster than ordinary traps because the preliminary branch to the actual exception handling routine is obviated.
  • the fast trap mechanism is also useful in microprocessors whose instructions are variable in length.
  • the fast trap vector addresses be separated by enough space to accommodate at least two of the shortest instructions available on the microprocessor, and preferably about 32 average-sized instructions.
  • the vector addresses should be separated by at least enough space to permit that instruction to be preceded by at least one other instruction in the handler.
  • the processor On dispatch to a trap handler, the processor enters both a kernel mode and an interrupted state. Concurrently, a copy of the compare state register (CSR) is placed in the prior carry state register (PCSR) and a copy of the PSR is stored in the prior PSR (PPSR) register.
  • the kernel and interrupted states modes are represented by bits in the processor status register (PSR). Whenever the interrupted -- state bit in the current PSR is set, the shadow registers or trap registers RT[24] through RT[31], as described above and as shown in FIG. 7B, become visible.
  • the interrupt handler may switch out of kernel mode merely by writing a new mode into the PSR, but the only way to leave the interrupted state is by executing a return from trap (RTT) instruction.
  • RTT return from trap
  • PCSR is restored to CSR register and PPSR register is restored to the PSR register, thereby automatically clearing the interrupt -- state bit in the PSR register.
  • the PF -- PC SEL selector 390 also selects special register xPC in the special register set 412 as the next address from which to prefetch. xPC is restored to either the MBUF PFnPC or the EBUF PFnPC as appropriate, via incrementor 394 and bus 396. The decision as to whether to restore xPC into the EBUF or MBUF PFnPC is made according to the "procedure -- in -- progress" bit of the PSR, once restored.
  • the processor does not use the same special register xPC to store the return address for both traps and procedural instructions.
  • the return address for a trap is stored in the special register xPC, as mentioned, but the address to return to after a procedural instruction is stored in a different special register, uPC.
  • uPC a different special register
  • the interrupted state remains available even while the processor is executing an emulation stream invoked by a procedural instruction.
  • exception handling routines should not include any procedural instructions since there is no special register to store an address for return to the exception handler after the emulation stream is complete.
  • processor status information is automatically backed up on dispatch to a trap handler, in particular CSR, PSR, the return PC, and in a sense the "A" register set ra [24] through ra[31], other context information is not protected.
  • a trap handler intends to alter these registers, it must perform its own backup.
  • a trap handler should back up any desired registers, clear any interrupt condition, read any information necessary for handling the trap from the system registers and process it as appropriate. Interrupts are automatically disabled upon dispatch to the trap handler. After processing, the handler can then restore the backed up registers, re-enable interrupts and execute the RTT instruction to return from the interrupt.
  • the trap handler should be divided into first and second portions.
  • the xPC should be copied, using a special register move instruction, and pushed onto the stack maintained by the trap handler.
  • the address of the beginning of the second portion of the trap handler should then be moved using the special register move instruction into the xPC, and a return from trap instruction (RTT) executed.
  • the RTT removes the interrupted state (via the restoration of PPSR into PSR) and transfers control to the address in the xPC, which now contains the address of the second portion of the handler.
  • the second portion may enable interrupts at this point and continue to process the exception in an interruptable mode.
  • the handler should preserve any of the "A" register values where these register values are likely to be altered by the handler.
  • the trap handling procedure When the trap handling procedure is finished, it should restore all backed up registers, pop the original xPC off the trap handler stack and move it back into the xPC special register using a special register move instruction, and execute another RTT. This returns control to the appropriate instruction in the main or emulation instruction stream.
  • the combined control and data path portions of IEU 104 are shown in FIG. 5.
  • the primary data path begins with the instruction/operand data bus 124 from the IFU 102.
  • immediate operands are provided to an operand alignment unit 470 and passed on to a register file (REG ARRAY) 472.
  • Register data is provided from the register file 472 through a bypass unit 474, via a register file output bus 476, to a parallel array of functional computing elements (FU 0-n ) 478 0-n , via a distribution bus 480.
  • Data generated by the functional units 478 0-n is provided back to the bypass unit 474 or the register array 472, or both, via an output bus 482.
  • a load/store unit 484 completes the data path portion of the IEU 104.
  • the load/store unit 484 is responsible for managing the transfer of data between the IEU 104 and CCU 106. Specifically, load data obtained from the data cache 134 of the CCU 106 is transferred by the load/store unit 484 to an input of the register array 472 via a load data bus 486. Data to be stored to the data cache 134 of the CCU 106 is received from the functional unit distribution bus 480.
  • the control path portion of the IEU 104 is responsible for issuing, managing, and completing the processing of information through the IEU data path.
  • the IEU control path is capable of managing the concurrent execution of multiple instructions and the IEU data path provides for multiple independent data transfers between essentially all data path elements of the IEU 104.
  • the IEU control path operates in response to instructions received via the instruction/operand bus 124. Specifically, instruction sets are received by the EDecode unit 490.
  • the EDecode 490 receives and decodes both instruction sets held by the IFIFO master registers 216, 224.
  • the carry checker unit 492 receives decoded information about the eight pending instructions from the EDecode unit 490 via control lines 502.
  • the function of the carry checker 492 is to identify those ones of the pending instructions that either affect the carry bit of the processor status word or are dependent on the state of the carry bit. This control information is provided via control lines 504 to the instruction issuer unit 498.
  • the function of the dependency checker unit 494 is to determine which of the pending instructions reference registers as the destination for data and which instructions, if any, are dependant on any of those destination registers. Those instructions that have register dependencies are identified by control signals provided via the control lines 508 to the register rename unit 496.
  • the EDecode unit 490 provides control information identifying the particular nature and function of each of the eight pending instructions to the instruction issuer unit 498 via control lines 510.
  • the issuer unit 498 is responsible for determining the data path resources, particularly of the availability of particular functional units, for the execution of pending instructions.
  • instruction issuer unit 498 allows for the out-of-order execution of any of the eight pending instructions subject to the availability of data path resources and carry and register dependency constraints.
  • the register rename unit 496 provides the instruction issuing unit 498 with a bit map, via control lines 512 of those instructions that are suitably unconstrained to allow execution. Instructions that have already been executed (done) and those with register or carry dependencies are logically removed from the bit map.
  • the instruction issuer unit 498 may initiate the execution of multiple instructions during each system clock cycle.
  • the status of the functional units 478 0-n are provided via a status bus 514 to the instruction issuer unit 498.
  • Control signals for initiating, and subsequently managing the execution of instructions are provided by the instruction issuer unit 498 on the control lines 516 to the register rename unit 496 and selectively to the functional units 478 0-n .
  • the register rename unit 496 provides register selection signals on a register file access control bus 518. The specific registers enabled via the control signals provided on the bus 518 are determined by the selection of the instruction being executed and by the determination by the register rename unit 496 of the registers referenced by that particular instruction.
  • a bypass control unit (BYPASS CTL) 520 generally controls the operation of the bypass data routing unit 474 via control signals on control lines 524.
  • the bypass control unit 520 monitors the status of each of the functional units 478 0-n and, in conjunction with the register references provided from the register rename unit 496 via control liner 522, determines whether data is to be routed from the register file 472 to the functional units 478 0-n or whether data being produced by the functional units 478 0-n can be immediately routed via the bypass unit 474 to the functional unit distribution bus 480 for use in the execution of a newly issued instruction selected by the instruction issuer unit 498. In either case, the instruction issuer unit 498 directly controls the routing of data from the distribution bus 480 to the functional units 478 0-n by selectively enabling specific register data to each of the functional units 478 0-n .
  • the remaining units of the IEU control path include a retirement control unit 500, a control flow control (CF CT1) unit 528, and a done control (DONE CTL) unit 540.
  • the retirement control unit 500 operates to void or confirm the execution of out-of-order executed instructions. Where an instruction has been executed out-of-order, that instruction can be confirmed or retired once all prior instructions have also been retired. Based on an identification of which of the current set of eight pending instructions have been executed provided on the control lines 532, the retirement control unit 500 provides control signals on control lines 534 coupled to the bus 518 to effectively confirm the result data stored by the register array 472 as the result of the prior execution of an out-of-order executed instruction.
  • the retirement control unit 500 provides the PC increment/size control signals on control lines 344 to the IFU 102 as it retires each instruction. Since multiple instructions may be executed out-of-order, and therefore ready for simultaneous retirement, the retirement control unit 500 determines a size value based on the number of instructions simultaneously retired. Finally, where all instructions of the IFIFO master register 224 have been executed and retired, the retirement control unit 500 provides the IFIFO read control signal one the control line 342 to the IFU 102 to initiate an IFIFO unit 264 shift operation, thereby providing the EDecode unit 490 with an additional four instructions as instructions pending execution.
  • the control flow control unit 528 performs the somewhat more specific function of detecting the logical branch result of each conditional branch instruction.
  • the control flow control unit 528 receives an 8 bit vector identification of the currently pending conditional branch instructions from the EDecode unit 490 via the control lines 510.
  • An 8 bit vector instruction done control signal is similarly received via the control lines 532 or 542 from the done control unit 540. This done control signal allows the control flow control unit 528 to identify when a conditional branch instruction is done at least to a point sufficient to determine a conditional control flow status.
  • the control flow status result for the pending conditional branch instructions are stored by the control flow control unit 528 as they are executed.
  • the data necessary to determine the conditional control flow instruction outcome is obtained from temporary status registers in the register array 472 via the control lines 530.
  • the control flow control unit provides a new control flow result signal on the control lines 348 to the IFU 102.
  • This control flow result signal preferably includes two 8 bit vectors defining whether the status results, by respective bit position, of the eight potentially pending control flow instruction are known and the corresponding status result states, also given by bit position correspondence.
  • the done control unit 540 is provided to monitor the operational execution state of each of the functional units 478 0-n . As any of the functional units 478 0-n signal completion of an instruction execution operation, the done control unit 540 provides a corresponding done control signal on the control lines 542 to alert the register rename unit 496, instruction issuer unit 498, retirement control unit 500 and bypass control unit 520.
  • the parallel array arrangement of the functional units 478 0-n enhances the control consistency of the IEU 104.
  • the particular nature of the individual functional units 478 0-n must be known by the instruction issuer unit 498 in order for instructions to be properly recognized and scheduled for execution.
  • the functional units 478 0-n are responsible for determining and implementing their specific control flow operation necessary to perform their requisite function.
  • the instruction issuer unit 498 and the functional units 478 0-n provide the necessary control signal prompting of the functions to be performed by the remaining control flow managing units 496, 500, 520, 528, 540.
  • alteration in the particular control flow operation of a functional unit 478 0-n does not impact the control operation of the IEU 104.
  • the functional augmentation of an existing functional unit 478 0-n and even the addition of one or more new functional units 478 0-n require only minor modification of the instruction issuer unit 498.
  • the required modifications must provide for recognition of the particular instruction, based on the corresponding instruction field isolated by the EDecode unit 490, a correlation of the instruction to the required functional unit 478 0-n . Control over the selection of register date, routing of data, instruction completion and retirement remain consistent with the handling of all other instructions executed with respect to all other ones of the functional units 478 0-n .
  • the central element of the IEU data path is the register file 472.
  • the present invention provides for a number of parallel data paths optimized generally for specific functions.
  • the two principal data paths are integer and floating point.
  • a portion of the register file 472 is provided to support the data manipulations occurring within that data path.
  • the data path register file 550 includes a temporary buffer 552, a register file array 564, an input selector 559, and an output selector 556.
  • Data ultimately destined for the register array 564 is typically first received by the temporary buffer 552 through a combined data input bus 558'. That is, all data directed to the data path register file 550 is multiplexed by the input selector 559 from a number of input buses 558, preferably two, onto the input bus 558'.
  • Register select and enable control signals provided on the control bus 518 select the register location for the received data within the temporary buffer 552.
  • control signals again provided on the control bus 518 enable the transfer of the data from the temporary buffer 552 to a logically corresponding register within the register file array 564 via the data bus 560.
  • data stored in the registers of the temporary buffer 552 may be utilized in the execution of subsequent instructions by routing the temporary buffer stored data to the output data selector 556 via a bypass portion of the data bus 560.
  • the selector 556 controlled by a control signal provided via the control bus 518 selects between data provided from the registers of the temporary buffer 552 and of the register file array 564. The resulting data is provided on the register file output bus 563.
  • the input selector 559 can be directed to route the result data directly to the register array 554 via bypass extension 558".
  • each data path register file 550 permits two simultaneous register operations to occur.
  • the input bus 558 provides for two full register width data values to be written to the temporary buffer 552.
  • the temporary buffer 552 provides a multiplexer array permitting the simultaneous routing of the input data to any two registers within the temporary buffer 552.
  • internal multiplexers allow any five registers of the temporary buffer 552 to be selected to output data Onto the bus 560.
  • the register file array 564 likewise includes input and output multiplexers allowing two registers to be selected to receive, on bus 560, or five to source, via bus 562, respective data simultaneously.
  • the register file output selector 556 is preferably implemented to allow any five of the ten register data values received via the buses 560, 562 to be simultaneously output on the register file output bus 563.
  • the register set within the temporary buffer is generally shown in FIG. 6B.
  • the register set 552' consists of eight single word (32 bit) registers IORD, I1RD . . . I7RD.
  • the register set 552' may also be used as a set of four double word registers IORD, IORD+1 (IORD4), I1RD, I1RD+1 (ISRD) . . . I3RD, I3RD+1 (I7RD).
  • the registers in the temporary buffer register set 552 are referenced by the register rename unit 496 based on the relative location of the respective instructions within the two IFIFO master registers 216, 224.
  • Each instruction implemented by the architecture 100 may reference for output up to two registers, or one double word register, for the destination of data produced by the execution of the instruction.
  • an instruction will reference only a single output register.
  • the data destination register I2RD will be selected to receive data produced by the execution of the instruction.
  • instruction I 5 the data stored in the I2RD register will be transferred out via the bus 560 and the resultant data stored back to the temporary buffer 552 into the register identified as I5RD.
  • instruction I 5 is dependent on instruction I 2 .
  • Instruction I 5 cannot be executed until the result data from I 2 is available.
  • instruction I 5 can execute prior to the retirement of instruction I 2 by obtaining its required input data from the instruction I 2 data location of the temporary buffer 552'.
  • instruction I 2 is retired, the data from the register I2RD is written to the register location within the register file array 564 as determined by the logical position of the instruction at the point of retirement. That is, the retirement control unit 500 determines the address of the destination registers in the register file array from the register reference field data provided from the EDecode unit 490 on the control lines 510.
  • the values in I4RD-I7RD are shifted into I0RD-I3RD simultaneous with a shift of the IFIFO unit 264.
  • instruction I 2 provides a double word result value.
  • a combination of locations I2RD and I6RD is used to store the data resulting from instruction I 2 until that instruction is retired or otherwise cancelled.
  • execution of instructions I 4-7 are held where a double word output reference by any of the instructions I 0-3 is detected by the register rename unit 496. This allows the entire temporary buffer 552' to be used as a single bank of double word registers. Once instructions I 0-3 have been retired, the temporary buffer 552' can again be used as two banks of single word registers. Further, the execution of any instruction I 4-7 is held where a double word output register is required until the instruction has been shifted into a corresponding I 0-3 location.
  • the register file array 564 for the integer data path consists of 40 32-bit wide registers. This set of registers, constituting a register set "A", is organized as a base register set ra[0 . . . 23] 565, a top set of general purpose registers ra[24 . . . 31] 566, and a shadow register set of eight general purpose trap registers rt[24 . . . 31].
  • the general purpose registers ra[0 . . . 31] 565, 566 constitutes the active "A" register set of the register file array for the integer data path.
  • the trap registers rt[24 . . . 31] 567 may be swapped into the active register set "A" to allow access along with the active base set of registers ra [0 . . . 23] 565.
  • This configuration of the "A" register set is selected upon the acknowledgement of an interrupt or the execution of an exception trap handling routine.
  • This state of the register set "A” is maintained until expressly returned to the state shown in FIG. 7A by the execution of an enable interrupts instruction or execution of a return from trap instruction.
  • the floating point data path utilizes an extended precision register file array 572 as generally shown in FIG. 8.
  • the register file array 572 consists of 32 registers, rf[0 . . . 31], each having a width of 64 bits.
  • the floating point register file 572 may also be logically referenced as a "B" set of integer registers rb[0 . . . 31]. In the architecture 100, this "B" set of registers is equivalent to the low-order 32 bits of each of the floating point registers rf [0 . . . 31].
  • a boolean operator register set 574 is provided, as shown in FIG. 9, to store the logical result of boolean combinatorial operations.
  • This "C" register set 574 consists of 32 single bit registers, rc [0 . . . 31].
  • the operation of the boolean register set 574 is unique in that the results of boolean operations can be directed To any instruction selected register of the boolean register set 574. This is in contrast to utilizing a single processor status word register that stores single bit flags for conditions such as equal, not equal, greater than and other simple boolean status values.
  • Both the floating point register set 572 and the boolean register set 574 are complimented by temporary buffers architecturally identical to the integer temporary buffer 552 shown in FIG. 6B.
  • the essential difference is that the width of the temporary buffer registers is defined to be identical to those of the complimenting register file array 572, 574; in the preferred implementation, 64 bits and one bit, respectively.
  • a number of additional special registers are at least logically present in the register array 472.
  • the registers that are physically present in the register array 472, as shown in FIG. 7C, include a kernel stack pointer 568, processor state register (PSR) 569, previous processor state register (PPSR) 570, and an array of eight temporary processor state registers (tPSR[0 . . . 7]) 571.
  • the remaining special registers are distributed throughout various parts of the architecture 100.
  • the special address and data bus 354 is provided to select and transfer data between the special registers and the "A" and "B" sets of registers.
  • a special register move instruction is provided to select a register from either the "A" or "B" register set, the direction of transfer and to specify the address identifier of a special register.
  • the kernel stack pointer register and temporary processor state registers differ from the other special registers.
  • the kernel stack pointer may be accessed through execution of a standard register to register move instruction when in kernel state.
  • the temporary processor state registers are not directly accessible. Rather, this array of registers is used to implement an inheritance mechanism for propagating the value of the processor state register for use by out-of-order executing instructions.
  • the initial propagation value is that of the processor state register: the value provided by the last retired instruction. This initial value is propagated forward through the temporary processor state registers so that any out-of-order executing instruction has access to the value in the positionally corresponding temporary processor state register.
  • the specific nature of an instruction defines the condition code bits, if any, that the instruction is dependent on and may change.
  • the instruction can be executed out-of-order. Any modification of the condition code bits of the processor state register are directed to the logically corresponding temporary processor state register. Specifically, only those bits that may change are applied to the value in the temporary processor state register and propagated to all higher order temporary processor state registers. Consequently, every out-of-order executed instruction executes from a processor state register value modified appropriately by any intervening PSR modifying instructions. Retirement of an instruction only transfers the corresponding temporary processor state registers value to the PSR register 569.
  • the integer data path of the IEU 104 constructed in accordance with the preferred embodiment of the present invention, is shown in FIG. 10. For purposes of clarity, the many control path connections to the integer data path 580 are not shown. Those connections are defined with respect to FIG. 5.
  • Input data for the data path 580 is obtained from the alignment units 582, 584 and the integer load/store unit 586.
  • Integer immediate data values, originally provided as an instruction embedded data field are obtained from the operand unit 470 via a bus 588.
  • the alignment unit 582 operates to isolate the integer data value and provide the resulting value onto the output bus 590 to a multiplexer 592.
  • a second input to the multiplexer 592 is the special register address and data bus 354.
  • Immediate operands obtained from the instruction stream are also obtained from the operand unit 470 via the data bus 594. These values are again right justified by the alignment unit 584 before provision onto an output bus 596.
  • the integer load/store unit 586 communicates bi-directionally via the external data bus 598 with the CCU 106. Inbound data to the IEU 104 is transferred by the integer load/store unit 586 onto the input data bus 600 to an input latch 602. Data output from the multiplexer 592 and latch 602 are provided on the multiplexer input buses 604, 606 of a multiplexer 608. Data from the functional unit output bus 482' is also received by the multiplexer 608.
  • This multiplexer 608, in the preferred embodiments of the architecture 100 provides for two simultaneous data paths to the output multiplexer buses 610. Further, the transfer of data through the multiplexer 608 can be completed within each half cycle of the system clock. Since most instructions implemented by the architecture 100 utilize a single destination register, a maximum of four instructions can provide data to the temporary buffer 612 during each system clock cycle.
  • Data from the temporary buffer 612 can be transferred to an integer register file array 614, via temporary register output buses 616 or to a output multiplexer 620 via alternate temporary buffer register buses 618.
  • Integer register array output buses 622 permit the transfer of integer register data to the multiplexer 620.
  • the output buses connected to the temporary buffer 612 and integer register file array 614 each permit five register values to be output simultaneously. That is, two instructions referencing a total of up to five source registers can be issued simultaneously.
  • the temporary buffer 612, register file array 614 and multiplexer 620 allow outbound register data transfers to occur every half system clock cycle. Thus, up to four integer and floating point instructions may be issued during each clock cycle.
  • the multiplexer 620 operates to select/outbound register data values from the register file array 614 or directly from the temporary buffer 612. This allows out-of-order executed instructions with dependencies on prior out-of-order executed instructions to be executed by the IEU 104. This facilitates the twin goals of maximizing the execution through-put capability of the IEU integer data path by the out-of-order execution of pending instructions while precisely segregating out-of-order data results from data results produced by instructions that have been executed and retired. Whenever an interrupt or other exception condition occurs that requires the precise state of the machine to be restored, the present invention allows the data values present in the temporary buffer 612 to be simply cleared. The register file array 614 is therefore left to contain precisely those data values produced only by the execution of instructions completed and retired prior to the occurrence of the interrupt or other exception condition.
  • the up to five register data values selected during each half system clock cycle operation of the multiplexer 629 are provided via the multiplexer output buses 624 to an integer bypass unit 626.
  • This bypass unit 626 is, in essence, a parallel array of multiplexers that provide for the routing of data presented at any of its inputs to any of its outputs.
  • the bypass unit 626 inputs include the special register addressed data value or immediate integer value via the output bus 604 from the multiplexer 592, the up to five register data values provided on the buses 624, the load operand data from the integer load/store unit 586 via the double integer bus 600, the immediate operand value obtained from the alignment unit 584 via its output bus 596, and, finally, a bypass data path from the functional unit output bus 482'.
  • This bypass data path, and the data bus 482' provides for the simultaneous transfer of four register values per system clock cycle.
  • Data is output by the bypass unit 626 onto an integer bypass bus 628 that is connected to the floating point data path, to two operand data buses providing for the transfer out of up to five register data values simultaneously, and a store data bus 632 that is used to provide data to the integer load/store unit 586.
  • the functional unit distribution bus 480 is implemented through the operation of a router unit 634.
  • the router unit 634 is implemented by a parallel array of multiplexers that permit five register values received at its inputs to be routed to the functional units provided in the integer data path.
  • the router unit 634 receives the five register data values provided via the buses 630 from the bypass unit 626, the current IF -- PC address value via the address bus 352 and the control flow offset value determined by the PC control unit 362 and as provided on the lines 378'.
  • the router unit 634 may optionally receive, via the data bus 636 an operand data value sourced from a bypass unit provided within the floating point data path.
  • the register data values received by the router unit 634 may be transferred onto the special register address and data bus 354 and to the functional units 640, 642, 644.
  • the router unit 634 is capable of providing up to three register operand values to each of the functional units 640, 642, 644 via router output buses 646, 648, 650. Consistent with the general architecture of the architecture 100, up to two instructions could be simultaneously issued to the functional units 640, 642, 644.
  • the preferred embodiment of the present invention provides for three dedicated integer functional units, implementing respectively a programmable shift function and two arithmetic logic unit functions.
  • An ALU0 functional unit 644, ALU1 functional unit 642 and shifter functional unit 640 provide respective output register data onto the functional unit bus 482'.
  • the output data produced by the ALU0 and shifter functional unit 644, 640 are also provided onto a shared integer functional unit bus 650 that is coupled into the floating point data path.
  • a similar floating point functional unit output value data bus 652 is provided from the floating point data path to the functional unit output bus 482'.
  • the ALU0 functional unit 644 is used also in the generation of virtual address values in support of both the prefetch operations of the IFU 102 and data operations of the integer load/store unit 586.
  • the virtual address value calculated by the ALU0 functional unit 644 is provided onto an output bus 654 that connects to both the target address bus 346 of the IFU 102 and to the CCU 106 to provide the execution unit physical address (EX PADDR).
  • a latch 656 is provided to store the virtualizing portion of the address produced by the ALU0 functional unit 644. This virtualizing portion of the address is provided onto an output bus 658 to the VMU 108.
  • Initial data is again received from a number of sources including the immediate integer operand bus 588, immediate operand bus 594 and the special register address data bus 354.
  • the final source of external data is a floating point load/store unit 662 that is coupled to the CCU 106 via the external data bus 598.
  • the immediate integer operand is received by an alignment unit 664 that functions to right justify the integer data field before submission to a multiplexer 666 via an alignment output data bus 668.
  • the multiplexer 666 also receives the special register address data bus 354. Immediate operands are provided to a second alignment unit 670 for right justification before being provided on an output bus 672.
  • Inbound data from the floating point load/store unit 662 is received by a latch 674 from a load data bus 676.
  • Data from the multiplexer 666, latch 674 and a functional unit data return bus 482" is received on the inputs of a multiplexer 678.
  • the multiplexer 678 provides for selectable data paths sufficient to allow two register data values to be written to a temporary buffer 680, via the multiplexer output buses 682, each half cycle of the system clock.
  • the temporary buffer 680 incorporates a register set logically identical to the temporary buffer 552' as shown in FIG. 6B.
  • the temporary buffer 680 further provides for up to five register data values to be read from the temporary buffer 680 to a floating point register file array 684, via data buses 686, and to an output multiplexer 688 via output data buses 690.
  • the multiplexer 688 also receives, via data buses 692, up to five register data values from the floating point register file array 684 simultaneously.
  • the multiplexer 688 functions to select up to five register data values for simultaneous transfer to a bypass unit 694 via data buses 696.
  • the bypass unit 694 also receives the immediate operand value provided by the alignment unit 670 via the data bus 672, the output data bus 698 from the multiplexer 666, the load data bus 676 and a data bypass extension of the functional unit data return bus 482".
  • the bypass unit 694 operates to select up to five simultaneous register operand data values for output onto the bypass unit output buses 700, a store data bus 702 connected to the floating point load/store unit 662, and the floating point bypass bus 636 that connects to the router unit 634 of the integer data path 580.
  • a floating point router unit 704 provides for simultaneous selectable data paths between the bypass unit output buses 700 and the integer data path bypass bus 628 and functional unit input buses 706, 708, 710 coupled to the respective functional units 712, 714, 716.
  • Each of the input buses 706, 708, 710 in accordance with the preferred embodiment of the architecture 100, permits the simultaneous transfer of up to three register operand data values to each of the functional unit 712, 714, 716.
  • the output buses of these functional units 712, 714, 716 are coupled to the functional unit data return bus 482" for returning data to the register file input multiplexer 678.
  • the integer data path functional unit output bus 650 may also be provided to connect to the functional unit data return bus 482".
  • the architecture 100 does provide for a connection of the functional unit output buses of a multiplier functional unit 712 and a floating point ALU 714 to be coupled via the floating point data path functional unit bus 652 to the functional unit data return bus 482' of the integer data path 580.
  • the boolean operations data path 720 is shown in FIG. 12. This data path 720 is utilized in support of the execution of essentially two types of instructions.
  • the first type is an operand comparison instruction where two operands, selected from the integer register sets, floating point register sets or provided as immediate operands, are compared by subtraction in one of the ALU functional units of the integer and floating point data paths. Comparison is performed by a subtraction operation by any of the ALU functional units 642, 644, 714, 716 with the resulting sign and zero status bits being provided to a combined input selector and comparison operator unit 722.
  • This unit 72 in response to instruction identifying control signals received from the EDecode unit 490, selects the output of an ALU functional unit 642, 644, 714, 716 and combines the sign and zero bits to extract a boolean comparison result value.
  • An output bus 723 allows the results of the comparison operation to be transferred simultaneously to an input multiplexer 726 and a bypass unit 742.
  • the bypass unit 742 is implemented as a parallel array of multiplexers providing multiple selectable data paths between the inputs of the bypass unit 742 to multiple outputs.
  • the other inputs of the bypass unit 742 include a boolean operation result return data bus 724 and two boolean operands on data buses 744.
  • the bypass unit 742 permits boolean operands representing up to two simultaneously executing boolean instructions to be transferred to a boolean operation functional unit 746, via operand buses 748.
  • the bypass unit 742 also permits transfer of up to two single bit boolean operand bits (CF0, CF1) to be simultaneously provided on the control flow result control lines 750, 752.
  • the remainder of the boolean operation data path 720 includes the input multiplexer 726 that receives as its inputs, the comparison and the boolean operation result values provided on the comparison result bus 723 and a boolean result bus 724.
  • the bus 724 permits up to two simultaneous boolean result bits to be transferred to the multiplexer 726.
  • up to two comparison result bits may be transferred via the bus 723 to the multiplexer 726.
  • the multiplexer 726 permits any two single bits presented at the multiplexer inputs to be transferred via the multiplexer output buses 730 to a boolean operation temporary buffer 728 during each half cycle of the system clock.
  • the temporary buffer 728 is logically equivalent to the temporary buffer 552', as shown in FIG.
  • each register entry in the temporary buffer 728 consists of a single bit.
  • the second distinction is that only a single register is provided for each of the eight pending instruction slots, since the result of a boolean operation is, by definition, fully defined by a single result bit.
  • the temporary buffer 728 provides up to four output operand values simultaneously. This allows the simultaneous execution of two boolean instructions, each requiring access to two source registers.
  • the four boolean register values may be transferred during each half cycle of the system clock onto the operand buses 736 to a multiplexer 738 or to a boolean register file array 732 via the boolean operand data buses 734.
  • the boolean register file array 732 is a single 32 bit wide data register that permits any separate combination of up to four single bit locations to be modified with data from the temporary buffer 728 and read from the boolean register file array 732 onto the output buses 740 during each half cycle of the system clock.
  • the multiplexer 738 provides for any two pairs of boolean operands received at its inputs via the buses 736, 740 to be transferred onto the operand output buses 744 to the bypass unit 742.
  • the boolean operation functional unit 746 is capable of performing a wide range of boolean operations on two source values.
  • the source values are a pair of operands obtained from any of the integer and floating point register sets and any immediate operand provided to the IEU 104, and, for a boolean instruction, any two of boolean register operands.
  • Tables III and IV identify the logical comparison operations provided by the preferred embodiment of the architecture 100.
  • Table V identifies the direct boolean operations provided by the preferred implementation of the architecture 100.
  • the instruction condition codes and function codes specified in the Tables III-V represent a segment of the corresponding instructions.
  • the instruction also provides an identification of the source pair of operand registers and the destination boolean register for storage of the corresponding boolean operation result.
  • FIG. 13 An exemplary load/store unit 760 is shown in FIG. 13. Although separately shown in the data paths 580, 660, the load/store units 586 662 are preferably implemented as a single shared load/store unit 760.
  • the interface from a respective data path 580, 660 is via an address bus 762 and load and store data buses 764 (600, 676), 766 (632, 702).
  • the address utilized by the load/store unit 760 is a physical address as opposed to the virtual address utilized by the IFU 102 and the remainder of the IEU 104. While the IFU 102 operates on virtual addresses, relying on coordination between the CCU 106 and VMU 108 to produce a physical address, the IEU 104 requires the load/store unit 760 to operate directly in a physical address mode. This requirement is necessary to insure data integrity in the presence of out-of-order executed instructions that may involve overlapping physical address data load and store operations and in the presence of out-of-order data returns from the CCU 106 to the load/store unit 760. In order to insure data integrity, the load/store unit 760 buffers data provided by store instructions until the store instruction is retired by the IEU 104.
  • store data buffered by the load store unit 760 may be uniquely present only in the load/store unit 760.
  • Load instructions referencing the same physical address as executed but not retired store instructions are delayed until the store instruction is actually retired. At that point the store data may be transferred to the CCU 106 by the load/store unit 760 and then immediately loaded back by the execution of a CCU data load operation.
  • full physical addresses are provided from the VMU 108 onto the load/store address bus 762.
  • Load addresses are, in general, stored in load address registers 768 0-3 .
  • Store addresses are latched into store address registers 770 3-0 .
  • a load/store control unit 774 operates in response to control signals received from the instruction issuer unit 498 in order to coordinate latching of load and store addresses into the registers 768 3-0 , 770 3-0 .
  • the load/store control unit 774 provides control signals on control lines 778 for latching load addresses and on control lines 780 for latching store addresses.
  • Store data is latched simultaneous with the latching of store addresses in logically corresponding slots of the store data register set 782 3-0 .
  • a 4 ⁇ 4 ⁇ 32 bit wide address comparator unit 772 is simultaneously provided with each of the addresses in the load and store address registers 768 3-0 , 770 3-0 .
  • the execution of a full matrix address comparison during each half cycle of the system clock is controlled by the load/store control unit 774 via control lines 776.
  • the existence and logical location of a load address that matches a store address is provided via-control signals returned to the load store control unit 774 via control lines 776.
  • the load address is bypassed directly from the bus 762 to an address selector 786 concurrent with the initiation of a CCU load operation. However, where store data is pending, the load address will be latched in an available load address latch 768 0-3 .
  • the load/store control unit 774 Upon receipt of a control signal from the retirement control unit 500, indicating that the corresponding store data instruction is retiring, the load/store control unit 774 initiates a CCU data transfer operation by arbitrating, via control lines 784 for access to the CCU 106.
  • the load/store control unit 774 directs the selector 786 to provide a CCU physical address onto the CCU PADDR address bus 788. This address is obtained from the corresponding store register 770 3-0 via the address bus 790. Data from the corresponding store data register 782 3-0 is provided onto the CCU data bus 792.
  • the load store control unit 774 Upon issuance of load instruction by the instruction issuer 498, the load store control unit 774 enables one of the load address latches 768 3-0 to latch the requested load address.
  • the instruction issuer 498 provides the load/store control unit 774 with a five bit vector identifying the load instruction within either of the two possible pending instruction sets. Where the comparator 772 does not identify a matching store address, the load address is routed via an address bus 794 to the selector 786 for output onto the CCU PADDR address bus 788. Provision of the address is performed in concert with CCU request and ready control signals being exchanged between the load/store control unit 774 and CCU 106.
  • An execution ID value (ExID) is also prepared and issued by the load/store control unit 774 to the CCU 106 in order to identify the load request when the CCU 106 subsequently returns the requested data including ExID value.
  • This ID value consists of a four bit vector utilizing unique bits to identify the respective load address latch 768 0-3 from which the current load request is generated. A fifth bit is utilized to identify the instruction set that contains the load instruction. The ID value is thus the same as the bit vector provided with the load request from the instruction issuer unit 498.
  • the load/store control unit 774 On subsequent signal from the CCU 106 to the load/store control unit 774 of the availability of prior requested load data, the load/store control unit 774 enables an alignment unit to receive the data and provide it on the load data bus 764.
  • An alignment unit 798 operates to right justify the load data.
  • the load/store control unit 774 receives the ExID value from the CCU 106.
  • the load/store control unit 774 provides a control signal to the instruction issuer unit 498 identifying that load data is being provided on the load data bus 764 and, further, returns a bit vector identifying the load instruction for which the load data is being returned.
  • FIG. 14 The timing of the execution of instructions represented in FIG. 14 is exemplary of the operation of the present invention, and not exhaustive of execution timing permutations.
  • the timing diagram of FIG. 14 shows a sequence of processor system clock cycles, P 0-6 . Each processor cycle begins with an internal T Cycle, T 0 . There are two T cycles per processor cycle in a preferred embodiment of the present invention as provided for by the architecture 100.
  • the IFU 102 and the VMU 108 operate to generate a physical address.
  • the physical address is provided to the CCU 106 and an instruction cache access operation is initiated. Where the requested instruction set is present .in the instruction cache 132, an instruction set is returned to the IFU 102 at about the mid-point of processor cycle one.
  • the IFU 102 then manages the transfer of the instruction set through the prefetch unit 260 and IFIFO 264, whereupon the instruction set is first presented to the IEU 104 for execution.
  • the EDecode unit 490 receives the full instruction/set in parallel for decoding prior to the conclusion of processor cycle one.
  • the EDecode unit 490 in the preferred architecture 100, is implemented as a pure combinatorial logic block that provides for the direct parallel decoding of all valid instructions that are received via the bus 124.
  • Each type of instruction recognized by the architecture 100 including the specification of the instruction, register requirements and resource needs are identified in Table VI.
  • the EDecode unit 490 decodes each instruction of an instruction set in parallel. The resulting identification of instructions, instruction functions, register references and function requirements are made available on the outputs of the EDecode unit 490. This information is regenerated and latched by the EDecode unit 490 during each half processor cycle until all instructions in the instruction set are retired. Thus, information regarding all eight pending instructions is constantly maintained at the output of the EDecode unit 490. This information is presented in the form of eight element bit vectors where the bits or sub-fields of each vector logically correspond to the physical location of the corresponding instruction within the two pending instruction sets.
  • восем ⁇ vectors are provided via the control lines 502 to the carry checker 492, where each vector specifies whether the corresponding instruction affects or is dependant on the carry bit of the processor status word.
  • Eight vectors are provided via the control lines 510 to identify the specific nature of each instruction and the function unit requirements.
  • Eight vectors are provided via the control lines 506 specifying the register references used by each of the eight pending instructions. These vectors are provided prior to the end of processor cycle one.
  • the carry checker unit 492 operates in parallel with the dependency check unit 494 during the data dependency phase of operation shown in FIG. 14.
  • the carry check unit 492 is implemented in the preferred architecture 100 as pure combinatorial logic. Thus, during each iteration of operation by the carry checker unit 492, all eight instructions are considered with respect to whether they modify the carry flag of the processor state register. This is necessary in order to allow the out-of-order execution of instructions that depend on the state of the carry bit as set by prior instructions. Control signals provided on the control lines 504 allow the carry check unit 492 to identify the specific instructions that are dependant on the execution of prior instructions with respect to the carry flag.
  • the carry checker unit 492 maintains a temporary copy of the carry bit for each of the eight pending instructions. For those instructions that do not modify the carry bit, the carry checker unit 492 propagates the carry bit to the next instruction forward in the order of the program instruction stream.
  • an out-of-order executed instruction that modifies the carry bit can be executed and, further, a subsequent instruction that is dependant on such an out-of-order executed instruction may also be allowed to execute, though subsequent to the instruction that modifies the carry bit.
  • maintenance of the carry bit by the carry checker unit 492 facilitates out-of-order execution in that any exception occurring prior to the retirement of those instructions merely requires the carry checker unit 492 to clear the internal temporary carry bit register.
  • the processor status register is unaffected by the execution of out-of-order executed instructions.
  • the temporary bit carry register maintained by the carry checker unit 492 is updated upon completion of each out-of-order executed instruction.
  • the carry bit corresponding to the last retired instruction in the program instruction stream is transferred to the carry bit location of the processor status register.
  • the data dependency checker unit 494 receives the eight register reference identification vectors from the EDecode unit 490 via the control lines 506.
  • Each register reference is indicated by a five bit value, suitable for identifying any one of 32 registers at a time, and a two bit value that identifies the register bank as located within the "A", "B" or boolean register sets.
  • the floating point register set is equivalently identified as the "B" register set.
  • Each instruction may have up to three register reference fields: two source register fields and one destination. Although some instructions, most notably the move register to register instructions, may specify a destination register, an instruction bit field recognized by the EDecode unit 490 may signify that no actual output data is to be produced. Rather, execution of the instruction is only for the purpose of determining an alteration of the value of the processor status register.
  • the data dependency checker 494 implemented again as pure combinatorial logic in the preferred architecture 100, operates to simultaneously determine dependencies between source register references of instructions subsequent in the program instruction stream and destination register references of relatively prior instructions.
  • a bit array is produced by the data dependency checker 494 that identifies not only which instructions are dependant on others, but also the registers upon which each dependency arises.
  • the carry and register data dependencies are identified shortly after the beginning of the second processor cycle.
  • the register rename unit 496 receives the identification of the register references of all eight pending instructions via the control lines 506, and register dependencies via the control lines 508. A matrix of eight elements is also received via the control lines 532 that identify those instructions within the current set of pending instructions that have been executed (done). From this information, the register rename unit 496 provides an eight element array of control signals to the instruction issuer unit 498 via the control lines 512. The control information so provided reflects the determination made by the register rename unit 496 as to which of the currently pending instructions, that have not already been executed, are now available to be executed given the current set of identified data dependencies. The register rename unit 496 receives a selection control signal via the lines 516 that identifies up to six instructions that are to be simultaneously issued for execution: two integer, two floating point and two boolean.
  • the register rename unit 496 performs the additional function of selecting, via control signals provided on the bus 518 to the register file array 472, the source registers for access in the execution of the identified instructions. Destination registers for out-of-order executed instructions are selected as being in the temporary buffers 612, 680, 728 of the corresponding data path. In-order executed instructions are retired on completion with result data being stored through to the register files 614, 684, 732.
  • the selection of source registers depends on whether the register has been prior selected as a destination and the corresponding prior instruction has not yet been retired. In such an instance, the source register is selected from the corresponding temporary buffer 612, 680, 728.
  • the register rename unit 496 operates to effectively substitute temporary buffer register references for register file register references in the case of out-of-order executed instructions.
  • the temporary buffers 612, 680, 728 are not duplicate register structures of their corresponding register file arrays. Rather, a single destination register slot is provided for each of eight pending instructions. Consequently, the substitution of a temporary buffer destination register reference is determined by the location of the corresponding instruction within the pending register sets. A subsequent source register reference is identified by the data dependency checker 494 with respect to the instruction from which the source dependency occurs. Therefore, a destination slot in the temporary buffer register is readily determinable by the register rename unit 496.
  • the instruction issuer unit 498 determines the set of instructions that can be issued, based on the output of the register rename unit 496 and the function requirements of the instructions as identified by the EDecode unit 490. The instruction issuer unit 498 makes this determination based on the status of each of the functional units 478 0-n as reported via control lines 514. Thus, the instruction issuer unit 498 begins operation upon receipt of the available set of instructions to issue from the register rename unit 496. Given that a register file access is required for the execution of each instruction, the instruction issuer unit 498 anticipates the availability of functional unit 478 0-n that may be currently executing an instruction. In order to minimize the delay in identifying the instructions to be issued to the register rename unit 496, the instruction issuer unit 498 is implemented in dedicated combinatorial logic.
  • the register rename unit 496 Upon identification of the instructions to issue, the register rename unit 496 initiates a register file access that continues to the end of the third processor cycle, P 2 .
  • the instruction issuer unit 498 initiates operation by one or more of the functional units 478 0-n , such as shown as "Execute 0", to receive and process source data provided from the register file array 472.
  • the architecture 100 typically, most instructions processed by the architecture 100 are executed through a functional unit in a single processor cycle. However, some instructions require multiple processor cycles to complete, such as shown as "Execute 1", a simultaneously issued instruction.
  • the Execute zero and Execute 1 instructions may, for example, be executed by an ALU and floating point multiplier functional units respectively.
  • the ALU functional unit as shown is FIG. 14, produces output data within one processor cycle and, by simple provision of output latching, available for use in executing another instruction during the fifth processor cycle, P 4 .
  • the floating point multiply functional unit is preferably an internally pipelined functional unit. Therefore, another additional floating point multiply instruction can be issued in the next processor cycle.
  • the result of the first instruction will not be available for a data dependant number of processor cycles; the instruction shown in FIG. 14 requires three processor cycles to complete processing through the functional unit.
  • the function of the instruction issuer unit 498 is repeated. Consequently, the status of the current set of pending instructions as well as the availability state of the full set of functional units 478 0-n are reevaluated during each processor cycle. Under optimum conditions, the preferred architecture 100 is therefore capable of executing up to six instructions per processor cycle. However, a typical instruction mix will result in an overall average execution of 1.5 to 2.0 instructions per processor cycle.
  • a final consideration in the function of the instruction issuer 498 is its participation in the handling of traps conditions and the execution of specific instructions.
  • the occurrence of a trap condition requires that the IEU 104 be cleared of all instructions that have not yet been retired. Such a circumstance may arise in response to an externally received interrupt that is relayed to the IEU 104 via the interrupt request/acknowledge control line 340, from any of the functional units 478 0-n in response to an arithmetic fault, or, for example, the EDecode unit 490 upon the decoding of an illegal instruction.
  • the instruction issuer unit 498 is responsible for halting or voiding all un-retired instructions currently pending in the IEU 104.
  • the instruction issuer 498 acknowledges the interrupt via a return control signal along the control lines 340. Also, in order to avoid the possibility that an exception condition relative to one instruction may be recognized based on a processor state bit which would have changed before that instruction would have executed in a classical pure in-order routine, the instruction issuer 498 is responsible for ensuring that all instructions which can alter the PSR (such as special move and return from trap) are executed strictly in-order.
  • Instructions of this type include subroutine returns, returns from procedural instructions, and returns from traps.
  • the instruction issuer unit 498 provides identifying control signals via the IEU return control lines 350 to the IFU 102.
  • a corresponding one of the special registers 412 is selected to provide the IF -- PC execution address that existed at the point in time of the call instruction, occurrence of the trap or encountering of a procedural instruction.
  • the done control unit 540 monitors the functional units 478 0-n for the completion status of their current operations.
  • the done control unit 540 anticipates the completion of operations by each functional unit sufficient to provide a completion vector, reflecting the status of the execution of each instruction in the currently pending set of instructions, to the register rename unit 496, bypass control unit 520 and retirement control unit 500 approximately one half processor cycle prior to the execution completion of an instruction by a functional unit 478 0-n .
  • This allows the instruction issuer unit 498, via the register rename unit 496, to consider the instruction completing functional units as available resources for the next instruction issuing cycle.
  • the bypass control unit 520 is allowed to prepare to bypass data output by the functional unit through the bypass unit 474.
  • the retirement control unit 500 nay operate to retire the corresponding instruction simultaneous with the transfer of data from the functional unit 478 0-n to the register file array 472.
  • the retirement control unit 500 monitors the oldest instruction set output from the EDecode output 490. As each instruction in instruction stream order is marked done by the done control unit 540, the retirement control unit 500 directs, via control signals provided on control lines 534, the transfer of data from the temporary buffer slot to the corresponding instruction specified register file register location within the register file array 472.
  • the PC Inc/Size control signals are provided on the control lines 344 for each one or more instruction simultaneously retired. Up to four instructions may be retired per processor cycle. Whenever an entire instruction set has been retired, an IFIFO read control signal is provided on the control line 342 to advance the IFIFO 264.
  • the control flow control unit 528 operates to continuously provide the IFU 102 with information specifying whether any control flow instructions within the current set of pending instructions have been resolved and, further, whether the branch result is taken or not taken.
  • the control flow control unit 528 obtains, via control lines 510, an identification of the control flow branch instructions by the EDecode 490.
  • the current set of register dependencies is provided via control lines 536 from the data dependency checker unit 494 to the control flow control unit 528 to allow the control flow control unit 528 to determine whether the outcome of a branch instruction is constrained by dependencies or is now known.
  • the register references provided via bus 518 from the register rename unit 496 are monitored by the control flow control 528 to identify the boolean register that mill define the branch decision. Thus, the branch decision may be determined even prior to the out-of-order execution of the control flow instruction.
  • the bypass unit 472 is directed by the bypass control unit 520 to provide the control flow results onto control lines 530, consisting of the control flow zero and control flow one 1 control lines 750, 752, to the control flow control unit 528.
  • the control flow control unit 528 continuously provides two vectors of eight bits each to the IFU 102 via control lines 348. These vectors define whether a branch instruction at the corresponding logical location corresponding to the bits within the vectors have been resolved and whether the branch result is taken or not taken.
  • control flow control unit 528 is implemented as pure combinatorial logic operating continuously in response to the input control signals to the control unit 528.
  • the instruction issuer unit 498 operates closely in conjunction with the bypass control unit 520 to control the routing of data between the register file array 472 and the functional units 478 0-n .
  • the bypass control unit 520 operates in conjunction with the register file access, output and store phases of operation shown in FIG. 14.
  • the bypass control unit 520 may recognize, via control lines 522, an access of a destination register within the register file array 472 that is in the process of being written during the output phase of execution of an instruction. In this case, the bypass control unit 520 directs the selection of data provided on the functional unit output bus 482 to be bypassed back to the functional unit distribution bus 480. Control over the bypass unit 520 is provided by the instruction issuer unit 498 via control lines 532.
  • the VMU 108 consists principally of a VMU control logic unit 800 and a content addressable memory (CAM) 802.
  • the general function of the VMU 108 is shown graphically in FIG. 16.
  • a representation of a virtual address is shown partitioned into a space identifier (sID[31:28]), a virtual page number (VADDR[27:14]), page offset (PADDR[13:4]), and a request ID (rID[3:0]).
  • the algorithm for generating a physical address is to use the space ID to select one of 16 registers within a space table 842.
  • the contents of the selected space register in combination with a virtual page number is used as an address for accessing a table look aside buffer (TLB) 844.
  • TLB table look aside buffer
  • the 34 bit address operates as a content address tag used to identify a corresponding buffer register within the buffer 844.
  • an 18 bit wide register value is provided as the high order 18 bits of a physical address 846.
  • the page offset and request ID are provided as the low order 14 bits of the physical address 846.
  • VMU miss is signalled.
  • This page table 850 contains entries for all memory pages currently in use by the architecture 100.
  • the hash algorithm 848 identifies those entries in the page table 850 necessary to satisfy the current virtual page translation operation.
  • Those page table entries are loaded from the MAU 112 to the trap registers of register set "A" and then transferred by special register move instructions to the table look aside buffer 844.
  • the instruction giving rise to the VMU miss exception is re-executed by the IEU 104.
  • the virtual to physical address translation operation should then complete without exception.
  • the VMU control logic 800 provides a dual interface to both the IFU 102 and IEU 104.
  • a ready signal is provided on control lines 822 to the IEU 104 to signify that the VMU 108 is available for an address translation.
  • the VMU 108 is always ready to accept IFU 120 translation requests.
  • Both the IFU and IEU 102, 104 may pose requests via control line 328, 804.
  • the IFU 102 has priority access to the VMU 108. Consequently, only a single busy control line 820 is provided to the IEU 104.
  • Both the IFU and IEU 102, 104 provide the space ID and virtual page number fields to the VMU control logic 800 via control lines 326, 808, respectively.
  • the IEU 104 provides a read/write control signal via control signal 806 to define whether the address is to be used for a load or store operation as necessary to modify memory access protection attributes of the virtual memory referenced.
  • the space ID and virtual page fields of the virtual address are passed to the CAM unit 802 to perform the actual translation operation.
  • the page offset and ExID fields are eventually provided by the IEU 104 directly to the CCU 106.
  • the physical page and request ID fields are provided on the address lines 836 to the CAM unit 802.
  • the occurrence of a table look aside buffer match is signalled via the hit line and control output lines 830 to the VMU control logic unit 800.
  • the resulting physical address 18 bits in length, is provided on the address output lines 824.
  • the VMU control logic unit 800 generates the virtual memory miss and virtual memory exception control signals on lines 334, 332 in response to the hit and control output control signals on lines 830.
  • a virtual memory translation miss is defined as failure to match a page table identifier in the table look aside buffer 844. All other translation errors are reported as virtual memory exceptions.
  • the data tables within the CAM unit 802 may be modified through the execution of special register to register move instructions by the IEU 104.
  • Read/write, register select, reset, load and clear control signals are provided by the IEU 104 via control lines 810, 812, 814, 816, 818.
  • Data to be written to the CAM unit registers is received by the VMU control logic unit 800 via the address bus 808 coupled to the special address data bus 354 from the IEU 104. This data is transferred via bus 836 to the CAM unit 802 simultaneous with control signals 628 that control the initialization, register selection, and read or write control signal. Consequently, the data registers within the CAM unit 802 may be readily written as required during the dynamic operation of the architecture 100 including read out for storage as required for the handling of context switches defined by a higher level operating system.
  • the control on data interface for the CCU 106 is shown in FIG. 17. Again, separate interfaces are provided for the IFU 102 and IEU 104. Further, logically separate interfaces are provided by the CCU 106 to the MCU 110 with respect to instruction and data transfers.
  • the IFU interface consists of the physical page address provided on address lines 324, the VMU converted page address as provided on the address lines 824, and request IDs as transferred separately on control lines 294, 296.
  • a unidirectional data transfer bus 114 is provided to transfer an entire instruction set in parallel to the IFU 102.
  • the read/busy and ready control signals are provided to the CCU 106 via control lines 298, 300, 302.
  • a complete physical address is provided by the IEU 102 via the physical address bus 788.
  • the request ExIDs are separately provided from and to the load/store unit of the IEU 104 via control lines 796.
  • An 80 bit wide bidirectional data bus is provided by the CCU 106 to the IEU 104. However, in the present preferred implementation of the architecture 100, only the lower 64 bits are utilized by the IEU 104. The availability and support within the CCU 106 of a full 80 bit data transfer bus is provided to support subsequent implementations of the architecture 100 that support, through modifications of the floating point data path 660, floating point operation in accordance with IEEE standard 754.
  • the IEU control interface established via request, busy, ready, read/write and with control signals 784 is substantially the same as the corresponding control signals utilized by the IFU 102.
  • the exception being the provision of a read/write control signal to differentiate between load and store operations.
  • the width control signals specify the number of bytes being transferred during each CCU 106 access by the IEU 104; in contrast every access of the instruction cache 132 is a fixed 128 bit wide data fetch operation.
  • the CCU 106 implements a substantially conventional cache controller function with respect to the separate instruction and data caches 132, 134.
  • the instruction cache 132 is a high speed memory providing for the storage of 256 128 bit wide instruction sets.
  • the data cache 134 provides for the storage of 1024 32 bit wide words of data. Instruction and data requests that cannot be immediately satisfied from the contents of the instruction and data caches 132, 134 are passed on to the MCU 110. For instruction cache misses, the 28 bit wide physical address is provided to the MCU 110 via the address bus 860.
  • the request ID and additional control signals for coordinating the operation of the CCU 106 and MCU 110 are provided on control lines 862.
  • Data transfer operations between the data cache 134 and MCU 110 are substantially the same as instruction cache operations. Since data load and store operations may reference a single byte, a full 32 bit wide physical address is provided to the MCU 110 via the address bus 864. Interface control signals and the request ExID are transferred via control lines 866. Bidirectional 64 bit wide data transfers are provided via the data cache bus 138.
  • the architecture efficiently implements out-of-order execution of instructions, separate main and target instruction stream prefetch instruction transfer paths, and a procedural instruction recognition and dedicated prefetch path.
  • the optimized instruction execution unit provides multiple optimized data processing paths supporting integer, floating point and boolean operations and incorporates respective temporary register files facilitating out-of-order execution and instruction cancellation while maintaining a readily established precise state-of-the-machine status.

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US07/817,810 US5539911A (en) 1991-07-08 1992-01-08 High-performance, superscalar-based computer system with out-of-order instruction execution
US08/602,021 US5689720A (en) 1991-07-08 1996-02-15 High-performance superscalar-based computer system with out-of-order instruction execution
US08/946,078 US6092181A (en) 1991-07-08 1997-10-07 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/150,706 US5961629A (en) 1991-07-08 1998-09-10 High performance, superscalar-based computer system with out-of-order instruction execution
US09/309,601 US6101594A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/309,603 US6128723A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/338,563 US6038654A (en) 1991-07-08 1999-06-23 High performance, superscalar-based computer system with out-of-order instruction execution
US09/436,986 US6256720B1 (en) 1991-07-08 1999-11-09 High performance, superscalar-based computer system with out-of-order instruction execution
US09/437,601 US6272619B1 (en) 1991-07-08 1999-11-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/852,293 US6647485B2 (en) 1991-07-08 2001-05-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,045 US6959375B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,207 US6948052B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/283,177 US6986024B2 (en) 1991-07-08 2002-10-30 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/283,106 US6915412B2 (en) 1991-07-08 2002-10-30 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/660,671 US7162610B2 (en) 1991-07-08 2003-09-12 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/697,257 US6934829B2 (en) 1991-07-08 2003-10-31 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/700,485 US7487333B2 (en) 1991-07-08 2003-11-05 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/700,520 US6941447B2 (en) 1991-07-08 2003-11-05 High-performance, superscalar-based computer system with out-of-order instruction execution
US11/642,599 US7739482B2 (en) 1991-07-08 2006-12-21 High-performance, superscalar-based computer system with out-of-order instruction execution
US12/235,215 US7721070B2 (en) 1991-07-08 2008-09-22 High-performance, superscalar-based computer system with out-of-order instruction execution

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US08/946,078 Expired - Fee Related US6092181A (en) 1991-07-08 1997-10-07 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/309,601 Expired - Fee Related US6101594A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/309,603 Expired - Fee Related US6128723A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/338,563 Expired - Fee Related US6038654A (en) 1991-07-08 1999-06-23 High performance, superscalar-based computer system with out-of-order instruction execution
US09/436,986 Expired - Fee Related US6256720B1 (en) 1991-07-08 1999-11-09 High performance, superscalar-based computer system with out-of-order instruction execution
US09/437,601 Expired - Fee Related US6272619B1 (en) 1991-07-08 1999-11-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/852,293 Expired - Fee Related US6647485B2 (en) 1991-07-08 2001-05-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,045 Expired - Fee Related US6959375B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,207 Expired - Fee Related US6948052B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
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US10/697,257 Expired - Fee Related US6934829B2 (en) 1991-07-08 2003-10-31 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/700,485 Expired - Fee Related US7487333B2 (en) 1991-07-08 2003-11-05 High-performance, superscalar-based computer system with out-of-order instruction execution
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US08/946,078 Expired - Fee Related US6092181A (en) 1991-07-08 1997-10-07 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/309,601 Expired - Fee Related US6101594A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/309,603 Expired - Fee Related US6128723A (en) 1991-07-08 1999-05-11 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/338,563 Expired - Fee Related US6038654A (en) 1991-07-08 1999-06-23 High performance, superscalar-based computer system with out-of-order instruction execution
US09/436,986 Expired - Fee Related US6256720B1 (en) 1991-07-08 1999-11-09 High performance, superscalar-based computer system with out-of-order instruction execution
US09/437,601 Expired - Fee Related US6272619B1 (en) 1991-07-08 1999-11-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US09/852,293 Expired - Fee Related US6647485B2 (en) 1991-07-08 2001-05-10 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,045 Expired - Fee Related US6959375B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/282,207 Expired - Fee Related US6948052B2 (en) 1991-07-08 2002-10-29 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/283,106 Expired - Fee Related US6915412B2 (en) 1991-07-08 2002-10-30 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/283,177 Expired - Fee Related US6986024B2 (en) 1991-07-08 2002-10-30 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/660,671 Expired - Fee Related US7162610B2 (en) 1991-07-08 2003-09-12 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/697,257 Expired - Fee Related US6934829B2 (en) 1991-07-08 2003-10-31 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/700,485 Expired - Fee Related US7487333B2 (en) 1991-07-08 2003-11-05 High-performance, superscalar-based computer system with out-of-order instruction execution
US10/700,520 Expired - Fee Related US6941447B2 (en) 1991-07-08 2003-11-05 High-performance, superscalar-based computer system with out-of-order instruction execution
US11/642,599 Expired - Fee Related US7739482B2 (en) 1991-07-08 2006-12-21 High-performance, superscalar-based computer system with out-of-order instruction execution
US12/235,215 Expired - Fee Related US7721070B2 (en) 1991-07-08 2008-09-22 High-performance, superscalar-based computer system with out-of-order instruction execution

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Cited By (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682492A (en) * 1989-02-24 1997-10-28 Advanced Micro Devices, Inc. Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US5715425A (en) * 1996-02-22 1998-02-03 Sun Microsystems, Inc. Apparatus and method for prefetching data into an external cache
US5724536A (en) * 1994-01-04 1998-03-03 Intel Corporation Method and apparatus for blocking execution of and storing load operations during their execution
US5734584A (en) * 1992-03-31 1998-03-31 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an integrated circuit chip
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
US5778434A (en) * 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
US5781753A (en) * 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
US5794027A (en) * 1993-07-01 1998-08-11 International Business Machines Corporation Method and apparatus for managing the execution of instructons with proximate successive branches in a cache-based data processing system
WO1998037485A1 (en) * 1997-02-21 1998-08-27 Richard Byron Wilmot Method and apparatus for forwarding of operands in a computer system
US5815688A (en) * 1996-10-09 1998-09-29 Hewlett-Packard Company Verification of accesses in a functional model of a speculative out-of-order computer system
US5838941A (en) * 1996-12-30 1998-11-17 Intel Corporation Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
US5867684A (en) * 1995-09-11 1999-02-02 International Business Machines Corporation Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction
US5897665A (en) * 1995-12-15 1999-04-27 Intel Corporation Register addressing for register-register architectures used for microprocessors and microcontrollers
WO1999026132A2 (en) * 1997-11-17 1999-05-27 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions
US5930490A (en) * 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US5956753A (en) * 1993-12-30 1999-09-21 Intel Corporation Method and apparatus for handling speculative memory access operations
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5983334A (en) * 1992-03-31 1999-11-09 Seiko Epson Corporation Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions
US6038654A (en) * 1991-07-08 2000-03-14 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US6092183A (en) * 1994-03-16 2000-07-18 Hitachi, Ltd. Data processor for processing a complex instruction by dividing it into executing units
US6195746B1 (en) 1997-01-31 2001-02-27 International Business Machines Corporation Dynamically typed register architecture
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US6249857B1 (en) * 1997-10-20 2001-06-19 Motorola, Inc. Apparatus using a multiple instruction register logarithm based processor
US6266761B1 (en) * 1998-06-12 2001-07-24 International Business Machines Corporation Method and system in an information processing system for efficient maintenance of copies of values stored within registers
US6308262B1 (en) * 1998-09-30 2001-10-23 Intel Corporation System and method for efficient processing of instructions using control unit to select operations
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6493790B1 (en) * 1998-01-30 2002-12-10 Sun Microsystems, Inc. Translation-lookaside buffer with current tracking reference circuit
US20030093771A1 (en) * 2001-11-05 2003-05-15 Hajime Ogawa Debugging aid device, a compiling device, a debugging aid program, a compiling program, and a computer readable record medium therefor
US6697908B2 (en) * 1992-09-18 2004-02-24 Renesas Technology Corporation Processor system using synchronous dynamic memory
US6754808B1 (en) * 2000-09-29 2004-06-22 Intel Corporation Valid bit generation and tracking in a pipelined processor
US20040172522A1 (en) * 1996-01-31 2004-09-02 Prasenjit Biswas Floating point unit pipeline synchronized with processor pipeline
US6799269B2 (en) * 1997-08-01 2004-09-28 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US20050195197A1 (en) * 2000-11-16 2005-09-08 Andrew Wolfe Superscalar 3D graphics engine
US20060253686A1 (en) * 2005-03-08 2006-11-09 Nec Electronics Corporation Instruction prefetch apparatus and instruction prefetch method
US20070294585A1 (en) * 2006-04-27 2007-12-20 Texas Instruments Incorporated Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment
US20080278169A1 (en) * 1999-01-28 2008-11-13 Halliburton Energy Services, Inc. Electromagnetic Wave Resistivity Tool Having a Tilted Antenna for Determining the Horizontal and Vertical Resistivities and Relative Dip Angle in Anisotropic Earth Formations
US20090147599A1 (en) * 2002-07-29 2009-06-11 Vinod Lakhani Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table
KR100930332B1 (ko) * 1999-12-17 2009-12-08 후지쯔 가부시끼가이샤 프로세서 및 그 제어 방법
US7685402B2 (en) 1991-07-08 2010-03-23 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets
US7802074B2 (en) 1992-03-31 2010-09-21 Sanjiv Garg Superscalar RISC instruction scheduling
US7823117B1 (en) * 2007-12-21 2010-10-26 Xilinx, Inc. Separating a high-level programming language program into hardware and software components
US7934078B2 (en) 1992-05-01 2011-04-26 Seiko Epson Corporation System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
US7979678B2 (en) 1992-12-31 2011-07-12 Seiko Epson Corporation System and method for register renaming
US8074052B2 (en) 1992-12-31 2011-12-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
CN109614145A (zh) * 2018-10-18 2019-04-12 中国科学院计算技术研究所 一种处理器核心结构及数据访存方法
US11176055B1 (en) 2019-08-06 2021-11-16 Marvell Asia Pte, Ltd. Managing potential faults for speculative page table access
US11243778B1 (en) * 2020-12-31 2022-02-08 Microsoft Technology Licensing, Llc Instruction dispatch for superscalar processors
EP4172760A4 (en) * 2020-06-26 2024-07-24 Advanced Micro Devices Inc MACHINE FOR TRANSLATION OF COMMAND ADDRESSES AND COMMAND SUMMONS

Families Citing this family (183)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04367936A (ja) * 1991-06-17 1992-12-21 Mitsubishi Electric Corp スーパースカラープロセッサ
EP1526446A3 (en) 1991-07-08 2007-04-04 Seiko Epson Corporation Extensible RISC microprocessor architecture
JP2801135B2 (ja) * 1993-11-26 1998-09-21 富士通株式会社 パイプラインプロセッサの命令読み出し方法及び命令読み出し装置
US6393550B1 (en) * 1993-12-30 2002-05-21 Intel Corporation Method and apparatus for pipeline streamlining where resources are immediate or certainly retired
US5546597A (en) * 1994-02-28 1996-08-13 Intel Corporation Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
US5564056A (en) * 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US5878244A (en) * 1995-01-25 1999-03-02 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
US5652774A (en) * 1996-07-08 1997-07-29 International Business Machines Corporation Method and apparatus for decreasing the cycle times of a data processing system
US5872951A (en) * 1996-07-26 1999-02-16 Advanced Micro Design, Inc. Reorder buffer having a future file for storing speculative instruction execution results
US5915110A (en) * 1996-07-26 1999-06-22 Advanced Micro Devices, Inc. Branch misprediction recovery in a reorder buffer having a future file
US5946468A (en) * 1996-07-26 1999-08-31 Advanced Micro Devices, Inc. Reorder buffer having an improved future file for storing speculative instruction execution results
US5983342A (en) * 1996-09-12 1999-11-09 Advanced Micro Devices, Inc. Superscalar microprocessor employing a future file for storing results into multiportion registers
US5774694A (en) * 1996-09-25 1998-06-30 Intel Corporation Method and apparatus for emulating status flag
US5864701A (en) * 1997-02-14 1999-01-26 Integrated Device Technology, Inc. Apparatus and method for managing interrupt delay associated with mask flag transition
US6263416B1 (en) * 1997-06-27 2001-07-17 Sun Microsystems, Inc. Method for reducing number of register file ports in a wide instruction issue processor
US5944810A (en) * 1997-06-27 1999-08-31 Sun Microsystems, Inc. Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data
US6035388A (en) 1997-06-27 2000-03-07 Sandcraft, Inc. Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units
US5966142A (en) * 1997-09-19 1999-10-12 Cirrus Logic, Inc. Optimized FIFO memory
US6345355B1 (en) 1998-05-29 2002-02-05 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for distributing commands to a plurality of circuit blocks
WO2000011547A1 (en) * 1998-08-21 2000-03-02 California Institute Of Technology Processing element with special application for branch functions
US6882642B1 (en) * 1999-10-14 2005-04-19 Nokia, Inc. Method and apparatus for input rate regulation associated with a packet processing pipeline
US6470427B1 (en) 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
US6467027B1 (en) * 1999-12-30 2002-10-15 Intel Corporation Method and system for an INUSE field resource management scheme
US6609193B1 (en) * 1999-12-30 2003-08-19 Intel Corporation Method and apparatus for multi-thread pipelined instruction decoder
US6601162B1 (en) * 2000-01-19 2003-07-29 Kabushiki Kaisha Toshiba Processor which executes pipeline processing having a plurality of stages and which has an operand bypass predicting function
US7149883B1 (en) * 2000-03-30 2006-12-12 Intel Corporation Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
US6606684B1 (en) 2000-03-31 2003-08-12 Intel Corporation Multi-tiered memory bank having different data buffer sizes with a programmable bank select
US6446181B1 (en) * 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
US6785802B1 (en) 2000-06-01 2004-08-31 Stmicroelectronics, Inc. Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor
US7080183B1 (en) * 2000-08-16 2006-07-18 Koninklijke Philips Electronics N.V. Reprogrammable apparatus supporting the processing of a digital signal stream and method
SE0003398D0 (sv) * 2000-09-22 2000-09-22 Ericsson Telefon Ab L M Optimization of a pipelined processor system
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7162718B1 (en) * 2000-12-12 2007-01-09 International Business Machines Corporation Language extension for light weight threading in a JVM
US7069422B2 (en) * 2000-12-22 2006-06-27 Modelski Richard P Load-shift carry instruction
US7007156B2 (en) * 2000-12-28 2006-02-28 Intel Corporation Multiple coprocessor architecture to process a plurality of subtasks in parallel
US6643755B2 (en) * 2001-02-20 2003-11-04 Koninklijke Philips Electronics N.V. Cyclically sequential memory prefetch
US6493814B2 (en) 2001-03-08 2002-12-10 International Business Machines Corporation Reducing resource collisions associated with memory units in a multi-level hierarchy memory system
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US7191430B2 (en) * 2001-09-24 2007-03-13 Hewlett-Packard Development Company, L.P. Providing instruction execution hints to a processor using break instructions
JP2003140886A (ja) * 2001-10-31 2003-05-16 Seiko Epson Corp インストラクションセット及びコンパイラ
US7376811B2 (en) * 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
JP3878508B2 (ja) * 2001-11-08 2007-02-07 松下電器産業株式会社 回路群制御システム
US6895460B2 (en) * 2002-07-19 2005-05-17 Hewlett-Packard Development Company, L.P. Synchronization of asynchronous emulated interrupts
US7493478B2 (en) * 2002-12-05 2009-02-17 International Business Machines Corporation Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
US7502910B2 (en) * 2003-01-28 2009-03-10 Sun Microsystems, Inc. Sideband scout thread processor for reducing latency associated with a main processor
US20040148489A1 (en) * 2003-01-28 2004-07-29 Sun Microsystems, Inc. Sideband VLIW processor
US20040199749A1 (en) * 2003-04-03 2004-10-07 Robert Golla Method and apparatus to limit register file read ports in an out-of-order, multi-stranded processor
US7873110B2 (en) * 2003-06-17 2011-01-18 Broadcom Corporation MPEG smart video transport processor with different transport packet handling
US7428631B2 (en) * 2003-07-31 2008-09-23 Intel Corporation Apparatus and method using different size rename registers for partial-bit and bulk-bit writes
US7552426B2 (en) * 2003-10-14 2009-06-23 Microsoft Corporation Systems and methods for using synthetic instructions in a virtual machine
US7310722B2 (en) * 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
US20050138297A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Register file cache
US7171545B2 (en) * 2003-12-30 2007-01-30 Intel Corporation Predictive filtering of register cache entry
US7484045B2 (en) 2004-03-30 2009-01-27 Intel Corporation Store performance in strongly-ordered microprocessor architecture
US7437536B2 (en) * 2004-05-03 2008-10-14 Sony Computer Entertainment Inc. Systems and methods for task migration
US7724263B2 (en) * 2004-05-14 2010-05-25 Nvidia Corporation System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories
US7868902B1 (en) * 2004-05-14 2011-01-11 Nvidia Corporation System and method for pixel data row forwarding in a 3-D graphics pipeline
US8719837B2 (en) 2004-05-19 2014-05-06 Synopsys, Inc. Microprocessor architecture having extendible logic
US8225034B1 (en) * 2004-06-30 2012-07-17 Oracle America, Inc. Hybrid instruction buffer
US7200693B2 (en) * 2004-08-27 2007-04-03 Micron Technology, Inc. Memory system and method having unidirectional data buses
US20080162877A1 (en) * 2005-02-24 2008-07-03 Erik Richter Altman Non-Homogeneous Multi-Processor System With Shared Memory
JP4841861B2 (ja) * 2005-05-06 2011-12-21 ルネサスエレクトロニクス株式会社 演算処理装置及びデータ転送処理の実行方法
US20070028027A1 (en) * 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
US7647487B2 (en) 2005-08-29 2010-01-12 Searete, Llc Instruction-associated processor resource optimization
US7725693B2 (en) 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US7627739B2 (en) * 2005-08-29 2009-12-01 Searete, Llc Optimization of a hardware resource shared by a multiprocessor
US8209524B2 (en) 2005-08-29 2012-06-26 The Invention Science Fund I, Llc Cross-architecture optimization
US7607042B2 (en) * 2005-08-29 2009-10-20 Searete, Llc Adjusting a processor operating parameter based on a performance criterion
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US7779213B2 (en) * 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US8255745B2 (en) * 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US8516300B2 (en) * 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US8423824B2 (en) 2005-08-29 2013-04-16 The Invention Science Fund I, Llc Power sparing synchronous apparatus
US20070050605A1 (en) * 2005-08-29 2007-03-01 Bran Ferren Freeze-dried ghost pages
US20070050606A1 (en) * 2005-08-29 2007-03-01 Searete Llc, A Limited Liability Corporation Of The State Of Delaware Runtime-based optimization profile
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US7774558B2 (en) * 2005-08-29 2010-08-10 The Invention Science Fund I, Inc Multiprocessor resource optimization
US7739524B2 (en) * 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US7653834B2 (en) 2005-08-29 2010-01-26 Searete, Llc Power sparing synchronous apparatus
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US8981996B2 (en) * 2005-09-27 2015-03-17 Qualcomm Incorporated Position location using transmitters with timing offset and phase adjustment
US8218635B2 (en) 2005-09-28 2012-07-10 Synopsys, Inc. Systolic-array based systems and methods for performing block matching in motion compensation
US8078845B2 (en) 2005-12-16 2011-12-13 Freescale Semiconductor, Inc. Device and method for processing instructions based on masked register group size information
US8266413B2 (en) * 2006-03-14 2012-09-11 The Board Of Trustees Of The University Of Illinois Processor architecture for multipass processing of instructions downstream of a stalled instruction
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
US7647486B2 (en) 2006-05-02 2010-01-12 Atmel Corporation Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode
US20080077777A1 (en) * 2006-09-25 2008-03-27 Arm Limited Register renaming for instructions having unresolved condition codes
EP2523101B1 (en) 2006-11-14 2014-06-04 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US7664932B2 (en) 2007-04-13 2010-02-16 Microsoft Corporation Scalable and configurable execution pipeline of handlers having policy information for selectively acting on payload
US8082540B2 (en) * 2007-04-19 2011-12-20 International Business Machines Corporation Method for visually indicating preceding and succeeding source code lines that are executed in a graphical debugging environment
JP2008305185A (ja) * 2007-06-07 2008-12-18 Nec Electronics Corp プロセッサ装置及び複合条件処理方法
JP4896837B2 (ja) * 2007-08-20 2012-03-14 株式会社東芝 携帯可能電子装置および携帯可能電子装置の制御方法
US8176406B2 (en) * 2008-03-19 2012-05-08 International Business Machines Corporation Hard error detection
US20090249035A1 (en) * 2008-03-28 2009-10-01 International Business Machines Corporation Multi-cycle register file bypass
US20090289943A1 (en) * 2008-05-22 2009-11-26 Howard Teece Anti-aliasing system and method
KR101012121B1 (ko) * 2008-06-05 2011-02-07 경상북도 (관련부서:경상북도축산기술연구소장) 송아지 사육 케이지
KR100892857B1 (ko) * 2008-07-30 2009-04-15 주식회사 유비콘테크놀로지 시스템온칩의 내부 메모리 장치 및 그 운영방법
GB2463278B (en) * 2008-09-05 2012-05-16 Advanced Risc Mach Ltd Scheduling control within a data processing system
US8312442B2 (en) * 2008-12-10 2012-11-13 Oracle America, Inc. Method and system for interprocedural prefetching
US9690625B2 (en) * 2009-06-16 2017-06-27 Oracle America, Inc. System and method for out-of-order resource allocation and deallocation in a threaded machine
KR101032771B1 (ko) * 2009-05-29 2011-05-06 광운대학교 산학협력단 구성형 프로세서에서 ｒｉｓｃ 명령어와 확장 명령어를 병렬 처리하기 위한 방법 및 그에 따른 구성형 프로세서
KR200448337Y1 (ko) * 2009-12-31 2010-04-05 임준기 통풍기능을 구비한 농산물 받침대
CN102193775B (zh) * 2010-04-27 2015-07-29 威盛电子股份有限公司 微处理器融合搬运/算术逻辑运算/条件跳跃指令
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
EP2628072B1 (en) 2010-10-12 2016-10-12 Soft Machines, Inc. An instruction sequence buffer to enhance branch prediction efficiency
TWI525541B (zh) 2010-10-12 2016-03-11 軟體機器公司 輸出可靠可預測指令序列的方法與系統，以及實施識別指令方法的微處理器
US9710270B2 (en) * 2010-12-20 2017-07-18 International Business Machines Corporation Exception control method, system, and program
CN108376097B (zh) 2011-03-25 2022-04-15 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
EP2689327B1 (en) 2011-03-25 2021-07-28 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
CN102789377B (zh) 2011-05-18 2015-09-30 国际商业机器公司 处理指令分组信息的方法和装置
CN103649931B (zh) 2011-05-20 2016-10-12 索夫特机械公司 用于支持由多个引擎执行指令序列的互连结构
KR101639853B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당
US8683261B2 (en) 2011-07-20 2014-03-25 International Business Machines Corporation Out of order millicode control operation
US8612959B2 (en) 2011-10-03 2013-12-17 International Business Machines Corporation Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
US9329869B2 (en) 2011-10-03 2016-05-03 International Business Machines Corporation Prefix computer instruction for compatibily extending instruction functionality
US10078515B2 (en) 2011-10-03 2018-09-18 International Business Machines Corporation Tracking operand liveness information in a computer system and performing function based on the liveness information
US8615745B2 (en) 2011-10-03 2013-12-24 International Business Machines Corporation Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
US8756591B2 (en) 2011-10-03 2014-06-17 International Business Machines Corporation Generating compiled code that indicates register liveness
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US9697002B2 (en) 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US9354874B2 (en) 2011-10-03 2016-05-31 International Business Machines Corporation Scalable decode-time instruction sequence optimization of dependent instructions
US9286072B2 (en) 2011-10-03 2016-03-15 International Business Machines Corporation Using register last use infomation to perform decode-time computer instruction optimization
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
KR101912427B1 (ko) 2011-12-12 2018-10-29 삼성전자주식회사 재구성가능 프로세서 및 재구성가능 프로세서의 미니 코어
US20140082333A1 (en) * 2011-12-22 2014-03-20 Elmoustapha Ould-Ahmed-Vall Systems, apparatuses, and methods for performing an absolute difference calculation between corresponding packed data elements of two vector registers
WO2013095666A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing vector packed unary decoding using masks
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9152566B2 (en) * 2012-06-15 2015-10-06 International Business Machines Corporation Prefetch address translation using prefetch buffer based on availability of address translation logic
US10255944B2 (en) * 2012-06-27 2019-04-09 Marvell World Trade Ltd. Systems and methods for reading and decoding encoded data from a storage device
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
US10299934B2 (en) * 2012-12-11 2019-05-28 Globus Medical, Inc Expandable vertebral implant
US20140281413A1 (en) * 2013-03-14 2014-09-18 Mips Technologies, Inc. Superforwarding Processor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9582322B2 (en) 2013-03-15 2017-02-28 Soft Machines Inc. Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
US9627038B2 (en) 2013-03-15 2017-04-18 Intel Corporation Multiport memory cell having improved density area
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US20140281116A1 (en) 2013-03-15 2014-09-18 Soft Machines, Inc. Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
GB2523823B (en) * 2014-03-07 2021-06-16 Advanced Risc Mach Ltd Data processing apparatus and method for processing vector operands
US9841974B2 (en) * 2014-04-25 2017-12-12 Avago Technologies General Ip (Singapore) Pte. Ltd. Renaming with generation numbers
JP2017516228A (ja) 2014-05-12 2017-06-15 インテル・コーポレーション 自己書き換えコードのハードウェアサポートを提供する方法及び装置
CN104156196B (zh) * 2014-06-12 2017-10-27 龚伟峰 重命名预处理方法
US9678758B2 (en) 2014-09-26 2017-06-13 Qualcomm Incorporated Coprocessor for out-of-order loads
US9483409B2 (en) 2015-02-05 2016-11-01 International Business Machines Corporation Store forwarding cache
US10698688B2 (en) 2015-06-24 2020-06-30 International Business Machines Corporation Efficient quantization of compare results
US10620952B2 (en) 2015-06-24 2020-04-14 International Business Machines Corporation Conversion of boolean conditions
US10705841B2 (en) 2015-06-24 2020-07-07 International Business Machines Corporation Instruction to perform a logical operation on conditions and to quantize the Boolean result of that operation
US9794660B2 (en) 2015-09-25 2017-10-17 Intel Corporation Integrated sound bar hinge assembly for mobile electronic device
US10445091B1 (en) * 2016-03-30 2019-10-15 Apple Inc. Ordering instructions in a processing core instruction buffer
US11687345B2 (en) 2016-04-28 2023-06-27 Microsoft Technology Licensing, Llc Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
US10496409B2 (en) 2016-11-22 2019-12-03 The Arizona Board Of Regents Method and system for managing control of instruction and process execution in a programmable computing system
US10162680B2 (en) * 2016-12-13 2018-12-25 GM Global Technology Operations LLC Control of data exchange between a primary core and a secondary core using a freeze process flag and a data frozen flag in real-time
US10983799B1 (en) 2017-12-19 2021-04-20 Apple Inc. Selection of instructions to issue in a processor
US11422821B1 (en) 2018-09-04 2022-08-23 Apple Inc. Age tracking for independent pipelines
US11269650B2 (en) * 2018-12-29 2022-03-08 Texas Instruments Incorporated Pipeline protection for CPUs with save and restore of intermediate results
CN111488176B (zh) * 2019-01-25 2023-04-18 阿里巴巴集团控股有限公司 一种指令调度方法、装置、设备及存储介质
US11573802B2 (en) 2019-10-23 2023-02-07 Texas Instruments Incorporated User mode event handling
US11656876B2 (en) 2020-10-29 2023-05-23 Cadence Design Systems, Inc. Removal of dependent instructions from an execution pipeline
US11886883B2 (en) 2021-08-26 2024-01-30 International Business Machines Corporation Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction
US11809874B2 (en) 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
KR20240124412A (ko) * 2022-02-01 2024-08-16 애플 인크. 조건부 명령어 예측

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3346851A (en) * 1964-07-08 1967-10-10 Control Data Corp Simultaneous multiprocessing computer system
US3771138A (en) * 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
GB2011682A (en) * 1977-12-30 1979-07-11 Honeywell Inf Systems Instruction buffer in computer
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4296470A (en) * 1979-06-21 1981-10-20 International Business Machines Corp. Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system
US4410939A (en) * 1979-07-17 1983-10-18 Matsushita Electric Industrial Co. Ltd. System for program interrupt processing with quasi-stack of register-sets
US4434641A (en) * 1982-03-11 1984-03-06 Ball Corporation Buckle resistance for metal container closures
US4459657A (en) * 1980-09-24 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system having re-entrant function for subroutines
US4476525A (en) * 1980-08-28 1984-10-09 Nec Corporation Pipeline-controlled data processing system capable of performing a plurality of instructions simultaneously
EP0171595A2 (en) * 1984-08-13 1986-02-19 International Business Machines Corporation Floating point arithmetic unit
FR2575564A1 (fr) * 1984-12-27 1986-07-04 Sony Corp Microprocesseur a architecture facilitant la liaison avec des dispositifs peripheriques
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
US4752873A (en) * 1985-05-22 1988-06-21 Hitachi Vlsi Eng. Corp. Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
US4858105A (en) * 1986-03-26 1989-08-15 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
US4901228A (en) * 1986-07-17 1990-02-13 Mitsubishi Denki K.K. Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing
EP0354585A2 (en) * 1988-08-11 1990-02-14 Kabushiki Kaisha Toshiba Instruction pipeline microprocessor
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4924376A (en) * 1985-12-26 1990-05-08 Nec Corporation System for dynamically adjusting the accumulation of instructions in an instruction code prefetched pipelined computer
EP0368332A2 (en) * 1988-11-11 1990-05-16 Hitachi, Ltd. Pipeline data processor
US4942525A (en) * 1986-11-21 1990-07-17 Hitachi, Ltd. Data processor for concurrent executing of instructions by plural execution units
US5003462A (en) * 1988-05-31 1991-03-26 International Business Machines Corporation Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means
EP0419105A2 (en) * 1989-09-21 1991-03-27 Texas Instruments Incorporated Integrated circuit having an embedded digital signal processor
EP0426393A2 (en) * 1989-11-01 1991-05-08 Fujitsu Limited Instructing method and execution system
EP0479390A2 (en) * 1990-10-05 1992-04-08 Koninklijke Philips Electronics N.V. Processing device including a memory circuit and a group of functional units

Family Cites Families (253)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3718912A (en) * 1970-12-22 1973-02-27 Ibm Instruction execution unit
US3789365A (en) * 1971-06-03 1974-01-29 Bunker Ramo Processor interrupt system
US3913074A (en) 1973-12-18 1975-10-14 Honeywell Inf Systems Search processing apparatus
JPS5110746A (ko) 1974-07-17 1976-01-28 Hitachi Ltd
US4041461A (en) * 1975-07-25 1977-08-09 International Business Machines Corporation Signal analyzer system
US4034349A (en) * 1976-01-29 1977-07-05 Sperry Rand Corporation Apparatus for processing interrupts in microprocessing systems
US4128880A (en) 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US4212076A (en) 1976-09-24 1980-07-08 Giddings & Lewis, Inc. Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former
US4101086A (en) 1977-07-20 1978-07-18 Eastman Kodak Company Yarn tie-up and transfer tail method, and yarn package tube and apparatus for the method
US4237532A (en) * 1977-09-02 1980-12-02 Sperry Corporation Table driven decision and control logic for digital computers
US4199811A (en) * 1977-09-02 1980-04-22 Sperry Corporation Microprogrammable computer utilizing concurrently operating processors
US4210960A (en) * 1977-09-02 1980-07-01 Sperry Corporation Digital computer with overlapped operation utilizing conditional control to minimize time losses
US4296465A (en) * 1977-11-03 1981-10-20 Honeywell Information Systems Inc. Data mover
US4315314A (en) * 1977-12-30 1982-02-09 Rca Corporation Priority vectored interrupt having means to supply branch address directly
US4228495A (en) * 1978-12-19 1980-10-14 Allen-Bradley Company Multiprocessor numerical control system
US4315308A (en) * 1978-12-21 1982-02-09 Intel Corporation Interface between a microprocessor chip and peripheral subsystems
US4336024A (en) * 1980-02-22 1982-06-22 Airwick Industries, Inc. Process for cleaning clothes at home
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
JPS57150040A (en) 1981-03-11 1982-09-16 Mitsubishi Electric Corp Pipeline computer
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
US4574349A (en) * 1981-03-30 1986-03-04 International Business Machines Corp. Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
US4814979A (en) * 1981-04-01 1989-03-21 Teradata Corporation Network to transmit prioritized subtask pockets to dedicated processors
JPS57204125A (en) 1981-06-10 1982-12-14 Hitachi Ltd Electron-ray drawing device
US4482950A (en) 1981-09-24 1984-11-13 Dshkhunian Valery Single-chip microcomputer
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
JPS58151655A (ja) * 1982-03-03 1983-09-08 Fujitsu Ltd 情報処理装置
US4484272A (en) * 1982-07-14 1984-11-20 Burroughs Corporation Digital computer for executing multiple instruction sets in a simultaneous-interleaved fashion
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4500963A (en) * 1982-11-29 1985-02-19 The United States Of America As Represented By The Secretary Of The Army Automatic layout program for hybrid microcircuits (HYPAR)
US4597054A (en) 1982-12-02 1986-06-24 Ncr Corporation Arbiter circuit and method
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4800486A (en) * 1983-09-29 1989-01-24 Tandem Computers Incorporated Multiple data patch CPU architecture
GB8329509D0 (en) * 1983-11-04 1983-12-07 Inmos Ltd Computer
JPS60120439A (ja) * 1983-12-05 1985-06-27 Nec Corp 演算処理装置
US4561051A (en) 1984-02-10 1985-12-24 Prime Computer, Inc. Memory access method and apparatus in multiple processor systems
JPS60168238A (ja) * 1984-02-10 1985-08-31 Hitachi Ltd パイプラインデータ処理装置
AU553416B2 (en) * 1984-02-24 1986-07-17 Fujitsu Limited Pipeline processing
JPS60225943A (ja) * 1984-04-25 1985-11-11 Hitachi Ltd 例外割込み処理方式
US4648045A (en) * 1984-05-23 1987-03-03 The Board Of Trustees Of The Leland Standford Jr. University High speed memory and processor system for raster display
JPS6140650A (ja) 1984-08-02 1986-02-26 Nec Corp マイクロコンピユ−タ
US4677545A (en) 1984-10-12 1987-06-30 American Telephone And Telegraph Company Microprocessor having macro-rom and main program queues
US4775927A (en) * 1984-10-31 1988-10-04 International Business Machines Corporation Processor including fetch operation for branch instruction with control tag
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
EP0185215B1 (en) * 1984-11-21 1993-09-22 Harris Corporation Forth-like language microprocessor
JPS61133439A (ja) 1984-12-04 1986-06-20 Nec Corp 命令先取り制御方式
JPH0652784B2 (ja) 1984-12-07 1994-07-06 富士通株式会社 ゲートアレイ集積回路装置及びその製造方法
US4829467A (en) 1984-12-21 1989-05-09 Canon Kabushiki Kaisha Memory controller including a priority order determination circuit
US5255384A (en) 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
CA1254661A (en) * 1985-06-28 1989-05-23 Allen J. Baum Method and means for instruction combination for code compression
US4613941A (en) 1985-07-02 1986-09-23 The United States Of America As Represented By The Secretary Of The Army Routing method in computer aided customization of a two level automated universal array
US4945479A (en) 1985-07-31 1990-07-31 Unisys Corporation Tightly coupled scientific processing system
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
US4777588A (en) 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance
US4719569A (en) * 1985-10-11 1988-01-12 Sun Microsystems, Inc. Arbitrator for allocating access to data processing resources
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
JPH0622035B2 (ja) * 1985-11-13 1994-03-23 株式会社日立製作所 ベクトル処理装置
IL81762A0 (en) * 1986-04-11 1987-10-20 Symbolics Inc Instruction prefetch unit
JP2545789B2 (ja) 1986-04-14 1996-10-23 株式会社日立製作所 情報処理装置
US4809169A (en) * 1986-04-23 1989-02-28 Advanced Micro Devices, Inc. Parallel, multiple coprocessor computer architecture having plural execution modes
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
JP2684362B2 (ja) 1986-06-18 1997-12-03 株式会社日立製作所 可変長データの記憶方式
US4814978A (en) * 1986-07-15 1989-03-21 Dataflow Computer Corporation Dataflow processing element, multiprocessor, and processes
US4942323A (en) * 1986-07-28 1990-07-17 Decesare Dominic Two pole electric motor with stator winding encircling the rotor
JPS6393041A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp 計算機
JPH0793358B2 (ja) 1986-11-10 1995-10-09 日本電気株式会社 ブロック配置処理方式
US4841453A (en) 1986-11-10 1989-06-20 Ibm Corporation Multidirectional scan and print capability
JPH0810430B2 (ja) 1986-11-28 1996-01-31 株式会社日立製作所 情報処理装置
US5283903A (en) * 1986-12-25 1994-02-01 Nec Corporation Priority selector
US5226170A (en) * 1987-02-24 1993-07-06 Digital Equipment Corporation Interface between processor and special instruction processor in digital data processing system
US5179689A (en) 1987-03-13 1993-01-12 Texas Instruments Incorporated Dataprocessing device with instruction cache
US4833599A (en) 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US4858116A (en) 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
JP2510591B2 (ja) * 1987-06-12 1996-06-26 株式会社日立製作所 命令処理装置
JPH07113903B2 (ja) * 1987-06-26 1995-12-06 株式会社日立製作所 キャッシュ記憶制御方式
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US4901233A (en) 1987-07-20 1990-02-13 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US5134561A (en) 1987-07-20 1992-07-28 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
JP2624484B2 (ja) 1987-07-31 1997-06-25 三井東圧化学株式会社 中国語の入力処理方法
US5150309A (en) 1987-08-04 1992-09-22 Texas Instruments Incorporated Comprehensive logic circuit layout system
US4980817A (en) 1987-08-31 1990-12-25 Digital Equipment Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports
US4991078A (en) * 1987-09-29 1991-02-05 Digital Equipment Corporation Apparatus and method for a pipelined central processing unit in a data processing system
EP0312764A3 (en) 1987-10-19 1991-04-10 International Business Machines Corporation A data processor having multiple execution units for processing plural classes of instructions in parallel
US5089951A (en) * 1987-11-05 1992-02-18 Kabushiki Kaisha Toshiba Microcomputer incorporating memory
US5197136A (en) * 1987-11-12 1993-03-23 Matsushita Electric Industrial Co., Ltd. Processing system for branch instruction
US4823201A (en) * 1987-11-16 1989-04-18 Technology, Inc. 64 Processor for expanding a compressed video signal
US5185878A (en) 1988-01-20 1993-02-09 Advanced Micro Device, Inc. Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
US4926323A (en) * 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
JPH0769821B2 (ja) * 1988-03-04 1995-07-31 日本電気株式会社 情報処理装置におけるバイパスライン制御方式
JPH01228865A (ja) 1988-03-09 1989-09-12 Minolta Camera Co Ltd プリンタ制御装置
US5187796A (en) * 1988-03-29 1993-02-16 Computer Motion, Inc. Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units
US5155817A (en) 1988-04-01 1992-10-13 Kabushiki Kaisha Toshiba Microprocessor
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US4897810A (en) * 1988-06-13 1990-01-30 Advanced Micro Devices, Inc. Asynchronous interrupt status bit circuit
US5261057A (en) 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
US5097409A (en) * 1988-06-30 1992-03-17 Wang Laboratories, Inc. Multi-processor system with cache memories
JP2761506B2 (ja) 1988-07-08 1998-06-04 株式会社日立製作所 主記憶制御装置
JPH0222736A (ja) 1988-07-12 1990-01-25 Nec Corp 中央処理装置
US5032985A (en) 1988-07-21 1991-07-16 International Business Machines Corporation Multiprocessor system with memory fetch buffer invoked during cross-interrogation
US5148536A (en) 1988-07-25 1992-09-15 Digital Equipment Corporation Pipeline having an integral cache which processes cache misses and loads data in parallel
US5291615A (en) * 1988-08-11 1994-03-01 Kabushiki Kaisha Toshiba Instruction pipeline microprocessor
US4974155A (en) * 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5167035A (en) * 1988-09-08 1992-11-24 Digital Equipment Corporation Transferring messages between nodes in a network
JPH0287229A (ja) 1988-09-24 1990-03-28 Nec Corp 実行命令の先取り制御方式
US4879787A (en) 1988-10-03 1989-11-14 Walls Thomas J Shoe lace knot securing device
EP0365188B1 (en) * 1988-10-18 1996-09-18 Hewlett-Packard Company Central processor condition code method and apparatus
JP2672599B2 (ja) * 1988-10-18 1997-11-05 ヤマハ 株式会社 コンピュータシステム
JPH0769824B2 (ja) 1988-11-11 1995-07-31 株式会社日立製作所 複数命令同時処理方式
US5058451A (en) * 1988-11-11 1991-10-22 Kabushiki Kaisha Kobe Seiko Sho Control lever apparatus and actuator operation apparatus
KR920006613B1 (ko) * 1988-12-01 1992-08-10 재단법인한국전자통신연구소 파이프라인으로 동작하는 프로세서의 명령어 페취 유니트
GB8828817D0 (en) * 1988-12-09 1989-01-18 Int Computers Ltd Data processing apparatus
IL92605A0 (en) * 1988-12-19 1990-08-31 Bull Hn Information Syst Production line method and apparatus for high performance instruction execution
JPH0769811B2 (ja) * 1988-12-21 1995-07-31 松下電器産業株式会社 データ処理装置
US5148533A (en) 1989-01-05 1992-09-15 Bull Hn Information Systems Inc. Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units
US5125092A (en) 1989-01-09 1992-06-23 International Business Machines Corporation Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes
JP2736092B2 (ja) 1989-01-10 1998-04-02 株式会社東芝 バッファ装置
US5075840A (en) * 1989-01-13 1991-12-24 International Business Machines Corporation Tightly coupled multiprocessor instruction synchronization
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
US5222223A (en) 1989-02-03 1993-06-22 Digital Equipment Corporation Method and apparatus for ordering and queueing multiple memory requests
US4985825A (en) * 1989-02-03 1991-01-15 Digital Equipment Corporation System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer
US5125083A (en) 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5109495A (en) * 1989-02-03 1992-04-28 Digital Equipment Corp. Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor
US5142633A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Preprocessing implied specifiers in a pipelined processor
US5167026A (en) 1989-02-03 1992-11-24 Digital Equipment Corporation Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5133074A (en) 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
US5226166A (en) 1989-02-10 1993-07-06 Mitsubishi Denki K.K. Parallel operation processor with second command unit
US5293500A (en) * 1989-02-10 1994-03-08 Mitsubishi Denki K.K. Parallel processing method and apparatus
JPH0630063B2 (ja) * 1989-02-17 1994-04-20 株式会社東芝 マイクロプロセッサ
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
US5239633A (en) * 1989-03-24 1993-08-24 Mitsubishi Denki Kabushiki Kaisha Data processor executing memory indirect addressing and register indirect addressing
JPH02278337A (ja) 1989-04-19 1990-11-14 Nec Corp 命令キュー装置
US5119485A (en) 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
CN1168004C (zh) * 1989-05-17 2004-09-22 国际商业机器公司 在数据处理系统中提供容错环境和体系结构的装置
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5072364A (en) 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
JPH0314025A (ja) * 1989-06-13 1991-01-22 Nec Corp 命令実行制御方式
JP2550213B2 (ja) 1989-07-07 1996-11-06 株式会社日立製作所 並列処理装置および並列処理方法
JP2505887B2 (ja) * 1989-07-14 1996-06-12 富士通株式会社 命令処理システム
JP2682217B2 (ja) * 1989-08-28 1997-11-26 日本電気株式会社 マイクロプロセッサ
US5317734A (en) * 1989-08-29 1994-05-31 North American Philips Corporation Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies
JPH07120284B2 (ja) * 1989-09-04 1995-12-20 三菱電機株式会社 データ処理装置
US5303382A (en) * 1989-09-21 1994-04-12 Digital Equipment Corporation Arbiter with programmable dynamic request prioritization
JPH03137729A (ja) 1989-10-23 1991-06-12 Hokuriku Nippon Denki Software Kk 先行制御方式
JPH03147134A (ja) 1989-11-02 1991-06-24 Oki Electric Ind Co Ltd 命令シーケンス制御装置
US5179530A (en) 1989-11-03 1993-01-12 Zoran Corporation Architecture for integrated concurrent vector signal processor
US5226125A (en) 1989-11-17 1993-07-06 Keith Balmer Switch matrix having integrated crosspoint logic and method of operation
DE68928980T2 (de) 1989-11-17 1999-08-19 Texas Instruments Inc. Multiprozessor mit Koordinatenschalter zwischen Prozessoren und Speichern
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JPH03186928A (ja) * 1989-12-16 1991-08-14 Mitsubishi Electric Corp データ処理装置
US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
US5197130A (en) 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
JPH061463B2 (ja) 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
US5251306A (en) 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
US5222240A (en) 1990-02-14 1993-06-22 Intel Corporation Method and apparatus for delaying writing back the results of instructions to a processor
US5241636A (en) 1990-02-14 1993-08-31 Intel Corporation Method for parallel instruction execution in a computer
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5185872A (en) * 1990-02-28 1993-02-09 Intel Corporation System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy
US5120083A (en) 1990-03-19 1992-06-09 Henkels & Mccoy, Inc. Expansion joint for conduit for cables
JP2818249B2 (ja) 1990-03-30 1998-10-30 株式会社東芝 電子計算機
US5333280A (en) * 1990-04-06 1994-07-26 Nec Corporation Parallel pipelined instruction processing system for very long instruction word
IT1247640B (it) 1990-04-26 1994-12-28 St Microelectronics Srl Operazioni booleane tra due qualsiasi bit di due qualsiasi registri
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
US5214763A (en) 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
EP0457403B1 (en) * 1990-05-18 1998-01-21 Koninklijke Philips Electronics N.V. Multilevel instruction cache and method for using said cache
US5249286A (en) 1990-05-29 1993-09-28 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
CA2038264C (en) * 1990-06-26 1995-06-27 Richard James Eickemeyer In-memory preprocessor for a scalable compound instruction set machine processor
US5197132A (en) * 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
CA2045773A1 (en) 1990-06-29 1991-12-30 Compaq Computer Corporation Byte-compare operation for high-performance processor
US5155843A (en) * 1990-06-29 1992-10-13 Digital Equipment Corporation Error transition mode for multi-processor system
EP0468831B1 (en) 1990-06-29 1997-10-15 Digital Equipment Corporation Bus protocol for write-back cache processor
EP0463965B1 (en) * 1990-06-29 1998-09-09 Digital Equipment Corporation Branch prediction unit for high-performance processor
JPH0475139A (ja) * 1990-07-18 1992-03-10 Toshiba Corp ループ並列化装置
JPH0814492B2 (ja) * 1990-09-21 1996-02-14 日本航空電子工業株式会社 光ファイバジャイロ
US5301340A (en) * 1990-10-31 1994-04-05 International Business Machines Corporation IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle
US5222244A (en) 1990-12-20 1993-06-22 Intel Corporation Method of modifying a microinstruction with operands specified by an instruction held in an alias register
USH1291H (en) 1990-12-20 1994-02-01 Hinton Glenn J Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5261071A (en) 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5488729A (en) 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US5355457A (en) 1991-05-21 1994-10-11 Motorola, Inc. Data processor for performing simultaneous instruction retirement and backtracking
US5630157A (en) 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5278963A (en) * 1991-06-21 1994-01-11 International Business Machines Corporation Pretranslation of virtual addresses prior to page crossing
US5440752A (en) 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5826055A (en) 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
EP0547240B1 (en) 1991-07-08 2000-01-12 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
ATE164463T1 (de) 1991-07-08 1998-04-15 Seiko Epson Corp Single-chip seitendrucker-steuerschaltung
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
EP1526446A3 (en) 1991-07-08 2007-04-04 Seiko Epson Corporation Extensible RISC microprocessor architecture
US5345569A (en) 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
GB2260628A (en) 1991-10-11 1993-04-21 Intel Corp Line buffer for cache memory
JPH0820949B2 (ja) * 1991-11-26 1996-03-04 松下電器産業株式会社 情報処理装置
US5285527A (en) * 1991-12-11 1994-02-08 Northern Telecom Limited Predictive historical cache memory
US5617554A (en) 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
US5398330A (en) * 1992-03-05 1995-03-14 Seiko Epson Corporation Register file backup queue
JPH07504773A (ja) 1992-03-18 1995-05-25 セイコーエプソン株式会社 マルチ幅のメモリ・サブシステムをサポートするためのシステム並びに方法
US5371684A (en) 1992-03-31 1994-12-06 Seiko Epson Corporation Semiconductor floor plan for a register renaming circuit
EP0636256B1 (en) 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
JP3137729B2 (ja) 1992-04-09 2001-02-26 本田技研工業株式会社 ガバリ部品の製造方法
EP0638183B1 (en) 1992-05-01 1997-03-05 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
US5619668A (en) 1992-08-10 1997-04-08 Intel Corporation Apparatus for register bypassing in a microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5524225A (en) 1992-12-18 1996-06-04 Advanced Micro Devices Inc. Cache system and method for providing software controlled writeback
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp., Tokio/Tokyo System und Verfahren zur Änderung der Namen von Registern
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5627984A (en) 1993-03-31 1997-05-06 Intel Corporation Apparatus and method for entry allocation for a buffer resource utilizing an internal two cycle pipeline
US5577217A (en) 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
KR100310581B1 (ko) 1993-05-14 2001-12-17 피터 엔. 데트킨 분기목표버퍼의추측기록메카니즘
JPH0728695A (ja) 1993-07-08 1995-01-31 Nec Corp メモリコントローラ
US5446912A (en) * 1993-09-30 1995-08-29 Intel Corporation Partial width stalls within register alias table
US5613132A (en) * 1993-09-30 1997-03-18 Intel Corporation Integer and floating point register alias table within processor device
US5630149A (en) 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
DE69429061T2 (de) 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5689672A (en) 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
JP3218524B2 (ja) 1993-12-22 2001-10-15 村田機械株式会社 ワークホルダーのはみ出し検出装置
US5574935A (en) 1993-12-29 1996-11-12 Intel Corporation Superscalar processor with a multi-port reorder buffer
US5630075A (en) 1993-12-30 1997-05-13 Intel Corporation Write combining buffer for sequentially addressed partial line operations originating from a single instruction
US5452426A (en) 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US5619664A (en) 1994-01-04 1997-04-08 Intel Corporation Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms
US5627985A (en) 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5604877A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5577200A (en) 1994-02-28 1996-11-19 Intel Corporation Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
US5625788A (en) 1994-03-01 1997-04-29 Intel Corporation Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto
US5630083A (en) 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5564056A (en) 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
US5608885A (en) * 1994-03-01 1997-03-04 Intel Corporation Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions
US5586278A (en) 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US5623628A (en) 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
US5394351A (en) * 1994-03-11 1995-02-28 Nexgen, Inc. Optimized binary adder and comparator having an implicit constant for an input
US5574927A (en) * 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5490280A (en) * 1994-03-31 1996-02-06 Intel Corporation Apparatus and method for entry allocation for a resource buffer
US5615126A (en) * 1994-08-24 1997-03-25 Lsi Logic Corporation High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing
US5819101A (en) 1994-12-02 1998-10-06 Intel Corporation Method for packing a plurality of packed data elements in response to a pack instruction
CN101211255B (zh) 1994-12-02 2012-07-04 英特尔公司 对复合操作数进行压缩操作的处理器、设备和计算系统
US5666494A (en) 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US5745375A (en) 1995-09-29 1998-04-28 Intel Corporation Apparatus and method for controlling power usage
US5778210A (en) * 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US5961129A (en) * 1997-02-07 1999-10-05 Post; Peter G. Quick-Release interlocking frame assembly for interchangeably mounting operative sports devices to a boot sole
US6418529B1 (en) 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
JP3147134U (ja) 2008-09-17 2008-12-18 洋 吉迫 プランター

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3346851A (en) * 1964-07-08 1967-10-10 Control Data Corp Simultaneous multiprocessing computer system
US3771138A (en) * 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
GB2011682A (en) * 1977-12-30 1979-07-11 Honeywell Inf Systems Instruction buffer in computer
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4296470A (en) * 1979-06-21 1981-10-20 International Business Machines Corp. Link register storage and restore system for use in an instruction pre-fetch micro-processor interrupt system
US4410939A (en) * 1979-07-17 1983-10-18 Matsushita Electric Industrial Co. Ltd. System for program interrupt processing with quasi-stack of register-sets
US4476525A (en) * 1980-08-28 1984-10-09 Nec Corporation Pipeline-controlled data processing system capable of performing a plurality of instructions simultaneously
US4459657A (en) * 1980-09-24 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system having re-entrant function for subroutines
US4434641A (en) * 1982-03-11 1984-03-06 Ball Corporation Buckle resistance for metal container closures
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
EP0171595A2 (en) * 1984-08-13 1986-02-19 International Business Machines Corporation Floating point arithmetic unit
FR2575564A1 (fr) * 1984-12-27 1986-07-04 Sony Corp Microprocesseur a architecture facilitant la liaison avec des dispositifs peripheriques
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
US4752873A (en) * 1985-05-22 1988-06-21 Hitachi Vlsi Eng. Corp. Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution
US4924376A (en) * 1985-12-26 1990-05-08 Nec Corporation System for dynamically adjusting the accumulation of instructions in an instruction code prefetched pipelined computer
US4858105A (en) * 1986-03-26 1989-08-15 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4901228A (en) * 1986-07-17 1990-02-13 Mitsubishi Denki K.K. Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US4942525A (en) * 1986-11-21 1990-07-17 Hitachi, Ltd. Data processor for concurrent executing of instructions by plural execution units
US5003462A (en) * 1988-05-31 1991-03-26 International Business Machines Corporation Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means
EP0354585A2 (en) * 1988-08-11 1990-02-14 Kabushiki Kaisha Toshiba Instruction pipeline microprocessor
EP0368332A2 (en) * 1988-11-11 1990-05-16 Hitachi, Ltd. Pipeline data processor
EP0419105A2 (en) * 1989-09-21 1991-03-27 Texas Instruments Incorporated Integrated circuit having an embedded digital signal processor
EP0426393A2 (en) * 1989-11-01 1991-05-08 Fujitsu Limited Instructing method and execution system
EP0479390A2 (en) * 1990-10-05 1992-04-08 Koninklijke Philips Electronics N.V. Processing device including a memory circuit and a group of functional units

Non-Patent Citations (18)

* Cited by examiner, † Cited by third party
Title
A 80 Mflops 64 BIT Microprocessor For Parallel Computer 1991 IEEE. *
A 80 Mflops 64-BIT Microprocessor For Parallel Computer 1991 IEEE.
Colwell et al., A VLIW Architecture for a Trace Scheduling Compiler, Proceedings 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 5 8, 1987, Ca US. *
Colwell et al., A VLIW Architecture for a Trace Scheduling Compiler, Proceedings 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 5-8, 1987, Ca US.
COMPUTER DESIGN, vol.28, no.9, 1 May 1989, Littleton, Massachussetts, U.S., pp 86-99, Andrews, Distinctions Blur Between DSP Solutions *
ELECTRO CONFERENCE RECORD, vol.14, 11 April 1989, Los Angeles, U.S. pp 511-519, Jelemensky, New Microcomputer Features Advanced Hardware for Real-Time Control Applications *
IBM Second Generation RISC Machine Organization 1990 IEEE. *
IBM Second-Generation RISC Machine Organization 1990 IEEE.
IBM Technical Disclosure Bulletin, Overlap of Store Multiple Operation with Succeeding Operations Through Second Set of General Purpose Registers , vol. 28, No. 6, Nov. 1989, NY, US, pp. 2727 2728. *
IBM Technical Disclosure Bulletin, Overlap of Store Multiple Operation with Succeeding Operations Through Second Set of General Purpose Registers, vol. 28, No. 6, Nov. 1989, NY, US, pp. 2727-2728.
IEEE MICRO, vol. 9, no. 2, April 1989, Los Alamitos, CA, U.S., pp 26-38, Charles Melear, Motorola, Inc., The Design of the 88000 RISC Family *
IEEE TRANSACTIONS ON COMPUTERS, vol.37, no.5, May 1988, New York, U.S., pp 562-573, J.E. Smith, A.R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors *
J. Hennessy & D. Patterson, Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, (in its entirety) *
Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991 (in its entirety) *
PATENT ABSTRACTS OF JAPAN, vol.010, no.089, April 1986, JP-A-60225943 (Hitachi Seisakusho K K) 11 November 1985 *
R. Weiss, Third-Generation RISC Processors, On Special Report, March 30, 1992, pp 96-108 *
The i1960CA Superscalar Implementation Of The B0960 Architecture 1990 IEEE. *
V.Popescu, M.Schultz, J.Spracklen, G.Gibson, B.Lightner & D. Isaman, The Metaflow Architecture, Metaflow Technologies, Inc., June, 1991 *

Cited By (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
US6499123B1 (en) 1989-02-24 2002-12-24 Advanced Micro Devices, Inc. Method and apparatus for debugging an integrated circuit
US6212629B1 (en) 1989-02-24 2001-04-03 Advanced Micro Devices, Inc. Method and apparatus for executing string instructions
US5682492A (en) * 1989-02-24 1997-10-28 Advanced Micro Devices, Inc. Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts
US5781753A (en) * 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
US6272619B1 (en) * 1991-07-08 2001-08-07 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6647485B2 (en) 1991-07-08 2003-11-11 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6128723A (en) * 1991-07-08 2000-10-03 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7739482B2 (en) 1991-07-08 2010-06-15 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7721070B2 (en) 1991-07-08 2010-05-18 Le Trong Nguyen High-performance, superscalar-based computer system with out-of-order instruction execution
US7685402B2 (en) 1991-07-08 2010-03-23 Sanjiv Garg RISC microprocessor architecture implementing multiple typed register sets
US20040054872A1 (en) * 1991-07-08 2004-03-18 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order intstruction execution
US20030056086A1 (en) * 1991-07-08 2003-03-20 Le Trong Nguyen High-performance, superscalar-based computer system with out-of-order instruction execution
US20040093483A1 (en) * 1991-07-08 2004-05-13 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US7487333B2 (en) 1991-07-08 2009-02-03 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US20040093485A1 (en) * 1991-07-08 2004-05-13 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US20040093482A1 (en) * 1991-07-08 2004-05-13 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6915412B2 (en) 1991-07-08 2005-07-05 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7941636B2 (en) 1991-07-08 2011-05-10 Intellectual Venture Funding Llc RISC microprocessor architecture implementing multiple typed register sets
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US6934829B2 (en) * 1991-07-08 2005-08-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6986024B2 (en) 1991-07-08 2006-01-10 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6038654A (en) * 1991-07-08 2000-03-14 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US6256720B1 (en) * 1991-07-08 2001-07-03 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US6092181A (en) * 1991-07-08 2000-07-18 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7162610B2 (en) 1991-07-08 2007-01-09 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6101594A (en) * 1991-07-08 2000-08-08 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6959375B2 (en) 1991-07-08 2005-10-25 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US20030079113A1 (en) * 1991-07-08 2003-04-24 Nguyen Le Trong High-performance, superscalar-based computer system with out-of-order instruction execution
US6941447B2 (en) 1991-07-08 2005-09-06 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6948052B2 (en) 1991-07-08 2005-09-20 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7343473B2 (en) 1992-03-31 2008-03-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US6782521B2 (en) 1992-03-31 2004-08-24 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US7174525B2 (en) 1992-03-31 2007-02-06 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US6083274A (en) * 1992-03-31 2000-07-04 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an integrated circuit chip
US6263423B1 (en) 1992-03-31 2001-07-17 Seiko Epson Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US5983334A (en) * 1992-03-31 1999-11-09 Seiko Epson Corporation Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions
US20070113214A1 (en) * 1992-03-31 2007-05-17 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US7802074B2 (en) 1992-03-31 2010-09-21 Sanjiv Garg Superscalar RISC instruction scheduling
US20040243961A1 (en) * 1992-03-31 2004-12-02 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US6954847B2 (en) 1992-03-31 2005-10-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US6401232B1 (en) 1992-03-31 2002-06-04 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US20030084270A1 (en) * 1992-03-31 2003-05-01 Transmeta Corp. System and method for translating non-native instructions to native instructions for processing on a host processor
US20020129324A1 (en) * 1992-03-31 2002-09-12 Iadonato Kevin R. Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US20080162880A1 (en) * 1992-03-31 2008-07-03 Transmeta Corporation System and Method for Translating Non-Native Instructions to Native Instructions for Processing on a Host Processor
US7555738B2 (en) 1992-03-31 2009-06-30 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US5734584A (en) * 1992-03-31 1998-03-31 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an integrated circuit chip
US7664935B2 (en) 1992-03-31 2010-02-16 Brett Coon System and method for translating non-native instructions to native instructions for processing on a host processor
US5831871A (en) * 1992-03-31 1998-11-03 Seiko Epson Corporation Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
US7958337B2 (en) 1992-05-01 2011-06-07 Seiko Epson Corporation System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
US7934078B2 (en) 1992-05-01 2011-04-26 Seiko Epson Corporation System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
US7376783B2 (en) 1992-09-18 2008-05-20 Renesas Technology Corp. Processor system using synchronous dynamic memory
US20040143700A1 (en) * 1992-09-18 2004-07-22 Kunio Uchiyama Processor system using synchronous dynamic memory
US6697908B2 (en) * 1992-09-18 2004-02-24 Renesas Technology Corporation Processor system using synchronous dynamic memory
US20070061537A1 (en) * 1992-09-18 2007-03-15 Kunio Uchiyama Processor system using synchronous dynamic memory
US7143230B2 (en) 1992-09-18 2006-11-28 Renesas Technology Corp. Processor system using synchronous dynamic memory
US20080229004A1 (en) * 1992-09-18 2008-09-18 Kunio Uchiyama Processor system using synchronous dynamic memory
US8234441B2 (en) 1992-09-18 2012-07-31 Renesas Electronics Corporation Processor system using synchronous dynamic memory
US7904641B2 (en) 1992-09-18 2011-03-08 Renesas Technology Corporation Processor system using synchronous dynamic memory
US6957320B2 (en) 1992-09-29 2005-10-18 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7447876B2 (en) 1992-09-29 2008-11-04 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US20030056089A1 (en) * 1992-09-29 2003-03-20 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US8019975B2 (en) 1992-09-29 2011-09-13 Seiko-Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7000097B2 (en) 1992-09-29 2006-02-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US20070101106A1 (en) * 1992-09-29 2007-05-03 Senter Cheryl D System and method for handling load and/or store operations in a superscalar microprocessor
US6434693B1 (en) 1992-09-29 2002-08-13 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7861069B2 (en) 1992-09-29 2010-12-28 Seiko-Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7844797B2 (en) 1992-09-29 2010-11-30 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US20050283591A1 (en) * 1992-09-29 2005-12-22 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US20090217001A1 (en) * 1992-09-29 2009-08-27 Seiko Epson Corporation System and Method for Handling Load and/or Store Operations in a Superscalar Microprocessor
US20040128487A1 (en) * 1992-09-29 2004-07-01 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6230254B1 (en) 1992-09-29 2001-05-08 Seiko Epson Corporation System and method for handling load and/or store operators in a superscalar microprocessor
US20020188829A1 (en) * 1992-09-29 2002-12-12 Senter Cheryl D. System and method for handling load and/or store operations in a superscalar microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6965987B2 (en) 1992-09-29 2005-11-15 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7979678B2 (en) 1992-12-31 2011-07-12 Seiko Epson Corporation System and method for register renaming
US8074052B2 (en) 1992-12-31 2011-12-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5794027A (en) * 1993-07-01 1998-08-11 International Business Machines Corporation Method and apparatus for managing the execution of instructons with proximate successive branches in a cache-based data processing system
US5956753A (en) * 1993-12-30 1999-09-21 Intel Corporation Method and apparatus for handling speculative memory access operations
US5724536A (en) * 1994-01-04 1998-03-03 Intel Corporation Method and apparatus for blocking execution of and storing load operations during their execution
US6092183A (en) * 1994-03-16 2000-07-18 Hitachi, Ltd. Data processor for processing a complex instruction by dividing it into executing units
US5778434A (en) * 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
US6173369B1 (en) 1995-06-07 2001-01-09 Seiko Epson Corporation Computer system for processing multiple requests and out of order returns using a request queue
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US5867684A (en) * 1995-09-11 1999-02-02 International Business Machines Corporation Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction
US5897665A (en) * 1995-12-15 1999-04-27 Intel Corporation Register addressing for register-register architectures used for microprocessors and microcontrollers
US5930490A (en) * 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US20040172522A1 (en) * 1996-01-31 2004-09-02 Prasenjit Biswas Floating point unit pipeline synchronized with processor pipeline
US7162616B2 (en) * 1996-01-31 2007-01-09 Renesas Technology America, Inc. Floating point unit pipeline synchronized with processor pipeline
US5715425A (en) * 1996-02-22 1998-02-03 Sun Microsystems, Inc. Apparatus and method for prefetching data into an external cache
US5815688A (en) * 1996-10-09 1998-09-29 Hewlett-Packard Company Verification of accesses in a functional model of a speculative out-of-order computer system
US5838941A (en) * 1996-12-30 1998-11-17 Intel Corporation Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
US6195746B1 (en) 1997-01-31 2001-02-27 International Business Machines Corporation Dynamically typed register architecture
GB2337142B (en) * 1997-02-21 2002-04-17 Richard Byron Wilmot Method and apparatus for forwarding of operands in a computer system
WO1998037485A1 (en) * 1997-02-21 1998-08-27 Richard Byron Wilmot Method and apparatus for forwarding of operands in a computer system
GB2337142A (en) * 1997-02-21 1999-11-10 Richard Byron Wilmot Method and apparatus for forwarding of operands in a computer system
US6799269B2 (en) * 1997-08-01 2004-09-28 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US6249857B1 (en) * 1997-10-20 2001-06-19 Motorola, Inc. Apparatus using a multiple instruction register logarithm based processor
US6112293A (en) * 1997-11-17 2000-08-29 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result
WO1999026132A3 (en) * 1997-11-17 1999-09-16 Advanced Micro Devices Inc Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions
WO1999026132A2 (en) * 1997-11-17 1999-05-27 Advanced Micro Devices, Inc. Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions
US6493790B1 (en) * 1998-01-30 2002-12-10 Sun Microsystems, Inc. Translation-lookaside buffer with current tracking reference circuit
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6266761B1 (en) * 1998-06-12 2001-07-24 International Business Machines Corporation Method and system in an information processing system for efficient maintenance of copies of values stored within registers
US6308262B1 (en) * 1998-09-30 2001-10-23 Intel Corporation System and method for efficient processing of instructions using control unit to select operations
US20080278169A1 (en) * 1999-01-28 2008-11-13 Halliburton Energy Services, Inc. Electromagnetic Wave Resistivity Tool Having a Tilted Antenna for Determining the Horizontal and Vertical Resistivities and Relative Dip Angle in Anisotropic Earth Formations
KR100930332B1 (ko) * 1999-12-17 2009-12-08 후지쯔 가부시끼가이샤 프로세서 및 그 제어 방법
US6754808B1 (en) * 2000-09-29 2004-06-22 Intel Corporation Valid bit generation and tracking in a pipelined processor
US7036000B2 (en) 2000-09-29 2006-04-25 Intel Corporation Valid bit generation and tracking in a pipelined processor
US20040210744A1 (en) * 2000-09-29 2004-10-21 Intel Corporation, A Delaware Corporation Valid bit generation and tracking in a pipelined processor
US7079133B2 (en) 2000-11-16 2006-07-18 S3 Graphics Co., Ltd. Superscalar 3D graphics engine
US20050195197A1 (en) * 2000-11-16 2005-09-08 Andrew Wolfe Superscalar 3D graphics engine
US20030093771A1 (en) * 2001-11-05 2003-05-15 Hajime Ogawa Debugging aid device, a compiling device, a debugging aid program, a compiling program, and a computer readable record medium therefor
US7237229B2 (en) * 2001-11-05 2007-06-26 Matsushita Electric Industrial Co., Ltd. Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration
US20090147599A1 (en) * 2002-07-29 2009-06-11 Vinod Lakhani Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table
US7911872B2 (en) * 2002-07-29 2011-03-22 Micron Technology, Inc. Column/row redundancy architecture using latches programmed from a look up table
US20060253686A1 (en) * 2005-03-08 2006-11-09 Nec Electronics Corporation Instruction prefetch apparatus and instruction prefetch method
US7685467B2 (en) * 2006-04-27 2010-03-23 Texas Instruments Incorporated Data system simulated event and matrix debug of pipelined processor
US20070294585A1 (en) * 2006-04-27 2007-12-20 Texas Instruments Incorporated Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment
US7823117B1 (en) * 2007-12-21 2010-10-26 Xilinx, Inc. Separating a high-level programming language program into hardware and software components
CN109614145A (zh) * 2018-10-18 2019-04-12 中国科学院计算技术研究所 一种处理器核心结构及数据访存方法
CN109614145B (zh) * 2018-10-18 2021-03-09 中国科学院计算技术研究所 一种处理器核心结构及数据访存方法
US11176055B1 (en) 2019-08-06 2021-11-16 Marvell Asia Pte, Ltd. Managing potential faults for speculative page table access
EP4172760A4 (en) * 2020-06-26 2024-07-24 Advanced Micro Devices Inc MACHINE FOR TRANSLATION OF COMMAND ADDRESSES AND COMMAND SUMMONS
US11243778B1 (en) * 2020-12-31 2022-02-08 Microsoft Technology Licensing, Llc Instruction dispatch for superscalar processors

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US6128723A (en) 2000-10-03
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US6959375B2 (en) 2005-10-25
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