IT1247640B - Operazioni booleane tra due qualsiasi bit di due qualsiasi registri - Google Patents

Operazioni booleane tra due qualsiasi bit di due qualsiasi registri

Info

Publication number
IT1247640B
IT1247640B IT08361790A IT8361790A IT1247640B IT 1247640 B IT1247640 B IT 1247640B IT 08361790 A IT08361790 A IT 08361790A IT 8361790 A IT8361790 A IT 8361790A IT 1247640 B IT1247640 B IT 1247640B
Authority
IT
Italy
Prior art keywords
registers
bits
boolean operations
boolean
operations
Prior art date
Application number
IT08361790A
Other languages
English (en)
Other versions
IT9083617A1 (it
IT9083617A0 (it
Inventor
Flavio Scarra
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT08361790A priority Critical patent/IT1247640B/it
Publication of IT9083617A0 publication Critical patent/IT9083617A0/it
Priority to EP91830167A priority patent/EP0454636B1/en
Priority to DE69130513T priority patent/DE69130513T2/de
Priority to JP3125538A priority patent/JPH04229322A/ja
Publication of IT9083617A1 publication Critical patent/IT9083617A1/it
Priority to US08/364,505 priority patent/US5657484A/en
Application granted granted Critical
Publication of IT1247640B publication Critical patent/IT1247640B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
IT08361790A 1990-04-26 1990-04-26 Operazioni booleane tra due qualsiasi bit di due qualsiasi registri IT1247640B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT08361790A IT1247640B (it) 1990-04-26 1990-04-26 Operazioni booleane tra due qualsiasi bit di due qualsiasi registri
EP91830167A EP0454636B1 (en) 1990-04-26 1991-04-24 Method for carrying out a boolean operation between any two bits of any two registers
DE69130513T DE69130513T2 (de) 1990-04-26 1991-04-24 Verfahren zur Durchführung boolescher Operationen zwischen zwei beliebigen Bits von zwei beliebigen Registern
JP3125538A JPH04229322A (ja) 1990-04-26 1991-04-26 任意の２個のレジスタの任意の２個のビット間のブール演算を行う方法
US08/364,505 US5657484A (en) 1990-04-26 1994-12-27 Method for carrying out a boolean operation between any two bits of any two registers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT08361790A IT1247640B (it) 1990-04-26 1990-04-26 Operazioni booleane tra due qualsiasi bit di due qualsiasi registri

Publications (3)

Publication Number Publication Date
IT9083617A0 IT9083617A0 (it) 1990-04-26
IT9083617A1 IT9083617A1 (it) 1991-10-26
IT1247640B true IT1247640B (it) 1994-12-28

Family

ID=11323206

Family Applications (1)

Application Number Title Priority Date Filing Date
IT08361790A IT1247640B (it) 1990-04-26 1990-04-26 Operazioni booleane tra due qualsiasi bit di due qualsiasi registri

Country Status (5)

Country Link
US (1) US5657484A (it)
EP (1) EP0454636B1 (it)
JP (1) JPH04229322A (it)
DE (1) DE69130513T2 (it)
IT (1) IT1247640B (it)

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US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
EP0636256B1 (en) 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
KR950701437A (ko) 1992-05-01 1995-03-23 요시오 야마자끼 슈퍼스칼라 마이크로프로세서에서의 명령어 회수를 위한 시스템 및 방법
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP3531166B2 (ja) 1992-12-31 2004-05-24 セイコーエプソン株式会社 レジスタ・リネーミングのシステム及び方法
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
GB2425912A (en) * 2005-05-04 2006-11-08 Psytechnics Ltd Packet filtering
CN107145334B (zh) * 2017-04-26 2020-10-09 龙芯中科技术有限公司 常量获取方法、装置、处理器及计算机可读存储介质

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US3611309A (en) * 1969-07-24 1971-10-05 Univ Iowa State Res Found Inc Logical processing system
JPS559742B2 (it) * 1974-06-20 1980-03-12
US4212076A (en) * 1976-09-24 1980-07-08 Giddings & Lewis, Inc. Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former
US4331893A (en) * 1976-09-24 1982-05-25 Giddings & Lewis, Inc. Boolean logic processor without accumulator output feedback
JPS5671154A (en) * 1979-11-15 1981-06-13 Nec Corp Information processing device
US4314349A (en) * 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
US4592005A (en) * 1982-07-06 1986-05-27 Sperry Corporation Masked arithmetic logic unit
US4621339A (en) * 1983-06-13 1986-11-04 Duke University SIMD machine using cube connected cycles network architecture for vector processing
US4716541A (en) * 1984-08-02 1987-12-29 Quatse Jesse T Boolean processor for a progammable controller
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JPS63239700A (ja) * 1987-03-27 1988-10-05 Ando Electric Co Ltd Ｒａｍとｐｒｏｍのデ−タ比較・判定回路
US5083267A (en) * 1987-05-01 1992-01-21 Hewlett-Packard Company Horizontal computer having register multiconnect for execution of an instruction loop with recurrance
JPH0648461B2 (ja) * 1987-07-09 1994-06-22 日本電気株式会社 マイクロプログラムの転送レジスタ指定方式
JP2583525B2 (ja) * 1987-09-30 1997-02-19 健 坂村 データ処理装置
US5133054A (en) * 1987-10-20 1992-07-21 Sharp Kabushiki Kaisha Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path
WO1989007297A1 (en) * 1988-01-27 1989-08-10 Oki Electric Industry Co., Ltd. Microcomputer and a method of testing the same
US5060143A (en) * 1988-08-10 1991-10-22 Bell Communications Research, Inc. System for string searching including parallel comparison of candidate data block-by-block
JP2633331B2 (ja) * 1988-10-24 1997-07-23 三菱電機株式会社 マイクロプロセッサ
US5060136A (en) * 1989-01-06 1991-10-22 International Business Machines Corp. Four-way associative cache with dlat and separately addressable arrays used for updating certain bits without reading them out first
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US5167029A (en) * 1989-12-13 1992-11-24 International Business Machines Corporation Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register

Also Published As

Publication number Publication date
IT9083617A1 (it) 1991-10-26
DE69130513T2 (de) 1999-04-15
JPH04229322A (ja) 1992-08-18
US5657484A (en) 1997-08-12
EP0454636B1 (en) 1998-11-25
IT9083617A0 (it) 1990-04-26
DE69130513D1 (de) 1999-01-07
EP0454636A1 (en) 1991-10-30

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429