TWI834682B - 模製直接接合且互連的堆疊 - Google Patents

模製直接接合且互連的堆疊 Download PDF

Info

Publication number
TWI834682B
TWI834682B TW108123487A TW108123487A TWI834682B TW I834682 B TWI834682 B TW I834682B TW 108123487 A TW108123487 A TW 108123487A TW 108123487 A TW108123487 A TW 108123487A TW I834682 B TWI834682 B TW I834682B
Authority
TW
Taiwan
Prior art keywords
substrate
die
bonding surface
circuit element
microelectronic
Prior art date
Application number
TW108123487A
Other languages
English (en)
Other versions
TW202006890A (zh
Inventor
桂蓮 高
賽普里恩 艾米卡 烏佐
傑瑞米 阿弗烈德 提爾
貝高森 哈巴
拉杰詡 卡特卡
Original Assignee
美商艾德亞半導體接合科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商艾德亞半導體接合科技有限公司 filed Critical 美商艾德亞半導體接合科技有限公司
Publication of TW202006890A publication Critical patent/TW202006890A/zh
Application granted granted Critical
Publication of TWI834682B publication Critical patent/TWI834682B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明係關於晶粒及/或晶圓，該些晶粒及/或晶圓以包括堆疊之各種配置而經堆疊且接合，且可覆蓋有模製物以便於處置、封裝以及類似操作。在各個實例中，該模製物可或多或少覆蓋一堆疊，以促進與該堆疊之裝置之連接性、增強熱管理等等。

Description

模製直接接合且互連的堆疊
以下描述關於積體電路（integrated circuit；「IC」）之處理。更特定而言，以下描述關於用於封裝晶粒或晶圓及其他微電子組件之技術。 ［優先權主張及相關申請案之交叉參考］
本申請案主張2019年7月2日申請之美國非臨時申請案第16/460,068號及2018年7月6日申請之美國臨時申請案第62/694,845號之權益，該些申請案以全文引用之方式併入本文中。
微電子元件通常包含半導體材料（諸如，矽或砷化鎵）之薄厚塊，其通常稱為半導體晶圓。晶圓可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個整合式晶片或晶粒。從晶圓分離之晶粒通常作為單獨的經預封裝單元提供。在一些封裝設計中，晶粒經安裝至基板或晶片載體，該基板或晶片載體繼而經安裝在諸如印刷電路板（printed circuit board；PCB）之電路板上。舉例而言，許多晶粒經設置於適合於表面黏著的封裝中。
經封裝半導體晶粒亦可以「堆疊」配置提供，其中一個封裝經設置於（例如）電路板或其他載體上，且另一封裝經黏著在第一封裝之頂部上。該些配置可允許數個不同晶粒或裝置經黏著於電路板上之單個佔據面積內，且可藉由在封裝之間設置短互連來進一步促成高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於將在晶粒封裝之堆疊內達成的互連，用於機械及電性連接之互連結構可設置於每一晶粒封裝（除了最頂部封裝以外）之兩側（例如，面）上。
另外，晶粒或晶圓可以三維配置經堆疊作為各種微電子封裝方案之部分。此可包括在較大基底晶粒、裝置、晶圓、基板或類似者上堆疊一或多個晶粒、裝置及/或晶圓之層，以垂直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。
晶粒或晶圓可使用各種接合技術（其包括直接介電接合、非黏合性技術（諸如ZiBond®）或混合接合技術（諸如DBI®），二者均購自英帆薩斯邦德科技有限公司（Invensas Bonding Technologies, Inc.）（前Ziptronix公司）、Xperi公司）以堆疊配置來接合。直接介電接合技術包含自發性共價接合過程，當兩個所製備介電性表面接合在一起時，該自發性共價接合過程在環境條件下進行，而無需黏合劑或介入材料，且混合接合技術添加相應晶粒或晶圓之接合表面處之相應金屬接合墊之金屬對金屬接合，而亦無需介入材料，從而形成統一傳導結構（見例如，美國專利第6,864,585號及第7,485,968號，該些專利以全文引用之方式併如本文中）。金屬接合墊之加熱退火可用於加強金屬對金屬接合。
接合晶粒或晶圓之相應配合表面通常包括嵌入式傳導互連結構（其可為金屬）或類似者。在一些實例中，接合表面經配置且對準使得來自相應表面之傳導互連結構在接合期間結合。結合的互連結構在堆疊晶粒或晶圓之間形成連續傳導互連（用於信號、功率等）。
實施堆疊晶粒及晶圓配置可存在多種挑戰。當使用直接接合技術或混合接合技術來接合堆疊晶粒或晶圓時，通常需要待接合之晶粒或晶圓的表面極平坦、平滑且清潔。舉例而言，大體上，該些表面應具有極低的表面拓樸偏差（亦即，奈米尺度偏差），使得該些表面可緊密配合以形成持續接合。
雙側晶粒或晶圓可經形成及製備用於堆疊及接合，其中晶粒或晶圓之兩側將接合至其他基板、晶圓或晶粒，其諸如具有多個晶粒對晶粒或晶粒對晶圓應用。製備晶粒或晶圓之兩側包括：對兩個表面進行表面處理以符合介電質粗糙度規範及金屬層（例如銅等）凹進規範。混合表面可使用化學機械拋光（chemical mechanical polishing；CMP）製程、電漿製程、濕式及乾式清潔法或類似者來製備以與另一晶粒、晶圓或其他基板接合。
可能需要封裝呈各種組態之堆疊及接合晶粒及晶圓以用於連接性多樣性、性能優化及增強熱管理。
本發明的多種態樣中的第一態樣為一種微電子組件，其包含：第一基板，其具有第一接合表面及嵌入至該第一基板中之第一微電子電路元件，該第一基板之該第一電路元件之一部分在該第一基板之該第一接合表面處暴露；第二基板，其具有第一接合表面及嵌入至該第二基板中之第一微電子電路元件，該第二基板之該第一電路元件之一部分在該第二基板之該第一接合表面處暴露，該第二基板之該第一接合表面混合接合至該第一基板之該第一接合表面而無需黏合劑，使得該第二基板之該第一電路元件電耦接至該第一基板之該第一電路元件，其中該第一基板之側邊緣相對於該第二基板之側邊緣未對準；以及模製物，其覆蓋至少該第二基板之前述側邊緣。
第一態樣之微電子組件進一步包含第一傳導通孔，該第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板。
在第一態樣之微電子組件中，該第一基板包括與該第一接合表面相對之第二表面，且其中該第一傳導通孔延伸至該第一基板之該第二表面且提供從該第一基板之該第一接合表面至該第一基板之該第二表面之電連接性。
第一態樣之微電子組件進一步包含端子連接件，該端子連接件耦接至該第一基板之該第二表面且電耦接至該第一傳導通孔。
在第一態樣之微電子組件中，該第二基板包括與該第一接合表面相對之第二接合表面及嵌入至該第二基板中之第二微電子電路元件，該第二基板之該第二電路元件之一部分在該第二基板之該第二接合表面處暴露。
第一態樣之微電子組件進一步包含第二傳導通孔，該第二傳導通孔電耦接至該第二基板之該第一電路元件及該第二電路元件且至少部分地延伸穿過該第二基板，該第二傳導通孔提供從該第二基板之該第一接合表面至該第二基板之該第二接合表面之電連接性。
在第一態樣之微電子組件中，該第二傳導通孔提供從該第一基板之第二表面至該第二基板之該第二接合表面之電連接性，該第一基板之該第二表面與該第一基板之該第一接合表面相對。
第一態樣之微電子組件進一步包含第三基板，該第三基板具有第一接合表面及嵌入至該第三基板中之第一微電子電路元件，該第三基板之該第一電路元件之一部分在該第三基板之該第一接合表面處暴露，該第三基板之該第一接合表面接合至該第二基板之該第二接合表面，使得該第三基板之該第一電路元件電耦接至該第二基板之該第二電路元件。
在第一態樣之微電子組件中，該第三基板之側邊緣相對於該第二基板之前述側邊緣或該第一基板之前述側邊緣未對準。
在第一態樣之微電子組件中，該模製物覆蓋該第一基板之前述側邊緣、該第二基板之前述側邊緣及該第三基板之前述側邊緣。
在第一態樣之微電子組件中，該模製物覆蓋該第二基板之前述側邊緣及該第三基板之前述側邊緣，而不覆蓋該第一基板之前述側邊緣。
在第一態樣之微電子組件中，該模製物覆蓋與該第三基板之該第一接合表面相對之該第三基板之第二表面。
在第一態樣之微電子組件中，該模製物覆蓋與該第一基板之該第一接合表面相對之該第二基板之第二表面。
本發明的多種態樣中的第二態樣為一種微電子組件，其包含複數個第一態樣之微電子組件。
在第二態樣之微電子組件中，第一基板、第二基板及第三基板之佔據面積為非均一的，且其中自該第一基板延伸至該第三基板之模製物之外部側邊緣為平面的。
本發明的多種態樣中的第三態樣為一種微電子組件，其包含：複數個模製微電子元件堆疊，每個堆疊包含：第一基板，其具有第一接合表面及嵌入至該第一基板中之第一微電子電路元件，該第一基板之該第一電路元件之一部分在該第一基板之該第一接合表面處暴露，且第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板；第二基板，其具有第一接合表面及嵌入至該第二基板中之第一微電子電路元件，該第二基板之該第一電路元件之一部分在該第二基板之該第一接合表面處暴露，且第二傳導通孔電耦接至該第二基板之該第一電路元件且至少部分地延伸穿過該第二基板，該第二基板之該第一接合表面混合接合至該第一基板之該第一接合表面而無需黏合劑，使得該第二基板之該第一電路元件電耦接至該第一基板之該第一電路元件，其中該第一基板之側邊緣相對於該第二基板之側邊緣未對準；以及模製物，其覆蓋至少該第二基板之前述側邊緣。
在第三態樣之微電子組件中，該第一基板包括與該第一接合表面相對之第二表面，且其中該第一傳導通孔延伸至該第一基板之該第二表面且提供從該第一基板之該第一接合表面至該第一基板之該第二表面之電連接性。
在第三態樣之微電子組件中，該第二基板包括與該第一接合表面相對之第二接合表面及嵌入至該第二基板中之第二微電子電路元件，該第二基板之該第二電路元件之一部分在該第二基板之該第二接合表面處暴露，且其中該第二傳導通孔電耦接至該第二基板之該第二電路元件。
在第三態樣之微電子組件中，該第二基板之該第一接合表面及該第二接合表面中之至少一者在該第二基板之周界邊緣處包括有意的凹部。
在第三態樣之微電子組件中，該模製物包含未具有顆粒之第一低黏度化合物，該第一低黏度化合物滲透該第二基板之該周界邊緣處的該凹部，且具有顆粒之第二化合物覆蓋在該第一低黏度化合物上方。
第三態樣之微電子組件進一步包含層合物及/或插入件，且其中該複數個模製微電子元件堆疊混合接合至該層合物或該插入件而無需黏合劑或中介材料。
第三態樣之微電子組件進一步在該層合物之表面上及/或在該插入件之表面上包含至少一個線接合墊。
在第三態樣之微電子組件中，該層合物使用接線來耦接至該插入件，該接線耦接於該層合物之表面上之線接合墊處及該插入件之表面上之線接合墊處。
在第三態樣之微電子組件進一步包含非模製晶粒，該非模製晶粒在無黏合劑之情況下混合接合至該層合物及/或該插入件。
在第三態樣之微電子組件中，至少該第二基板包含固態記憶體裝置。
本發明的多種態樣中的第四態樣為一種形成微電子組件之方法，其包含：形成微電子堆疊，其包含：提供具有前側及背側之第一基板，該背側具有包含非傳導接合層之接合表面以及經暴露電性傳導第一電路元件，該第一基板具有第一傳導通孔，該第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板；提供具有前側及背側之第二基板，該前側包括非傳導接合層及經暴露電性傳導第一電路元件；藉由使該第一基板之該非傳導接合層與該第二基板之該非傳導接合層接觸來將該第二基板之該前側耦接至該第一基板之該背側，該第一基板之側邊緣相對於該第二基板之側邊緣未對準，且使該第一基板之該第一電路元件與該第二基板之該第一電路元件接觸；以及用模製物覆蓋至少該第二基板之前述側邊緣。
第四態樣之方法進一步包含用該模製物覆蓋該第二基板之該背側。
在第四態樣之方法中，該第二基板之該背側包括第二非傳導接合層及經暴露電性傳導第二電路元件，該第二基板具有第二傳導通孔，該第二傳導通孔電耦接該第二基板之該第一電路元件及該第二電路元件。
第四態樣之方法進一步包含：提供具有前側及背側之第三基板，該前側包括非傳導接合層及經暴露電性傳導第一電路元件；藉由使該第三基板之該非傳導接合層與該第二基板之該非傳導接合層接觸來將該第三基板之該前側耦接至該第二基板之該背側，該第三基板之側邊緣相對於該第二基板之側邊緣及/或該第一基板之側邊緣未對準，且使該第三基板之該第一電路元件與該第二基板之該第二電路元件接觸；以及用該模製物覆蓋該第三基板之前述側邊緣。
第四態樣之方法進一步包含在該第一基板之一周界處之該第一基板之該接合層處及/或該第二基板之一周界處之該第二基板之該接合層處形成一凹部，及在用該模製物覆蓋該第一基板之該些側邊緣及該第二基板之該些側邊緣之前，用一低黏度化合物填充至少該凹部。
第四態樣之方法進一步包含將該微電子堆疊混合接合至具有至少一個線接合接觸墊之半導體插入件。
第四態樣之方法進一步包含將該插入件耦接至具有第二線接合接觸墊之層合物，及用接線將該插入件之該至少一個線接合接觸墊接合至該層合物之該第二線接合接觸墊。
在第四態樣之方法中，形成該微電子組件包含形成複數個微電子堆疊。
本發明的多種態樣中的第五態樣為一種微電子組件，其包含：第一晶粒，其具有第一接合表面及嵌入至該第一晶粒中之第一微電子電路元件，該第一電路元件之一部分在該第一晶粒之該第一接合表面處暴露；以及第二晶粒，其具有第一接合表面及嵌入至該第二晶粒中之第一微電子電路元件，該第二晶粒之該第一電路元件之一部分在該第二晶粒之該第一接合表面處暴露，該第一晶粒之該第一接合表面混合接合至該第二晶粒之該第一接合表面，使該第一晶粒電耦接至該第二晶粒而無需黏合層，其中該第一晶粒之側邊緣包含比安置於該第二晶粒之側邊緣上之模製層薄的模製層。
本發明的多種態樣中的第六態樣為一種微電子組件，其包含：第一晶粒，其具有包含第一微電子電路元件之第一接合表面；第二晶粒，其具有包含第二微電子電路元件之第一接合表面；該第一晶粒之該第一接合表面混合接合至該第二晶粒之該第一接合表面，使該第一晶粒電耦接至該第二晶粒而無需黏合層；以及模製層，其安置於該第一晶粒之側邊緣及該第二晶粒之側邊緣上，其中該第一晶粒上的該模製層之厚度不同於該第二晶粒上的該模製層之厚度。
第六態樣之微電子組件進一步包含第一傳導通孔，該第一傳導通孔電耦接至該第一晶粒之該第一電路元件且至少部分地延伸穿過該第一晶粒。
在第六態樣之微電子組件中，該第一晶粒之該第一接合表面或該第二晶粒之該第一接合表面包含具有小於20微米之間距的複數個電路元件。
在第六態樣之微電子組件中，該第一晶粒之該第一接合表面或該第二晶粒之該第一接合表面包含具有小於1微米之間距的複數個電路元件。
概述
揭示代表性技術及裝置，其包括用於堆疊及接合晶粒及/或晶圓（包括混合接合晶粒與晶粒、晶粒與晶圓及晶圓與晶圓而無需黏合劑）之製程步驟。在各種具體實例中，晶粒及/或晶圓以包括堆疊之各種配置而經堆疊且接合，且可覆蓋有模製物以便於處置、封裝以及類似操作。在各個實例中，模製物可或多或少覆蓋一堆疊，以促進與該堆疊之裝置之連接性、增強熱管理等等。
參考電性及電子構件以及變化之載體論述各種實施方案及配置。雖然提及具體構件（即，晶粒、晶圓、積體電路（IC）晶片晶粒、基板等），但此不意欲為限制性的，而是為了易於論述及便於說明。參考晶圓、晶粒、基板或類似者論述之技術及裝置適用於任一類型或數目之電性構件、電路（例如，積體電路（IC）、混合電路、ASICS、記憶體裝置、處理器等）、構件之群組、被動元件、微機電系統（Micro-Electro Mechanical Systems；MEMS）構件、封裝式構件、結構（例如，晶圓、面板、板、PCB等）及類似者，其可經整合及耦接以彼此介接，與外部電路、系統、載體及類似者介接。這些不同構件、電路、群組、封裝、結構及類似者中之每一者可大體上稱作「微電子構件」。為簡單起見，除非另外指定，否則接合至另一構件之構件將在本文中稱作「晶粒」。 例示性具體實例
圖1為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖。在所展示之實例中，藉由堆疊且接合（例如，混合接合而無需黏合劑）複數個晶粒102（例如，所需任何數量之晶粒102）來形成堆疊100（或微電子組件100）。在一替代具體實例中，藉由堆疊且接合（例如，混合接合而無需黏合劑）複數個晶圓來形成堆疊100，該複數個晶圓隨後單體化（singulation）為圖1中所展示之晶粒102。在一實施方案中，如圖1中所示，晶粒102在堆疊100中可不完全對準。換言之，晶粒102之邊緣不精確排列，且自堆疊100之一個晶粒102至另一晶粒102存在一些誤差或未對準「e」。在各個實例中，未對準「e」可歸因於取放工具之準確度容限或類似者。
可使用各種技術形成晶粒102（或晶圓），以包括基底基板104及一或多個絕緣層或介電層106。舉例而言，圖1處所展示之晶粒102可表示雙側晶粒102，其在基底層104之兩個表面上具有絕緣層106。如圖1中亦展示，亦可包含晶粒102'，其可為單側或雙側主晶粒或主晶圓。單側晶粒102或102'可定位於堆疊100中作為頂部晶粒102、底部晶粒102或作為堆疊100中之任一其他晶粒102，在該任一其他晶粒中不需要與晶粒102之兩側之直接接合連接。除非另外規定，否則如本文中所使用之參考「晶粒102」包括單側及雙側晶粒及晶圓兩者。
基底基板104可包含矽、鍺、玻璃、石英、介電表面、直接或間接能隙半導體材料或層或另一合適的材料。絕緣層106沉積或形成於基板104上方，且可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、類金剛石材料、玻璃、陶瓷、玻璃陶瓷以及類似者。
晶粒102之接合表面108可包括傳導特徵110，諸如TSV、跡線、襯墊及互連結構，該些傳導特徵（例如）嵌入至絕緣層106中且經配置以使得在接合期間可視需要配合且結合來自相對裝置之相應接合表面108之傳導特徵110。結合的傳導特徵110可形成堆疊裝置之間的連續傳導互連（以用於信號、功率、接地等）。
鑲嵌製程（或類似者）可用以在絕緣層106中形成嵌入式傳導特徵110。傳導特徵110可包含金屬（例如，銅等）或其他傳導材料或材料組合，且包括結構、跡線、襯墊、圖案等等。在一些實例中，障壁層可在沉積傳導特徵110之材料之前經沉積於用於傳導特徵110之空腔中，使得障壁層安置於傳導特徵110與絕緣層106之間。障壁層可包含鉭層、鈦層、鎢層或具有其各種相應化合物或合金之其組合（例如，或另一傳導材料），以防止或減少傳導特徵110之材料擴散至絕緣層106中。在形成傳導特徵110後，裝置晶圓102（其包括絕緣層106及傳導特徵110）之經暴露表面可（例如，經由CMP）平面化以形成平坦接合表面108。
形成接合表面108包括對表面108進行表面處理以符合介電質粗糙度規範及金屬層（例如，銅等）凹進規範（若規定），從而製備用於混合接合之表面108。換言之，接合表面108經形成為儘可能平坦及平滑的，且具有極小（奈米尺度）表面拓樸偏差。各種習知製程（諸如化學機械拋光（CMP）、乾式或濕式蝕刻等等）可用於實現低表面粗糙度。此製程提供產生可靠接合之平坦且光滑的表面108。
部分地延伸至所製備表面108下方之介電基板106中之嵌入式傳導跡線112可用於貫穿晶粒102將傳導特徵110電耦接至所需構件。舉例而言，傳導特徵110可耦接至傳導（例如，銅）矽穿孔（through-silicon vias；TSV）114或類似者，該矽穿孔部分地或完全延伸穿過晶粒102以穿過晶粒102之厚度形成電連接。舉例而言，取決於晶粒102之厚度，在一些情況下，TSV 114可延伸約50微米。圖式展示晶粒102的實例，其具有傳導特徵110、跡線112及TSV 114之並不意欲為限制的各種配置。在各種具體實例中，傳導特徵110、跡線112及TSV 114中之一些可不存在於晶粒102（或晶圓）中，且在其他具體實例中，額外傳導特徵110、跡線112及TSV 114可存在，或其他電路構件以及類似者可存在。
晶粒102可（例如）在無黏合劑之情況下經混合接合至具有金屬襯墊110、跡線112及/或TSV 114之其他晶粒102，以在形成堆疊100時穿過晶粒102形成所需電連接。混合接合包括各晶粒102之相應絕緣層106之直接介電質對介電質接合（例如，ZIBOND®）而無需黏合劑或其他中介材料，以及各晶粒102之相應傳導特徵110之直接金屬對金屬接合（例如，DBI®）亦而無需中介材料。當在環境溫度下使相應接合表面108在一起時，介電質對介電質接合自發地進行。金屬對金屬接合（其可包括傳導特徵10之金屬之間的擴散）可在有壓力或無壓力之情況下憑藉加熱進行。
如圖1中所示，可（例如，經由傳導特徵110）自堆疊100之頂部晶粒102之頂部表面、（例如，經由傳導特徵110、跡線112及TSV 114）經過堆疊100之晶粒102（任何數目的晶粒102）且（例如，經由TSV 114）至堆疊100之底部晶粒102之底部表面建立電連接性。在圖1的實例中，傳導特徵110提供至堆疊100之頂部表面的連接性，且具有至少一個電耦接墊116之TSV 114提供至堆疊100之底部晶粒102之底部表面的連接性（在一些情況下，鈦層（圖中未示）或類似者可將TSV 114耦接至襯墊116）。在替代具體實例中，堆疊100之頂部表面及底部表面中的一者或兩者可不具有連接性，或與所展示不同的構件可提供至堆疊100之頂部表面或底部表面的連接性。舉例而言，在一些具體實例中，堆疊100可不包括堆疊100之頂部表面處之傳導特徵110，或頂部晶粒102中之TSV 114，或底部晶粒102中之TSV 114及襯墊116。
在一些實施方案中，TSV 114中之一或多者提供晶粒102之間的熱連接性。舉例而言，TSV可幫助將熱量自一些晶粒102耗散或傳輸至其他晶粒102及/或至外部環境。在實施方案中，TSV 114包含導熱材料，且可包括導熱障壁層（圖中未示）。在一些實例中，基於相關晶粒102之功能（例如，產熱），TSV 114可經大小設定以用於最佳熱耗散。
圖2為微電子組件200之橫截面剖面圖，該微電子組件包含晶粒102之多個堆疊100。在一些具體實例中，各堆疊100包括相同數量之晶粒102。在其他具體實例中，一些堆疊100可包括與組件200之其他堆疊100不同數量之晶粒102。在一實施方案中，如圖2中所示，晶粒102在堆疊100中不完全對準。換言之，晶粒102之邊緣在堆疊100內並不精確排列，且自晶粒102至晶粒102存在一些邊緣之誤差或未對準。在一些具體實例中，堆疊100自已如上文所論述經堆疊及接合之複數個晶圓中經單體化。
在一實施方案中，晶粒102'之底部集合包含用於堆疊100之主晶圓202。在實施方案中，晶粒102可堆疊至主晶圓202上，其隨後視需要在堆疊100之邊界處經單體化。在其他實施方案中，若存在，主晶圓202可在製程中之不同步驟處經單體化。
如圖2中所示，組件200之堆疊100中之一或多者可經覆蓋於包含密封體或類似者之模製物204中。在各種具體實例中，模製物204可包含高強度、高熱應力（高耐熱性）密封體材料，其亦可具有高熱耗散特徵。此外，模製物204可需要具有小於20之熱膨脹係數（coefficient of thermal expansion；CTE），以輔助控制翹曲。舉例而言，HITACHI®提供此類密封體或「環氧模製化合物」，其稱作「CEL」。其他相似產品亦可購得。在一個具體實例中，組件200覆蓋有模製物204，隨後組件200分割成多個堆疊100。單獨堆疊100可視需要覆蓋有額外密封體204。在其他具體實例中，堆疊100在堆疊100之形成後經模製，該堆疊之形成包括將單獨晶粒102堆疊且接合至堆疊100中或晶圓之單體化以形成晶粒102及堆疊100。舉例而言，模製物204可在晶粒102之單體化之前或之後經沉積。在任一情況下，模製物204可覆蓋晶粒102或所選晶粒102之整個堆疊100。舉例而言，在一具體實例中，主晶圓202（及晶粒102'）可不覆蓋有模製物204。此可歸因於製造製程或因為設計。
對於本文中所揭示之所有實施方案，模製物204可包含覆蓋在堆疊100之晶粒102中的一些或全部上方及/或圍繞其之單層密封體，或模製物204可包含相同或不同材料之密封體之多個層（例如，層合物）。此外，在一實施方案中，模製物204包含密封體內之顆粒，且模製物204具有進展之顆粒密度，即自在堆疊100之頂部或底部處低顆粒或無顆粒之狀態至在堆疊100之頂部或底部中之另一者處較高顆粒密度之狀態。在一個實例中，當存在時，顆粒可以不同密度存在於密封體之多個層中。在各種具體實例中，模製物204包含無機殼體或類似者。
在一些實例中，將模製物204添加至晶粒102之堆疊100及/或組件200向堆疊100或組件200提供最終封裝。堆疊解決方案使得易於處理期間之處置及組裝，以及應用中之部署。模製物204對晶粒102及堆疊100以及組件200及可封裝有晶粒102之任何離散構件提供保護。
在一實施方案中，如圖2處所示，堆疊100中之一或多者（或所有堆疊100）之頂部表面可不含模製物204。頂部晶粒102之裸頂部表面可用於堆疊100之頂部晶粒102與其他電路、裝置（例如，光學、射頻（radio frequency；RF）、類比、數位、邏輯、記憶或其他裝置）或（例如）包括額外晶粒102或組件200之類似者（例如，當傳導特徵110存在於頂部晶粒102之頂部表面處時）之進一步互連。替代地或額外地，頂部晶粒102之頂部表面可經覆蓋以增強熱耗散。舉例而言，熱量可自晶粒102更容易及有效地耗散而無需組件200之頂部晶粒102之頂部表面處的密封體204。在此類情況下，傳導特徵110（以及跡線112）可不存在於頂部晶粒102之頂部表面處。舉例而言，若TSV 114用於經由頂部表面幫助耗散熱量，則TSV可存在。
在一實施方案中，組件200包括組件200之表面（諸如，底部表面）處之一或多個電接觸或端子206。端子206可用於將組件電耦接至另一電路、裝置、印刷電路板（PCB）或類似者。如圖2中所示，端子206可經由襯墊116電耦接至組件200之堆疊100之晶粒102（諸如，最底部晶粒102）之TSV 114（或其他互連件）。舉例而言，組件200可包括自堆疊100中之一或多者之頂部晶粒102（例如，在一些情況下，頂部晶粒102之頂部表面）穿過堆疊100之晶粒102至端子206的電連接性。
在一些具體實例中，額外層、電路構件、通孔以及類似者亦可視需要併入至堆疊100及/或組件200中。在替代實施方案中，TSV 114可在一些晶粒102中及/或一些堆疊100中為可選的。
在一實施方案中，如圖3處所示，堆疊100中之一或多者（或所有堆疊100）之頂部表面可包括模製物204。在實施方案中，堆疊100及組件200之頂部表面處之模製物204在處置、組裝、部署等等期間保護堆疊100及組件200。在一具體實例中，堆疊100中之每一者分別覆蓋有模製物204，此包括堆疊100之頂部及側部。在一具體實例中，主晶圓202（及晶粒102'）可不覆蓋有模製物204。如圖3的實例中所示，在一些具體實例中，當不在晶粒102及組件200之頂部表面處形成電連接時，組件200之頂部晶粒102可不包括傳導特徵110（或跡線112及/或TSV 114）。舉例而言，當這些構件用於其他目的時（例如，當電路構件安置於上部絕緣層106上或內時，或類似者），這些構件可為可選的。
亦如圖3在的實例中所示，在一些應用中，晶粒102可具有構件之各種組態及配置。舉例而言，如圖3處所示，晶粒102"可包括TSV 114，該些TSV直接耦接至鄰近晶粒102上之傳導墊110以提供與相鄰接合晶粒102之連接性。舉例而言，TSV 114之末端表面可在晶粒102"之接合表面108處暴露，從而形成與相鄰晶粒102上之傳導墊110接合之接觸表面。在其他具體實例中，亦如圖3處所示，晶粒102"可包括接合表面處之傳導墊110，其中TSV 114直接耦接至傳導墊110。這些傳導墊110可接合至相鄰晶粒102上之傳導墊110（或其他傳導結構）。
在一實施方案中，如圖4及5所示，整個堆疊100可覆蓋有模製物204，此包括主晶圓202及晶粒102'。在實施方案中，主晶圓202可在密封步驟之前單體化為晶粒102'，從而有助於該主晶圓由模製物204覆蓋。多個晶粒102可經堆疊（以群組方式或一次一個地）至主晶粒102'上以形成堆疊100，該堆疊可隨後覆蓋有模製物204。替代地，在所有晶粒102經堆疊及接合至堆疊100中後，模製物204可應用於組件200。在任何情況下，模製物204可存在於堆疊100之側部上。此外，在替代具體實例中之模製步驟後，組件200之堆疊100可彼此分隔開。
如所示，圖4說明例示性組件200，其中組件200及堆疊100之頂部表面（亦即，背部）不含模製物204。在一具體實例中，模製物204可沉積於組件200上方，且隨後自堆疊100之頂部表面經移除。在各個實例中，模製物204可自堆疊100之頂部表面經移除以提供與頂部晶粒102之互連，以用於改良的熱耗散或類似者。圖5說明頂部表面（亦即，背部）覆蓋有模製物204的情況。
如圖6及7中所示，堆疊100之晶粒102可不為大小均一的（例如，尺寸、面積、佔據面積、厚度等）。具有不同佔據面積或厚度之晶粒102（例如）可經堆疊及接合以形成堆疊100。在無模製物204之情況下，非均一晶粒102之堆疊100呈現不均勻側邊緣及/或不同高度之堆疊100。用模製物204覆蓋堆疊100可呈現均一封裝（在側邊緣/表面中以及高度），如堆疊100及/或組件200。
圖6處所說明之實例展示一具體實例，其中晶粒102覆蓋有模製物204，但主晶圓（主晶粒102'）不覆蓋有模製物204。在一些具體實例中，頂部晶粒102之側邊緣上之模製層204的厚度比安置於下方第二晶粒102之側邊緣上之模製層204的厚度厚。圖7之實例展示一具體實例，其中晶粒102及主晶粒102'全部覆蓋有模製物204，如上文所論述。
如圖8及9處所示，在一些實施方案中，堆疊100可包括晶粒102，該些晶粒在一側上具有互連件而在另一側上不具有互連件。舉例而言，如圖解中所示，頂部晶粒102可不具有與晶粒102之頂部表面之互連件。在此類情況下，在堆疊100或組件200之頂部（例如，背部）表面上可不需要互連件。在替代具體實例中，其他晶粒102可包括僅一側上之互連件。在一些具體實例中，TSV 114亦可選用於頂部晶粒102，然而，TSV 114可用於熱耗散。
在一些實例中，如圖8及9處所示，散熱片802或其他構件902（例如，感測器、光學構件等）可包括於堆疊100中。舉例而言，散熱片802可位於堆疊100之頂部處以幫助熱量自堆疊100之一或多個晶粒102耗散至環境中。在一些情況下，導熱TSV 114可幫助將餘熱自一些晶粒102轉移至其他晶粒102且轉移至散熱片802。在替代具體實例中，散熱片802或其他構件902可視其應用及效能需要定位於堆疊100內的某處或堆疊100之底部處的某處。
如圖8及9處所示，當散熱片802或其他構件902位於堆疊100之頂部處時，堆疊100之頂部（例如，晶粒102之頂部或「背部」表面）可不含模製物204。在一些情況下，當其他堆疊100（例如，包括散熱片802或其他構件902之堆疊100）可不含頂部表面處之模製物204，同時具有堆疊100之側部處之模製物204時，組件200之堆疊100中之一些可包括模製物204，該模製物整個圍繞堆疊100且包括堆疊100之頂部表面處。
如圖10及11處所示，在一些具體實例中，均一及/或非均一晶粒102可經堆疊及接合以形成堆疊100，其中多個晶粒102橫向地放置於組件200封裝內之單一層級（level）上。舉例而言，如圖10處所示，主晶圓202可不在堆疊100中之每一者處經單體化。因此，超過一個堆疊100可經接合至單個主晶粒102'。舉例而言，在圖10的實例中，第二及第三堆疊100經接合至單個主晶粒102'，且第四及第五堆疊100經接合至另一主晶粒102'。
如圖10處所示，接合至主晶粒102'之堆疊100之群組可一起經覆蓋於模製物204中。舉例而言，在實例中，第二及第三堆疊100可一起覆蓋於模製物204中（例如，通常經密封），且第四及第五堆疊100可一起經覆蓋於模製物204中（例如，通常經密封）。替代地或組合地，接合至共同主晶粒102'之堆疊100之一些群組的模製物204可經分隔，其中分隔的模製物204分別圍繞每一堆疊100。主晶粒102'（或晶圓）可不含模製物，如實例中所示。替代地，主晶粒102'（或晶圓）可覆蓋有模製物204。
如圖11處所示，在一些具體實例中，額外晶粒102可以橫向配置堆疊於組件200之單一層級上，從而形成一或多個共同堆疊或部分共同堆疊1100。舉例而言，圖11展示部分共同堆疊1100之實例。在實例中，接合至主晶粒102'之第一列晶粒102在堆疊100中之每一者處可不經單體化。因此，超過一個堆疊100可經接合至單個主晶粒102'及單個「第一列」晶粒102。
舉例而言，在圖11的實例中，第二及第三堆疊100包含接合至單個主晶粒102'之單個第一列晶粒102。第二及第三堆疊100之晶粒102之後續列接合至單個第一列晶粒102。相應地，第二及第三堆疊100共用共同主晶粒102'及共同第一列晶粒102。當一些晶粒102為多個堆疊100所共用時，此產生部分共同堆疊1100。在其他具體實例中，晶粒102之額外列可為第二及第三堆疊100所共用。舉例而言，若多個堆疊100之所有列之晶粒102為多個堆疊100所共用，則此將產生共同堆疊1100。
如圖11中所示，第四及第五堆疊100亦包含接合至單個主晶粒102'之單個第一列晶粒102。第四及第五堆疊100之晶粒102之後續列接合至單個第一列晶粒102。相應地，第四及第五堆疊100共用共同主晶粒102'及共同第一列晶粒102，從而產生部分共同堆疊1100。
如圖10及11處所示，第一堆疊100覆蓋有模製物204（除主晶粒102'以外），且部分共同堆疊1100中之每一者亦覆蓋有模製物204（除主晶粒102'以外）。然而，如圖10及11處所示，一或多個部分共同堆疊1100可包括部分共同堆疊1100之晶粒102之頂部表面處的模製物204，且一或多個部分共同堆疊1100可不含部分共同堆疊1100之晶粒102之頂部表面處的模製物204。如上文所論述，移除頂部晶粒102之頂部表面處之模製物204（或不沉積模製物204）可允許與頂部晶粒102之互連性，可允許自頂部晶粒102之改良熱耗散，等等。 額外具體實例
圖12及13說明組件200之例示性具體實例，其中接合晶粒102之一或多個堆疊100接合至主晶圓202。在一些實例中，主晶圓202可經單體化為主晶粒102'（圖中未示）。在如所示的各種具體實例中，晶粒102可為雙側晶粒，該些雙側晶粒具有嵌入於基底層104之任一側上之絕緣層106內之傳導特徵110。可假定諸如跡線112及TSV 114之一些細節存在於一些具體實例中，但為了圖式清楚起見，未說明該些細節。
在一實施方案中，如圖12及13處所示，絕緣層106中之一或多者可在晶粒102之周界邊緣處經蝕刻（見1202），從而移除周界處之絕緣層106中之一些。周界蝕刻1202可基於裝置、封裝、處理或類似者之規範而為有意的（intentional）。在實施方案中，蝕刻1202可存在於晶粒102之一或多個側部或邊緣上。在一些情況下，蝕刻1202包含移除周界處之絕緣層106之一部分及暴露下方之基底層104。在其他情況下，蝕刻1202並不暴露基底層104，或蝕刻1202亦同樣移除基底層104中之一些。
圖14為根據一具體實例之具有經蝕刻周界邊緣（凹部1202）之晶粒102之額外圖解。在一例示性具體實例中，圖14之圖解更緊密展示凹部1202相對於基底層104及絕緣層106之相對尺度。在其他具體實例中，其他比例可存在。
在一些情況下，模製物204化合物可經顆粒填充，如上文所論述。舉例而言，顆粒可添加至模製物204以改變模製物204之熱膨脹係數（CTE）。此可例如藉由均衡跨封裝（例如，組件200）之CTE來幫助減少封裝翹曲。然而，在一些情況下，模製物204中之顆粒可過大以至於不能裝配於由周界蝕刻形成之較小凹部1202內。在模製物204應用於堆疊100後留下之任何空隙可引起封裝（例如，組件200）之組件中的「爆米花（popcorn）」故障。
在各種實施方案中，如圖13處所示，模製物204之多個層可用於降低可能的故障，而非不包括模製物204中之顆粒（且不接受如此操作之益處）。舉例而言，第一低黏度化合物1302可圍繞堆疊100經應用，從而形成圍繞堆疊100且滲透經蝕刻凹部1202之一層化合物1302。層1302可隨後緊接有一層模製物204。
在實施方案中，第一層化合物1302可不包括填充劑或顆粒。舉例而言，由於具有低黏度，化合物1302之主要目的可為填充晶粒102中之經蝕刻凹部1302。然而，化合物1302亦可在堆疊100之晶粒102之垂直壁上方形成層。在應用第一層化合物1302後，堆疊100及/或組件200可覆蓋有模製物204。在替代具體實例中，額外層亦可用以覆蓋堆疊100及/或組件200。
在其他實施方案中，第一層（低黏度）化合物1302（或樹脂）可包括足夠小之亞微米顆粒或甚至奈米顆粒以併入於凹部1202內。亞微米或奈米顆粒可包含二氧化矽（silica）、矽、二氧化矽/矽化合物或類似者。奈米顆粒可在一些情況下平均為20 nm大小（例如，直徑），且可在其他情況下更小或更大。
在一具體實例中，第一層化合物1302（具有亞微米或奈米級填充劑顆粒）在晶粒102之垂直壁及凹部1202上方形成層。在一些具體實例中，較佳的係第一層化合物1302之亞微米或奈米顆料含量大於5%。模製層204通常包含顆粒含量通常大於50%之強化顆粒，且可較佳的係模製層204之顆粒含量高於凹部1202內之第一層化合物1302之顆粒含量。類似地，在一些應用中，可較佳的係模製層204中之顆粒的標稱大小大於第一層化合物1302中之顆粒的標稱大小。
參考圖15及16，在通常實踐中，使用球柵格陣列（ball-grid arrays；BGA）及其他類似技術將記憶體晶粒耦接至其他記憶體晶粒。在那些情況中，記憶體晶粒對記憶體晶粒間距通常為約45微米。使用類似技術，邏輯晶粒對插入件間距為約90至100微米。然而，在一些具體實例中，可能及切實可行的係分別以較細間距來組裝記憶體晶粒堆疊（諸如堆疊100），且然後將其堆疊在邏輯晶粒上。應注意在一些情況下，邏輯晶粒可不大於記憶體晶粒。
圖15及16展示「高頻寬記憶體」組件200之實例，該組件包括耦接至邏輯晶粒1502之記憶體晶粒102（例如，動態隨機存取記憶體（dynamic random access memory；DRAM）、靜態隨機存取記憶體（static random access memory；SRAM）、快閃記憶體等）之堆疊100。在各種實施方案中，晶粒102經混合接合（DBI®）以形成堆疊100，如上文所論述。如圖15中所示，堆疊100（或底部晶粒102）可經混合接合至邏輯晶粒1502。邏輯晶粒1502可包括端子206，該些端子用於將組件200耦接至電路、PCB、裝置或類似者，如上文所論述。使用直接或混合接合技術，晶粒102之間及晶粒102與邏輯晶粒1502之間的距離極大地減小（由於晶粒厚度相對於當前技術，距離為晶粒厚度加上Cu柱及焊球高度）。在一個具體實例中，經接合晶粒102中之一或多者之接合表面處的電路元件（諸如傳導特徵110或類似者）小於20微米且在其他應用中小於5微米或甚至小於1微米。
如圖16中所示，可使用覆晶技術或類似者替代地將堆疊100耦接至邏輯晶粒1502。舉例而言，覆晶端子1602可耦接至底部晶粒102之底部側，該底部晶粒之底部側與邏輯晶粒1502之頂部表面處之端子1602介接。相應地，混合接合及覆晶技術之組合可與組件200一起使用。在替代具體實例中，其他耦接技術亦可視需要用以將混合接合之堆疊100耦接至邏輯晶粒1502、插入件或類似者。
亦展示於圖16中的為模製物1604，該模製物覆蓋覆晶端子1602且填充堆疊100與邏輯晶粒1502之間的間隙。在一些具體實例中，組件200亦可視需要覆蓋有模製物204以供處置、封裝等等。
圖17至20展示在各種應用中使用堆疊100及/或組件200之額外實施方案。舉例而言，在圖17處，展示包括各種晶粒102之組件1700，該組件包括混合接合至插入件1702之晶粒102之堆疊100。在一具體實例中，插入件1702包含半導體，例如矽。為了清楚起見簡化圖式。
在各種具體實例中，如圖17處所示，一些晶粒102可經模製，且其他晶粒102可未經模製。散熱片或其他冷卻裝置1704（例如，風扇等）耦接至未模製晶粒102以冷卻晶粒102（其可包含大功率構件，諸如處理器或類似者）。插入件1702包括混合接合墊110以及至少一個線接合墊1706。
如圖18中所示，線接合墊1706可用於經由接線1804將遠端構件（例如，耦接至（或穿過）層合物1802或與該層合物一體化之構件）耦接至襯墊1706。在所展示之一具體實例中，層合物1802混合接合至插入件1702。替代地，層合物1802可藉由另一接合技術耦接至插入件1702。
舉例而言，如圖19中所示，層合物1802可藉由BGA技術、另一表面黏著技術或類似者來耦接至插入件1702。在一實施方案中，如圖19所示，層合物1802可包括一或多個線接合墊1902，該些線接合墊可與接線1804一起使用以耦接至線接合墊1706或類似者。
在一具體實例中，如圖19所示，組件200或堆疊100可封裝有另一構件1904，該另一構件可混合接合至插入件1702。構件1904及組件200或堆疊100可經覆蓋於模製物1906中，該模製物視需要包含密封體（或其他封裝）。封裝或堆疊100及構件1904可混合接合至插入件1702。冷卻裝置1704可耦接至構件1904及/或堆疊100，如圖19中所示。或者，填充物1604可用於覆蓋端子206且填充插入件1702與層合物1802之間的間隙。或者，插入件1702可與其他構件一起或單獨地經密封。
如圖20所示，堆疊100可覆蓋有模製物204，且其他晶粒102及/或構件可不覆蓋有該模製物。散熱片或其他冷卻裝置1704（例如，風扇等）耦接至未模製晶粒102以冷卻晶粒102（其可包含大功率構件，諸如處理器或類似者）。額外冷卻裝置亦可耦接至堆疊100，該堆疊在堆疊100之頂部表面處可不含模製物204。插入件1702包括混合接合墊110以及至少一個線接合墊1706。如所示，插入件1702可經由BGA配置或其他耦接技術來耦接至層合物1802。 例示性製程
圖21為說明形成包含晶粒堆疊（諸如，晶粒102之堆疊100）之經堆疊及接合之微電子組件（諸如，微電子組件200）之例示性製程2100的流程圖。在一些具體實例中，晶粒之堆疊可覆蓋有模製物（諸如，模製物204）以供處置、處理、應用以及類似者。製程2100係指圖1至20。
描述製程之次序並不意欲理解為限制，且製程中之任何數目的所描述程序區塊可按任何次序組合以實施該製程或替代製程。或者，可在不脫離本文中所描述之主題之精神及範疇的情況下自製程刪除單獨區塊。此外，可在不脫離本文中所描述之主題之範疇的情況下以任何適合之硬體、軟體、韌體或其組合實施製程。在替代實施方案中，其他技術可以各種組合包括於製程中且保持在本發明之範疇內。
在區塊2102處，製程包括形成微電子堆疊（諸如，晶粒102之堆疊100）。在一替代具體實例中，製程包含形成複數個微電子堆疊。在一實施方案中，形成微電子堆疊包括以下區塊：
在區塊2104處，製程包括提供具有前側及背側之第一基板（諸如，第一晶粒102）。背側具有包含非傳導接合層之接合表面及經暴露電性傳導第一電路元件。第一基板具有第一傳導通孔，該第一傳導通孔電耦接至第一基板之第一電路元件且至少部分地延伸穿過第一基板。
在區塊2106處，製程包括提供具有前側及背側之第二基板。前側包括非傳導接合層及經暴露電性傳導第一電路元件。
在區塊2108處，製程包括藉由接觸第一基板之非傳導接合層及第二基板之非傳導接合層來將第二基板之前側耦接至第一基板之背側。在一具體實例中，第一基板之側邊緣相對於第二基板之側邊緣未對準。耦接包括使第一基板之第一電路元件與第二基板之第一電路元件接觸（例如，混合接合）。
在區塊2110處，製程包括用模製物（諸如，模製物204）覆蓋第一基板之側邊緣及第二基板之側邊緣。在一實施方案中，製程包括用模製物覆蓋第二基板之背側。在各種具體實例中，模製物包括超過一個層或超過一種材料或化合物。在一些具體實例中，複數個模製物層中之至少一者包括顆粒以幫助均衡組件之CTE，從而避免組件之翹曲。
在一具體實例中，第二基板之背側包括第二非傳導接合層及經暴露電性傳導第二電路元件。在具體實例中，第二基板具有第二傳導通孔，該第二傳導通孔電耦接第二基板之第一電路元件及第二電路元件。
在一實施方案中，製程包括提供具有前側及背側之第三基板，前側包括非傳導接合層及經暴露電性傳導第一電路元件。製程包括藉由使第三基板之非傳導接合層與第二基板之非傳導接合層接觸來將第三基板之前側耦接至第二基板之背側。在一具體實例中，第三基板之側邊緣相對於第二基板之側邊緣及/或第一基板之側邊緣未對準。耦接包括使第三基板之第一電路元件與第二基板之第二電路元件接觸（例如，混合接合）。
在實施方案中，製程包括在第一基板之周界及/或第二基板之周界處形成第一基板之接合層及/或第二基板之接合層處之凹部，及在用模製物覆蓋第一基板之側邊緣及第二基板之側邊緣之前用低黏度化合物填充至少該凹部。
在另一實施方案中，製程包括用模製物覆蓋第三基板之側邊緣。在再一實施方案中，製程包括用模製物覆蓋第三基板之背側。
在一實施方案中，製程包括將微電子堆疊混合接合至具有至少一個線接合接觸墊之半導體插入件。在另一實施方案中，製程包括將插入件耦接至具有第二線接合接觸墊之層合物，及用接線將插入件之至少一個線接合接觸墊接合至層合物之第二線接合接觸墊。舉例而言，插入件可混合接合至層合物。
在其他實施方案中，微電子組件之各種部分覆蓋有一或多個模製物層，而其他部分不覆蓋有模製物。
儘管在此處論述各種實施方案及實例，但其他實施方案及實例可藉由組合個別實施方案及實例之特徵及元件來成為可能。在各種具體實例中，相較於本文中所描述之製程步驟，一些製程步驟可經修改或消除。
本文中所描述之技術、構件及裝置不限於圖1至21之說明，且可在不脫離本發明之範疇的情況下應用於包括其他電性構件之其他設計、類型、配置及構造。在一些情況下，額外或替代構件、技術、序列或製程可用於實施本文中所描述之技術。此外，構件及/或技術可以各種組合經配置及/或組合，同時引起類似或大致相同之結果。 結論
儘管已以特定針對於結構特徵及/或方法行動之語言描述了本發明之實施方案，但應理解，實施方案不一定限於所描述之特定特徵或行動。確切而言，將特定特徵及動作揭示為實施實例裝置及技術之代表性形式。
本文之每項申請專利範圍構成單獨具體實例，且組合不同申請專利範圍之具體實例及/或不同具體實例在本發明之範疇內，且將在查閱本發明之後對於所屬領域中具有通常知識者顯而易見。
100‧‧‧堆疊/微電子組件 102‧‧‧晶粒 102'‧‧‧晶粒 102"‧‧‧晶粒 104‧‧‧基底基板 106‧‧‧絕緣層/介電層 108‧‧‧接合表面 110‧‧‧傳導特徵 112‧‧‧傳導跡線 114‧‧‧傳導矽穿孔 116‧‧‧電耦接墊/襯墊 200‧‧‧微電子組件 202‧‧‧主晶圓 204‧‧‧模製物 206‧‧‧電接觸/端子 802‧‧‧散熱片 902‧‧‧其他構件 1100‧‧‧共同堆疊/部分共同堆疊 1202‧‧‧蝕刻/凹部 1302‧‧‧第一低黏度化合物 1502‧‧‧邏輯晶粒 1602‧‧‧覆晶端子 1604‧‧‧模製物 1700‧‧‧組件 1702‧‧‧插入件 1704‧‧‧散熱片/冷卻裝置 1706‧‧‧線接合墊 1802‧‧‧層合物 1804‧‧‧接線 1902‧‧‧線接合墊 1904‧‧‧構件 1906‧‧‧模製物 2100‧‧‧製程 2102‧‧‧區塊 2104‧‧‧區塊 2106‧‧‧區塊 2108‧‧‧區塊 2110‧‧‧區塊 e‧‧‧誤差/未對準
參看隨附圖式闡述具體實施方式。在圖式中，元件符號之一或多個最左側數字鑑別首次出現該元件符號之圖式。在不同圖式中使用相同元件符號指示類似或相同物件。 對此論述，圖式中所說明之裝置及系統展示為具有大量構件。如本文中所描述，裝置及/或系統之各種實施方案可包括較少構件且保持在本發明之範疇內。替代地，裝置及/或系統之其他實施方案可包括額外構件或所描述構件之各種組合，且保持在本發明之範疇內。 圖1為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖。 圖2為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中不覆蓋該堆疊之頂部。 圖3為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中覆蓋該堆疊之頂部。 圖4為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中不覆蓋該堆疊之頂部且模製物延伸至堆疊之底部。 圖5為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中覆蓋該堆疊之頂部且模製物延伸至堆疊之底部。 圖6為根據一具體實例之具有大小不等晶粒之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中覆蓋該堆疊之頂部。 圖7為根據一具體實例之具有大小不等晶粒之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中覆蓋該堆疊之頂部且模製物延伸至堆疊之底部。 圖8為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中堆疊之頂部晶粒在一側上並不具有互連件。 圖9為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖，在該具體實例中堆疊之頂部晶粒在一側上並不具有互連件且模製物延伸至堆疊之底部。 圖10為根據一具體實例之包括晶粒在單一層級上之一些橫向放置的例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖。 圖11為根據一具體實例之包括晶粒及晶圓在單一層級上之一些橫向放置的例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖。 圖12為根據一具體實例之包括晶粒邊緣之一些蝕刻的例示性晶粒對晶圓及/或晶粒對晶粒堆疊之橫截面剖面圖。 圖13為根據一具體實例之包括晶粒邊緣之一些蝕刻的例示性晶粒對晶圓及/或晶粒對晶粒堆疊及模製物之橫截面剖面圖。 圖14為根據另一具體實例之包括晶粒邊緣之一些蝕刻的例示性晶粒對晶圓及/或晶粒對晶粒混合接合堆疊之橫截面剖面圖。 圖15為根據一具體實例之例示性晶粒對晶圓及/或晶粒對晶粒記憶體堆疊之橫截面剖面圖。 圖16為根據一具體實例之包括覆晶封端的例示性晶粒對晶圓及/或晶粒對晶粒混合接合堆疊之橫截面剖面圖。 圖17至20展示根據各種具體實例之包括基板上之各種組合的例示性晶粒對晶圓及/或晶粒對晶粒混合接合堆疊之橫截面剖面圖。 圖21為根據一具體實例之說明用於形成經堆疊及經接合結構之例示性製程的流程圖。
100‧‧‧堆疊/微電子組件
102‧‧‧晶粒
102'‧‧‧晶粒
104‧‧‧基底基板
106‧‧‧絕緣層/介電層
108‧‧‧接合表面
110‧‧‧傳導特徵
112‧‧‧傳導跡線
114‧‧‧傳導矽穿孔
116‧‧‧電耦接墊/襯墊
e‧‧‧誤差/未對準

Claims (35)

  1. 一種微電子組件，其包含：第一基板，其具有第一接合表面及嵌入至該第一基板中之第一微電子電路元件，該第一基板之該第一電路元件之一部分在該第一基板之該第一接合表面處暴露；第二基板，其具有第一接合表面及嵌入至該第二基板中之第一微電子電路元件，該第二基板之該第一電路元件之一部分在該第二基板之該第一接合表面處暴露，該第二基板之該第一接合表面混合接合至該第一基板之該第一接合表面而無需黏合劑，使得該第二基板之該第一電路元件電耦接至該第一基板之該第一電路元件，其中該第一基板之側邊緣相對於該第二基板之側邊緣未對準；以及多層密封體，其覆蓋至少該第二基板之前述側邊緣，其中所述多層密封體包括所述第二基板的周界表面處具有第一熱膨脹係數的第一層以及覆蓋在所述第一層上的具有與所述第一熱膨脹係數不同的熱膨脹係數的第二層。
  2. 如請求項1所述之微電子組件，其進一步包含第一傳導通孔，該第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板。
  3. 如請求項2所述之微電子組件，其中該第一基板包括與該第一接合表面相對之第二表面，且其中該第一傳導通孔延伸至該第一基板之該第二表面且提供從該第一基板之該第一接合表面至該第一基板之該第二表面之電連接性。
  4. 如請求項3所述之微電子組件，其進一步包含端子連接件，該端子連接件耦接至該第一基板之該第二表面且電耦接至該第一傳導通孔。
  5. 如請求項2所述之微電子組件，其中該第二基板包括與該第一接合 表面相對之第二接合表面及嵌入至該第二基板中之第二微電子電路元件，該第二基板之該第二電路元件之一部分在該第二基板之該第二接合表面處暴露。
  6. 如請求項5所述之微電子組件，其進一步包含第二傳導通孔，該第二傳導通孔電耦接至該第二基板之該第一電路元件及該第二電路元件且至少部分地延伸穿過該第二基板，該第二傳導通孔提供從該第二基板之該第一接合表面至該第二基板之該第二接合表面之電連接性。
  7. 如請求項6所述之微電子組件，其中該第二傳導通孔提供從該第一基板之第二表面至該第二基板之該第二接合表面之電連接性，該第一基板之該第二表面與該第一基板之該第一接合表面相對。
  8. 如請求項6所述之微電子組件，其進一步包含第三基板，該第三基板具有第一接合表面及嵌入至該第三基板中之第一微電子電路元件，該第三基板之該第一電路元件之一部分在該第三基板之該第一接合表面處暴露，該第三基板之該第一接合表面接合至該第二基板之該第二接合表面，使得該第三基板之該第一電路元件電耦接至該第二基板之該第二電路元件。
  9. 如請求項8所述之微電子組件，其中該第三基板之側邊緣相對於該第二基板之前述側邊緣或該第一基板之前述側邊緣未對準。
  10. 如請求項8所述之微電子組件，其中該密封體覆蓋該第一基板之前述側邊緣、該第二基板之前述側邊緣及該第三基板之前述側邊緣。
  11. 如請求項8所述之微電子組件，其中該密封體覆蓋該第二基板之前述側邊緣及該第三基板之前述側邊緣，而不覆蓋該第一基板之前述側邊緣。
  12. 如請求項8所述之微電子組件，其中該密封體覆蓋與該第三基板之該第一接合表面相對之該第三基板之第二表面。
  13. 如請求項1所述之微電子組件，其中該模製物覆蓋與該第一基板之該第一接合表面相對之該第二基板之第二表面。
  14. 一種微電子組件，其包含第一微電子組件和第二微電子組件，其中所述第一微電子組件和第二微電子組件皆為如請求項10所述之微電子組件。
  15. 如請求項14所述之微電子組件，其中第一基板、第二基板及第三基板之佔據面積為非均一的，且其中自該第一基板延伸至該第三基板之密封體之外部側邊緣為平面的。
  16. 一種微電子組件，其包含：多個微電子元件的複數個相鄰堆疊，每個堆疊包含：第一基板，其具有第一接合表面及嵌入至該第一基板中之第一微電子電路元件，該第一基板之該第一電路元件之一部分在該第一基板之該第一接合表面處暴露，且第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板；第二基板，其具有第一接合表面及嵌入至該第二基板中之第一微電子電路元件，該第二基板之該第一電路元件之一部分在該第二基板之該第一接合表面處暴露，且第二傳導通孔電耦接至該第二基板之該第一電路元件且至少部分地延伸穿過該第二基板，該第二基板之該第一接合表面混合接合至該第一基板之該第一接合表面而無需黏合劑，使得該第二基板之該第一電路元件電耦接至該第一基板之該第一電路元件，其中該第一基板之側邊緣相對於該第二基板之側邊緣未對準；以及密封體，其覆蓋每個堆疊中的至少該第二基板之前述側邊緣，每個堆疊包括面向相鄰堆疊的側邊緣之所述側邊緣。
  17. 如請求項16所述之微電子組件，其中該第一基板包括與該第一接合表面相對之第二表面，且其中該第一傳導通孔延伸至該第一基板之該第二表面且提供從該第一基板之該第一接合表面至該第一基板之該第二表面之電連接性。
  18. 如請求項17所述之微電子組件，其中該第二基板包括與該第一接合表面相對之第二接合表面及嵌入至該第二基板中之第二微電子電路元件，該第二基板之該第二電路元件之一部分在該第二基板之該第二接合表面處暴露，且其中該第二傳導通孔電耦接至該第二基板之該第二電路元件。
  19. 如請求項18所述之微電子組件，其中該第二基板之該第一接合表面及該第二接合表面中之至少一者包括該第一接合表面及該第二接合表面中之前述至少一者的周界的蝕刻部分，其在該第二基板之周界邊緣處形成有意的凹部。
  20. 如請求項19所述之微電子組件，其中該密封體包含未具有顆粒之第一低黏度材料，該第一低黏度材料滲透該第二基板之該周界邊緣處的該凹部，且具有顆粒之第二材料覆蓋在該第一低黏度材料上方。
  21. 如請求項16所述之微電子組件，其進一步包含層合物及/或插入件，且其中複數個經密封的該微電子元件之堆疊混合接合至該層合物或該插入件而無需黏合劑或中介材料。
  22. 如請求項21所述之微電子組件，其進一步在該層合物之表面上及/或在該插入件之表面上包含至少一個線接合墊。
  23. 如請求項21所述之微電子組件，其中該層合物使用接線來耦接至該插入件，該接線耦接於該層合物之表面上之線接合墊處及該插入件之表面上之線接合墊處。
  24. 如請求項21所述之微電子組件，其進一步包含非密封晶粒，該非密封晶粒在無黏合劑之情況下混合接合至該層合物及/或該插入件。
  25. 如請求項16所述之微電子組件，其中至少該第二基板包含固態記憶體裝置。
  26. 一種形成微電子組件之方法，其包含： 形成微電子堆疊，其包含：提供具有前側及背側之第一基板，該背側具有包含非傳導接合層之接合表面以及經暴露電性傳導第一電路元件，該第一基板具有第一傳導通孔，該第一傳導通孔電耦接至該第一基板之該第一電路元件且至少部分地延伸穿過該第一基板；提供具有前側及背側之第二基板，該前側包括非傳導接合層及經暴露電性傳導第一電路元件；藉由使該第一基板之該非傳導接合層與該第二基板之該非傳導接合層接觸來將該第二基板之該前側耦接至該第一基板之該背側，該第一基板之側邊緣相對於該第二基板之側邊緣未對準，且使該第一基板之該第一電路元件與該第二基板之該第一電路元件接觸；以及用多層密封體覆蓋至少該第二基板之前述側邊緣，所述多層密封體包括在所述第二基板的周界表面處具有每體積第一顆粒含量的第一層和覆蓋在所述第一層上的每顆粒含量大於所述每體積第一顆粒含量的第二層。
  27. 如請求項26所述之方法，其進一步包含用該密封體覆蓋該第二基板之該背側。
  28. 如請求項26所述之方法，其中該第二基板之該背側包括第二非傳導接合層及經暴露電性傳導第二電路元件，該第二基板具有第二傳導通孔，該第二傳導通孔電耦接該第二基板之該第一電路元件及該第二電路元件。
  29. 如請求項28所述之方法，其進一步包含：提供具有前側及背側之第三基板，該前側包括非傳導接合層及經暴露電性傳導第一電路元件；藉由使該第三基板之該非傳導接合層與該第二基板之該非傳導接合層接觸來將該第三基板之該前側耦接至該第二基板之該背側，該第三基板之側邊緣相 對於該第二基板之側邊緣及/或該第一基板之側邊緣未對準，且使該第三基板之該第一電路元件與該第二基板之該第二電路元件接觸；以及用該密封體覆蓋該第三基板之前述側邊緣。
  30. 如請求項26所述之方法，其進一步包含在該第一基板之一周界處之該第一基板之該接合層處及/或該第二基板之一周界處之該第二基板之該接合層處形成一凹部，及在用該密封體覆蓋該第一基板之該些側邊緣及該第二基板之該些側邊緣之前，用一低黏度層填充至少該凹部。
  31. 如請求項26所述之方法，其進一步包含將該微電子堆疊混合接合至具有至少一個線接合接觸墊之半導體插入件。
  32. 如請求項31所述之方法，其進一步包含將該插入件耦接至具有第二線接合接觸墊之層合物，及用接線將該插入件之該至少一個線接合接觸墊接合至該層合物之該第二線接合接觸墊。
  33. 如請求項26所述之方法，其中形成該微電子組件包含形成複數個微電子堆疊。
  34. 一種微電子組件，其包含：第一晶粒，其具有第一接合表面及嵌入至該第一晶粒中之第一微電子電路元件，該第一電路元件之一部分在該第一晶粒之該第一接合表面處暴露；以及第二晶粒，其具有第一接合表面及嵌入至該第二晶粒中之第一微電子電路元件，該第二晶粒之該第一電路元件之一部分在該第二晶粒之該第一接合表面處暴露，該第一晶粒之該第一接合表面混合接合至該第二晶粒之該第一接合表面，使該第一晶粒電耦接至該第二晶粒而無需黏合層，其中該第一晶粒之側邊緣包含比安置於該第二晶粒之側邊緣上之密封體層薄的密封體層，以及其中在該第一晶粒處的所述密封體層及/或在該第二晶粒處的所述密封體層具有不均勻的密度。
  35. 一種微電子組件，其包含：第一晶粒，其具有第一接合表面以及嵌入所述第一晶粒的第一微電子電路元件，所述第一微電子電路元件的一部分在所述第一晶粒的所述第一接合表面處暴露；第二晶粒，其具有第一接合表面以及嵌入所述第二晶粒的第一微電子電路元件，所述第二晶粒的所述第一微電子電路元件的一部分在所述第二晶粒的所述第一接合表面處暴露，該第一晶粒之該第一接合表面混合接合至該第二晶粒之該第一接合表面，使該第一晶粒電耦接至該第二晶粒而無需黏合劑並且形成堆疊；密封體，其覆蓋至少該第二晶粒之側邊緣；以及半導體插入件，其具有至少一個線接合接觸墊，所述堆疊混合接合到所述插入件。
TW108123487A 2018-07-06 2019-07-03 模製直接接合且互連的堆疊 TWI834682B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862694845P 2018-07-06 2018-07-06
US62/694,845 2018-07-06
US16/460,068 2019-07-02
US16/460,068 US11158606B2 (en) 2018-07-06 2019-07-02 Molded direct bonded and interconnected stack

Publications (2)

Publication Number Publication Date
TW202006890A TW202006890A (zh) 2020-02-01
TWI834682B true TWI834682B (zh) 2024-03-11

Family

ID=69060191

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108123487A TWI834682B (zh) 2018-07-06 2019-07-03 模製直接接合且互連的堆疊

Country Status (3)

Country Link
US (4) US11158606B2 (zh)
TW (1) TWI834682B (zh)
WO (1) WO2020010136A1 (zh)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US11176450B2 (en) 2017-08-03 2021-11-16 Xcelsis Corporation Three dimensional circuit implementing machine trained network
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
WO2018186198A1 (ja) * 2017-04-04 2018-10-11 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、及び電子機器
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
KR20210009426A (ko) 2018-06-13 2021-01-26 인벤사스 본딩 테크놀로지스 인코포레이티드 패드로서의 ｔｓｖ
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
WO2020129808A1 (ja) * 2018-12-21 2020-06-25 株式会社村田製作所 電子部品モジュールの製造方法及び電子部品モジュール
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
CN111276469A (zh) * 2020-02-25 2020-06-12 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) * 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11424191B2 (en) * 2020-06-30 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
CN112164674A (zh) * 2020-09-24 2021-01-01 芯盟科技有限公司 堆叠式高带宽存储器
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
US11387207B2 (en) * 2020-11-13 2022-07-12 Nanya Technology Corporation Method for fabricating semiconductor device including etching an edge portion of a bonding layer by using an etching mask
CN114628262A (zh) * 2020-12-10 2022-06-14 武汉新芯集成电路制造有限公司 半导体器件的制作方法
US11574891B2 (en) 2021-01-26 2023-02-07 Nanya Technology Corporation Semiconductor device with heat dissipation unit and method for fabricating the same
US20220320039A1 (en) * 2021-03-31 2022-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of forming the same
US20240023341A1 (en) * 2021-04-14 2024-01-18 Taiwan Semiconductor Manufacturing Company Limited Ferroelectric tunnel junction memory device using a magnesium oxide tunneling dielectric and methods for forming the same
US11721685B2 (en) * 2021-05-26 2023-08-08 Avago Technologies International Sales Pte. Limited Copper-bonded memory stacks with copper-bonded interconnection memory systems
US12040300B2 (en) 2021-11-04 2024-07-16 Airoha Technology Corp. Semiconductor package using hybrid-type adhesive
US11658152B1 (en) * 2021-11-05 2023-05-23 Nanya Technology Corporation Die bonding structure, stack structure, and method of forming die bonding structure
US20230207475A1 (en) * 2021-12-23 2023-06-29 Intel Corporation Hybrid bonded stacked memory with tsv as chiplet for package structure
US20230275066A1 (en) * 2022-02-25 2023-08-31 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
JP2024000909A (ja) * 2022-06-21 2024-01-09 キオクシア株式会社 半導体装置及び半導体記憶装置
US20240021571A1 (en) * 2022-07-18 2024-01-18 Applied Materials, Inc. Hybrid bonding of semiconductor structures to advanced substrate panels
CN115295435A (zh) * 2022-08-24 2022-11-04 武汉新芯集成电路制造有限公司 中介层结构及其制造方法
WO2024182545A1 (en) * 2023-03-01 2024-09-06 Adeia Semiconductor Bonding Technologies Inc. Multichannel memory with serdes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130169355A1 (en) * 2012-01-04 2013-07-04 Kuan-Neng Chen Integrated Circuit Device
US20150235949A1 (en) * 2014-02-20 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Functional Block Stacked 3DIC and Method of Making Same

Family Cites Families (358)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272642A (ja) 1988-09-07 1990-03-12 Nec Corp 基板の接続構造および接続方法
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5019673A (en) 1990-08-22 1991-05-28 Motorola, Inc. Flip-chip package for integrated circuits
JPH04337694A (ja) 1991-05-15 1992-11-25 Nec Yamagata Ltd 電子部品保護用樹脂膜
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
DE69429848T2 (de) 1993-11-01 2002-09-26 Matsushita Electric Industrial Co., Ltd. Elektronische Anordnung und Verfahren zur Herstellung
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
DE4433330C2 (de) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
JP3979687B2 (ja) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法
KR100274333B1 (ko) 1996-01-19 2001-01-15 모기 쥰이찌 도체층부착 이방성 도전시트 및 이를 사용한 배선기판
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JP4032454B2 (ja) 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JP2000100679A (ja) 1998-09-22 2000-04-07 Canon Inc 薄片化による基板間微小領域固相接合法及び素子構造
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001313350A (ja) 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
JP4322402B2 (ja) 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
JP3420748B2 (ja) 2000-12-14 2003-06-30 松下電器産業株式会社 半導体装置及びその製造方法
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
TWI309074B (en) 2002-02-07 2009-04-21 Advanced Epitaxy Technology Method of forming semiconductor device
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
JP4579489B2 (ja) 2002-09-02 2010-11-10 新光電気工業株式会社 半導体チップ製造方法及び半導体チップ
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
JP2004193493A (ja) 2002-12-13 2004-07-08 Nec Machinery Corp ダイピックアップ方法および装置
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
TW586677U (en) 2003-01-22 2004-05-01 Via Tech Inc Stack structure of chip package
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
TWI239629B (en) 2003-03-17 2005-09-11 Seiko Epson Corp Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI275168B (en) 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
US6873049B2 (en) 2003-07-31 2005-03-29 The Boeing Company Near hermetic power chip on board device and manufacturing method therefor
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
KR100538158B1 (ko) 2004-01-09 2005-12-22 삼성전자주식회사 웨이퍼 레벨 적층 칩 접착 방법
US20050161808A1 (en) 2004-01-22 2005-07-28 Anderson Douglas G. Wafer, intermediate wafer assembly and associated method for fabricating a silicon on insulator wafer having an improved edge profile
TWI427700B (zh) 2004-08-20 2014-02-21 Kamiyacho Ip Holdings 三維積層構造之半導體裝置之製造方法
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060076634A1 (en) 2004-09-27 2006-04-13 Lauren Palmateer Method and system for packaging MEMS devices with incorporated getter
US7262492B2 (en) 2004-09-28 2007-08-28 Intel Corporation Semiconducting device that includes wirebonds
FR2880184B1 (fr) 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
GB0505680D0 (en) 2005-03-22 2005-04-27 Cambridge Display Tech Ltd Apparatus and method for increased device lifetime in an organic electro-luminescent device
JP4275096B2 (ja) 2005-04-14 2009-06-10 パナソニック株式会社 半導体チップの製造方法
US7354862B2 (en) 2005-04-18 2008-04-08 Intel Corporation Thin passivation layer on 3D devices
JP4983049B2 (ja) 2005-06-24 2012-07-25 セイコーエプソン株式会社 半導体装置および電子機器
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7682937B2 (en) 2005-11-25 2010-03-23 Advanced Laser Separation International B.V. Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
US7781309B2 (en) 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US20070158024A1 (en) 2006-01-11 2007-07-12 Symbol Technologies, Inc. Methods and systems for removing multiple die(s) from a surface
TWI299552B (en) 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure
US7972683B2 (en) 2006-03-28 2011-07-05 Innovative Micro Technology Wafer bonding material with embedded conductive particles
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
KR100809696B1 (ko) 2006-08-08 2008-03-06 삼성전자주식회사 사이즈가 상이한 복수의 반도체 칩이 적층된 멀티 칩패키지 및 그 제조방법
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
JP5011981B2 (ja) 2006-11-30 2012-08-29 富士通株式会社 デバイス素子製造方法およびダイシング方法
US8178964B2 (en) 2007-03-30 2012-05-15 Advanced Chip Engineering Technology, Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US8178963B2 (en) 2007-01-03 2012-05-15 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving through-hole and method of the same
US20080165521A1 (en) 2007-01-09 2008-07-10 Kerry Bernstein Three-dimensional architecture for self-checking and self-repairing integrated circuits
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
JP2008258383A (ja) 2007-04-04 2008-10-23 Spansion Llc 半導体装置及びその製造方法
DE102007020656B4 (de) 2007-04-30 2009-05-07 Infineon Technologies Ag Werkstück mit Halbleiterchips, Halbleiterbauteil und Verfahren zur Herstellung eines Werkstücks mit Halbleiterchips
US20090001599A1 (en) 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
US20090029274A1 (en) 2007-07-25 2009-01-29 3M Innovative Properties Company Method for removing contamination with fluorinated compositions
US8044497B2 (en) 2007-09-10 2011-10-25 Intel Corporation Stacked die package
JP2009135348A (ja) 2007-12-03 2009-06-18 Panasonic Corp 半導体チップと半導体装置およびそれらの製造方法
US7871902B2 (en) 2008-02-13 2011-01-18 Infineon Technologies Ag Crack stop trenches
EP2963675A1 (en) 2008-03-05 2016-01-06 The Board of Trustees of The University of Illinois Stretchable and foldable electronic devices
KR20100122110A (ko) 2008-03-07 2010-11-19 쓰리엠 이노베이티브 프로퍼티즈 컴파니 패턴화된 배킹이 있는 다이싱 테이프 및 다이 부착 접착제
KR20090106822A (ko) 2008-04-07 2009-10-12 삼성전자주식회사 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
WO2010024678A1 (en) 2008-09-01 2010-03-04 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Chip die clamping device and transfer method
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
JP2010073964A (ja) 2008-09-19 2010-04-02 Fujitsu Microelectronics Ltd 半導体装置の製造方法
US7843052B1 (en) 2008-11-13 2010-11-30 Amkor Technology, Inc. Semiconductor devices and fabrication methods thereof
WO2010059781A1 (en) 2008-11-19 2010-05-27 Semprius, Inc. Printing semiconductor elements by shear-assisted elastomeric stamp transfer
KR100945800B1 (ko) 2008-12-09 2010-03-05 김영혜 이종 접합 웨이퍼 제조방법
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
JP2010245383A (ja) 2009-04-08 2010-10-28 Elpida Memory Inc 半導体装置および半導体装置の製造方法
JP5304536B2 (ja) 2009-08-24 2013-10-02 ソニー株式会社 半導体装置
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
US9202769B2 (en) 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
EP2339614A1 (en) 2009-12-22 2011-06-29 Imec Method for stacking semiconductor chips
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
US8138014B2 (en) 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
JP2011171614A (ja) 2010-02-22 2011-09-01 Casio Computer Co Ltd 半導体装置及び半導体装置の製造方法
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
US8415808B2 (en) 2010-07-28 2013-04-09 Sandisk Technologies Inc. Semiconductor device with die stack arrangement including staggered die and efficient wire bonding
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8288201B2 (en) 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
KR20120032254A (ko) * 2010-09-28 2012-04-05 삼성전자주식회사 반도체 적층 패키지 및 이의 제조 방법
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
JP5659033B2 (ja) 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
US8623702B2 (en) 2011-02-24 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
US8846493B2 (en) 2011-03-16 2014-09-30 Sunedison Semiconductor Limited Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
KR20120123919A (ko) 2011-05-02 2012-11-12 삼성전자주식회사 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지
EP3534399A1 (en) 2011-05-24 2019-09-04 Sony Corporation Semiconductor device
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8710648B2 (en) 2011-08-09 2014-04-29 Alpha & Omega Semiconductor, Inc. Wafer level packaging structure with large contact area and preparation method thereof
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP5780228B2 (ja) 2011-11-11 2015-09-16 住友ベークライト株式会社 半導体装置の製造方法
US8698308B2 (en) 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
JP5994274B2 (ja) 2012-02-14 2016-09-21 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
TWI469312B (zh) 2012-03-09 2015-01-11 Ind Tech Res Inst 晶片堆疊結構及其製作方法
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US8723309B2 (en) 2012-06-14 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via and method of manufacture thereof
US8759961B2 (en) 2012-07-16 2014-06-24 International Business Machines Corporation Underfill material dispensing for stacked semiconductor chips
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20140070405A1 (en) 2012-09-13 2014-03-13 Globalfoundries Inc. Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
US9368404B2 (en) 2012-09-28 2016-06-14 Plasma-Therm Llc Method for dicing a substrate with back metal
DE102012224310A1 (de) 2012-12-21 2014-06-26 Tesa Se Gettermaterial enthaltendes Klebeband
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
TWI518991B (zh) 2013-02-08 2016-01-21 Sj Antenna Design Integrated antenna and integrated circuit components of the shielding module
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9054063B2 (en) 2013-04-05 2015-06-09 Infineon Technologies Ag High power single-die semiconductor package
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
FR3007403B1 (fr) 2013-06-20 2016-08-05 Commissariat Energie Atomique Procede de realisation d'un dispositif microelectronique mecaniquement autonome
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
JP2015012244A (ja) 2013-07-01 2015-01-19 株式会社東芝 半導体発光素子
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9324698B2 (en) 2013-08-13 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
JP6212720B2 (ja) 2013-09-20 2017-10-18 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
FR3011679B1 (fr) 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
KR102143518B1 (ko) 2013-10-16 2020-08-11 삼성전자 주식회사 칩 적층 반도체 패키지 및 그 제조 방법
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9530730B2 (en) 2013-11-08 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Configurable routing for packaging applications
JP6441025B2 (ja) 2013-11-13 2018-12-19 株式会社東芝 半導体チップの製造方法
US9570421B2 (en) 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9768038B2 (en) 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9343433B2 (en) 2014-01-28 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stacked dies and methods of forming the same
US20150255349A1 (en) 2014-03-07 2015-09-10 JAMES Matthew HOLDEN Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9418924B2 (en) 2014-03-20 2016-08-16 Invensas Corporation Stacked die integrated circuit
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9076860B1 (en) 2014-04-04 2015-07-07 Applied Materials, Inc. Residue removal from singulated die sidewall
US8975163B1 (en) 2014-04-10 2015-03-10 Applied Materials, Inc. Laser-dominated laser scribing and plasma etch hybrid wafer dicing
US9601463B2 (en) 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9601437B2 (en) 2014-09-09 2017-03-21 Nxp B.V. Plasma etching and stealth dicing laser process
US10468381B2 (en) 2014-09-29 2019-11-05 Apple Inc. Wafer level integration of passive devices
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US9673096B2 (en) 2014-11-14 2017-06-06 Infineon Technologies Ag Method for processing a semiconductor substrate and a method for processing a semiconductor wafer
KR102360381B1 (ko) 2014-12-01 2022-02-11 삼성전자주식회사 적층 구조를 갖는 반도체 소자 및 그 제조방법
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
US9508660B2 (en) 2015-02-10 2016-11-29 Intel Corporation Microelectronic die having chamfered corners
DE102015103274A1 (de) 2015-03-06 2016-09-08 HARTING Electronics GmbH Kabelabdichtung
JP6738591B2 (ja) 2015-03-13 2020-08-12 古河電気工業株式会社 半導体ウェハの処理方法、半導体チップおよび表面保護テープ
US10068862B2 (en) 2015-04-09 2018-09-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a package in-fan out package
KR101664411B1 (ko) 2015-06-04 2016-10-14 주식회사 에스에프에이반도체 웨이퍼 레벨의 팬 아웃 패키지 제조방법
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US10352991B2 (en) 2015-07-21 2019-07-16 Fermi Research Alliance, Llc Edgeless large area ASIC
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9754891B2 (en) 2015-09-23 2017-09-05 International Business Machines Corporation Low-temperature diffusion doping of copper interconnects independent of seed layer composition
WO2017052652A1 (en) 2015-09-25 2017-03-30 Intel Corporation Combination of semiconductor die with another die by hybrid bonding
US10032751B2 (en) 2015-09-28 2018-07-24 Invensas Corporation Ultrathin layer for forming a capacitive interface between joined integrated circuit components
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9881882B2 (en) 2016-01-06 2018-01-30 Mediatek Inc. Semiconductor package with three-dimensional antenna
US20170200659A1 (en) 2016-01-08 2017-07-13 International Business Machines Corporation Porous underfill enabling rework
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US20170330855A1 (en) 2016-05-13 2017-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Immersion Bonding
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
KR102521881B1 (ko) 2016-06-15 2023-04-18 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9818729B1 (en) 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
KR102570582B1 (ko) * 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9892961B1 (en) 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
BR112019001313A2 (pt) 2016-08-26 2019-04-30 Intel Corporation estruturas de dispositivo de circuito integrado e técnicas de fabricação de frente e verso
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US11176450B2 (en) 2017-08-03 2021-11-16 Xcelsis Corporation Three dimensional circuit implementing machine trained network
US9722098B1 (en) 2016-10-18 2017-08-01 Ase Electronics (M) Sdn Bhd Semiconductor device package and method of manufacturing the same
US10304801B2 (en) 2016-10-31 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US20180130768A1 (en) 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
CN117878055A (zh) 2016-12-28 2024-04-12 艾德亚半导体接合科技有限公司 堆栈基板的处理
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
US9865567B1 (en) 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10658335B2 (en) 2017-06-16 2020-05-19 Futurewei Technologies, Inc. Heterogenous 3D chip stack for a mobile processor
US10707145B2 (en) 2017-09-08 2020-07-07 Kemet Electronics Corporation High density multi-component packages
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US10332899B2 (en) 2017-09-29 2019-06-25 Intel Corporation 3D package having edge-aligned die stack with direct inter-die wire connections
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10818624B2 (en) 2017-10-24 2020-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for manufacturing the same
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
US10672820B2 (en) 2017-11-23 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonded structure
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11127738B2 (en) 2018-02-09 2021-09-21 Xcelsis Corporation Back biasing of FD-SOI circuit blocks
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US10937743B2 (en) 2018-04-30 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mixing organic materials into hybrid packages
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US10403577B1 (en) 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11469138B2 (en) 2018-05-04 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Via for coupling attached component upper electrode to substrate
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10510629B2 (en) 2018-05-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
WO2019241367A1 (en) 2018-06-12 2019-12-19 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
KR20210009426A (ko) 2018-06-13 2021-01-26 인벤사스 본딩 테크놀로지스 인코포레이티드 패드로서의 ｔｓｖ
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10333623B1 (en) 2018-06-25 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Optical transceiver
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010136A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US20200035641A1 (en) 2018-07-26 2020-01-30 Invensas Bonding Technologies, Inc. Post cmp processing for hybrid bonding
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US10797031B2 (en) 2018-09-20 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US10868353B2 (en) 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic device and manufacturing method thereof
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11158607B2 (en) 2018-11-29 2021-10-26 Apple Inc. Wafer reconstitution and die-stitching
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10770430B1 (en) 2019-03-22 2020-09-08 Xilinx, Inc. Package integration for memory devices
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US11145623B2 (en) 2019-06-14 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11094613B2 (en) 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US20210118864A1 (en) 2019-10-21 2021-04-22 Invensas Corporation Non-Volatile Dynamic Random Access Memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
KR20230095110A (ko) 2020-10-29 2023-06-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 방법 및 구조체
KR20230125309A (ko) 2020-12-28 2023-08-29 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법
JP2024501017A (ja) 2020-12-28 2024-01-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 基板貫通ビアを有する構造体及びそれを形成する方法
US20220208723A1 (en) 2020-12-30 2022-06-30 Invensas Bonding Technologies, Inc. Directly bonded structures
EP4272249A1 (en) 2020-12-30 2023-11-08 Adeia Semiconductor Bonding Technologies Inc. Structure with conductive feature and method of forming same
EP4302325A1 (en) 2021-03-03 2024-01-10 Adeia Semiconductor Bonding Technologies Inc. Contact structures for direct bonding
US20220320036A1 (en) 2021-03-31 2022-10-06 Invensas Bonding Technologies, Inc. Direct bonding and debonding of carrier
EP4315411A1 (en) 2021-03-31 2024-02-07 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
WO2022212595A1 (en) 2021-03-31 2022-10-06 Invensas Bonding Technologies, Inc. Direct bonding and debonding of carrier
WO2023278605A1 (en) 2021-06-30 2023-01-05 Invensas Bonding Technologies, Inc. Element with routing structure in bonding layer
EP4371153A1 (en) 2021-07-16 2024-05-22 Adeia Semiconductor Bonding Technologies Inc. Optically obstructive protective element for bonded structures
JP2024528964A (ja) 2021-08-02 2024-08-01 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ボンデッド構造体用の保護半導体素子
KR20240052815A (ko) 2021-09-01 2024-04-23 아데이아 세미컨덕터 테크놀로지스 엘엘씨 인터포저를 갖는 적층 구조체
US20230067677A1 (en) 2021-09-01 2023-03-02 Invensas Bonding Technologies, Inc. Sequences and equipment for direct bonding
US20230115122A1 (en) 2021-09-14 2023-04-13 Adeia Semiconductor Bonding Technologies Inc. Method of bonding thin substrates
EP4406020A1 (en) 2021-09-24 2024-07-31 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with active interposer
WO2023069323A1 (en) 2021-10-18 2023-04-27 Adeia Semiconductor Technologies Llc Reduced parasitic capacitance in bonded structures
WO2023069912A1 (en) 2021-10-19 2023-04-27 Adeia Semiconductor Bonding Technologies Inc. Stacked inductors in multi-die stacking
EP4420197A1 (en) 2021-10-22 2024-08-28 Adeia Semiconductor Technologies LLC Radio frequency device packages
CN118355491A (zh) 2021-10-25 2024-07-16 美商艾德亚半导体接合科技有限公司 堆叠电子器件的功率分配
US20230125395A1 (en) 2021-10-27 2023-04-27 Adeia Semiconductor Bonding Technologies Inc. Stacked structures with capacitive coupling connections
WO2023076495A1 (en) 2021-10-28 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Diffusion barriers and method of forming same
US20230142680A1 (en) 2021-10-28 2023-05-11 Adeia Semiconductor Bonding Technologies Inc. Stacked electronic devices
US20230140107A1 (en) 2021-10-28 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
WO2023081273A1 (en) 2021-11-05 2023-05-11 Adeia Semiconductor Bonding Technologies Inc. Multi-channel device stacking
US20230154816A1 (en) 2021-11-17 2023-05-18 Adeia Semiconductor Bonding Technologies Inc. Thermal bypass for stacked dies
CN118613910A (zh) 2021-11-18 2024-09-06 美商艾德亚半导体接合科技有限公司 用于裸片堆叠的流体冷却
US20230187264A1 (en) 2021-12-13 2023-06-15 Adeia Semiconductor Technologies Llc Methods for bonding semiconductor elements
CN118613904A (zh) 2021-12-13 2024-09-06 美商艾德亚半导体接合科技有限公司 互连结构
KR20240118874A (ko) 2021-12-17 2024-08-05 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합을 위한 전도성 특징부를 갖는 구조체 및 그 형성 방법
US20230197560A1 (en) 2021-12-20 2023-06-22 Adeia Semiconductor Bonding Technologies Inc. Thermoelectric cooling in microelectronics
WO2023122509A1 (en) 2021-12-20 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Thermoelectric cooling for die packages
US20230197496A1 (en) 2021-12-20 2023-06-22 Adeia Semiconductor Bonding Technologies Inc. Direct bonding and debonding of elements
KR20240126868A (ko) 2021-12-22 2024-08-21 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 낮은 스트레스 직접 하이브리드 접합
WO2023122687A1 (en) 2021-12-23 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Apparatuses and methods for die bond control
KR20240119164A (ko) 2021-12-23 2024-08-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 패키지 기판 상의 직접 결합
CN118648105A (zh) 2021-12-23 2024-09-13 美商艾德亚半导体接合科技有限公司 具有互连组件的键合结构
US20230207402A1 (en) 2021-12-27 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Directly bonded frame wafers
WO2023147502A1 (en) 2022-01-31 2023-08-03 Adeia Semiconductor Bonding Technologies Inc. Heat dissipating system for electronic devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130169355A1 (en) * 2012-01-04 2013-07-04 Kuan-Neng Chen Integrated Circuit Device
US20150235949A1 (en) * 2014-02-20 2015-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Functional Block Stacked 3DIC and Method of Making Same

Also Published As

Publication number Publication date
TW202006890A (zh) 2020-02-01
US11837582B2 (en) 2023-12-05
US11158606B2 (en) 2021-10-26
US20200013754A1 (en) 2020-01-09
US20240243103A1 (en) 2024-07-18
WO2020010136A1 (en) 2020-01-09
US20230253367A1 (en) 2023-08-10
US11764189B2 (en) 2023-09-19
US20220020729A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
TWI834682B (zh) 模製直接接合且互連的堆疊
TWI664685B (zh) 具有無矽基底的中介層的封裝及其形成方法
TWI591798B (zh) 用於保護防止機械薄化和其它目的之具有剛性層的積體電路組件和製造此組件之方法
US9905507B2 (en) Circuit assemblies with multiple interposer substrates, and methods of fabrication
US10083919B2 (en) Packaging for high speed chip to chip communication
US20120149150A1 (en) Vented die and package
WO2015183959A1 (en) Structure and method for integrated circuits packaging with increased density
TW201533861A (zh) 製造半導體封裝體的方法
CN102543927A (zh) 嵌埋穿孔中介层的封装基板及其制造方法
US10211139B2 (en) Chip package structure
TWI773400B (zh) 半導體元件及其製造方法
TWI776693B (zh) 封裝結構及其形成方法
TWI585932B (zh) 晶片封裝結構
US9013040B1 (en) Memory device with die stacking and heat dissipation
TW202427685A (zh) 模製直接接合且互連的堆疊
CN112385036A (zh) 模制的直接键合和互连的堆叠
CN110828430A (zh) 一种封装结构及其制备方法
CN210516718U (zh) 一种封装结构
TWI834469B (zh) 半導體封裝及其製造方法
CN210692483U (zh) 一种封装结构
TWI710090B (zh) 半導體封裝結構及其製造方法
TW202046417A (zh) 堆疊微電子構件的中間層連接