TWI698925B - 堆疊晶粒和形成接合結構的方法 - Google Patents
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- TWI698925B TWI698925B TW108120324A TW108120324A TWI698925B TW I698925 B TWI698925 B TW I698925B TW 108120324 A TW108120324 A TW 108120324A TW 108120324 A TW108120324 A TW 108120324A TW I698925 B TWI698925 B TW I698925B
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Abstract
在各個實施例中,揭示一種用於形成一接合結構之方法。該方法可包含將一第一整合裝置晶粒裝配至一載體。在裝配之後,可薄化該第一整合裝置晶粒。該方法可包括在該第一整合裝置晶粒之一暴露表面上提供一第一層。可移除該第一層之至少一部分。可在無一介入黏著劑之情況下將一第二整合裝置晶粒直接接合至該第一整合裝置晶粒。
Description
本領域係關於具有保護材料之接合結構及用於形成具有保護材料之接合結構之方法。
在各種封裝配置中,可有利的是提供薄化整合裝置晶粒,例如,使能夠在低剖面封裝(low-profile package)內使用多個整合裝置晶粒。舉例而言,三維(3D)整合技術常常利用兩個或多於兩個整合裝置晶粒堆疊於彼此之上且彼此電連接的封裝。用於晶粒薄化及/或3D整合之習知方法可具有有限的產品良率,此係因為在組裝期間賦予至晶粒之應力可損壞堆疊中之晶粒。此外,可具挑戰性的是堆疊具有不同厚度且可源自不同類型之基板及/或晶圓的晶粒。因此,仍不斷地需要用於堆疊整合裝置晶粒之改良型系統及方法。
本發明之一態樣包含一種用於形成一接合結構之方法,該方法包含:將一第一單粒化整合裝置晶粒裝配至一載體;在裝配之後,薄化該第一整合裝置晶粒;及在該第一整合裝置晶粒之一暴露表面上提供包含一第一層之一保護材料。
本發明之另一態樣包含一種接合結構,其包含:一載體;一第一整合裝置晶粒,其具有裝配至該載體之一上表面的一下表面,該第一整合裝置晶粒包含與該下表面相對之一上表面及在該第一整合裝置晶粒之該上表面與該下表面之間的一側表面;及一保護材料,其包含具有安置於該第一整合裝置晶粒之該側表面上之一第一部分的一第一層,該第一層硬於該第一整合裝置晶粒之側表面。
本發明之一另外態樣包含一種電子裝置,其包含如本文中所描述之接合結構。
本發明之一另外態樣包含一種用於形成一接合結構之方法,該方法包含:將一第一整合裝置晶粒裝配至一載體;及在裝配之後,在該第一整合裝置晶粒之一表面上提供包含一第一層之一保護材料;及平坦化該第一層之至少一部分以移除該第一整合裝置晶粒之一部分。
本文中所揭示之各個實施例使單粒化整合裝置晶粒能夠被裝配至封裝結構(例如,封裝基板、晶圓、另一整合裝置晶粒等等)且在裝配之後被薄化。薄化單粒化整合裝置晶粒可輔助封裝組裝之各個態樣,包括(例如)暴露或形成互連件(諸如直通矽穿孔(through-silicon via)或TSV)。然而,藉由拋光或研磨來薄化晶粒可在晶粒中誘發應力,此可損壞或破壞晶粒之邊緣。在一些實施例中,可將保護材料(其可包含一或多個保護層)施加於整合裝置晶粒上方及/或周圍以在薄化期間及在一些配置中在後續處理步驟期間保護晶粒。
此外,本文中所揭示之各個實施例促進以改良型良率高效地堆疊整合裝置晶粒以及縮減賦予至晶粒之損壞及應力。整合裝置封裝及較大電子系統可併有不同類型之整合裝置晶粒,例如,具有不同功能性之晶粒、由不同材料集形成之晶粒,及/或具有不同厚度之晶粒。可具挑戰性的是將此等多樣整合裝置晶粒併入至封裝中及/或以堆疊關係配置不同類型之晶粒。舉例而言,可難以接合由不同材料形成或被塗佈有不同材料之兩個晶粒。材料失配可針對堆疊晶粒引入熱及/或化學鍵結挑戰。此外,堆疊具有不同厚度之晶粒可不必要地增加總封裝高度及/或可涉及對準挑戰。有利地,本文中所揭示之實施例亦使能夠堆疊具有任意初始厚度之整合裝置晶粒。
因此,在各個實施例中,可將第一整合裝置晶粒裝配至載體,諸如基板(例如,晶圓、印刷電路板、平板、玻璃表面、包含介電層之表面、包含導電層或區段之表面等等)。在將第一晶粒裝配至載體之後,可薄化第一整合裝置晶粒。有利地,可在載體上將第一整合裝置晶粒及後續晶粒薄化至所要厚度。在各個實施例中,可使薄化晶粒超薄,此可縮減總封裝高度且使能夠在特定晶粒堆疊內使用眾多晶粒。薄化亦可促進暴露先前形成之互連件,或在薄化之後形成互連件,諸如直通矽穿孔(TSV)。在一些配置中,可將多個晶粒彼此鄰近地裝配於載體上,且可使用研磨程序、拋光程序、蝕刻程序或任何其他合適程序來薄化多個晶粒。在一些配置中,舉例而言,當藉由研磨來薄化及/或平坦化多個鄰近晶粒時,晶粒之邊緣可經受應力,此可造成晶粒之邊緣破壞、開裂或以其他方式損壞。為了縮減晶粒邊緣損耗之發生率,可藉由諸如濕式蝕刻或乾式蝕刻或其組合之低應力移除方法而自晶粒邊緣移除額外材料。
在一些實施例中,可運用蝕刻程序來薄化第一整合裝置晶粒(及鄰近裝置晶粒)。薄化可暴露有用於電連接堆疊晶粒之互連件(例如,直通矽穿孔、跡線、接觸襯墊等等),或可促進形成此等互連件。安置於載體上之第一晶粒可被塗佈有保護材料,包括用以在研磨或拋光操作期間保護晶粒(包括晶粒邊緣)之第一保護層。在一些實施例中,可將第二層提供於第一層上方以填充第一層中之橫向間隙。可移除第二層及第一層之至少一部分。第二層及第一層之部分之移除可暴露通過第一整合裝置晶粒所形成之一或多個電互連件。可將第二整合裝置晶粒堆疊於第一整合裝置晶粒上。在一些實施例中,在無介入黏著劑之情況下將第二晶粒之非導電區域直接接合至第一晶粒之對應非導電區域。在一些實施例中,在無介入黏著劑之情況下將第二晶粒之非導電區域及電互連件兩者分別直接接合至第一晶粒之對應非導電區域及電互連件。
圖1A至圖1F為根據一個實施例的用於形成接合結構1之方法之各種階段的示意性側視橫截面圖。在圖1A中,可將一或多個第一整合裝置晶粒3(其可包含第一晶粒3a、3b)裝配至包含基板2之載體。基板2可包含任何合適類型之基板或插入物。舉例而言,在一些實施例中,基板2可包含矽基板(例如,晶圓之部分或全部)、玻璃基板,或絕緣體上矽(silicon on insulator;SOI)基板。將矽、玻璃或其他半導體材料用於基板2可有利地使基板2之上表面8能夠被拋光至極低表面粗糙度,使得可將第一晶粒3a、3b直接接合至基板2。舉例而言,此矽基板2可呈插入物之形式。然而,在其他實施例中,基板2可包含印刷電路板(PCB)、陶瓷基板、聚合物基板或任何其他合適基板,且在基板與裝置晶粒之間可或可不具有黏著層。雖然圖1A至圖1F所展示之載體包含基板,但在其他實施例中,第一整合裝置晶粒3被裝配至之載體可包含一或多個裝置晶粒、光學裝置,或任何合適主動或被動裝置。
第一整合裝置晶粒3可包含任何合適類型之裝置晶粒。舉例而言,第一晶粒3a、3b中之每一者可包含處理器晶粒、記憶體晶粒、微機電系統(microelectromechanical systems;MEMS)晶粒、被動組件、光學裝置,或任何其他合適類型之裝置晶粒。在各個實施例中,可在第一晶粒3a、3b之主動表面6處或附近圖案化電路系統(諸如類似於電晶體之主動組件)。主動表面6可在與第一晶粒3a、3b之各別背側18相對的第一晶粒3a、3b之側上。背側18可或可不包括任何主動電路系統或被動裝置。第一晶粒3a、3b可為相同類型之整合裝置晶粒或不同類型之裝置晶粒。如圖1A所展示,第一晶粒3a可沿著基板2之表面而與晶粒3b橫向地隔開間隙7。在一個實施例中,鄰近晶粒之間的間距7與該等第一晶粒3a或3b之厚度相當。在其他實施例中,鄰近晶粒之間的間距7小於第一晶粒3a或3b之厚度的10倍,例如,較佳地小於第一晶粒3a或3b之厚度的5倍。在另一實施例中,鄰近晶粒之間的間隙7可小於該等晶粒之橫向尺寸中之一者。雖然圖1A中展示僅兩個第一晶粒3a、3b,但應瞭解,可將多於或少於兩個第一晶粒3a、3b裝配至基板2。另外,在一些實施例中,可在將第一晶粒3a、3b裝配至基板2之前測試第一晶粒3a、3b之適當電功能性。在一些實施例中,可僅選擇良裸晶粒(known good die;KGD)以供裝配至基板2。在其他實施例中,可在將晶粒裝配至基板2之後測試晶粒之電功能性。圖1A之第一晶粒3a、3b包含具有各種主動(及/或被動)組件之整合裝置晶粒。在其他實施例中,可將一或多個離散被動裝置裝配至基板而不形成為整合裝置晶粒之部分。
可在基板2之上表面8上之一或多個層中提供導電元件以提供至其他裝置之電連接及/或至基板2內之其他組件之佈線。在一些實施例中,一或多個層可包含佈線層34及緩衝層5,如圖1A所展示。佈線層34可包含重佈層(redistribution layer;RDL)或後段製程(back end of line;BEOL)層。舉例而言,在各個實施例中,佈線層34可包含銅、金、鋁、銦、鎵、錫、鎳、其各別合金或任何其他合適導電材料。佈線層34可經圖案化以在各種電路元件之間及/或在電路元件與基板2被連接至之較大電子系統之間橫越基板2引導電信號。舉例而言,在一些實施例中,佈線層34可包含具有嵌入式及圖案化金屬跡線之BEOL介電層。在各個實施例中,佈線層34可包含一個層或多個層。緩衝層5可在基板2與第一晶粒3a、3b之間提供於佈線層34上方。緩衝層5可包含非導電層,諸如聚合物層(例如,聚醯亞胺或氧化物)。在各個實施例中,緩衝層5可包含單一層或多個層。緩衝層5可相對柔順以便在第一晶粒3a、3b與基板2之間提供減震以考量機械及/或熱失配。緩衝層5可具有在1微米至10微米之範圍中或在3微米至6微米之範圍中的厚度,例如,在4微米至5微米之範圍中。應瞭解,雖然圖1A中說明兩個層(例如,緩衝層5及佈線層34),但在一些實施例中,可使用包括導電元件(其可嵌入於絕緣材料中)之僅一個層。
可通過每一第一晶粒3a、3b之至少一部分形成一或多個電互連件10。每一互連件10可形成於非導電襯套9內部。在各個實施例中,可使用形成一或多個空腔之鑲嵌程序來形成互連件10及非導電襯套9,且可將非導電襯套9及互連件10沉積於空腔(例如,溝槽)中。在各個實施例中,互連件10可包含直通基板穿孔(through substrate via;TSV)、跡線或此兩者。在一些實施例中,互連件10可包含暴露於第一晶粒3a、3b之表面處的跡線或接觸襯墊。如圖1A所展示,可製造第一晶粒3a、3b,使得互連件10自主動表面6延伸通過第一晶粒3a、3b之初始厚度ti
之部分。在圖1A中,將互連件10說明為不始終延伸至第一晶粒3a、3b之背側18,但在其他實施例中,互連件10可延伸至背側18。互連件10可電連接至形成於第一晶粒3a、3b之主動表面6處或附近的電路元件。互連件10可與基板2之緩衝層5及/或佈線層34中之對應襯墊或跡線電耦接。
有利地,本文中所揭示之方法可與具有任何合適初始厚度ti
(包括薄晶粒、厚晶粒、中等大小晶粒,或任何其他任意晶粒厚度)之第一晶粒3a、3b一起被利用。此外,雖然圖1A所展示之第一晶粒3a、3b具有大致相同的初始厚度ti
,但在一些實施例中,鄰近第一晶粒3a、3b之初始厚度ti
可不同。舉例而言,在一些實施例中,第一晶粒3a、3b之初始厚度ti
可在3微米至2000微米之範圍中,或更特定言之,在5微米至200微米之範圍中,或更特定言之,在5微米至100微米之範圍中。
可使用任何合適方法將第一晶粒3a、3b附接至基板2。舉例而言,在所說明之實施例中,可在無介入黏著劑之情況下將第一晶粒3a、3b直接接合至基板2。在直接接合配置中,第一晶粒3a、3b之非導電區域20可與基板2之對應非導電區域直接接觸及直接接合。主動表面6處之接合襯墊或跡線(諸如連接至導電互連件10之接合襯墊或跡線)可接觸及直接接合至佈線層34之對應金屬襯墊(或跡線或其他導電特徵),該等金屬襯墊可通過緩衝層5中之開口而暴露,且可凸出或凹入。
在一些實施例中,主動表面6處之接合襯墊或跡線中之一些或全部(諸如連接至導電互連件10之接合襯墊或跡線)可直接接合至佈線層34之非導電特徵。在此等實施例中,在後續步驟中,可自背側薄化基板2,且可自薄化基板2形成導電接點以電耦接至第一晶粒3a及/或3b之主動表面上的導電接合襯墊或跡線。在其他實施例中,可運用任何合適黏著劑(諸如焊料、導電環氧樹脂、各向異性導電膜等等)將第一晶粒3a、3b黏附至基板2。
為了實現直接接合,在一些實施例中,可製備第一晶粒3a、3b與基板2之接合表面以供接合。可將第一晶粒3a、3b拋光至極高平滑度(例如,小於20 nm表面粗糙度,或更特定言之,小於5 nm表面粗糙度)。在一些實施例中,可將接合層11(例如,諸如氧化矽之介電質)沉積於第一晶粒3a、3b之主動表面6上且拋光至極高平滑度。相似地,可將基板2之接合表面(例如,基板2之上表面8或緩衝層5之上表面)拋光至極高平滑度(例如,小於20 nm表面粗糙度,或更特定言之,小於5 nm表面粗糙度)。在一些實施例中,可氟化接合表面(例如,緩衝層5、基板2之上表面8、接合層11,及/或主動表面6)以改良接合。接合表面亦可包括導電特徵,諸如接合襯墊。在一些實施例中,可運用合適物種將待接合表面進行封端且在接合之前進行活化。舉例而言,在一些實施例中,可極輕地蝕刻待接合表面以供活化且暴露於含氮溶液,且運用含氮物種進行封端。作為一個實例,可在極輕微的蝕刻之後將待接合表面暴露於氨浸液,及/或暴露於含氮電漿(運用或不運用單獨蝕刻)。
一旦製備表面,就可使第一晶粒3a、3b之非導電區域20與基板2之對應非導電區域接觸。活化表面之相互作用可致使第一晶粒3a、3b之非導電區域20在無介入黏著劑之情況下、在不施加外部壓力之情況下、在不施加電壓之情況下及在室溫下與基板2之對應非導電區域直接接合。在各個實施例中,非導電區域之接合力可為大於凡得瓦爾鍵(Van der Waals bond)之共價鍵,且在第一晶粒3a之表面上之導電特徵與基板2之對應接觸襯墊之間施加顯著力。在一些實施例中,互連件10及/或接觸襯墊與第一晶粒3a、3b及基板2之外表面齊平。在其他實施例中,互連件10及/或接觸襯墊可在第一晶粒3a、3b及基板2之外表面上方延伸。在再其他實施例中,互連件10及/或接觸襯墊相對於第一晶粒3a、3b及基板2之外表面(例如,氧化物場區域)凹入。在各個實施例中,可在接合之後加熱基板2及第一晶粒3a、3b以加強非導電區域之間、導電區域之間及/或對置的導電區域與非導電區域之間的接合,以致使第一晶粒3a、3b與基板2接合。可貫穿美國專利第7,126,212號、第8,153,505號、第7,622,324號、第7,602,070號、第8,163,373號、第8,389,378號及第8,735,219號以及貫穿美國專利申請案第14/835,379號、第62/278,354號及第62/303,930號找到直接接合程序之額外細節,該等專利及專利申請案中之每一者之內容特此以引用的方式全部且出於所有目的而併入本文中。
雖然圖1A之實施例說明直接接合至基板2之第一晶粒3a、3b,但在其他實施例中,第一晶粒3a、3b可以其他方式裝配至基板2。舉例而言,在其他實施例中,第一晶粒3a、3b可運用焊球或其他電接點而連接至基板2。在再其他實施例中,第一晶粒3a、3b可運用各向異性導電膜或非導電膏而與基板2連接。
轉至圖1B,將第一晶粒3a、3b之背側18自初始厚度ti
薄化至最終厚度tf
,如在第一晶粒3a、3b之背表面19與對置前表面之間所界定。舉例而言,如圖1B所展示,可使用合適蝕刻劑來蝕刻背側18達足以暴露互連件10及非導電襯套9之時間段。在一些實施例中,使用矽反應性離子蝕刻(reactive ion etch;RIE)技術來蝕刻第一晶粒3a、3b。可使用其他類型之薄化技術以薄化第一晶粒3a、3b。舉例而言,可使用其他類型之蝕刻程序,包括熟習此項技術者所知之各向異性或各向同性蝕刻技術(例如,乾式或濕式蝕刻程序)。可薄化第一晶粒3a、3b直至第一晶粒3a、3b具有所要最終厚度tf
。一旦薄化,互連件10及非導電襯套9就可在第一晶粒3a、3b之暴露的背表面19上方延伸且可通過第一晶粒3a、3b之暴露的背表面19而暴露。如圖1B所展示,在使用選擇性矽蝕刻之情況下,互連件10之遠側暴露末端可包含非導電襯套9之遠側襯套部分9a,其對應於在鑲嵌處理期間沉積於溝槽之底部中的非導電襯套9之部分。
在各個實施例中,第一晶粒3a、3b之最終厚度tf
可小於40微米、小於30微米或小於20微米。第一晶粒3a、3b之最終厚度tf
可在5微米至30微米之範圍中,或更特定言之,在5微米至15微米之範圍中,或更特定言之,在5微米至10微米之範圍中。第一晶粒3a、3b之最終厚度tf
可相同或可彼此不同。在各個實施例中,第一晶粒3a、3b之最終厚度tf
可小於300微米、小於200微米或小於100微米。在一些實施例中,第一晶粒3a、3b之最終厚度tf
可在40微米至100微米之範圍中。
轉至圖1C,可將保護材料提供於第一晶粒3a、3b上方及在鄰近第一晶粒3a、3b之間的基板2之部分上方。在一些實施例中,保護材料可包含沉積(例如,運用電漿沉積程序以促進較低溫度)於緩衝層5(或在不存在緩衝層之情況下為基板2之上表面8)上方及第一晶粒3a、3b之背表面19上方的第一層12以塗佈緩衝層5(或在不存在緩衝層之情況下為基板2之上表面8)及第一晶粒3a、3b。在其他實施例中,可將第一層12層壓於基板2及第一晶粒3a、3b上。在其他實施例中,可藉由鑄漿成型方法、絲網印刷或塗佈或旋塗、3D印刷方法或藉由電泳方法或其組合來沉積第一層12。如圖1C所展示,第一層12可具有可不小於第一晶粒3a、3b之最終厚度tf
的厚度tc
。所施加之第一層12之厚度tc
可在0.5微米至50微米之範圍中,在1微米至35微米、5微米至30微米之範圍中,或更特定言之,在2微米至25微米之範圍中,或更特定言之,在5微米至15微米之範圍中,或在2微米至15微米之範圍中,或在5微米至10微米之範圍中。所施加之第一層12之厚度tc
可小於40微米,小於30微米或小於20微米。此外,如圖1C所展示,第一層12可包括安置於第一晶粒3a、3b之間的間隙7中的第一部分13及安置於第一晶粒3a、3b之背表面19上方的第二部分14。第二部分14可安置於暴露電互連件10及非導電襯套9周圍且可環繞暴露電互連件10及非導電襯套9。
有利地,第一層12可充當保護層以在後續處理步驟期間保護第一晶粒3a、3b。舉例而言,如下文結合圖1E所闡釋,可平坦化部分形成之接合結構1之背側。保護性第一層12可在移除操作(例如,拋光)期間有利地保護第一晶粒3a、3b(諸如晶粒邊緣),以防止第一晶粒3a、3b之邊緣及其他部分破裂或以其他方式損壞。因此,第一層12可在後續處理步驟期間有效地鎖定及密封第一晶粒3a、3b以保護第一晶粒3a、3b之結構完整性。
在一些實施例中,第一層12可硬於第一晶粒3a、3b之暴露的背表面19。第一層12相較於未填充之聚醯亞胺或環氧樹脂塗層可硬且緻密,以便保護第一晶粒3a、3b。舉例而言,第一層12可具有在12 GPa至500 GPa之範圍中的相對高楊氏模數(Young's modulus),或更特定言之,在20 GPa至200 GPa之範圍中。有益地,第一層12可具有與基板2之熱膨脹係數實質上匹配的熱膨脹係數。使熱膨脹係數匹配可有利地縮減第一晶粒3a、3b上之熱誘發性應力。在一些實施例中,第一層12之熱膨脹係數可在第一晶粒3a、3b之熱膨脹係數的25 ppm/℃內,或更特定言之,在第一晶粒3a、3b之熱膨脹係數的20 ppm//℃內。舉例而言,第一層12之熱膨脹係數可在0.3 ppm/℃至22 ppm/℃之範圍中,在0.5 ppm/℃至至15 ppm/℃之範圍中,在2 ppm/℃至15 ppm/℃之範圍中,或更特定言之,在0.5 ppm/℃至12 ppm/℃之範圍中,或更特定言之,在2 ppm/℃至10 ppm/℃之範圍中。
此外,可重要的是選擇第一層12,使得其具有足夠高的玻璃轉變溫度(glass transition temperature;GTT)。後續處理步驟可涉及將部分形成之接合結構1加熱至高溫。舉例而言,可在後續導電層(諸如RDL層)之處理期間及/或在接合期間將接合結構1加熱至大於150℃、大於200℃或大於250℃之溫度。一些聚合物、環氧樹脂及其他材料可在此高溫處理期間顯著地軟化。可重要的是針對第一層12選擇可耐受高溫處理且維持其幾何剖面及/或在各種熱處理步驟期間不會不可逆地變形之材料。因此,可有利的是選擇具有高GTT之第一層12,例如,GTT大於100℃、大於150℃、大於200℃、大於250℃或大於300℃。在一些實施例中,對於交聯材料,第一層之GTT可小於100℃,其限制條件為帕松比(Poisson ratio)大於0.4且較佳地接近於0.5,例如,帕松比在0.25至0.8之範圍中,且熱分解溫度大於250℃或大於300℃。在一些實施例中,如本文中所闡釋,聚合物材料可用於第一層12(及/或用於諸如下文所描述之第二層15的額外保護層)。聚合物材料或基質可具有大於150℃、大於200℃、大於250℃、大於300℃或大於350℃之熔點,例如,在一些實施例中大於280℃。
因此,可重要的是選擇具有高楊氏模數之勁及/或硬的第一層12,其具有相似於基板之熱膨脹係數(例如,在矽或玻璃基板之狀況下相似於矽或玻璃之熱膨脹係數)的熱膨脹係數,且其具有超過用以形成接合結構1之最高處理溫度的玻璃轉變溫度或GTT。舉例而言,在一些實施例中,第一層12可包含矽、無機氧化物、無機氮化物、無機碳化物或碳酸鹽,例如,氧化矽、氮化矽、碳化矽、類鑽碳(diamond like carbon;DLC)或其他類型之半導體材料及非半導體材料。在其他實施例中,可使用聚合物。舉例而言,第一層12可包含聚醯亞胺或聚醯亞胺-醯胺。在一些實施例中,第一層12可包含Torlon®
。在一些實施例中,如本文中所闡釋,第一層12可包含填充有填料粒子(諸如氧化物或氮化物粒子、碳酸鹽、雲母、經處理或未經處理之高嶺土、滑石,或經處理或未經處理之黏土材料,例如,膨潤土等等)之基底材料(諸如聚合物)。填料粒子可輔助縮減第一層12之熱膨脹係數及致使第一層12之CTE較接近於基板2之CTE。填料粒子可增加第一層12之硬度或勁度。填料含量可在10%至90%之間變化,例如,在20%與85%之間,或更特定言之,在30%與80%之間。填料粒子之大小可在2 nm至小於20微米之範圍中,例如,在50 nm與5微米之間。在一個實施例中,填料微粒之平均大小小於安置於第一晶粒3a及3b之間的間隙7之30%。在其他實施例中,填料微粒之平均大小小於第一晶粒3a及3b之間的間隙7之10%,例如,小於第一晶粒3a及3b之間的間隙7之2%。在一些實施例中,間隙7中的填料微粒之平均大小小於最終晶粒厚度tf
之30%,例如,填料粒子中之至少一些小於晶粒之最終厚度tf
之5%。在一些實施例中,第一晶粒3a或3b之垂直側壁上或鄰近處的微粒之寬度或長度小於第一晶粒3a或3b之最終厚度tf
之15%。因為在所說明之實施例中已經薄化第一晶粒3a、3b,所以此等材料可與第一層12一起被使用,而不會引入過多應力或過多成本。
在圖1D中,可將第二層15提供於第一層12上。第二層15可包含填充第一層12中之空間或間隙以促進平坦化的填料層。第二填料層15可包含上文針對第一層12所敍述之類型之微粒。如圖1D所展示,第二層15可包含在第一層12之第二部分14(其提供於第一晶粒3a、3b之背表面19上方)之間橫向地安置於第一部分13上方的第三部分16。第二層15亦可包括安置於第一層12之第二部分14上方的第四部分17。因此,如圖1D所展示,第二層15可充當填充第一層12之間隙的平坦化層,且無需具有上文針對第一層12所提到之硬度或CTE特性。第二層15可包含任何合適材料,諸如聚合物(例如,在一些實施例中為硬烘烤之平坦化負型光阻,或鑄漿成型或層壓之平坦化層)。
轉至圖1E,可研磨及/或拋光部分形成之接合結構1之背側,使得移除第二層15之至少部分及第一層12之至少部分。舉例而言,可回蝕或回拋光接合結構1,例如,使用化學機械拋光(CMP)技術、機械碾磨技術、研磨技術,或運用(例如)濕式雷射切除方法進行移除,及其組合。在圖1E之實施例中,舉例而言,可大部分地或全部地移除第二層15。可選擇程序以停止於第一層12上。因此,可僅移除第一層12之部分,使得第一層12之第一部分13中之至少一些保持安置於第一晶粒3a、3b之間的間隙7中,且第一層12之第二部分14中之至少一些保持安置於第一晶粒3a、3b上方。
如圖1E所展示,移除步驟可藉由移除在互連件10之遠側末端處的非導電襯套9之遠側襯套部分9a來暴露導電互連件10之遠側末端。在圖1E中,互連件10之末端可在第一晶粒3a、3b上方稍微延伸。有利地,圖1E之移除步驟可在第一晶粒3a、3b上方至少留下第一層12之第二部分14之薄層。剩餘第二部分14可有益地防止互連件10在平坦化期間塗抹至第一晶粒3a、3b上。可製備第一層12之暴露表面(例如,第一部分13及第二部分14之暴露表面)、非導電襯套9及互連件10以供直接接合,如上文所闡釋。
在圖1F中,可將一或多個第二晶粒4(諸如第二晶粒4a、4b)堆疊於第一晶粒3a、3b上且電連接至第一晶粒3a、3b。如上文所闡釋,可製備第一晶粒3a、3b之接合表面及第二晶粒4a、4b之接合表面以供直接接合。舉例而言,可將接合表面拋光至高平滑度,運用合適物種進行活化。可使第二晶粒4a、4b之非導電區域與第一晶粒3a、3b之對應非導電區域接觸以將第二晶粒4a、4b直接接合至第一晶粒3a、3b。運用共價鍵來接合非導電區域之力可在第二晶粒4a、4b之表面上的導電特徵與第一晶粒3a、3b之背側上的對應導電特徵之間誘發內力,此可致使對應導電特徵接合在一起。在一些實施例中,舉例而言,第二晶粒4上之接觸襯墊可與第一整合裝置晶粒3上之對應接觸襯墊直接接合。接觸襯墊可與互連件10連接(及/或可形成互連件10之部分)。後續退火處理可加強各別導電互連件特徵與第二晶粒4a、4b及第一晶粒3a、3b之非導電區域之間的接合。在一些實施例中,第一晶粒3a、3b及第二晶粒4a、4b每一者之互連件10可藉助於在第一晶粒3a、3b之互連件10與第二晶粒4a、4b之互連件10之間提供電連接之跡線而與重佈層或BEOL電連接(例如,藉由直接接合或藉由黏著技術)。
所得接合結構1可因此包括在無介入黏著劑之情況下直接接合至一或多個第一晶粒3a、3b之一或多個第二晶粒4a、4b,第一晶粒3a、3b又直接接合至基板2。在一些實施例中,第一晶粒3a、3b及第二晶粒4a、4b之各別互連件10亦可直接接合在一起。互連件10可包含形成於晶粒3至4中之直通矽穿孔(TSV)及在晶粒之主動表面6處的接觸襯墊。第一層12之第一部分13可橫向地安置於第一晶粒3a、3b之間。第一層之第一部分13可安置於第一晶粒3a、3b之側表面上。第一層12之第二部分14可垂直地安置於第一晶粒3a與第二晶粒4a之間,及第一晶粒3b與第二晶粒4b之間。第一層12之第二部分14可橫向地安置於電互連件10周圍,使得通過第一層12暴露電互連件10。在一些實施例中,可在組裝之後將堆疊第一整合裝置晶粒3、第二晶粒4一起封裝於整合裝置封裝中。在其他實施例中,可單粒化兩個堆疊第一整合裝置晶粒3、第二晶粒4且封裝於單獨整合裝置封裝中。
此外,雖然圖1A至圖1F中未展示,但應瞭解,可將圖1A至圖1F所描繪之程序重複任何合適次數,使得可將額外整合裝置晶粒堆疊於第二晶粒4a、4b之上。可堆疊任何合適數目個及/或類型之整合裝置晶粒以界定接合結構1。舉例而言,整合裝置晶粒(第一晶粒3a、第一晶粒3b、第二晶粒4a、第二晶粒4b)可包含主動及/或被動電子組件。在一些實施例中,一或多個被動插入物可在插入物之對置側上連接晶粒。在一些實施例中,接合結構1可包括間隔物、熱散播器,或具有有限電功能性之其他組件。在一些實施例中,一或多個互連件可用於電屏蔽目的,例如,作為法拉弟籠結構(Faraday cage structure)之成形部件。本文中所描述之薄化晶粒可呈現用於積體電路封裝之較低剖面,且亦縮減互連件之總電阻,特別是在使用直接接合之實施例中,因此增加系統之總速度及封裝之可靠性。
圖2A至圖2K為根據另一實施例的用於形成接合結構1之方法之各種階段的示意性側視橫截面圖,其中在薄化之後形成電互連件10。除非另有提到,否則圖2A至圖2K所展示之參考數字表示與圖1A至圖1F之類似編號組件相同或相似的組件。此外,結合圖1A至圖1F所揭示之程序、材料、功能性及結構中之任一者可用於圖2A至圖2K之實施例中。不同於圖1A至圖1F之實施例,可在薄化之前形成保護材料,且可在薄化之後形成互連件10。
如同圖1A至圖1F,在圖2A中,可將第一晶粒3a、3b(其可包含KGD)裝配(例如,直接接合)至基板2。第一晶粒3a、3b可具有初始厚度ti
。然而,在圖2B中,在薄化第一晶粒3a、3b之前,可將第一層12施加於第一晶粒3a、3b之背側18上方及第一晶粒3a、3b之間的間隙7中。如同圖1A至圖1F,可沿著第一晶粒3a、3b之側及沿著第一晶粒3a、3b之間的間隙7中之基板2安置第一層12之第一部分13。第一層12可包含上文結合圖1A至圖1F所描述之材料及性質中之任一者。第一層12可具有經選擇及處理使得不超過所要最終晶粒厚度ti
且縮減或消除整個層壓物接合結構1(參見圖2D)之翹曲的厚度。
轉至圖2C,可將第二層15沉積或以其他方式提供於第一層12上方。如同圖1D之實施例,可將第二層15之第三部分16安置於第一晶粒3a、3b之間的間隙7中,包括(例如)在第一層12之第一部分13之側表面之間。可將第二層15之第四部分17安置於第一層12之第二部分14上方。如上文所闡釋,第二層15可充當填料材料以促進接合結構1之背側之平坦化。在一些配置中,第二層15相比於第一層12可較不昂貴且較不硬。
轉至圖2D,可移除部分形成之接合結構1之背側以移除第二層15之至少部分(例如,全部)、第一層12之部分及第一晶粒3a、3b之部分以暴露第一晶粒3a、3b之暴露的背表面19。舉例而言,可研磨及/或搭接部分形成之接合結構1以將第一晶粒3a、3b薄化至所要最終厚度tf
,其可在與上文結合圖1A至圖1F所闡釋之範圍相同的範圍中。在圖2D中,第一層12之第一部分13之至少部分橫向地安置於第一晶粒3a、3b之間,包括(例如)沿著第一晶粒3a、3b之側。保護材料之第一層12因此保護晶粒之邊緣在晶粒薄化程序期間免於碎裂。
在圖2E中,可將佈線介電層22(其可包含氧化矽或其他合適絕緣體或半導體材料)沉積或以其他方式形成於部分形成之接合結構1之背側上方。舉例而言,視需要,可將佈線介電層22提供於第一層12之第一部分13上方及第一晶粒3a、3b之暴露的背表面19上方,且拋光至低粗糙度(例如,小於約0.5 nm RMS)。轉至圖2F,可將遮罩24沉積於佈線介電層22上方且可圖案化以界定用於互連件之位置。舉例而言,在一些實施例中,遮罩24可包含可經遮蔽及暴露於光源之光阻。對於正型抗蝕劑實例,可使用合適顯影劑來移除未經遮蔽之暴露部分以在遮罩24中界定圖案化空間25。在圖2G中,可使用合適材料移除程序(諸如蝕刻)來形成一或多個通孔或跡線26。舉例而言,可將蝕刻劑供應至部分形成之接合結構以通過在未由遮罩24覆蓋之位置處的第一晶粒3a、3b之厚度蝕刻通孔26。可使用任何合適蝕刻程序(例如,濕式蝕刻、乾式蝕刻、RIE等等)以界定通孔26。在一些實施例中,接合層5可充當蝕刻終止層。在其他實施例中,基板2之佈線層34或上表面可充當蝕刻終止層。在一些實施例中,可使用單或雙鑲嵌蝕刻程序以在佈線介電層22中界定通孔及溝槽,例如,用於形成重佈層(RDL)。在一些實施例中,鑲嵌結構之溝槽可延伸至薄化第一晶粒3a及/或3b中。
轉至圖2H,可移除遮罩24且清潔表面以自先前蝕刻方法移除非想要的污染物。可供應非導電襯套9及導電互連件10以填充通孔26。舉例而言,在一些實施例中,將障壁層沉積於第一晶粒3a、3b之半導體材料上方,且形成晶種層。可將通孔26(及任何橫向溝槽)填充有金屬以界定互連件10。在一些配置中,可將接合結構1退火以使金屬互連件10穩定或部分地穩定,且可拋光互連件10(及部分形成之接合結構1之背側),例如,使用CMP程序。圖2I說明在一些實施例中可將一或多個測試襯墊28併入於佈線介電層22內或上。測試襯墊28可用以促進在組裝期間對第一晶粒3a、3b與基板2之間的連續性進行電測試。
轉至圖2J,可將一或多個第二晶粒4a、4b堆疊於第一晶粒3a、3b上且與第一晶粒3a、3b直接接合。在圖2J中,測試襯墊28亦可用以促進在組裝期間對第一晶粒3a與第二晶粒4a之間、第一晶粒3b與第二晶粒4b之間、第一晶粒3a與第二晶粒4b之間及/或第一晶粒3b與第二晶粒4a之間的連續性進行電測試。圖2K說明相似於圖2J之接合結構1的替代例,惟測試襯墊28係運用通孔29而連接至基板2除外。如上文所闡釋,第二晶粒4a、4b之表面上的互連件或導電特徵可與第一晶粒3a、3b之背表面之對應互連件或導電特徵直接接合。第二晶粒4a、4b之非導電區域亦可與第一晶粒3a、3b之對應非導電區域直接接合。在圖2J至圖2K之實施例中,將第二晶粒4a、4b說明為在薄化之前包括互連件10。在此配置中,可使用圖1A至圖1F之實施例以薄化第二晶粒4a、4b且製備第二晶粒4a、4b以用於與第三組晶粒(圖中未示)接合。然而,在其他實施例中,應瞭解,第二晶粒4a、4b在薄化之前可不包括互連件,且圖2A至圖2I之實施例可用以薄化第二晶粒4a、4b且在薄化之後提供互連件10。
圖3A至圖3O為根據另一實施例的用於形成接合結構1之方法之各種階段的示意性側視橫截面圖,其中保護材料包括包含薄保護襯套之第一層12。除非另有提到,否則圖3A至圖2O所展示之參考數字表示與圖1A至圖2K之類似編號組件相同或相似的組件。此外,結合圖1A至圖2K所揭示之程序、材料、功能性及結構中之任一者可用於圖3A至圖3O之實施例中。圖3A至圖3O之實施例大體上相似於上文結合圖1A至圖1F所揭示之實施例,惟第一層12包含薄於用於薄化晶粒之目標厚度的薄襯套且保持鄰近於薄化之後的薄化晶粒之保護材料進一步包含填料材料除外。
如同圖1A至圖1F,在圖3A中,將第一晶粒3a、3b裝配至(例如,直接接合至)諸如基板2之載體。在圖3B中,薄化背對基板2的第一晶粒3a、3b之背側18,例如,藉由回蝕晶粒散裝材料(例如,矽)以留下經薄化的第一晶粒3a、3b之暴露的背表面19。可通過第一晶粒3a、3b之背表面19暴露互連件10及非導電襯套9。此外,如同圖1A至圖1F,在圖3C中,可將第一層12施加(例如,沉積、層壓等等)於第一晶粒3a、3b之背表面19上方及晶粒7之間的間隙7中。舉例而言,可沿著第一晶粒3a、3b之側表面及在基板2上方安置第一層12之第一部分13。可將第一層12之第二部分14安置於第一晶粒3a、3b之背表面19上方及互連件10周圍。
圖3C所展示之第一層12可與上文結合圖1A至圖2K所描述之第一層相同,惟圖3C中之第一層12可包含薄於經薄化的第一晶粒3a、3b之薄保護襯套層除外。舉例而言,第一層12可具有在300奈米至15微米之範圍中的厚度,或更特定言之,在1微米至10微米之範圍中,或在1微米至5微米之範圍中。在一些實施例中,第一層12可具有在2微米至10微米之範圍中的厚度,例如,在2微米至5微米之範圍中。如同圖1A至圖2K之實施例,第一層12可在後續處理步驟期間保護第一晶粒3a、3b(例如,晶粒邊緣)。第一層12可用以在處理期間鎖定及密封第一晶粒3a、3b。有利地,圖3C之保護性第一層12可包含氧化矽,其對於在與薄化晶粒一樣厚之較大氧化矽厚度中的使用原本可能太昂貴、耗時及/或有壓力。在其他實施例中,第一層12可包含具有上文結合圖1A至圖1F所闡釋之特性的材料中之任一者。
在圖3D中,可將保護材料之第二層15沉積於第一層12上方。第二層15可厚於第一層12。第二層15可包含填充有填料粒子之填料材料(例如,聚合物)。舉例而言,第二層可包含具有聚合基底層之複合材料,聚合基底層填充有直徑在2 nm至30 nm之範圍中的粒子。在一些實施例中,填料粒子可包含氧化矽或氮化矽粒子。填料粒子可增強第二層15之硬度,且可改良與第一層12及第一晶粒3a、3b之熱匹配。複合第二層15可具有如上文所闡釋之高玻璃轉變溫度(GTT),例如,大於150℃、大於200℃、大於250℃或大於300℃。
因此,可有利的是選擇具有高GTT之第二層15,例如,GTT大於100℃、大於150℃、大於200℃、大於250℃或大於300℃。在一些實施例中,對於交聯材料,第一層之GTT可小於100℃,其限制條件為帕松比大於0.4且較佳地接近於0.5,例如,帕松比在0.25至0.8之範圍中,且熱分解溫度大於250℃或大於300℃。
如上文所闡釋,可重要的是選擇具有高楊氏模數之勁及/或硬的第二層15,其具有相似於基板之熱膨脹係數(例如,在矽或玻璃基板之狀況下相似於矽或玻璃之熱膨脹係數)的熱膨脹係數,且其具有超過用以形成接合結構1之最高處理溫度的玻璃轉變溫度或GTT。舉例而言,在一些實施例中,第二層15可包含矽、無機氧化物、無機氮化物、無機碳化物或碳酸鹽,例如,氧化矽、氮化矽、碳化矽、類鑽碳(DLC)或其他類型之半導體材料及非半導體材料。在其他實施例中,可使用聚合物。舉例而言,第二層15可包含聚醯亞胺或聚醯亞胺-醯胺。在一些實施例中,第二層125可包含Torlon®
。在一些實施例中,如本文中所闡釋,第一層12可包含填充有填料粒子(諸如氧化物或氮化物粒子,或碳酸鹽,或雲母、經處理或未經處理之高嶺土、經處理之滑石或黏土材料,例如,未經處理之膨潤土)之基底材料(諸如聚合物)。填料粒子可輔助縮減第二層15之熱膨脹係數及致使第二層15之CTE較接近於基板2或第一層12之CTE。填料可增加第一層12之硬度或勁度。第一層12中之填料含量可在10%至90%之間變化,例如,在20%與85%之間,或更特定言之,在30%與80%之間。填料粒子之大小可在2 nm至小於20微米之範圍中,例如,在50 nm與5微米之間。在一個實施例中,填料微粒之大小小於安置於第一晶粒3a及3b之間的間隙7之30%。在其他實施例中,填料微粒之大小小於第一晶粒3a及3b之間的間隙7之10%,例如,小於第一晶粒3a及3b之間的間隙7之2%。在一些實施例中,間隙7中的填料微粒之大小小於最終晶粒厚度tf
之30%,且較佳地小於晶粒之最終厚度tf
之5%。在一些實施例中,鄰近於第一晶粒3a或3b之微粒之寬度或長度可小於第一晶粒3a或3b之最終厚度tf
之15%。因為在所說明之實施例中已經薄化第一晶粒3a、3b,所以此等材料可與第一層12一起被使用,而不會引入過多壓力或過多費用。
第二層15可包含填充第一層12中之空間或間隙以促進平坦化的填料層。第二填料層15可包含上文針對第一層12所敍述之類型之微粒。第二層15可具有在4微米至120微米之範圍中的厚度,或更特定言之,在8微米至45微米之範圍中。如所展示,第二層15包含鄰近於第一晶粒3a、3b(諸如在晶粒之間的間隙7中,其中多個晶粒橫向地排列,如所展示)之第三部分16,及在第一晶粒3a、3b上方之第四部分17。
如同圖1A至圖1F之實施例,可部分地移除部分形成之接合結構1之背側,例如,可使用(例如)平坦化或拋光(例如,CMP)程序來移除第二層15之部分及第一層12之部分。如圖3E所展示,可移除第二層15之第四部分17,且可移除互連件10之部分以暴露互連件10之導電區域(例如,可移除遠側襯套部分9a)。在圖3E中,第一層12之第一部分13可保持鄰近於晶粒側壁而安置,在所說明之實施例中安置於第一晶粒3a、3b之間的間隙7中,且第二層15之第三部分16可鄰近於晶粒側壁而安置,在所說明之實施例中安置於第一部分13之側之間的間隙7中。第一層12之第二部分14之至少部分可保持安置於第一晶粒3a、3b上方及暴露互連件10及非導電襯套9周圍。如上文所闡釋,第一層12之第二部分14可防止互連件10在平坦化期間橫越第一晶粒3a、3b而塗抹。包括第一層12及第二層15之剩餘部分(例如,第三部分16)的保護材料可在平坦化期間有益地保護第一晶粒3a、3b之拐角。在一些實施例(圖中未示)中,連同互連件10之部分一起僅移除第二層15之第四部分17之部分以暴露互連件10之導電區域(例如,可移除遠側襯套部分9a)。在此組態中,在移除或平坦化程序之後,第二層15橫向地環繞導電互連件10。
在圖3F中,可製備接合結構1以用於與第二晶粒4a、4b直接接合,如上文所闡釋。可將導電重佈層36施加於第一晶粒3a、3b上方,例如,在第一層12之第二部分14上方及在第二層15之第三部分16上方。可將第二晶粒4a、4b與第一晶粒3a、3b直接接合。此外,如圖3G至圖3K所展示,可薄化及製備第二晶粒4a、4b以供後續直接接合,如結合圖3A至圖3E所闡釋。在圖3L中,可將第三晶粒30a、30b堆疊於第二晶粒4a、4b上且與第二晶粒4a、4b直接接合。可將任何合適數目個整合裝置晶粒堆疊及接合在一起以形成最終接合結構1。在一些其他應用中,可無需重佈層,如在圖3F中,可製備接合結構1以用於與第二晶粒4a、4b直接接合。第二晶粒4a、4b之互連特徵可與第一晶粒3a、3b直接接合。
圖3M說明相似於圖3J所展示之接合結構的至少部分形成之接合結構1,惟在第二層15內可存在空隙37(例如,氣穴)除外。空隙37可不負面地影響接合結構1或其總成之機械效能,且可有利地降低層壓物中之有效應力,因此縮減接合結構1之弓曲。空隙37之存在可有利地降低總成之導電元件之間的介電質之k值且縮減寄生電容。相似地,在圖3N中,第二層15可包含具有多個孔隙38之多孔材料。孔隙38可為有序的或隨機的。在一些配置中,孔隙38可以網路連接結構而定向。在圖3O中,在保護材料僅包含第一層12的相似於圖1A至圖2K之實施例中,第一層12可包含填充第一晶粒3a、3b之間的整個空間或間隙7之均質材料。在第一層12中可存在或可不存在空隙37。
有利地,圖3A至圖3O之實施例可使能夠使用包括第一層12(例如,氧化矽)之保護材料以保護在處理期間之第一晶粒3a、3b及在鄰近第一晶粒3a、3b之間的第二層15之第三部分16。第二填料層15可包含任何合適材料(且可包括空隙或孔隙)以促進平坦化。相較於薄化的第一晶粒3a、3b之厚度(其在較厚層中原本可能太昂貴及/或太有壓力而不能應用),使用第一層12作為襯套可使能夠使用較薄氧化矽或其他相似材料。圖3A至圖3O之實施例在用於薄化第一晶粒3a、3b之目標厚度介於約2微米與240微米之間(例如,介於3微米與50微米之間)的情況下特別有用,但並不限於此情形。
圖4A至圖4K為根據又一實施例的用於形成接合結構1之方法之各種階段的示意性側視橫截面圖,其中第一晶粒3a、3b之間的介電層對稱(或大致對稱)且包括額外保護層。除非另有提到,否則圖4A至圖4K所展示之參考數字表示與圖1A至圖3O之類似編號組件相同或相似的組件。此外,結合圖1A至圖3O所揭示之程序、材料、功能性及結構中之任一者可用於圖4A至圖4K之實施例中。圖4A至圖4K之實施例大體上相似於上文結合圖3A至圖3K所揭示之實施例,惟保護材料包括施加於第二層15上方之額外保護層40除外。
舉例而言,在圖4A中,可將一或多個第一晶粒3a、3b裝配及直接接合至包含基板2之載體。在圖4B中,可(例如)藉由蝕刻來部分地移除第一晶粒3a、3b之背側18,以暴露互連件10及非導電襯套9。在圖4C中,可將保護材料(其包含薄襯套)之第一層12施加於經薄化的第一晶粒3a、3b之暴露的背表面19上方及基板2上方。在圖4D中,可將第二填料層15施加於第一層12上方。在圖4E中,可部分地移除部分形成之接合結構1之背側,例如,可自第一晶粒3a、3b上之第一層12上方移除第二層15之第四部分17,且亦可使第二層15之第三部分16鄰近於第一晶粒3a、3b或在第一晶粒3a、3b之間部分地凹入於間隙7內。在一些實施例中,第二層15(第二保護層)可包含具有0.4與0.5之間的帕松比之柔順聚合層。可以各種方式(例如,藉由蝕刻)來移除第二層15。在其他實施例中,可藉由方向性或各向同性蝕刻來移除第二層15。在一些實施例中,亦可移除第一層12之部分。
然而,不同於圖3A至圖3O之實施例,保護材料可進一步包括施加於部分形成之接合結構1之背側上方的額外保護層40(第三保護層)。舉例而言,如圖4F所展示,可將額外保護層40施加(例如,沉積)於第二層之第三部分16上方、第一層12之第二部分14上方以及暴露互連件10及非導電襯套9周圍。額外保護層40可與第一保護層12相似或相同。舉例而言,在所說明之實施例中,第一層12及額外保護層40可包含矽或基底無機或有機介電材料。然而,上文針對第一層12所描述之材料中之任一者亦可用於額外保護層40。
有益地,額外保護層40可提供鄰近於晶粒之對稱保護材料,其可充當晶粒間介電層。在無額外保護層40之一些配置中,當拋光(例如,藉由CMP)接合結構1之背側時,在第一晶粒3a、3b之間的區域中可存在表面凹陷,例如,在第二層15之第三部分16中的表面凹陷。舉例而言,第二層15可包含不與第一或第三層一樣硬之材料。拋光第二層15之第三部分16可造成可負面地影響晶粒之堆疊及接合的表面凹陷及/或可產生空隙或未對準。因此,提供額外保護層40可填入第二層15(其可硬)之第三部分16之凹入區域,且可保護第二層15免於表面凹陷且進一步保護第一晶粒3a、3b。此外,保護材料之對稱性針對基板2上之第一晶粒3a、3b之間的空腔提供平衡的熱膨脹係數(CTE)。
因此,在圖4F中,保護材料可包含第一層12(其可形成於第一晶粒3a、3b之側壁及背表面19上方)、在第一晶粒3a、3b之間的第二層15之第三部分16,及提供於第三部分16之背側及第一晶粒3a、3b上方的額外保護層40。在所說明之實施例中,可將額外保護層40施加於在第一晶粒3a、3b上的第一層12之第二部分14上方及第二層15之第三部分16上方。然而,在其他配置中,可將額外保護層40僅提供於第二層15之第三部分16上方,且可不沉積於第一層12或第一晶粒3a、3b上方。
在圖4G中,可(例如)使用CMP來平坦化(例如,拋光)部分形成之接合結構1之背側。平坦化可經組態以停止於額外保護層40上,且移除互連件10及非導電襯套9之暴露部分,使得互連件10及非導電襯套9與額外保護層40實質上齊平。在圖4H中,可將第二晶粒4a、4b堆疊於第一晶粒3a、3b上且直接接合至第一晶粒3a、3b,如上文所闡釋。圖4I至圖4K說明亦可以相似於結合圖4A至圖4G所描述之方式的方式薄化及製備第二晶粒4a、4b以供直接接合。此外,熟習此項技術者鑒於本文中之揭示內容而應易於瞭解,可相似地堆疊額外(第三、第四等等)晶粒,且圖4A至圖4K之對稱保護材料亦可包括第二層15中之空隙,相似於圖3M及圖3N所說明之鑰孔及孔隙。
圖5A至圖5I為根據另一實施例的用於形成接合結構1之方法之各種階段的示意性側視橫截面圖,其中在堆疊之前將多於兩個介電層提供於晶粒上方。除非另有提到,否則圖5A至圖5I所展示之參考數字表示與圖1A至圖4K之類似編號之組件相同或相似的組件。此外,結合圖1A至圖4K所揭示之程序、材料、功能性及結構中之任一者可用於圖5A至圖5I之實施例中。圖5A至圖5I之實施例大體上相似於上文結合圖3A至圖4K所揭示之實施例,惟在薄化及堆疊之前將三個層施加於第一晶粒3a、3b上方除外。
如圖5A所展示,可將第一晶粒3a、3b裝配至包含基板2之載體及與該載體直接接合。第一晶粒3a、3b之初始厚度ti
可厚於在一些配置中之厚度。舉例而言,初始厚度ti
可在30微米至1500微米之範圍中,在200微米至1000微米之範圍中,或在500微米至1000微米之範圍中。如上文所闡釋,本文中所揭示之方法可與為任何合適厚度之晶粒一起被利用。在圖5B中,保護材料包括第一保護層12,其可在第一晶粒3a、3b被薄化之前沉積於第一晶粒3a、3b上方。如上,第一層12可薄於用於薄化晶粒之目標厚度,且可在後續處理期間保護第一晶粒3a、3b(例如,晶粒邊緣)。在圖5C中,保護材料亦包括第二填料層15,其可提供於第一層12上方。如圖5C所展示,第二填料層15可不完全地填充或平坦化部分形成之接合結構1。實情為,如圖5C所展示,在第二層15之部分之間可存在空間47。然而,第二填料層15之厚度可大於用於薄化晶粒之目標厚度。
為了平坦化部分形成之結構,在圖5D中,可將第三填料層45提供於第二層15上方以填充留存於第二層15中之空間47。可將第三層45之第五部分48安置於空間47中。可將第三層45之第六部分49安置於第二層15上方,例如,在第二層15之第四部分17上方。第三層45可為任何合適材料。舉例而言,第三層45可包含上文針對第一層12或第二層15所描述之任何合適材料。在圖5E中,可至少部分地移除部分形成之接合結構1之背側,例如,藉由研磨及/或拋光(例如,藉由CMP)。研磨或拋光可移除大多數或全部第三層45,以及第二層15及第一層12之部分。研磨或拋光可終止於非導電襯套9之遠側襯套部分9a處或附近。
轉至圖5F,可移除(例如,藉由回蝕)第一晶粒3a、3b之背側18,以便暴露薄化第一晶粒3a、3b之背表面19。背側18之移除可暴露互連件10及非導電襯套9。在圖5G中,可將額外保護層40(例如,諸如氧化矽之介電層)提供於部分形成之結構上方。舉例而言,可將額外保護層40安置於第二層之第三部分16上方、第一層12之第一部分13之邊緣上方、第一晶粒3a、3b之背表面19上方,以及非導電襯套9及互連件10周圍。在圖5H中,可移除額外保護層40之部分及/或互連件10之部分以暴露互連件10之導電材料。舉例而言,可拋光(例如,藉由CMP)部分形成之接合結構1以移除額外保護層40之上部分及非導電襯套9之遠側襯套部分9a。轉至圖5I,可製備第一晶粒3a、3b以供直接接合(如上文所闡釋),且可將第二晶粒4a、4b堆疊於第一晶粒3a、3b上且直接接合至第一晶粒3a、3b。可重複圖5A至圖5H之步驟以堆疊及接合任何合適數目個整合裝置晶粒以形成最終接合結構1。雖然序列取決於針對第一層12(襯套)、第二層15(填料)及額外保護層40(頂蓋)所選擇之材料及厚度而不同,但所得結構可相似於圖4A至圖4K之實施例中的對稱保護材料。
圖6A至圖6E為用於形成多個第一晶粒3a至3c具有不同初始厚度ti
之接合結構1之方法之各種階段的示意性側視橫截面圖。除非另有提到,否則圖6A至圖6E所展示之參考數字表示與圖1A至圖5I之類似編號組件相同或相似的組件。此外,結合圖1A至圖5I所揭示之程序、材料、功能性及結構中之任一者可用於圖6A至圖6E之實施例中。
在圖6A中,可將多個第一晶粒3a至3c裝配至且直接接合至包含基板2之載體。然而,不同於上文所說明之實施例,鄰近第一晶粒3a至3c可具有不同初始厚度ti a
、ti b
及ti c
。初始厚度ti a
、ti b
及ti c
可為任何合適厚度。舉例而言,初始厚度ti a
、ti b
及ti c
可在40微米至2000微米之範圍中,在100微米至1500微米之範圍中,在200微米至1000微米之範圍中,在500微米至1000微米之範圍中等等。
轉至圖6B,可將包括第一層12之保護材料提供於第一晶粒3a至3c上方及基板2上方。如上文所闡釋,第一層12可在處理期間保護晶粒。在圖6C中,可將第二層15提供於第一層上方以輔助平坦化部分形成之接合結構1。如同圖5A至圖5I之實施例,第二層15可不完全地平坦化及填充第一層12中之間隙。因此,可將第三層45提供於第二層15上方以填充第二層15中之間隙且完成接合結構1之平坦化。雖然圖6D中展示三個介電層(第一層12、第二層15、第三層45),但應瞭解,可提供額外介電層以平坦化部分形成之結構。相反地,第一及第二層可由單一保形或襯裡保護層替換。
在圖6E中,可部分地移除部分形成之接合結構1之背側,例如,可藉由(例如)研磨、拋光及/或蝕刻來移除第三層45、第二層15及第一層12之部分。在所說明之實施例中,可在薄化之後提供互連件及襯套,如圖2A至圖2K所展示。然而,在其他實施例中,可在薄化之前形成互連件及襯套。在圖6E之實施例中,第一晶粒3a至3c可具有大約相同的最終厚度tf
,即使初始厚度ti a
、ti b
及ti c
可顯著地不同亦如此。因此,有利地,本文中所揭示之實施例可使能夠使用具有不同厚度之晶粒,且將此等晶粒併入至堆疊及接合結構1中。在一些實施例中,在基板或載體2上堆疊多個晶粒以形成接合結構之後,可自背側(圖中未示)薄化基板2且處理基板2以在貫通基板上方形成電耦接結構且在基板2中形成導電互連件10。可將基板單粒化成多個封裝,其中每一封裝包含一或多個經堆疊的第一晶粒3a或經堆疊的第一晶粒3a、3b。可將單粒化堆疊晶粒或封裝裝配於另一基板、板或另一封裝上。
圖7A為說明根據一個實施例的用於形成接合結構之方法70的流程圖。方法70可結合圖1A至圖6E之實施例而使用。在區塊72中,可將第一單粒化整合裝置晶粒裝配至載體。如本文中所闡釋,第一晶粒可包含任何合適類型之整合裝置晶粒。在一些實施例中,晶粒可包含KGD,例如,可在裝配之前測試晶粒。如本文中所闡釋,在一些實施例中,可將晶粒直接接合至載體,例如,可合適地製備晶粒及載體以供接合。可在無介入黏著劑之情況下及在不施加外部壓力之情況下將晶粒及載體之非導電及導電區域彼此直接接合。
轉至區塊74,在裝配之後,可薄化第一整合裝置晶粒。舉例而言,在一些配置中,可蝕刻、研磨或拋光第一晶粒之背側(其可與主動或前側相對)以移除第一晶粒之部分。薄化第一晶粒可使能夠使用呈低剖面封裝配置之多個裝置晶粒。此外,如本文中所闡釋,在一些實施例中,可在薄化之前或在薄化之後在第一晶粒中形成互連件(例如,TSV)。在圖1A至圖6E之實施例中,可將保護材料(其可包括第一層12、第二層15、額外保護層40及第三層45中之一或多者之各種部分)施加於第一晶粒上方及安置於晶粒之間的載體之部分上方。可在薄化之前或在薄化之後提供保護材料。在各個實施例中,可將額外裝置晶粒堆疊於第一晶粒上且連接至(例如,直接接合至)第一晶粒。
圖7B為說明根據另一實施例的用於形成接合結構之方法76的流程圖。方法76可結合圖1A至圖6E之實施例而使用。在區塊77中,可將第一整合裝置晶粒(其可被單粒化)裝配至載體。如本文中所闡釋,第一晶粒可包含任何合適類型之整合裝置晶粒。在一些實施例中,晶粒可包含KGD,例如,可在裝配之前測試晶粒。如本文中所闡釋,在一些實施例中,可將晶粒直接接合至載體,例如,可合適地製備晶粒及載體以供接合。可在無介入黏著劑之情況下及在不施加外部壓力之情況下將晶粒及載體之非導電及導電區域彼此直接接合。
轉至區塊78,在裝配之後,可在第一整合裝置晶粒之表面上提供包含第一層之保護材料。有益地,第一層可保護第一晶粒之邊緣在平坦化或其他處理步驟期間免於碎裂。第一層可包含CTE接近於第一晶粒之CTE且具有相對高GTT的相對硬材料。可將第一層提供於第一晶粒之暴露背表面上方及鄰近晶粒之間的載體之部分上方。如本文中所闡釋,在一些實施例中,保護材料可包括安置於第一晶粒上方及/或鄰近晶粒之間的空間中的額外層(諸如第二層15、第三層45及額外保護層40之部分)。
在區塊79中,可平坦化第一層之至少一部分以移除第一整合裝置晶粒之部分。舉例而言,在一些實施例中,可使用化學機械拋光(CMP)技術以移除第一層中之一些,此在一些實施例中可暴露互連件。在保護材料包含多個層之實施例中,可在平坦化期間部分地或全部地移除其他層。有利地,保護材料可在平坦化程序期間保護晶粒。如本文中所闡釋,可將額外裝置晶粒堆疊於第一整合裝置晶粒上且連接至(例如,直接接合至)第一整合裝置晶粒。
圖8為根據各個實施例的併有一或多個接合結構1之系統80的示意圖。系統80可包含任何合適類型之電子裝置,諸如行動電子裝置(例如,智慧型手機、平板計算裝置、膝上型電腦等等)、桌上型電腦、汽車或其組件、立體聲系統、醫療裝置、攝影機,或任何其他合適類型之系統。在一些實施例中,電子裝置可包含微處理器、圖形處理器、電子記錄裝置,或數位記憶體。系統80可包括機械及電連接至系統80(例如,藉助於一或多個主板)之一或多個裝置封裝82。每一裝置封裝82可包含一或多個接合結構1。圖8所展示之接合結構1可包含上文結合圖1A至圖7B所展示及描述之接合結構1中之任一者。接合結構1可包括執行用於系統80之各種功能的一或多個整合裝置晶粒。
因此,本文中所揭示之實施例可有利地使能夠在封裝級下在單粒化之後薄化晶粒。使用包括第一保護層12之保護材料可有益地在拋光期間保護晶粒,且尤其是保護晶粒邊緣。第一保護層12可在處理期間鎖定及密封晶粒。此外,保護材料可進一步包括在第一層12之間隙之間的第二填料材料,其可有益地促進結構之平坦化。在一些實施例中,第三填料材料及實際上任何合適數目個填料材料可用以促進結構之平坦化。在一些實施例中,第二填料材料可包括嵌入式填料粒子以改良填料材料之機械及熱性質。在一些實施例中,可將額外保護層40提供於第二層15(或其他層)上方以提供抵抗表面凹陷且改良總良率之對稱介電結構。在將單粒化晶粒裝配於基板上之後的薄化亦可促進晶粒之後續堆疊及接合。
有利地,本文中所揭示之方法可使用具有任何合適初始厚度之晶粒,且鄰近晶粒可具有不同厚度。此外,由於蝕刻之量可小於在其他程序中之量,故可縮減晶粒(例如,矽晶粒)之蝕刻時間。此外,在一些實施例中,由於可在形成互連件之前薄化晶粒,故亦可縮減用於拋光、鍍敷及提供導電互連件之時間。
在一個實施例中,揭示一種用於形成一接合結構之方法。該方法可包含將一第一單粒化整合裝置晶粒裝配至一載體。該方法可包含在裝配之後薄化該第一整合裝置晶粒。該方法可包含在該第一整合裝置晶粒之一暴露表面上提供包含一第一層之一保護材料。
在另一實施例中,揭示一種接合結構。該接合結構可包括一載體,及一第一整合裝置晶粒,其具有裝配至該載體之一上表面的一下表面。該第一整合裝置晶粒可包含與該下表面相對之一上表面及在該第一整合裝置晶粒之該上表面與該下表面之間的一側表面。該接合結構可包含一保護材料,其包含具有安置於該第一整合裝置晶粒之該側表面上之一第一部分的一第一層,該第一層硬於該第一整合裝置晶粒之側表面。
在另一實施例中,揭示一種用於形成一接合結構之方法。該方法可包含將一第一整合裝置晶粒裝配至一載體。該方法可包含:在裝配之後,在該第一整合裝置晶粒之一表面上提供包含一第一層之一保護材料。該方法可包含平坦化該第一層之至少一部分以移除該第一整合裝置晶粒之一部分。
出於概述所揭示之實施例及相比於先前技術所達成之優點的目的,本文中已描述某些目標及優點。當然,應理解,根據任何特定實施例,可未必達成所有此等目標或優點。因此,舉例而言,熟習此項技術者將認識到,可以如本文中所教示或建議而達成或最佳化一個優點或一群優點而未必達成如本文中可能教示或建議之其他目標或優點的方式來體現或進行所揭示之實施方案。
所有此等實施例皆意欲在本發明之範圍內。此等及其他實施例將自參考附圖的實施例之以下詳細描述而對於熟習此項技術者變得易於顯而易見,申請專利範圍並不限於所揭示之任何特定實施例。雖然本文中已揭示某些實施例及實例,但熟習此項技術者應理解,所揭示之實施方案超出特定揭示之實施例而延伸至其他替代性實施例及/或用途以及其明顯修改及等效者。此外,雖然已詳細地展示及描述若干變化,但基於本發明,其他修改對於熟習此項技術者將易於顯而易見。亦預料到,可進行實施例之特定特徵及態樣的各種組合或子組合且其仍在該範圍內。應理解,所揭示之實施例之各種特徵及態樣可彼此組合或取代,以便形成所揭示之實施方案之變化模式。因此,希望本文中所揭示之主題之範圍不應受到上文所描述的特定揭示之實施例限制,而應僅藉由接下來的申請專利範圍之公平閱讀予以判定。
本發明亦包含以下條項:
條項1:一種用於形成一接合結構之方法,該方法包含:
將一第一單粒化整合裝置晶粒裝配至一載體;
在裝配之後,薄化該第一整合裝置晶粒;及
在該第一整合裝置晶粒之一暴露表面上提供包含一第一層之一保護材料。
條項2:如條項1之方法,其進一步包含移除該第一層之至少一部分。
條項3:如條項2之方法,其中該第一層硬於該第一整合裝置晶粒之該暴露表面。
條項4:如條項2至3中任一項之方法,其中該第一層具有在該第一整合裝置之一熱膨脹係數之15 ppm/℃內的一熱膨脹係數。
條項5:如條項2至4中任一項之方法,其中該第一層包含一矽基介電質。
條項6:如條項2至5中任一項之方法,其中該第一層包含一聚合物。
條項7:如條項6之方法,其中該聚合物具有大於250℃之一玻璃轉變溫度。
條項8:如條項6之方法,其中該聚合物具有大於250℃之一玻璃轉變溫度及在0.25與0.8之間的一帕松比。
條項9:如條項6或8之方法,其中該聚合物在其中包含複數個填料粒子。
條項10:如條項9之方法,其中該等填料粒子之大小在2 nm至30 nm之一範圍中。
條項11:如條項1至10中任一項之方法,其進一步包含移除該第一整合裝置晶粒之一背側之一部分以暴露該第一整合裝置晶粒之一背表面。
條項12:如條項2至11中任一項之方法,其進一步包含提供通過該第一整合裝置晶粒之至少該暴露表面所暴露的一電互連件。
條項13:如條項12之方法,其中提供該第一層包含圍繞該電互連件沉積該第一層。
條項14:如條項11或13之方法,其中移除該第一整合裝置晶粒之該背側之該部分包含暴露該電互連件。
條項15:如條項11至14中任一項之方法,其中移除該背側之該部分包含蝕刻該第一整合裝置晶粒之該背側。
條項16:如條項2至15中任一項之方法,其中提供該第一層包含將該第一層沉積至不小於該第一整合裝置晶粒之一厚度的一厚度,該第一整合裝置晶粒之該厚度界定於該第一整合裝置晶粒之一背表面與一前表面之間。
條項17:如條項16之方法,其中該第一整合裝置晶粒之該厚度小於20微米。
條項18:如條項2至17中任一項之方法,其進一步包含在該第一層上提供一第二層。
條項19:如條項18之方法,其進一步包含移除該第二層之至少一部分。
條項20:如條項2至19中任一項之方法,其進一步包含平坦化留存於該第一整合裝置晶粒上方的該第一層之一剩餘部分。
條項21:如條項12至20中任一項之方法,其進一步包含在無一介入黏著劑之情況下將一第二整合裝置晶粒之一第二電互連件直接接合至該電互連件。
條項22:如條項21之方法,其進一步包含將該第二整合裝置晶粒之一非導電部分直接接合至該第一層。
條項23:如條項1至22中任一項之方法,其中將該第一整合裝置晶粒裝配至該載體包含將該第一整合裝置晶粒接合至一基板。
條項24:如條項23之方法,其中該基板包含玻璃、矽或一陶瓷材料。
條項25:如條項23至24中任一項之方法,其中將該第一整合裝置晶粒接合至該基板包含在無一介入黏著劑之情況下將該第一整合裝置晶粒之導電及非導電層直接接合至該基板。
條項26:如條項2至25中任一項之方法,其進一步包含在一第三整合裝置晶粒之一暴露表面上提供該第一層,該第三整合裝置晶粒鄰近於該第一整合裝置晶粒而橫向地定位。
條項27:如條項26之方法,其進一步包含暴露該第三整合裝置晶粒之一第三電互連件,及在無一介入黏著劑之情況下將一第四整合裝置晶粒之一第四電互連件直接接合至該第三電互連件。
條項28:如條項26至27中任一項之方法,其中該第一電裝置晶粒及該第三電裝置晶粒裝配於一基板上,其中提供該第一層包含在該第一整合裝置晶粒及該第三整合裝置晶粒之背表面上方及在該第一整合裝置晶粒與該第三整合裝置晶粒之間的該基板之一上表面上方保形地塗佈該第一層。
條項29:如條項28之方法,其進一步包含在該第一層上方沉積一第二層,使得該第二層之一部分橫向地安置於該第一層之安置於該第一整合裝置晶粒及該第三整合裝置晶粒上方的各別部分之間。
條項30:如條項12至29中任一項之方法,其中提供該電互連件包含在移除該第一層之該至少一部分之後形成該電互連件。
條項31:如條項30之方法,其中形成該電互連件包含在該第一整合裝置晶粒中圖案化一溝槽及運用導電材料來填充該溝槽。
條項32:如條項2至31中任一項之方法,其中提供該第一層包含將該第一層沉積至小於該第一整合裝置晶粒之一厚度的一厚度,該第一整合裝置晶粒之該厚度界定於該第一整合裝置晶粒之一背表面與該第一整合裝置晶粒之一前表面之間。
條項33:如條項32之方法,其進一步包含將該第一層沉積至在1微米至15微米之一範圍中的一厚度。
條項34:如條項32至33中任一項之方法,其進一步包含在該第一層上方提供一第二層,該第二層厚於該第一層。
條項35:如條項34之方法,其中一第三整合裝置晶粒鄰近於該第一整合裝置晶粒而安置且與該第一整合裝置晶粒橫向地隔開一間隙,其中提供該第二層包含在該第一晶粒與該第三晶粒之間的該間隙中沉積該第二層。
條項36:如條項34至35中任一項之方法,其進一步包含移除該第二層之一部分以暴露一電互連件。
條項37:如條項34至36中任一項之方法,其進一步包含在該第二層上方提供一第三層。
條項38:如條項37之方法,其中該第三層包含與該第一層相同的材料。
條項39:如條項37至38中任一項之方法,其進一步包含在安置於該第一整合裝置晶粒上方的該第一層之一對應第一部分上方施加該第三層之一第一部分,及在該第二層之一對應部分上方施加該第三層之一第二部分。
條項40:如條項39之方法,其進一步包含在該第一整合裝置晶粒被裝配至的該載體之一上表面上方施加該第一層之一第二部分。
條項41:如條項40之方法,其進一步包含在該第一層之該第二部分上方施加該第二層之該對應部分。
條項42:一種接合結構,其包含:
一載體;
一第一整合裝置晶粒,其具有裝配至該載體之一上表面的一下表面,該第一整合裝置晶粒包含與該下表面相對之一上表面及在該第一整合裝置晶粒之該上表面與該下表面之間的一側表面;及
一保護材料,其包含具有安置於該第一整合裝置晶粒之該側表面上之一第一部分的一第一層,該第一層硬於該第一整合裝置晶粒之側表面。
條項43:如條項42之結構,其進一步包含直接接合至該第一整合裝置晶粒之該上表面的一第二整合裝置晶粒。
條項44:如條項43之結構,其中該第一層之一第二部分安置於該第一整合裝置晶粒與該第二整合裝置晶粒之間的該第一整合裝置晶粒之該上表面上。
條項45:如條項42至43中任一項之結構,其中該第一整合裝置晶粒之一電互連件直接接合至該第二整合裝置晶粒之一第二電互連件。
條項46:如條項45之結構,其中該電互連件包含在該第一整合裝置晶粒之該上表面處的一接觸襯墊及形成於該第一整合裝置晶粒中之一直通矽穿孔。
條項47:如條項44至46中任一項之結構,其中該第一層之該第二部分橫向地安置於該電互連件周圍,使得該電互連件通過該第一層而暴露。
條項48:如條項42至47中任一項之結構,其中該第一層具有在該第一整合裝置晶粒之一熱膨脹係數之10 ppm/℃內的一熱膨脹係數。
條項49:如條項42至48中任一項之結構,其中該第一層包含二氧化矽。
條項50:如條項42至49中任一項之結構,其中該第一層包含一聚合物。
條項51:如條項50之結構,其中該聚合物具有大於250℃之一玻璃轉變溫度。
條項52:如條項50或51之結構,其中該聚合物在其中包含複數個填料粒子。
條項53:如條項52之結構,其中該等填料粒子之大小在2 nm至30 nm之一範圍中。
條項54:如條項42至53中任一項之結構,其中該保護材料包含安置於該第一整合裝置晶粒之該側表面上的該第一層之該第一部分上方的一第二填料層。
條項55:如條項54之結構,其中該保護材料包含具有安置於該第一層之該第二部分上方之一第一部分及安置於該第二填料層上方之一第二部分的一第三層。
條項56:如條項42至55中任一項之結構,其中該載體包含一基板,該基板包含玻璃或矽。
條項57:如條項56之結構,其中該第一整合裝置晶粒直接接合至該基板。
條項58:一種電子裝置,其包含如條項42至57中任一項之結構。
條項59:如條項58之電子裝置,其中該電子裝置包含一智慧型手機、一平板計算裝置、一膝上型電腦或一攝影機。
條項60:如條項58之電子裝置,其中該電子裝置包含一微處理器、一圖形處理器、一電子記錄裝置或數位記憶體。
條項61:一種用於形成一接合結構之方法,該方法包含:
將一第一整合裝置晶粒裝配至一載體;及
在裝配之後,在該第一整合裝置晶粒之一表面上提供包含一第一層之一保護材料;及
平坦化該第一層之至少一部分以移除該第一整合裝置晶粒之一部分。
條項62:如條項61之方法,其中該第一層硬於該第一整合裝置晶粒。
條項63:如條項61至62中任一項之方法,其中該第一層具有在該第一整合裝置晶粒之一熱膨脹係數之10 ppm/℃內的一熱膨脹係數。
條項64:如條項61至63中任一項之方法,其中該第一層包含二氧化矽。
條項65:如條項61至63中任一項之方法,其中該第一層包含一聚合物。
條項66:如條項65之方法,其中該聚合物具有大於250℃之一玻璃轉變溫度。
條項67:如條項65或66之方法,其中該聚合物在其中包含複數個填料粒子。
條項68:如條項67之方法,其中該等填料粒子之大小在2 nm至30 nm之一範圍中。
條項69:如條項61至68中任一項之方法,其進一步包含移除該第一整合裝置晶粒之一背側之一部分以暴露該第一整合裝置晶粒之一背表面。
條項70:如條項61至69中任一項之方法,其進一步包含提供通過該第一整合裝置晶粒之至少一暴露背表面所暴露的一電互連件。
條項71:如條項61至70中任一項之方法,其中提供該第一層包含將該第一層沉積至不小於該第一整合裝置晶粒之一厚度的一厚度,該第一整合裝置晶粒之該厚度界定於該第一整合裝置晶粒之一背表面與一前表面之間。
條項72:如條項71之方法,其中該第一整合裝置晶粒之該厚度小於20微米。
條項73:如條項61至72中任一項之方法,其進一步包含在該第一層上提供一第二層。
條項74:如條項73之方法,其進一步包含移除該第二層之至少一部分。
條項75:如條項61至74中任一項之方法,其進一步包含平坦化留存於該第一整合裝置晶粒上方的該第一層之一剩餘部分。
條項76:如條項70至75中任一項之方法,其進一步包含在無一介入黏著劑之情況下將一第二整合裝置晶粒之一第二電互連件直接接合至該電互連件。
條項77:如條項76之方法,其進一步包含將該第二整合裝置晶粒之一非導電部分直接接合至該第一層。
條項78:如條項61至77中任一項之方法,其中將該第一整合裝置晶粒裝配至該載體包含將該第一整合裝置晶粒接合至一基板。
條項79:如條項78之方法,其中該基板包含玻璃或矽。
1‧‧‧接合結構
2‧‧‧基板
3‧‧‧第一整合裝置晶粒
3a‧‧‧第一晶粒
3b‧‧‧第一晶粒
3c‧‧‧第一晶粒
4‧‧‧第二晶粒
4a‧‧‧第二晶粒
4b‧‧‧第二晶粒
5‧‧‧緩衝層
6‧‧‧主動表面
7‧‧‧間隙/間距
8‧‧‧基板之上表面
9‧‧‧非導電襯套
9a‧‧‧遠側襯套部分
10‧‧‧互連件
11‧‧‧接合層
12‧‧‧第一層/第一保護層
13‧‧‧第一部分
14‧‧‧第二部分
15‧‧‧第二層/第二填料層
16‧‧‧第三部分
17‧‧‧第四部分
18‧‧‧晶粒之背側
19‧‧‧背表面
20‧‧‧非導電區域
22‧‧‧佈線介電層
24‧‧‧遮罩
25‧‧‧圖案化空間
26‧‧‧通孔或跡線
28‧‧‧測試襯墊
29‧‧‧通孔
30a‧‧‧第三晶粒
30b‧‧‧第三晶粒
34‧‧‧佈線層
36‧‧‧導電重佈層
37‧‧‧空隙
38‧‧‧孔隙
40‧‧‧額外保護層
45‧‧‧第三層/第三填料層
48‧‧‧第三層之第五部分
49‧‧‧第三層之第六部分
70‧‧‧用於形成接合結構之方法
72‧‧‧區塊
74‧‧‧區塊
76‧‧‧用於形成接合結構之方法
77‧‧‧區塊
78‧‧‧區塊
79‧‧‧區塊
80‧‧‧系統
82‧‧‧裝置封裝
此等態樣及其他態樣將自較佳實施例及隨附圖式之以下描述顯而易見,隨附圖式意在說明而非限制本發明,其中:
圖1A至圖1F為根據一個實施例的用於形成具有保護材料之接合結構之方法之各種階段的示意性側視橫截面圖。
圖2A至圖2K為根據另一實施例的用於形成具有保護材料之接合結構之方法之各種階段的示意性側視橫截面圖,其中在薄化之後形成電互連件。
圖3A至圖3O為根據另一實施例的用於形成接合結構之方法之各種階段的示意性側視橫截面圖,其中在處理期間之保護材料包含薄保護襯套及填料材料。
圖4A至圖4K為根據又一實施例的用於形成接合結構之方法之各種階段的示意性側視橫截面圖,其中保護材料包含在填料材料上方之額外保護層。
圖5A至圖5I為根據另一實施例的用於形成接合結構之方法之各種階段的示意性側視橫截面圖,其中在製造期間提供多個層作為保護材料。
圖6A至圖6E為用於形成多個晶粒具有不同初始厚度之接合結構之方法之各種階段的示意性側視橫截面圖。
圖7A為說明根據一個實施例的用於形成接合結構之方法的流程圖。
圖7B為說明根據另一實施例的用於形成接合結構之方法的流程圖。
圖8為根據各個實施例的併有一或多個接合結構之系統的示意圖。
1‧‧‧接合結構
2‧‧‧基板
3a‧‧‧第一晶粒
3b‧‧‧第一晶粒
4‧‧‧第二晶粒
4a‧‧‧第二晶粒
4b‧‧‧第二晶粒
5‧‧‧緩衝層
9‧‧‧非導電襯套
10‧‧‧互連件
12‧‧‧第一層/第一保護層
34‧‧‧佈線層
Claims (41)
- 一種用於封裝整合裝置晶粒之方法,所述方法包含:將多個單粒化的整合裝置晶粒直接接合至載體,以使得所述多個單粒化的整合裝置晶粒的各自接合表面和所述載體直接接觸;在直接接合之後,薄化所述多個單粒化的整合裝置晶粒;將保護材料提供在所述多個單粒化的整合裝置晶粒的暴露表面上,包括在所述多個單粒化的整合裝置晶粒的側壁表面上;及在提供所述保護材料之後,將第二單粒化的整合裝置晶粒直接接合至所述多個單粒化的整合裝置晶粒中的第一單粒化的整合裝置晶粒。
- 如請求項1之方法,其進一步包含移除所述保護材料的至少一部分。
- 如請求項1之方法,其中提供所述保護材料包括提供保形的無機介電層。
- 如請求項3之方法,其中所述保形的無機介電層具有在所述第一整合裝置之熱膨脹係數之15ppm/℃內的熱膨脹係數。
- 如請求項3之方法,其中所述保形的無機介電層包括矽基材料。
- 如請求項1之方法,其中提供所述保護材料包括沉積聚合物。
- 如請求項1之方法,其進一步包括在薄化之後,將多個第二晶粒直接接合在所述多個單粒化的整合裝置晶粒上方以形成堆疊晶粒。
- 如請求項7之方法,其進一步包括在將所述多個第二晶粒直接接合在所述多個單粒化的整合裝置晶粒上方之後單粒化所述堆疊晶粒。
- 如請求項8之方法,其進一步包括在直接接合所述多個第二晶粒之後以及在單粒化所述堆疊晶粒之前,在所述多個第二晶粒的暴露表面上提供另一層的所述保護材料。
- 如請求項7之方法,其中所述保護材料包括在所述多個單粒化的整合裝置晶粒的側表面上的第一保護層和在所述多個第二整合裝置晶粒的側表面上的第二保護層,垂直相鄰的晶粒的所述第一保護層和所述第二保護層之間具有介面。
- 一種用於封裝整合裝置晶粒之方法,所述方法包含:將多個第一整合裝置晶粒直接接合至載體,在彼此相鄰的所述第一整合裝置晶粒之間具有間隙,所述第一整合裝置晶粒包括電互連件,所述電互連件延伸穿過所述第一整合裝置晶粒的厚度的至少一部分;在直接接合所述第一整合裝置晶粒之後,提供保護材料以填充所述第一整合裝置晶粒之間的所述間隙;暴露所述第一整合裝置晶粒的所述電互連件;及將多個第二整合裝置晶粒安裝且電互連至所述第一整合裝置晶粒的暴露的所述電互連件上。
- 如請求項11之方法,其中提供所述保護材料包括圍繞所述電互連件沉積所述第一層。
- 如請求項11之方法,其中將所述第二整合裝置晶粒安裝且電互連至所述第一整合裝置晶粒的暴露的所述電互連件上包括直接接合所述第一整合裝置晶粒和所述第二整合裝置晶粒的導電表面和非導電表面。
- 如請求項13之方法,其進一步包括:暴露所述第二整合裝置晶粒的電互連件;及將多個第三整合裝置晶粒安裝且電互連至所述第二整合裝置晶粒的暴露的所述電互連件上。
- 如請求項13之方法,其進一步包括在安裝且電連接所述第二整合裝置晶粒之後單粒化所述堆疊晶粒。
- 如請求項11之方法,其中提供所述保護材料包括將第一層沉積至不小於所述第一整合裝置晶粒之厚度的厚度,所述第一整合裝置晶粒之所述厚度界定於所述第一整合裝置晶粒之背表面與前表面之間。
- 如請求項11之方法,其中提供所述保護材料包括在所述第一整合裝置晶粒上方提供保形的第一層且在所述第一層上提供第二層以填充所述第一整合裝置晶粒之間的間隙。
- 如請求項11之方法,其中暴露所述第一整合裝置晶粒的電互連件包括平坦化所述保護材料和所述第一整合裝置晶粒。
- 如請求項11之方法,其中所述載體包括玻璃、矽或陶瓷材料。
- 如請求項11之方法,其進一步包括在第三整合裝置晶粒的暴露表面上提供所述第一層,所述第三整合裝置晶粒被定位以橫向鄰近所述第一整合裝置晶粒。
- 如請求項11之方法,其中暴露所述第一整合裝置晶粒的所述電互連件包括在移除所述保護材料的至少一部分之後形成所述電互連件。
- 如請求項21之方法,其中形成所述電互連件包括在所述第一整合裝置晶粒中圖案化出溝槽及用導電材料填充所述溝槽。
- 一種堆疊晶粒的接合結構,其包括:第一整合裝置晶粒,所述第一整合裝置晶粒包括與下表面相對之上表面和在所述第一整合裝置晶粒的所述上表面和所述下表面之間的側表面;第二整合裝置晶粒,在沒有介入黏著劑下,所述第二整合裝置晶粒直接接合至所述第一整合裝置晶粒的所述上表面,所述第二整合裝置晶粒包括與下表面相對之上表面和在所述第二整合裝置晶粒的所述上表面和所述下表面之間的側表面;及保護材料,其被設置在所述第一整合裝置晶粒和所述第二整合裝置晶粒的 所述側表面上,所述保護材料在形成所述保護材料和將所述第二整合裝置晶粒直接接合至所述第一整合裝置晶粒的所述上表面之後具有連續外表面而有單一化特徵。
- 如請求項23之接合結構,其中所述保護材料的部分被設置在所述第一整合裝置晶粒和所述第二整合裝置晶粒之間的所述第一整合裝置晶粒的所述上表面上。
- 如請求項23之接合結構,其中所述第二整合裝置晶粒被直接接合至所述第一整合裝置晶粒的所述上表面。
- 如請求項23之接合結構,其中所述第一整合裝置晶粒的電互連件被直接接合至所述第二整合裝置晶粒的第二電互連件。
- 如請求項26之接合結構,其中所述電互連件包括在所述第一整合裝置晶粒的所述上表面處的接觸墊和形成在所述第一整合裝置晶粒中的直通矽穿孔。
- 如請求項23之接合結構,其中所述保護材料的楊氏模數在20GPa至200GPa之範圍中。
- 如請求項23之接合結構,其中所述保護材料具有在所述第一整合裝置晶粒之熱膨脹係數之10ppm/℃內的熱膨脹係數。
- 如請求項29之接合結構,其中所述保護材料包括二氧化矽。
- 如請求項23之接合結構,其中所述保護材料包括在所述第一整合裝置的側表面上的第一保護層和在所述第二整合裝置的側表面上的第二保護層,所述第一保護層和所述第二保護層之間具有介面。
- 如請求項23之接合結構,其中所述保護材料包括在所述第一整合裝置晶粒和所述第二整合裝置晶粒的所述側表面上的第一保形層和設置在所述第一整合裝置晶粒和所述第二整合裝置晶粒的所述側表面上的所述第一保形 層上方的第二填充層。
- 如請求項32之接合結構,其中所述第一保形層比所述第一整合裝置晶粒的塊狀半導體材料還硬。
- 如請求項23之接合結構,其中所述載體包括基板,所述基板包括玻璃或矽。
- 一種用於封裝晶粒之方法,所述方法包含:在沒有介入黏著劑下,將多個第一整合裝置晶粒直接接合至載體,以使得所述第一整合裝置晶粒的各自接合表面和所述載體直接接觸;在直接接合之後提供保護材料,所述保護材料包括在所述第一整合裝置晶粒的表面上的第一層;及平坦化所述第一層的至少一部分以移除所述第一整合裝置晶粒的部分。
- 如請求項35之方法,其中所述第一層具有在所述第一整合裝置晶粒之熱膨脹係數之10ppm/℃內的熱膨脹係數。
- 如請求項35之方法,其中平坦化包括移除所述第一整合裝置晶粒的背側的部分以暴露所述第一整合裝置晶粒的背表面。
- 如請求項35之方法,其中提供所述第一層包括將所述第一層沉積至不小於所述第一整合裝置晶粒之厚度的厚度,所述第一整合裝置晶粒之所述厚度界定於所述第一整合裝置晶粒之背表面與前表面之間。
- 如請求項35之方法,進一步包括在所述第一層上提供第二層且移除所述第二層的至少一部分。
- 一種用於封裝整合裝置晶粒之方法,所述方法包含:將多個單粒化的整合裝置晶粒直接接合至載體,以所述多個單粒化的整合裝置晶粒的各自接合表面和所述載體直接接觸;在直接接合之後提供保護材料,所述保護材料在所述多個單粒化的整合裝 置晶粒的被曝露的表面上,所述表面包括所述多個單粒化的整合裝置晶粒的側壁表面;以及在提供所述保護材料之後,薄化所述多個單粒化的整合裝置晶粒。
- 如請求項40之方法,其進一步包括形成穿透所述多個單粒化的整合裝置晶粒的至少一部份的互連件。
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