TWI434416B - 通道穿過一埋藏介電層的記憶體晶格 - Google Patents

通道穿過一埋藏介電層的記憶體晶格 Download PDF

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TWI434416B
TWI434416B TW099143141A TW99143141A TWI434416B TW I434416 B TWI434416 B TW I434416B TW 099143141 A TW099143141 A TW 099143141A TW 99143141 A TW99143141 A TW 99143141A TW I434416 B TWI434416 B TW I434416B
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trench
region
insulating layer
source
channel
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TW201138115A (en
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Carlos Mazure
Richard Ferrant
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Soitec Silicon On Insulator
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Description

通道穿過一埋藏介電層的記憶體晶格
本發明的領域為半導體裝置，更特別的是，屬於包含多個記憶體晶格之記憶體裝置的領域。
更特別的是，本發明係有關於一種由具有浮動通道或浮動閘極之FET(場效電晶體)形成的記憶體晶格，以及一種由多個此類記憶體晶格組成的記憶體陣列。
第1圖的橫截面圖係圖示習知浮動通道DRAM記憶體晶格(DRAM為動態隨機存取記憶體的簡寫)。此晶格係形成於包含經由埋藏氧化物層2(BOX)而與半導體基板1隔開之薄矽層3的SOI(絕緣體上矽)基板。浮動通道4、源極區5及汲極區6均形成於在BOX層2上方的薄層3。閘極介電層7與控制閘電極8(control gate electrode)係依序沉積浮動通道4上方。汲極區6連接至位元線BL，源極區5連接至源極線SL，以及閘電極8連接至字元線WL。
浮動通道被BOX層、閘極介電層、源極區及汲極區電氣隔離。由於有此隔離，導致浮動通道跟電容器一樣可儲存電荷。
在寫入資料於此電晶體的操作期間，浮動通道通過衝擊離子化效應(impact ionization effect)來儲存電荷，從而修改電晶體的臨界電壓。因而，在資料讀取操作期間，在電晶體的源極、汲極之間流動的電流量會取決於儲存於浮動通道的電荷數量。
儘管製作較小的電晶體致使較多個電晶體可整合於一基板上，然而縮小比例可能產生不合意的效應。特別是，有相對短之通道的FET電晶體可能會有習稱短通道效應(SCE)的不合意電氣特性。
由於半導體裝置的尺寸持續地減少，證明SCE現象的問題也會跟著會增加。
針對積體電路物理尺寸減少的解決方案之一是形成有埋藏於通道之閘極區的所謂“埋藏閘極式”電晶體。
不同於在通道上方形成控制閘電極(用閘極介電層與其隔離)於基板表面上的習知平面電晶體，埋藏閘極式電晶體的控制閘電極係填滿經形成有通道之厚度的溝槽。
在美國專利第US 2006/0220085號的文獻中有舉例描述此類電晶體，縮寫為RCAT(凹槽通道陣列電晶體)。
藉由提供延伸進入基板的閘極區，可增加通道的有效長度，從而使得埋藏閘極式RCAT電晶體有較小的SCE。
儘管在65奈米及45奈米技術的情形下，此類RCAT電晶體有助於解決與通道尺寸減少有關的問題，然而在下一代(尤其是，32奈米)技術的情形下，通道的體積會小到只能儲存數量很少的電荷。因此，可明白，少數幾個電荷的變化則可能導致相對大的擾動。
舉例說明之，基於SOI的平面電晶體只能包含數十個電荷。僅僅失去一個電荷則表示會損失約百分之2的訊號。此時，每次存取與處於保存模式(retention mode)之晶格共享連線的晶格可能通過在每個周期藉由耦合來“唧取”例如一或多個電荷而干擾該晶格。
因此，亟須一種可排除先前技術由小通道體積所致之前述缺點的記憶體晶格。本發明的目標是要滿足這些要求，而且為此，根據第一方面，本發明提供一種記憶體晶格，其係包含：
-　一絕緣體上半導體基板(semiconductor-on-insulator substrate)，其係包含藉由一絕緣層而與一底座基板隔開的一半導體材料薄層；
-　一FET電晶體，其係包含至少實質配置於該絕緣體上半導體基板之該薄層中的一源極區與一汲極區，有一溝槽製造於其中的一通道，以及在該溝槽中之一閘極區，
其特徵在於：該溝槽延伸超過該絕緣層進入該底座基板的深度以及該通道至少實質在該絕緣層下方延伸於該源極區與該汲極區之間。
此記憶體晶格之方面有以下特徵為較佳，但不具限定性：
-　該汲極區與該源極區係整體地配置於該絕緣體上半導體基板之該薄層中，以及一通道傳導區(channel conduction region)在該絕緣層水平配置於該溝槽之兩側使得該通道經由該通道傳導區在該絕緣層的上下方延伸於該源極區與該汲極區之間；
-　該源極及汲極區係各自經由一源極傳導區(source conduction zone)與一汲極傳導區在該絕緣層的上下方延伸，該等區域在該絕緣層水平配置於該溝槽之兩側，以及該通道在該絕緣層下方整體地延伸於該源極及汲極區在該絕緣層下方的部份之間；
-　該閘極區係藉由一介電層而與該通道隔開；
-　該通道在該絕緣層下方的部份係由製作於該底座基板之上半部的一阱區(well)形成；
-　該阱區係藉由傳導性與該阱區相反的一層來與該底座基板之其餘部份隔離；
-　該晶格更包含屬於該通道在該絕緣層下方之部份且沿著深度在該絕緣層下方延伸的數個橫向隔離區(lateral isolation region)；
-　該FET電晶體為部份空乏型(partially depleted)，以及該晶格更包含屬於該通道在該絕緣層上方之部份的數個橫向隔離區；
-　該通道為浮動型，以及該閘極區用作用以驅動該FET電晶體的控制閘電極；
-　該晶格更包含一雙極電晶體(bipolar transistor)，該雙極電晶體之集極(collector)係用作該FET電晶體的通道；
-　該FET電晶體的源極係用作該雙極電晶體的基極(base)；
-　該底座基板係用作該雙極電晶體的基極；以及
-　該閘極區為浮動型，以及該FET電晶體更包含經由一介電層而與該浮動閘極區隔離的一控制閘電極。
根據另一方面，本發明有關於包含如本發明第一方面所述之多個記憶體晶格的記憶體陣列。
根據又一方面，本發明有關於一種用於製造記憶體晶格的方法，其特徵在於有下列步驟：
-　在該絕緣體上半導體基板中形成一溝槽使得該溝槽延伸超過該絕緣層；
-　用一層半導體材料覆蓋該溝槽之壁面；
-　在該材料上進行再結晶退火操作(recrystallization annealing operation)，讓材料再結晶使得：
o　位在該絕緣層上下方的區域處於單晶態(single-crystal state)；
o　在該絕緣層水平為多晶態(polycrystalline state)以便在該絕緣層水平與該溝槽之側面定義在該溝槽兩側之該通道傳導區；
-　用一介電層覆蓋該溝槽之壁面；以及
-　藉由填滿該溝槽來形成一閘極區。
根據又一方面，本發明有關於一種用於製造記憶體晶格的方法，其特徵在於有下列步驟：
-　在該絕緣層正下方，形成一摻雜層，該摻雜層旨在定義在該絕緣層下方延伸於該溝槽之兩側的源極區及汲極區；
-　在該絕緣體上半導體基板中形成一溝槽使得該溝槽延伸超過該絕緣層；
-　用一層半導體材料覆蓋該溝槽之壁面；
-　用一介電層覆蓋該溝槽之壁面；
-　藉由填滿該溝槽來形成一閘極區；以及
-　導致該摻雜物由在該絕緣層上下方之該源極及汲極區各自在該絕緣層水平沿著該溝槽之壁擴散，以便形成該源極傳導區及汲極傳導區，使得各自在該絕緣層上下方延伸之該等源極區及該等汲極區相連接。
根據又一方面，本發明有關於一種用於製造記憶體晶格的方法，其特徵在於有下列步驟：
-　在該絕緣體上半導體基板中形成一第一溝槽，該第一溝槽係由該絕緣體上半導體基板之表面向下延伸至該底座基板；
-　用傳導性與想要在該絕緣層上方延伸之該汲極及源極區相同的數個摻雜間隔體(doped spacer)覆蓋該第一溝槽之壁面；
-　在該第一溝槽中形成一第二溝槽，該第二溝槽係由該第一溝槽之底部延伸超過該絕緣層進入該底座基板之深度；
-　用一介電層覆蓋該第二溝槽及該第一溝槽之壁面；
-　藉由填滿該第二溝槽及該第一溝槽來形成一閘極區；以及
-　在該第二溝槽之兩側藉由擴散自該等間隔體之摻雜物來形成局部源極及汲極區於該絕緣層正下方，在摻雜物擴散後，該等間隔體各自用作通道傳導區與汲極傳導區，以便連接在該絕緣層上下方延伸之該源極及汲極區。
第2a圖的橫截面圖係根據本發明第一方面圖示DRAM記憶體晶格之第一可能具體實施例，其係包含具有源極S、汲極D、以及在源極、汲極間之通道C的FET電晶體。
該記憶體晶格係於SeOI基板(絕緣體上半導體基板)上製成，SOI基板(絕緣體上矽基板)為較佳，該基板包含藉由一絕緣層(例如，埋藏氧化物層BOX)而與底座基板隔開的一薄層半導體材料。
在此第一具體實施例的背景下，汲極D與源極S係整體地配置於SeOI基板之薄層中。
通道C本身在絕緣層的上下方延伸。通道在絕緣層上方之部份與通道在絕緣層下方之部份的體積差(通常有200倍至1000倍)，使得，在本發明的背景下，可認為通道實質位於絕緣層的下方。
在第2a圖的背景下，汲極D、源極S均與絕緣層BOX接觸使得FET電晶體為完全空乏(fully depleted)型。
因此，兩個相鄰記憶體晶格(沿著落在第2a圖平面的記憶體陣列的一橫列，該記憶體陣列有數條直行與第2a圖平面垂直)可共享源極S。此一共享可減少記憶體晶格的覆蓋區(footprint)。
不過，本發明不受限於完全空乏的記憶體晶格，也可擴及部份空乏的SeOI記憶體晶格(未圖示)。因此，證明需要以習知方式沿著記憶體陣列之橫列隔離晶格以便產生浮動通道效應。習知方式是用由基板表面向下延伸至BOX層的橫向隔離溝槽來實現。這些溝槽通常提供所謂的STI(淺溝槽隔離)。
汲極D以習知方式連接至位元線BL。此位元線BL可沿著記憶體陣列之一橫列延伸而與沿著此橫列安置的每個記憶體晶格之汲極接觸。
源極S本身連接至源極線SL。此源極線SL通常垂直於位元線BL而與沿著記憶體陣列之直行安置的每個記憶體晶格之源極接觸。就上文以第2a圖圖示的情形而言，兩個相鄰晶格共享源極，單一源極線SL則用來定址這兩個記憶體晶格的源極S。
回到第2a圖的描述，源極S通常包含主要用來與源極線SL接觸的重度摻雜(例如，n+ 型摻雜)中央區21以及包圍該中央區和主要用來操作該電晶體的輕度摻雜(例如，n- 型摻雜)周邊區22。
應注意，汲極D也可具有主要用來與位元線BL接觸的重度摻雜中央區11(例如，n+ 型摻雜)以及包圍該中央區和主要用來操作該電晶體的輕度摻雜周邊區12(例如，n- 型摻雜)。
在此給出的實施例為n型FET電晶體記憶體晶格。不過，應瞭解，本發明不受限於此類型之電晶體，也可擴及p型FET電晶體記憶體晶格。
在本發明的背景下，該通道有一溝槽，以及該FET電晶體在該溝槽中更包含一閘極區G。該溝槽係由絕緣體上半導體基板的表面沿著深度延伸超越該絕緣層進入底座基板。
該溝槽有底部與經由底部連接在一起的側壁。回想前文，沿著記憶體陣列之一直行，該等晶格有用以使該直行之晶格相互隔離的隔離溝槽。因此，溝槽中之閘極區在縱向係以隔離溝槽為界。
此外，在絕緣層水平製作通道傳導區30(參考第2b圖，其係圖示第2a圖中之圓圈區域的放大圖)於絕緣層與溝槽側壁之間使得該通道可經由該通道傳導區在該絕緣層的上下方延伸於源極、汲極之間(從而，基於通道在絕緣層上方之部份與通道在絕緣層下方之部份的體積差，視為該通道實質在絕緣層下方延伸)。
溝槽中之閘極區G係藉由事先沉積於溝槽壁上的介電層31與通道C及通道傳導區30隔開。
以下詳細解釋製造通道傳導區30的一種可能方式。
首先，在SeOI基板形成由絕緣體上半導體基板表面沿著深度超過絕緣層進入底座基板的溝槽。為此，使用有直徑約40奈米之蝕刻圖樣的溝槽遮罩。
然後溝槽壁可塗上一層半導體材料，矽為較佳。
更特別的是，可保形沉積(conformally deposit)非晶矽於SeOI基板的整個表面上(遮罩上及治著溝槽之側壁和底部)。利用非晶材料，特別有可能不破壞構成SeOI基板之薄層的材料之結晶學排列(crystallographic arrangement)。
通常非晶矽的沉積厚度小於10個原子的厚度(5奈米)。
替換地，ALD(原子層沉積法)可用來沉積單矽原子層。
接下來，進行溫和的蝕刻步驟以移除存在於溝槽遮罩上面的沉積矽層。
接下來，對於沿著溝槽壁沉積的矽，進行再結晶退火操作，讓矽再結晶使得：
-　溝槽在絕緣層上下方的區域處於單晶態；
-　在絕緣層水平處於多晶態以便在溝槽的兩側定義通道傳導區30於絕緣層BOX、溝槽壁之間。
在絕緣層水平的再結晶係特別經由來自出現於絕緣層上下方之半導體區的再結晶前緣(recrystallization front)。取決於絕緣層的厚度，該等再結晶前緣甚至可相會。
接下來，以閘極介電層31覆蓋經再結晶之矽層。
然後，填滿溝槽以便形成閘極區G於其中，例如藉由沉積摻雜多晶矽(doped polysilicon)。作為變體，該閘極區可予以金屬化。
回到第2a圖的描述，通道在絕緣層下方的部份由製成於底座基板上半部的阱區40形成為較佳。阱區40可用傳導性與該阱區相反的層50來與底座基板的其餘部份隔離(當阱區的傳導性為p+ 型，它的傳導性為n- 型，例如，在此以n型通道記憶體晶格為例，是用Vdd 偏壓以便強迫產生處於反向偏壓模式的二極體，反向推理適用於p型通道晶格)。
該記憶體晶格更包含通道在絕緣層下方之部份的數個橫向隔離區60，彼等在絕緣層下面沿著深度延伸直到用以使阱區40與底座基板之其餘部份隔離的層50。
應注意，如前述，在部份空乏SeOI記憶體晶格的情形下，區域60所實現的功能與置於絕緣層上方的STI型隔離區一樣。
根據第一可能具體實施例，通道在絕緣層下方之部份的橫向隔離區60為用STI技術製成的隔離溝槽。
根據第二可能具體實施例，區域60均由傳導性與通道相反的半導體材料製成(在此以p- 型通道區40為例，它的傳導性為n+ 型)。
根據本發明的較佳具體實施例(圖示於第2a圖)，該通道為浮動型，以及閘極區用來作為驅動FET電晶體的控制閘電極。
因此，可定義DRAM記憶體晶格使得它的寫入操作經由衝擊離子化效應有可能儲存電荷於在絕緣層BOX上下方延伸的浮動通道。
應瞭解，在本發明的背景下，與習知晶格相比，可增加電荷儲存量(如前述有200至1000倍)，因為浮動通道在絕緣層下方有延伸部份。
換言之，遵循朝向更加減少半導體裝置之尺寸的技術發展藍圖，電荷可儲存於本發明晶格之浮動通道的數量可保持相對不變，或者最起碼減少的速度比習知晶格可觀測到的慢。
特別是，可用更深地埋藏於絕緣層下方的浮動通道來補償半導體裝置沿著X、Y軸(沿著記憶體陣列的橫列、直行)的減少量。
此外，由本發明記憶體晶格組成之記憶體陣列的周邊電路(放大器及解碼器)仍為使用平面電晶體的習知SOI技術。這使得有可能減少可變性、耗電量等等的問題。
根據本發明之一具體實施例(未圖示)，該閘極區為浮動型，以及FET電晶體更包含藉由一介電層而與該浮動閘極區隔離的一控制閘電極。
因此，可定義快閃型記憶體晶格使得它的寫入操作經由熱載子注入(hot carrier injection)的現象有可能儲存電荷於浮動閘極區，該浮動閘極區係形成於溝槽且伸入在絕緣層BOX下方的溝槽。
在此具體實施例的背景下，由於在絕緣層下方延伸之溝槽中形成的浮動閘極區有較大的容積，因此可增加電荷儲存量。
此具體實施例證明對於減少要求高工作電壓之功率電晶體的整體大小特別有利。
第3a圖至第3b圖以及第4a至4b圖係根據本發明圖示DRAM記憶體晶格之第一具體實施例的兩個變體。在該等變體中，雙極電晶體與FET電晶體聯繫以便注入電荷於FET電晶體的通道。因此，雙極電晶體的集極由FET電晶體的通道形成。
在圖示於第3a圖(第3b圖為等價電氣圖)之變體的情形下，FET電晶體的源極(在第3b圖以元件符號9表示)用來作為雙極電晶體的基極(在第3b圖以元件符號71表示)。
在此變體的背景下，雙極電晶體的射極70係經設計成FET電晶體的源極可用作雙極電晶體的基極。一般而言，該FET電晶體為水平電晶體而且該射極係經更精密地設計成射極/源極總成可形成垂直堆疊.
該射極在源極的下半區整合於該源極為較佳。在上述源極包含重度摻雜中央區21及包圍該中央區之輕度摻雜周邊區22的情形下，射極70則經安置成與該源極之中央區接觸同時仍藉由源極之周邊區22而與浮動通道隔離。在此，該射極係完全整合於在中央區21及其周邊區22之間的源極電極。
在完全空乏型SeOI記憶體晶格的情形下，以及如第3a圖所示，該BOX層也可促成射極與浮動通道的隔離。
在圖示於第4a圖(第4b圖為等價電氣圖)之變體的情形下，底座基板(更具體言之，為阱區40的隔離層50)用來作為雙極電晶體的基極(在第4b圖以元件符號72表示)。
因此，雙極電晶體的射極80被安置成可與底座基板接觸(亦即，在圖示實施例中，與阱區的隔離層50接觸)。
在此變體的背景下，該射極設於通道在絕緣層下方之部份的橫向隔離區60之下半部同時仍經由包圍隔離區30以便與浮動通道隔離以及傳導性與底座基板相同(此例為n- 型區)的區域來與隔離區30隔開。
有射極在下面的區域60則最好由傳導性與通道相反的半導體材料形成(此例為n+ 型)。
在上述兩個變體的情形下，射極70、80連接至與源極線SL平行地延伸的注入線(injection line)IL以便定址沿著記憶體陣列之一直行安置的記憶體晶格。結果，在注入線IL不佔用表面區域的情形下，可產生特別緊湊的配置。
注入線IL可特別由摻雜半導體材料製成(在第3a圖變體的情形下，薄層之材料做p+ 型摻雜，而在第4a圖變體的情形下，底座基板之材料做p+ 型摻雜)。
在第二變體的的背景下，FET及雙極電晶體實際上是獨立的，使得各自可優化而不必尋求妥協。
此第二變體更提供附加節點(經由用作雙極電晶體之基極的底座基板，更具體言之，藉由控制阱區40之隔離層50的電壓，如第4b圖之中的GND)。就晶格的寫入/讀取操作而言，此附加節點提供較大的彈性。
以上係描述本發明記憶體晶格的第一具體實施例，其中汲極區及源極區係一體安置於絕緣體上半導體基板之薄層中，以及通道在絕緣層上下方經由通道傳導區延伸於源極區、汲極區之間。
以下用第5a圖及第5b圖描述本發明記憶體晶格第二具體實施例的兩個變體，其中源極區S與汲極區D各自經由在絕緣層水平各自配置於溝槽一側的源極傳導區90與汲極傳導區100在絕緣層的上方(91、21、22；101、11、12)與下方(92、93；102、103)延伸。不過，在各自位於該絕緣層上方的源極區及汲極區的容積實質高於各自位於該絕緣層下方的源極區及汲極區的容積(通常有200倍至1000倍)的情形下，視為該源極及汲極區實質位於該薄層中。
通道C本身整體地在絕緣層下方延伸於源極區在絕緣層下方之部份92、93與汲極區在絕緣層下方之部份102、103之間。
第5a圖及第5b圖中，元件符號91(替換地，元件符號101)表示源極區S(替換地，汲極區D)在絕緣層上方的部份，請參考第2a圖，該源極區S係由中央區22(替換地，12)與周邊區21(替換地，11)組成。
在圖示於第5a圖之變體的背景下，源極及汲極區在絕緣層下方的部份92、102係由摻雜層形成，該摻雜層位在底座基板表面上，在絕緣層的正下方，以及在此以n-FET電晶體為例的情形下，其傳導型為n-型。
此摻雜層包含藉由溝槽相互隔開的源極區92與汲極區102。
在圖示於第5b圖之變體的背景下，源極及汲極區在絕緣層下方的部份93、103各自由一局部源極區與一局部汲極區形成，該局部源極區及局部汲極區在絕緣層的正下方各在溝槽一邊。
局部區93與103各自形成源極及汲極貯池(reservoir)或囊體(pocket)。通道係於該等貯池或囊體之間在絕緣層下方整體地延伸。
應指明，藉由添加囊體93、103至摻雜層92、102可組合圖示於第5a圖及第5b圖的變體。
此外，可將該等變體實作成第5a圖及第5b圖之完全空乏型記憶體晶格與部份空乏型記憶體晶格(在此情形下，STI隔離需要在絕緣層上方以便使晶格相互隔開)。
至於在圖示於第2a圖之具體實施例的情形下，第5a圖及第5b圖的記憶體晶格更包含數個橫向通道隔離區，彼等係沿著深度在絕緣層下方延伸直到用於使阱區40與底座基板之其餘部份隔離的層50。
以下詳細解釋製造第5a圖之晶格的一可能方法。
在用以藉由在絕緣層下方植入摻雜物於底座基板中來製造正面型電晶體(front-face transistor)的任何製程之前，形成在絕緣層下方的區域(例如，阱區40、射極80、想要形成源極92及汲極102區的層)。
然後，用與形成第2a圖晶格類似的方式，在SeOI基板中形成溝槽，該溝槽由絕緣體上半導體基板的表面延伸超越絕緣層沿著深度進入底座基板。
就形成晶格2a的情形而言，隨後，藉由用ALD技術來共形沉積非晶矽或沉積矽，使溝槽壁覆上一層半導體材料，矽為較佳。
也可進行溫和的蝕刻操作以便移除存在於溝槽遮罩上面的沉積矽層。
接下來，形成沿著溝槽壁的閘極介電層31。然後，填滿該溝槽以便形成閘極區G於其中，例如藉由沉積摻雜多晶矽。作為變體，該閘極區可予以金屬化。
接下來，進行退火操作以便使摻雜物在絕緣層水平由各在絕緣層上下透的源極及汲極區沿著溝槽壁擴散，以便在溝槽兩側形成源極傳導區90與汲極傳導區100。應注意，該擴散退火操作可使在絕緣層下方的區域再結晶。至於在絕緣層上下方的區域不一定有相同的晶體取向(crystalline orientation)，兩個單一晶體之間儘量有完美但不必絕對的接面。這是為何在絕緣層下方想要在絕緣層下方形成源極區92及汲極區102的摻雜層具有傳導性(例如，n+型)與在通道上方之源極區91及汲極區101相同的理由之一。因此，這可有效避免通道(p-型)產生晶體缺陷以及無意中促成對晶格保持電荷有害的電荷再結合。
在擴散退火操作後，源極區91、92與汲極區101、102則各自經由源極傳導區90、汲極傳導區100在絕緣層上下方延伸。
以下詳細解釋製造第5b圖之晶格的一可能方法。
在用以藉由在絕緣層下方植入摻雜物於底座基板中來製造正面型電晶體的任何製程之前，形成在絕緣層下方的區域(例如，阱區40、射極80)。
接下來，在絕緣體上半導體基板中形成第一溝槽，該第一溝槽係由絕緣體上半導體基板的表面向下延伸至底座基板使得第一溝槽的厚度對應至薄層與絕緣層的組合厚度。
接下來，用間隔體覆蓋第一溝槽的壁面，在圖示於此的n型電晶體之示範具體實施例中，該等間隔體係經n-型摻雜。為此，例如，沉積摻雜多晶矽。
接下來，在第一溝槽中形成第二溝槽，該第二溝槽係沿著深度由第一溝槽的底部伸入底座基板，該等間隔體界定該第二溝槽的開口。
接下來，沿著該第二溝槽的壁面形成閘極介電層31。然後，填滿該第二及第一溝槽以便形成閘極區G於其中，例如藉由沉積摻雜多晶矽。作為變體，該閘極區可予以金屬化。
此外，藉由從間隔體擴散進入底座基板的摻雜物來在溝槽兩側形成在絕緣層正下方的局部源極與汲極區93、103。因此，該等間隔體可定義用作傳導層的源極傳導區90及汲極傳導區100用以連接在絕緣層上下方延伸的源極區及汲極區。
由上述可瞭解，本發明不受限於第一方面的記憶體晶格，本發明也可擴及包含本發明第一方面之多個記憶體晶格的記憶體陣列，以及也可擴及用於製造該記憶體晶格的方法。
1．．．半導體基板
2．．．埋藏氧化物層
3．．．薄矽層
4．．．浮動通道
5．．．源極區
6．．．汲極區
7．．．閘極介電層
8．．．控制閘電極
9．．．源極
11．．．重度摻雜中央區
12．．．輕度摻雜周邊區
21．．．重度摻雜中央區
22．．．輕度摻雜周邊區
30．．．通道傳導區
31．．．介電層
40．．．阱區
50．．．層
60．．．橫向隔離區
70．．．射極
71．．．基極
72．．．基極
80．．．射極
90．．．源極傳導區
91．．．源極區
92．．．源極區
93、103．．．位於絕緣層下方的源極、汲極區
100．．．汲極傳導區
101．．．汲極區
102．．．汲極區
BL‧‧‧位元線
BOX‧‧‧絕緣層
C‧‧‧通道
D‧‧‧汲極
G‧‧‧閘極區
IL‧‧‧注入線
S‧‧‧源極
SL‧‧‧源極線
WL‧‧‧字元線
閱讀以下以不具限定性之實例及附圖描述本發明之較佳具體實施例的說明可更加明白本發明的其他方面、目標及優點。
第1圖圖示上文已提及之習知浮動通道DRAM晶格；
第2a圖根據本發明之第一方面圖示DRAM記憶體晶格之第一具體實施例；
第2b圖為第2a圖之放大圖，其係圖示在絕緣層水平有在溝槽兩側的通道傳導區；
第3a圖及第3b圖分別以橫截面圖與等價電氣圖圖示本發明晶格第一具體實施例之一變體，其中雙極電晶體與FET電晶體聯繫以便注入電荷於FET電晶體之通道；
第4a圖及第4b圖分別以橫截面圖與等價電氣圖圖示晶格第一具體實施例之另一變體，其係使用用以注入電荷於FET電晶體之通道的雙極電晶體；以及
第5a圖及第5b圖根據本發明之第一方面圖示記憶體晶格第二可能具體實施例之兩個變體。
11．．．重度摻雜中央區
12．．．輕度摻雜周邊區
21．．．重度摻雜中央區
22．．．輕度摻雜周邊區
50．．．層
60．．．橫向隔離區
BL．．．位元線
BOX．．．絕緣層
C．．．通道
D．．．汲極
S．．．源極
WL．．．字元線

Claims (13)

  1. 一種記憶體晶格，包含：一絕緣體上半導體基板，包含藉由一絕緣層(BOX)而與一底座基板隔開的一半導體材料薄層；一FET電晶體，包含至少實質配置於該絕緣體上半導體基板之該薄層中的一源極區(S)與一汲極區(D)，一溝槽製造於其中的一通道(C)，以及一閘極區(G)在該溝槽之中，其特徵在於該溝槽延伸超過該絕緣層(BOX)進入該底座基板的深度以及該源極及汲極區係各自經由一源極傳導區與一汲極傳導區在該絕緣層的上下方延伸，該等傳導區在該絕緣層(BOX)水平配置於該溝槽之兩側，以及該通道在該絕緣層下方整體地延伸於該源極及汲極區在該絕緣層下方的部份(92、102；93、103)之間。
  2. 如申請專利範圍第1項之記憶體晶格，其中該閘極區(G)係藉由一介電層(31)而與該通道隔開。
  3. 如申請專利範圍第1項至第2項中任一項之記憶體晶格，其中該通道在該絕緣層下方係由製作於該底座基板之上半部的一阱區(40)形成。
  4. 如申請專利範圍第3項之記憶體晶格，其中該阱區(40)係藉由傳導性與該阱區相反的一層(50)來 與該底座基板之其餘部份隔離。
  5. 如申請專利範圍第1項至第4項中任一項之記憶體晶格，更包含該通道在該絕緣層下方且沿著深度在該絕緣層下方延伸的數個橫向隔離區(60)。
  6. 如申請專利範圍第1項之記憶體晶格，其中該通道為浮動型，以及該閘極區用作用以驅動該FET電晶體的控制閘電極。
  7. 如申請專利範圍第6項之記憶體晶格，更包含一雙極電晶體(71、72)，該雙極電晶體(71、72)之集極係用作該FET電晶體的通道。
  8. 如申請專利範圍第7項之記憶體晶格，其中該FET電晶體的源極係用作該雙極電晶體(71)的基極。
  9. 如申請專利範圍第7項之記憶體晶格，其中該底座基板係用作該雙極電晶體(72)的基極。
  10. 如申請專利範圍第1項之記憶體晶格，其中該閘極區為浮動型，以及該FET電晶體更包含經由一介電層而與該浮動閘極區隔離的一控制閘電極。
  11. 一種記憶體陣列，其係包含如申請專利範圍第1項所述的多個記憶體晶格。
  12. 一種用於製造如申請專利範圍第1項之記憶體晶格的方法，其特徵在於具有下列步驟：在該絕緣層正下方，形成一摻雜層，該摻雜層旨在定義在該絕緣層下方延伸於該溝槽之兩側的源極區(92)及汲極區(102)；在該絕緣體上半導體基板中形成該溝槽使得該溝槽延伸超過該絕緣層；用一層半導體材料覆蓋該溝槽之壁面；用一介電層覆蓋該溝槽之該等壁面；藉由填滿該溝槽來形成一閘極區；以及導致該摻雜物由在該絕緣層上下方之該源極及汲極區各自在該絕緣層水平沿著該溝槽之壁擴散，以便形成該源極傳導區(90)及汲極傳導區(100)，使得各自在該絕緣層上下方延伸之該等源極區(91、92)及該等汲極區(101、102)相連接。
  13. 一種用於製造如申請專利範圍第1項之記憶體晶格的方法，其特徵在於具有下列步驟：在該絕緣體上半導體基板中形成一第一溝槽，該第一溝槽係由該絕緣體上半導體基板之表面向下延伸至該底座基板；用傳導性與想要在該絕緣層上方延伸之該汲極 及源極區相同的數個摻雜間隔體覆蓋該第一溝槽之該等壁面；在該第一溝槽中形成一第二溝槽，該第二溝槽係由該第一溝槽之底部延伸超過該絕緣層進入該底座基板之深度；用一介電層覆蓋該第二溝槽及該第一溝槽之該等壁面；藉由填滿該第二溝槽及該第一溝槽來形成一閘極區；以及在該第二溝槽之兩側藉由擴散自該等間隔體之摻雜物來形成局部源極(93)及汲極(103)區於該絕緣層正下方，在摻雜物擴散後，該等間隔體各自用作通道傳導區與汲極傳導區，以便連接在該絕緣層上下方延伸之該源極及汲極區。
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TW201138115A (en) 2011-11-01
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US8304833B2 (en) 2012-11-06
SG173255A1 (en) 2011-08-29

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