CN102184926B - 沟道穿过埋入介电层的存储单元 - Google Patents

沟道穿过埋入介电层的存储单元 Download PDF

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CN102184926B
CN102184926B CN201010625058.7A CN201010625058A CN102184926B CN 102184926 B CN102184926 B CN 102184926B CN 201010625058 A CN201010625058 A CN 201010625058A CN 102184926 B CN102184926 B CN 102184926B
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insulating barrier
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CN102184926A (zh
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卡洛斯·马祖拉
理查德·费朗
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Soitec SA
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Abstract

本发明的第一方面涉及一种存储单元，该存储单元包括：绝缘体上半导体基板，其包括通过绝缘层BOX与底部基板间隔开的半导体材料的薄层；FET晶体管，其包括源区S和漏区D、内有沟槽的沟道C，以及位于该沟槽中的栅区G，其中，该源区和该漏区至少基本上被布置在该绝缘体上半导体基板的该薄层内，其特征在于，该沟槽沿该底部基板的深度方向延伸超过该绝缘层BOX，并且该沟道至少基本上在该绝缘层下方在该源区和该漏区之间延伸。本发明还涉及一种包括多个根据本发明第一方面的多个存储单元的存储阵列，还涉及一种制造上述存储单元的制造工艺。

Description

沟道穿过埋入介电层的存储单元
技术领域
本发明涉及半导体器件的领域，更具体地说，涉及包括多个存储单元的存储器件的领域。
本发明特别涉及一种由具有浮沟(floating channel)或浮栅(floating gate)的场效应晶体管(FET)形成的存储单元，以及由多个这种存储单元组成的存储阵列。
背景技术
图1所示为传统浮沟DRAM(动态随机存取存储器)存储单元的截面图。该存储单元形成在SOI(绝缘体上硅)基板上，该SOI基板包括通过埋入式氧化物层(BOX)2与半导体基板1间隔开的薄硅层3。浮沟4、源区5和漏区6都形成在薄硅层3中BOX层2上方。栅介电层7和控制栅极8依次被沉积在浮沟4上方。漏区6与位线(bit line)BL相连接，源区5与源线(source line)SL相连接，栅极8与字线(wordline)WL相连接。
浮沟通过BOX层与栅介电层、源区和漏区电绝缘。由于这种绝缘，浮沟能够存储电荷，从而产生了与电容器相同的结果。
在向这种晶体管中写入数据的操作过程中，浮沟通过碰撞离化效应来存储电荷，从而调整晶体管的阈值电压。因此，在数据读取操作过程中，在晶体管的源漏之间流动的电流量取决于存储在浮沟中的电荷量。
尽管制造更小的晶体管能够更多地将它们集成在同一个基板上，但是小型化会导致不希望的效果。具体来讲，沟道长度相对较短的场效应晶体管可能产生不希望的电学特性，称之为短沟道效应(SCE)。
由于半导体器件尺寸的不断减小，SCE现象成为愈加严重的问题。
一个解决集成电路物理尺寸缩小的办法就是形成所谓的“埋栅”晶体管，这种晶体管具有埋入在沟道内的栅区。
与控制栅极形成在基板表面上的沟道上方(通过栅介电层与之绝缘)的传统平面晶体管不同，埋栅晶体管的控制栅极填充在被形成在沟道厚度上的沟槽(trench)内。
这样的晶体管也被简称为RCAT(凹沟道阵列晶体管)，例如在专利文献US2006/0220085中有所描述。
通过提供延伸到基板中的栅区，沟道的有效长度得到增加，从而使得埋栅RCAT晶体管有更小的SCE。
尽管这种RCAT晶体管有助于解决65nm和45nm技术情况下沟道尺寸减小带来的问题，但是在下一代技术情况下(尤其是32nm技术)问题依然存在，沟道体积太小以致于只有少量的电荷能被存储在其中。因此，应该理解，只要少量的电荷变化就能引起相对大的微扰。
举一个例子，基于SOI的平面晶体管只能包含几十个电荷。只损失一个电荷就表现出信号大约2％的损失。目前，每一次对与处于保持模式(retention mode)的单元相连接的单元的存取都可能因为耦合“抽取”而扰动到所述单元，例如每次循环中一或多个电荷。
发明内容
因此存储单元需要避免上述现有技术中存在的由于小沟道体积而导致的缺陷。本发明的目的是满足这些需要，为了这个目的，根据第一方面，本发明提供了一种存储单元，该存储单元包括：
绝缘体上半导体基板，其包括通过绝缘层与底部基板(base substrate)之间间隔开的半导体材料的薄层；
FET晶体管，其包括源区和漏区、内有沟槽的沟道，以及位于该沟槽中的栅区，其中源区和漏区至少基本上被布置在该绝缘体上半导体基板的薄层内，
其特征在于，该沟槽沿该基板深度方向延伸超过该绝缘层，并且该沟道至少基本上在该绝缘层下方在该源区和该漏区之间延伸。
当然优选的但非限定性的是，该存储单元如下所述：
所述漏区和所述源区整体布置在所述绝缘体上半导体基板的薄层内，并且沟道传导区(channel conduction region)布置在所述沟槽的任一侧、与所述绝缘层等高的位置，使得所述沟道经由所述沟道传导区同时在所述绝缘层上方和下方、在所述源区和所述漏区之间延伸；
所述源区和所述漏区分别经由源传导区和漏传导区同时在所述绝缘层上方和下方延伸，这些传导区布置在所述沟槽任一侧与所述绝缘层等高的位置，并且所述沟道完全在所述绝缘层下方、在所述源区和所述漏区的位于所述绝缘层下方的部分之间延伸；
所述栅区通过介电层与所述沟道间隔开；
所述沟道的位于所述绝缘层下方的那部分是由在所述底部基板的上部中制成的阱来形成的；
所述阱通过与该阱的导电类型(conductivity)相反的层与所述底部基板的其余部分相隔离；
所述存储单元还包括所述沟道的位于所述绝缘层下方的那部分的横向隔离区，其在所述绝缘层下方沿深度方向延伸；
所述FET晶体管是部分耗尽的，而且所述存储单元还包括所述沟道的位于所述绝缘层上方的那部分的横向隔离区；
所述沟道是浮置(floating)的，并且所述栅区充当驱动所述FET晶体管的控制栅极；
所述存储单元还包括双极型晶体管，其集电极充当所述FET晶体管的沟道；
所述FET晶体管的源极充当该双极型晶体管的基极；
所述底部基板充当该双极型晶体管的基极；
所述栅区是浮置的，并且所述FET晶体管还包括经由介电层与浮置的栅区相隔离的控制栅极。
根据另一方面，本发明涉及一种存储阵列，该存储阵列包括多个根据本发明第一方面的存储单元。
根据再一方面，本发明涉及一种制造存储单元的工艺，其特征在于包括以下步骤：
在绝缘体上半导体基板上形成沟槽，使该沟槽延伸超过绝缘层；
用一层半导体材料覆盖该沟槽的壁(wall)；
对所述材料实施再结晶退火操作，使得该材料：
在位于所述绝缘层上方和下方的区域中再结晶为单晶态；
在与所述绝缘层等高处再结晶为多晶态，从而在与所述绝缘层BOX等高的位置处的所述沟槽的任一侧并且在所述沟槽的横向表面处限定出所述沟道传导区。
用介电层来覆盖所述沟槽的壁；以及
通过填充所述沟槽来形成栅区。
根据再一方面，本发明涉及一种制造存储单元的工艺，其特征在于包括以下步骤：
在绝缘层的正下方形成掺杂层，以在沟槽的任一侧限定出在所述绝缘层的下方延伸的源区和漏区；
在绝缘体上半导体基板中形成沟槽，使得该沟槽延伸超过所述绝缘层；
用一层半导体材料覆盖所述沟槽的壁；
用介电层覆盖所述沟槽的所述壁；
通过填充所述沟槽来形成栅区；以及
使掺杂剂分别从位于绝缘层上方和下方的源区和漏区、沿与绝缘层等高处的沟槽的壁进行扩散，以形成源传导区和漏传导区，从而能够将分别延伸到绝缘层上方和下方的源区和漏区连接起来。
根据再一方面，本发明涉及一种制造存储单元的工艺，其特征在于包括以下步骤：
在绝缘体上半导体基板上形成第一沟槽，该第一沟槽从绝缘体上半导体基板的表面向下延伸到底部基板；
用掺杂间隔物覆盖第一沟槽的壁，该掺杂间隔物的导电类型与要在绝缘层上方延伸的源区和漏区相同；
在第一沟槽中形成第二沟槽，所述第二沟槽沿深度方向从第一沟槽的底部向底部基板延伸而超过所述绝缘层；
用介电层覆盖所述第二沟槽的壁和第一沟槽的壁；
通过填充所述第二沟槽和第一沟槽来形成栅区；以及
通过从所述间隔物扩散掺杂剂，在绝缘层的正下方所述第二沟槽的任一侧上形成局部源区和漏区，进行了掺杂剂扩散后的所述间隔物分别充当沟道传导区和漏传导区，以将在绝缘层上方和下方延伸的源区和漏区连接起来。
附图说明
另一方面，通过以下参照附图以非限定方式给出的对优选实施方式的更详细阐述，本发明的目的和优点将会变得更加明了。附图中：
图1为上面已经描述过的传统浮沟DRAM单元；
图2a所示为根据本发明第一方面的DRAM存储单元的第一实施方式；
图2b所示为图2a所示的在与绝缘层等高处沟槽任一侧出现的沟道传导区的局部放大图；
图3a和图3b所示为根据本发明第一实施方式的存储单元的一个变型例，其中双极型晶体管与FET晶体管相结合以向FET晶体管的沟道中注入电荷，分别以截面图和等效电路图的方式示出；
图4a和4b所示为根据本发明第一实施方式的存储单元的另一个变型例，采用双极型晶体管来将电荷注入到FET晶体管的沟道中，分别以截面图和等效电路图的方式示出；
图5a和5b所示为根据本发明第一方面的存储单元的第二个可能实施方式的两个变型例。
具体实施方式
图2a所示为根据本发明第一方面的第一个可能实施方式的DRAM存储单元的截面图，包括具有源极S、漏极D以及源极与漏极之间的沟道C的FET晶体管。
存储单元被制造在SeOI(绝缘体上半导体)基板上，优选是SOI(绝缘体上硅)基板上，包括通过绝缘层(例如埋入式氧化物层BOX)与底部基板间隔开的半导体材料薄层。
在第一实施方式的背景下，漏极D和源极S完全布置在SeOI基板的该薄层中。
沟道C本身同时在绝缘层的上方和下方延伸。沟道的位于绝缘层上方的部分和沟道的位于绝缘层下方的部分之间的体积差(典型为200-1000的因子)在本发明中被认为，使得沟道基本上位于绝缘层的下方。
如图2a所示，漏极D和源极S与BOX绝缘层相接触，从而FET晶体管被充分耗尽。
因此，相邻两个存储单元(沿着图2a所示平面中存储阵列的行、与图2a所示平面垂直的方向的存储阵列的列)共享一个源极S。这种分享能够减小存储单元的覆盖区(footprint)。
可是，本发明不仅局限于全耗尽存储单元，同样也可以是部分耗尽的SeOI存储单元(未示出)。因此证明在众所周知的传统模式中，必须对沿存储阵列的行方向的单元进行间隔，使得能产生浮沟效应。传统上是借助于从基板的表面到BOX层在深度方向延伸的横向间隔沟槽来实现上述间隔的。这些沟槽通常提供了所谓的STI(浅沟槽间隔)。
在传统模式下，漏极D和位线BL相连接。位线BL可以沿存储阵列的行来延伸，从而与沿该行放置的每一个存储单元的漏极相接触。
源极S本身和源极线SL连接。源极线SL通常与位线BL垂直排列，与沿存储阵列的列方向放置的每一个存储单元的源极相接触。图2a所示即为上述情况，其中源极被相邻的两个单元共享，于是单个源极线SL就充当了两个存储单元的源极的地址(address)。
回到图2a的描述，源极S通常包括主要用于和源极线SL连接的重掺杂(如n+掺杂)中心区21，和主要用于操作该晶体管的围绕中心区的轻掺杂(如n-掺杂)外周区22。
需要注意的是，漏极D也有主要用于与位线BL连接的重掺杂(如n+掺杂)中心区11，和主要用于操作该晶体管的围绕中心区的轻掺杂(如n-掺杂)外周区12。
本例中所示为n型FET晶体管存储单元。可是，需要理解的是本发明不局限于这种晶体管，也可以是p型FET晶体管存储单元。
在本发明的上下文中，沟道具有沟槽，而场效应晶体管还包括沟槽中的栅区G。沟槽从绝缘体上半导体基板的表面沿深度方向延伸到底部基板中超过绝缘层。
沟槽具有底部和几个经由底部连接在一起的侧壁。这样，沿存储阵列的列方向，存储单元具有用于使该列上的存储单元彼此间隔的间隔沟槽。因此沟槽中的栅区被这些间隔沟槽纵向限制。
沟道传导区30(参见图2b，示出了图2a中画圈部分的放大图)也形成在与绝缘层和沟槽壁之间的绝缘层等高的位置，使得沟道能够经由沟道传导区同时在绝缘层上方和下方、源极与漏极之间延伸(因此，考虑到沟道的位于绝缘层上方的部分和沟道的位于绝缘层下方的部分的体积差，沟道基本上延伸到沟道下方)。
沟槽中的栅区G通过预先沉积在沟槽壁上的介电层31与沟道C以及沟道传导区30相间隔。
下面详细解释一种可能的产生沟道传导区30的方式。
首先在SeOI基板上形成沟槽，使之从绝缘体上半导体基板的表面、超过绝缘层沿着深度方向延伸至底部基板中。为此，使用直径约40nm的带有蚀刻图形的沟槽掩模。
之后，用一层半导体材料(优选为硅)来覆盖沟槽的壁。
更具体来讲，可以在SeOI基板的整个表面(在掩模上沿着沟槽的壁和底部)保形地(conformally)沉积非晶硅。通过使用非晶硅材料，特别能使构成SeOI基板上的薄层材料的结晶排列不受到破坏。
典型地，沉积的非晶硅的厚度小于10个原子层的厚度(5nm)。
另选地，可以使用ALD(原子层沉积)来沉积单硅原子层。
接着，执行缓蚀刻(gentle etching)步骤以去除沉积在沟槽掩模上的硅层。
接着，对沿沟槽的壁沉积的硅实施退火再结晶操作，使得硅：
在沟槽的位于绝缘层上方和下方的区域中再结晶为单晶态；
在与绝缘层等高位置处再结晶为多晶态，从而在绝缘层BOX和沟槽壁之间的沟槽的任一侧限定出沟道传导区30。
与绝缘层等高位置的再结晶尤其是通过来自于出现在绝缘层上方和下方的半导体区的再结晶前沿(front)而发生的。取决于绝缘层的厚度，甚至能看到(meet)再结晶前沿。
接着，用栅介电层31覆盖再结晶硅层。
然后，例如通过沉积掺杂多晶硅来填充该沟槽以便在其中形成栅区G。作为变型，可以对栅区进行金属化。
回到图2a的描述，沟道的位于绝缘层下方的那部分优选地通过在底部基板上部制成的阱40来形成。特别地，阱40可通过与该阱的导电类型相反的层50(本例为Vdd偏置的n沟道存储单元，在本例中，当阱的导电类型为p-型时该层导电类型为n-，以便使产生的二极管处于反偏模式，反之也适用于p沟道存储单元)来与底部基板的其余部分间隔。
该存储单元还包括沟道的位于绝缘层下方的那部分的横向间隔区60，其沿深度方向在绝缘层下方延伸，直到抵达层50，用以将阱40与底部基板的其余部分间隔。
应当注意，区域60实现了与在前面提到的部分耗尽型SeOI存储单元中、位于绝缘层上方的STI型间隔区相同的作用。
根据第一可能实施方式，沟道的位于绝缘层下方的那部分的这些横向间隔区60是用STI技术产生的间隔沟槽。
根据第二可能实施方式，这些区域60是由导电类型与沟道相反的半导体材料形成的(例如在这里描述的p-型沟道区40的例子中，是n+型导电类型)。
根据本发明的一个优选实施方式(如图2a所示)，沟道是浮置的，栅区充当驱动FET晶体管的控制栅极。
因此，定义了一种DRAM存储单元，能够通过撞击离化效应在浮沟中存储电荷来实现该存储单元的写操作，该浮沟同时在绝缘层BOX的上方和下方延伸。
可以理解，在本发明的上下文中，与传统存储单元相比，由于浮沟在绝缘层下方的延伸，电荷存储量显著增加(参照上述的200-1000因子)。
换句话说，根据本发明，能够存储在存储单元的浮沟中的电荷量仍然是一个遵循半导体器件尺寸的急速减小的技术发展路线的相对常数，或者至少和传统存储单元中观察到的相比更快减小。
特别地，通过埋入在绝缘层下方更深处的浮沟能够补偿半导体器件尺寸沿X和Y轴(沿存储阵列行和列的方向)的减小。
而且，根据本发明，构成该存储单元的存储阵列的外围电路(放大器和解码器)仍然是传统的采用平面晶体管的SOI技术。这样就可以减小可变性和功耗等问题。
根据本发明的一个实施方式(未示出)，栅区是浮置的，FET晶体管还包括通过介电层与浮栅区相间隔的控制栅极。
因此，定义了一种闪存型存储单元，可以通过热载流子注入现象在形成于沟槽中的浮栅区中存储电荷来实现写操作，其中沟槽延伸到绝缘层BOX下方的沟道中。
在这个实施方式中，存储量由于形成在延伸到绝缘层下方的沟槽中的浮动栅区的更大尺寸而自增加。
这个实施方式被证明对于降低需要高操作电压的功率晶体管的整体尺寸是特别有利的。
图3a-3b和图4a-4b所示为根据本发明的DRAM存储单元的第一实施方式的两个变型例。在这两个变型例中，双极型晶体管与FET晶体管相关联以便将电荷注入到FET晶体管的沟道中。因此，双极型晶体管的集电极是由FET晶体管的沟道形成的。
在图3a所示变型例中(图3b为等效电路图)，FET晶体管的源极(联系图3b中的标号9)充当双极型晶体管的基极(联系图3b中的标号71)。
在这个变型例中，设计双极型晶体管的发射极70被设计成，使得FET晶体管的源极能充当双极型晶体管的基极。典型地，FET晶体管是一种水平型晶体管，发射极被更精确地设计为，使得发射极/源极组合形成垂直堆栈。
优选的是，发射极集成到比源极更低的区域。在上述情况下，其中源极包括重掺杂的中心区21和轻掺杂的围绕中心区的外周区22，然后将发射极70放置成与源极的中心区相接触，而通过源极的外周区22与浮沟仍然是间隔的。这里，发射区完全集成到源极的中心区21和外周区22之间。
在全耗尽SeOI存储单元中，如图3a所示，BOX层也可以起到将发射极与浮沟间隔开的作用。
在图4a所示的变型例中(图4b为等效电路图)，底部基板-更确切地说是阱40的间隔层50-充当双极型晶体管的基极(联系图4b的标号72)。
因此，双极型晶体管的发射极80被放置成与底部基板相接触(例如，与本例中所示的阱的间隔层50相接触)。
在这个变型例中，发射极被放置在沟道的位于绝缘层下方的那部分的横向间隔区60的下部，而通过围绕它的一个区域仍然与间隔区30分隔开，以使其与浮沟间隔开，其中发射极的导电类型与底部基板的相同(本例中为n-型区)。
发射极位于区60下方，优选的，区60采用导电类型与沟道相反的半导体材料形成(本例中沟道的导电类型为n+型)。
上述两个变型例中的任何一个中，发射极70、80与平行于源极线SL延伸的注入线IL相连接，以便对沿存储阵列的列布置的存储单元进行寻址。这导致只要注入线IL不占用表面区域就可以得到显著紧密的排列。
特别地，注入线IL可由掺杂半导体材料(在图3a所示的变型例中薄层为p+掺杂材料，在图4a所示的变型例中底部基板的材料为p+掺杂材料)构成。
在第二变型例的上下文中，FET和双极型晶体管实质上是彼此独立的，因此不需要寻求折衷来优化各自的性能。
第二变型例进一步提供了一个额外的结点(通过充当双极型晶体管的基极的底部基板，更确切地说是通过控制阱40的间隔层50上的电压，如图4b中GND所示)。此额外的结点提供了在存储单元写/读操作时更大的灵活性。
以上描述是针对根据本发明的存储单元的第一实施方式进行的，其中，漏区和源区完全放置在绝缘体上半导体的薄层中，沟道经由沟道传导区、在绝缘层上方和下方在源区和漏区之间延伸。
下面参照图5a、5b详细描述本发明存储单元的第二实施方式的两个变型例，其中源区S和漏区D分别通过源传导区90和漏传导区100都在两个高度上延伸，绝缘层的上方(91、21、22；101、11、12)和下方(92、93；102、103)，它们被布置在沟槽任一侧与绝缘层等高处。可是，只要分别高于绝缘层的源、漏区的体积比分别位于绝缘层下方的源、漏区的体积明显更高(通常为200-1000的因子)，源区和漏区就实质上在薄层内。
沟道C本身完全在绝缘层下方、在源区的位于绝缘层下方的部分92、93和漏区的位于绝缘层下方的部分102、103之间延伸。
在图5a、5b中，标记91(另选地为标记101)代表源区S(另选地为漏区D)的位于绝缘层上方的部分，由中心区22(参照图2a，另选为12)和外周区21(另选为11)组成。
在图5a所示的变型例中，源区和漏区的位于绝缘层下方的部分92和102是通过位于底部基板的表面上、紧靠绝缘层的下方的掺杂层形成的，在本例的n-FET中其为n-型。
这个掺杂层包括通过沟槽彼此间隔开的源区92和漏区102。
在图5b所示的变型例中，源区和漏区的位于绝缘层下方的部分93和103分别是由局部(localized)源区和局部漏区(形成在紧挨绝缘层下方的沟槽任一侧)。
这些局部区域93和103分别形成了源漏贮藏区或容纳区(pocket)。沟道完全在绝缘层下方这些贮藏区或容纳区之间延伸。
需要指出的是，可通过将容纳区93、103添加到掺杂层92、102而将图5a和图5b所示的变型例组合在一起。
而且，这些变型例的实现即可在全耗尽存储单元(如图5a、5b所示情况)又可在部分耗尽存储单元(在绝缘层上方必须采用STI间隔以彼此分隔单元的情况)。
和图2a所示的实施方式的情况一样，图5a和5b的存储单元还包括沿深度方向在绝缘层下方延伸直到抵达层50的横向沟道间隔区，该横向沟道间隔区用来间隔阱40和底部基板其余部分。
下面详细描述一种可能的制造如图5a所示的存储单元的方法。
在其它任何通过在位于绝缘层下方的底部基板中植入掺杂剂来制造正面晶体管的步骤之前，形成位于绝缘层下方的区域(如阱40、发射极80、要形成源区92和漏区102的层)。
接着，按照与形成图2a的存储单元相类似的方法在SeOI基板上形成沟槽。该沟槽沿深度方向从绝缘体上半导体基板的表面超过绝缘层而延伸到底部基板中。
与形成图2a的单元的情况相同，然后采用ALD技术通过保形地沉积非晶硅或者沉积硅，用一层半导体材料(优选为硅)来覆盖沟槽的壁。
还可以实施缓蚀刻操作以去除沉积在沟槽掩模顶部上的硅层。
接着，沿着沟槽的壁形成栅介电层31。然后，例如通过沉积掺杂的多晶硅来对沟槽进行填充以在其中形成栅区G。在一个变型例中，可以对栅区进行金属化。
接着，进行退火以使掺杂剂沿着沟槽的壁在与绝缘层等高的位置从分别位于绝缘层上方和下方的源区和漏区开始扩散，以在沟槽任一侧形成源传导区90和漏传导区100。需要注意的是，扩散退火操作使得位于绝缘层下方的区域再结晶。在位于绝缘层上方和下方的区域不必非有相同的结晶取向，最好是两个单晶之间形成结，但这不是绝对的。这正是绝缘层下方的、用来形成位于绝缘层下方的源区92和漏区102的掺杂层具有和位于沟道上方的源区91和漏区101相同的导电类型(本例为n+型)的一个原因。因此，这有效地避免了在沟道(p-型)中产生晶体缺陷，同时提升了存储单元中有害的电荷复合为电荷保持。
扩散退火操作之后，分别通过源传导区90和漏传导区100使得源区91、92和漏区101、102在绝缘层上方和下方延伸。
下面详细描述一种可能的制造如图5b所示的存储单元的方法。
在其它任何通过向绝缘层下方的底部基板中植入掺杂剂而制造正面晶体管的步骤之前，形成位于绝缘层下方的区域(如阱40、发射极80)。
接着，在SOI基板上形成第一沟槽，该第一沟槽从SOI基板表面向下一直延伸到底部基板，使得第一沟槽的厚度对应于薄层和绝缘层的组合厚度。
接着，在第一沟槽的壁上覆盖间隔物，在这里示出的n型晶体管的示范实施方式中间隔物是n-掺杂的。为此，例如，沉积掺杂的多晶硅。
接着，在第一沟槽中形成第二沟槽，所述第二沟槽沿深度方向从第一沟槽底部开始一直延伸到底部基板，间隔物限定了所述第二沟槽的开口。
接着，沿所述第二沟槽的壁形成栅介电层31。然后填充所述第二和第一沟槽以在其中形成栅区G，例如通过沉积掺杂多晶硅。作为变型例中，可以对栅区进行金属化。
而且，通过掺杂剂从间隔物向底部基板的扩散，在紧靠绝缘层下方、所述沟槽的任一侧位置形成了局部源区和漏区93、103。因此，间隔物限定了源传导区90和漏传导区100，它们充当用于连接在绝缘层上方和下方延伸的源区和漏区的传导层。
本领域技术人员应该理解，前述的发明并不局限于它的第一方面的存储单元，而是也适用于由多个根据本发明第一方面的存储单元组成的存储阵列以及制造这种的存储单元的制造工艺。

Claims (13)

1.一种存储单元，该存储单元包括：
绝缘体上半导体基板，其包括通过绝缘层BOX与底部基板间隔开的半导体材料的薄层；
FET晶体管，其包括源区S和漏区D、内有沟槽的沟道C，以及位于该沟槽中的栅区G，其中，该源区和该漏区至少被布置在该绝缘体上半导体基板的该薄层内，
该存储单元的特征在于，该沟槽沿该底部基板的深度方向延伸超过该绝缘层BOX，并且所述源区和所述漏区分别经由源传导区和漏传导区在所述绝缘层的上方和下方延伸，这些传导区被布置在所述沟槽的任一侧与所述绝缘层BOX等高的位置，并且其中，所述沟道整体在所述绝缘层的下方、在所述源区和所述漏区的位于所述绝缘层下方的部分（92、102；93、103）之间延伸。
2.根据权利要求1所述的存储单元，其中，所述栅区G通过介电层（31）与所述沟道间隔开。
3.根据权利要求1或2所述的存储单元，其中，所述沟道的位于所述绝缘层下方的那部分是由在所述底部基板的上部中制成的阱（40）来形成的。
4.根据权利要求3所述的存储单元，其中，所述阱（40）通过与该阱的导电类型相反的层（50）与所述底部基板的其余部分相隔离。
5.根据权利要求1所述的存储单元，该存储单元还包括：所述沟道的位于所述绝缘层下方的那部分的横向隔离区（60），该横向隔离区（60）在所述绝缘层的下方沿深度方向延伸。
6.根据权利要求1所述的存储单元，其中，所述沟道是浮置的，并且所述栅区充当驱动所述FET晶体管的控制栅极。
7.根据权利要求6所述的存储单元，该存储单元还包括：双极型晶体管（71，72），其集电极充当所述FET晶体管的沟道。
8.根据权利要求7所述的存储单元，其中，所述FET晶体管的源极充当所述双极型晶体管（71）的基极。
9.根据权利要求7所述的存储单元，其中，所述底部基板充当所述双极型晶体管（72）的基极。
10.根据权利要求1所述的存储单元，其中，所述栅区是浮置的，并且所述FET晶体管还包括经由介电层与浮置的栅区相隔离的控制栅极。
11.一种存储阵列，该存储阵列包括多个根据权利要求1至10中任意一项所述的存储单元。
12.一种制造根据权利要求1所述的存储单元的工艺，其特征在于包括以下步骤：
所述绝缘层的正下方形成掺杂层，该掺杂层用于在所述沟槽的任一侧限定出在所述绝缘层的下方延伸的所述源区（92）和所述漏区（102）；
在所述绝缘体上半导体基板中形成所述沟槽，使得该沟槽延伸超过所述绝缘层；
用一层半导体材料覆盖所述沟槽的壁；
用介电层覆盖所述沟槽的所述壁；
通过填充所述沟槽来形成栅区；以及
使掺杂剂分别从位于所述绝缘层的上方和下方的所述源区和所述漏区、沿与所述绝缘层等高的位置处的所述沟槽的壁进行扩散，以形成所述源传导区（90）和漏传导区（100），从而能够将分别在所述绝缘层的上方和下方延伸的所述源区（91，92）和所述漏区（101，102）连接起来。
13.一种制造权利要求1所述的存储单元的工艺，其特征在于包括以下步骤：
在所述绝缘体上半导体基板中形成第一沟槽，该第一沟槽从所述绝缘体上半导体基板的表面向下延伸到所述底部基板；
用掺杂间隔物覆盖第一沟槽的壁，该掺杂间隔物的导电类型与要在所述绝缘层上方延伸的所述源区和所述漏区的导电类型相同；
在第一沟槽中形成第二沟槽，该第二沟槽从第一沟槽的底部向所述底部基板的深度方向延伸而超过所述绝缘层；
用介电层覆盖所述第二沟槽的壁和第一沟槽的壁；
通过填充所述第二沟槽和第一沟槽来形成栅区；以及
通过从所述间隔物扩散掺杂剂，在所述第二沟槽的任一侧、所述绝缘层的正下方形成局部源区（93）和局部漏区（103），进行了掺杂剂扩散后的所述间隔物分别充当沟道传导区和漏传导区，以将在所述绝缘层的上方和下方延伸的所述源区和所述漏区连接起来。
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US8304833B2 (en) 2012-11-06

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