JP5222520B2 - 半導体装置の製造方法 - Google Patents
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Description
Hou-Yu Chen et al,"Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183μm26T-SRAM Cell by Immersion Lithography", Sypm. on VLSI Technology 2005
図1〜3に、本発明の実施の形態である半導体装置を示す。図1は、要部平面図、図2は、図1のA−A’線に沿った要部断面図、図3は、図1のB−B’線に沿った要部断面図である。なお、図1の平面図では、図を見やすくするために、絶縁膜など、一部の部材の図示を省略してある。
本発明の実施の形態2である半導体装置の要部平面図は、例えば図1からなり、このときの図1のA−A’線に沿った半導体基板の要部断面図は、図24となる。
2 埋め込み絶縁層(絶縁層)
3 SOI層(半導体層)
4 シリコン酸化膜
5 素子分離領域
6 P型ウエル
7 拡散層領域
8 N型ウエル
9 拡散層領域
10 フォトレジストパターン
11 P型ウエル
12 拡散層領域
13 N型ウエル
14 拡散層領域
15 ゲート絶縁膜
16 ゲート絶縁膜
17 多結晶シリコン膜
18 シリコン酸化膜
19 シリコン窒化膜
20 エクステンション層(N型拡散層)
21 エクステンション層(P型拡散層)
22 シリコン酸化膜
23 サイドウォール
24 積上げ層
25 積上げ層
26 N型拡散層
26a 半導体領域
27 N型拡散層
27a 半導体領域
28 拡散層不純物補償領域
29 P型拡散層
29a 半導体領域
30 P型拡散層
30a 半導体領域
31 拡散層不純物補償領域
32 エクステンション層(N型拡散層)
33 エクステンション層(P型拡散層)
34 サイドウォール
35a ゲート電極
35b ゲート電極
36 シリサイド層
37 シリサイド層
38 CESL
39 層間絶縁膜
40 コンタクト孔
41 バックゲートコンタクト電極
42 第1積上げ層(最下層)
43 第1積上げ層(最下層)
44 スペーサ層
100 SOI領域
200 バルク領域
300 バックゲートコンタクト領域
Claims (10)
- 以下の工程を含む半導体装置の製造方法:
(a)第1MISFETが形成される第1領域とその周辺の第2MISFETが形成される第2領域とを有する半導体基板と、前記半導体基板に埋め込まれた絶縁層上の半導体層とからなる基板を準備する工程、
(b)前記第2領域における前記半導体層および前記絶縁層を除去して、前記第2領域の前記半導体基板を露出する工程、
(c)前記第1領域の前記半導体層上に第1ゲート絶縁膜を介して第1ゲート電極を形成する工程、
(d)前記第2領域の前記半導体基板上に前記第1ゲート絶縁膜より厚い第2ゲート絶縁膜を介して第2ゲート電極を形成する工程、
(e)前記第2ゲート電極の両側壁側の前記半導体基板に、前記半導体層より不純物濃度が高い第1エクステンション層を形成する工程、
(f)前記工程(e)の後、前記基板の全面に第1絶縁膜を堆積し、異方性エッチングすることによって、前記第1ゲート電極の両側壁および前記第2ゲート電極の両側壁に前記第1絶縁膜を残す工程、
(g)前記工程(f)の後、前記第1ゲート電極の両側壁側の前記半導体層上に、前記半導体層を下地とする選択エピタキシャル成長によって、第1積上げ層を形成する工程、
(h)前記工程(f)の後、前記第2ゲート電極の両側壁側の前記半導体基板上に、前記第1エクステンション層を下地とする選択エピタキシャル成長によって、第2積上げ層を形成する工程、
(i)前記工程(g)および(h)の後、前記第1積上げ層およびその下の前記半導体層に第1不純物を注入して、前記第1不純物を拡散することにより、前記第1MISFETの第1ソース・ドレインを構成する第1拡散層を形成する工程、
(j)前記工程(g)および(h)の後、前記第2積上げ層およびその下の前記半導体基板に第2不純物を注入して、前記第2不純物を拡散することにより、前記第2MISFETの第2ソース・ドレインを構成する第2拡散層を形成する工程、
(k)前記工程(i)および(j)の後、前記第1絶縁膜を除去する工程、
(l)前記工程(k)の後、前記第1ゲート電極の両側壁側の前記半導体層に、第2エクステンション層を形成する工程。 - 更に以下の工程を含む請求項1記載の半導体装置の製造方法:
(m)前記工程(l)の後、前記基板の全面に第2絶縁膜を堆積し、異方性エッチングすることによって、前記第2ゲート電極の両側壁、前記第2ゲート電極、前記第1積上げ層および前記第2積上げ層の両側壁に前記第2絶縁膜を残す工程、
(n)前記工程(m)の後、前記基板の全面に金属膜を堆積し、熱処理を施すことによって、前記第1ゲート電極の全体、前記第2ゲート電極の全体、前記第1ソース・ドレインの一部および前記第2ソース・ドレインの一部をシリサイド化する工程。 - 請求項1または2記載の半導体装置の製造方法において、
前記工程(a)では、前記絶縁層の厚さが20nm以下であり、前記半導体層の厚さが20nm以下である前記基板を準備することを特徴とする半導体装置の製造方法。 - 請求項2または3記載の半導体装置の製造方法において、
前記工程(n)では、前記第1ソース・ドレインを構成する前記第1積上げ層の上部または全体をシリサイド化し、前記第2ソース・ドレインを構成する前記第2積上げ層の全体とその下の前記半導体基板をシリサイド化することを特徴とする半導体装置の製造方法。 - 請求項2または4記載の半導体装置の製造方法において、
前記工程(n)では、Ni、Co、Ti、W、Ta、Mo、Cr、Al、Pt、PaまたはRuの前記金属膜を堆積することを特徴とする半導体装置の製造方法。 - 以下の工程を含む半導体装置の製造方法:
(a)第1MISFETが形成される第1領域とその周辺の第2MISFETが形成される第2領域とを有する半導体基板と、前記半導体基板に埋め込まれた絶縁層上の半導体層とからなる基板を準備する工程、
(b)前記第2領域における前記半導体層および前記絶縁層を除去して、前記第2領域の前記半導体基板を露出する工程、
(c)前記第1領域の前記半導体層上に第1ゲート絶縁膜を介して第1ゲート電極を形成する工程、
(d)前記第2領域の前記半導体基板上に前記第1ゲート絶縁膜より厚い第2ゲート絶縁膜を介して第2ゲート電極を形成する工程、
(e)前記第2ゲート電極の両側壁側の前記半導体基板に、前記半導体層より不純物濃度が高い第1エクステンション層を形成する工程、
(f)前記工程(e)の後、前記基板の全面に第1絶縁膜を堆積し、異方性エッチングすることによって、前記第1ゲート電極の両側壁および前記第2ゲート電極の両側壁に前記第1絶縁膜を残す工程、
(g)前記工程(f)の後、前記第1ゲート電極の両側壁側の前記半導体層上に、前記半導体層を下地とする選択エピタキシャル成長によって、第1積上げ層を構成する第1最下層を形成する工程、
(h)前記工程(f)の後、前記第2ゲート電極の両側壁側の前記半導体基板上に、前記第1エクステンション層を下地とする選択エピタキシャル成長によって、第2積上げ層を構成する第2最下層を形成する工程、
(i)前記工程(g)および(h)の後、前記基板の全面に第2絶縁膜を堆積し、異方性エッチングすることによって、前記第1ゲート電極の両側壁および前記第2ゲート電極の両側壁に前記第2絶縁膜を残す工程、
(j)前記工程(i)の後、前記第1ゲート電極の両側壁側の前記第1最下層上に、前記第1最下層を下地とする選択エピタキシャル成長によって、前記第1積上げ層を構成する第1上層を形成する工程、
(k)前記工程(i)の後、前記第2ゲート電極の両側壁側の前記第2最下層上に、前記第2最下層を下地とする選択エピタキシャル成長によって、前記第2積上げ層を構成する第2上層を形成する工程、
(l)前記工程(j)および(k)の後、前記第1積上げ層およびその下の前記半導体層に第1不純物を注入して、前記第1不純物を拡散することにより、前記第1MISFETの第1ソース・ドレインを構成する第1拡散層を形成する工程、
(m)前記工程(j)および(k)の後、前記第2積上げ層およびその下の前記半導体基板に第2不純物を注入して、前記第2不純物を拡散することにより、前記第2MISFETの第2ソース・ドレインを構成する第2拡散層を形成する工程、
(n)前記工程(l)および(m)の後、前記第2絶縁膜および前記第1絶縁膜を除去する工程、
(o)前記工程(n)の後、前記第1ゲート電極の両側壁側の前記半導体層に、第2エクステンション層を形成する工程。 - 更に以下の工程を含む請求項6記載の半導体装置の製造方法:
(p)前記工程(o)の後、前記基板の全面に第3絶縁膜を堆積し、異方性エッチングすることによって、前記第2ゲート電極の両側壁、前記第2ゲート電極、前記第1積上げ層および前記第2積上げ層の両側壁に前記第3絶縁膜を残す工程、
(q)前記工程(p)の後、前記基板の全面に金属膜を堆積し、熱処理を施すことによって、前記第1ゲート電極の全体、前記第2ゲート電極の全体、前記第1ソース・ドレインの一部および前記第2ソース・ドレインの一部をシリサイド化する工程。 - 請求項6または7記載の半導体装置の製造方法において、
前記工程(a)では、前記絶縁層の厚さが20nm以下であり、前記半導体層の厚さが20nm以下である前記基板を準備することを特徴とする半導体装置の製造方法。 - 請求項7または8記載の半導体装置の製造方法において、
前記工程(q)では、前記第1ソース・ドレインを構成する前記第1積上げ層の上部または全体をシリサイド化し、前記第2ソース・ドレインを構成する前記第2積上げ層の全体とその下の前記半導体基板をシリサイド化することを特徴とする半導体装置の製造方法。 - 請求項7または9記載の半導体装置の製造方法において、
前記工程(q)では、Ni、Co、Ti、W、Ta、Mo、Cr、Al、Pt、PaまたはRuの前記金属膜を堆積することを特徴とする半導体装置の製造方法。
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