TWI431690B - 回復ｋ的紫外光及還原處理及半導體處理中的表面清潔 - Google Patents

回復ｋ的紫外光及還原處理及半導體處理中的表面清潔 Download PDF

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TWI431690B
TWI431690B TW099123184A TW99123184A TWI431690B TW I431690 B TWI431690 B TW I431690B TW 099123184 A TW099123184 A TW 099123184A TW 99123184 A TW99123184 A TW 99123184A TW I431690 B TWI431690 B TW I431690B
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reducing agent
radiation
dielectric
feature
substrate
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Bhadri Varadarajan
George A Antonelli
Schravendijk Bart Van
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Novellus Systems Inc
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Description

回復K的紫外光及還原處理及半導體處理中的表面清潔
本發明係關於半導體處理，尤其係關於低介電常數介電材料在例如鑲嵌處理中的表面清理及製程引起損傷之修復。
此申請案主張2009年11月12日申請、題為「UV AND REDUCING TREATMENT FOR K RECOVERY AND SURFACE CLEAN IN SEMICONDUCTOR PROCESSING」的美國臨時專利申請案第61/260,789號以及2009年12月23日申請、題為「UV AND REDUCING TREATMENT FOR K RECOVERY AND SURFACE CLEAN IN SEMICONDUCTOR PROCESSING」的美國實用專利申請案第12/646,830號之權益。此臨時專利申請案之全文為所有目的以引用之方式併入本文中。
低介電常數(低k)絕緣材料已被整合於半導體裝置中以便解決縮減的特徵尺寸及較高的性能要求。這些低k介電質在機械上弱於前代的介電材料。該低k介電材料固有的脆弱性質為下游電子封裝製程及材料相容性帶來重大的挑戰。
定義低k材料為介電常數(k)低於SiO2 之介電常數，即3.9的半導體級絕緣材料。各種類型的低k材料之介電常數在大約3.8-3.6之間(例如氟矽酸鹽玻璃(FSG))、小於大約3.2(例如摻碳氧化物(CDO))、低至2.2(例如旋塗玻璃(SOG))或更低，並包含稱為「超低k」(ULK)及「極低k「(ELK)的低k介電質。在許多例如描述於此作為本發明之一態樣的CDO低k實施中，適當的含碳低k材料具有一為大約2.7或更低的介電常數。為進一步縮減在積體電路上之裝置的尺寸，必要的係使用具有低電阻率的導電材料及具有低介電常數的導體以降低相鄰金屬線路之間的電容耦合。低k材料被整合於該等裝置中以改善裝置性能並允許裝置縮放。
低k材料之密度比諸如SiO2 的標準絕緣材料小。此低密度引起許多製程整合及材料相容困難。具挑戰性的係在維持一低k膜之完整性、將其正確整合及執行必要之剝離、清潔及調節之間維持平衡。型樣化製程(蝕刻、剝離、沉積及清潔)亦對含碳低k材料，尤其係基於SiOC之低k材料具有嚴重影響。
賦予含碳低k介電材料其理想低介電常數的屬性與導致極大整合挑戰的屬性相同。含碳低k材料經由合併非極性共價鍵(例如來自碳的添加)及導入多孔性以降低膜密度而實現較低的介電常數。導入多孔性或合併諸如Si-CH3 的端鍵打斷傳統氧化物之剛性Si-O-Si晶格之連續性，產生一在機械及化學上皆更脆弱的較低介電常數膜。由於機械脆弱性，含碳低k膜易受可非預期增大該膜之密度的動態電漿損傷之影響並因此增大該膜之有效k值。
此外，在半導體處理操作中使用化學電漿，介電質被暴露於該化學電漿下可修改諸如Si-CH3 之鍵易被打斷的含碳低k膜。含碳低k材料對於電漿修改的敏感性帶來一嚴重的整合挑戰，因為常規的係使用電漿製程以便在一半導體裝置之製造中蝕刻、清潔及沉積膜。在一典型的鑲嵌製程中，在金屬阻障沉積之前，製程引起的含碳低k介電質損傷可被一型樣化低k介電質因(電漿)蝕刻、乾式光阻剝離、濕式清潔及乾式清潔的而引起。含碳低k材料亦易受既可吸附至該膜中、除去該膜中之氣體、或化學修改該膜的電漿種類、殘留物、溶劑、水分及前驅體分子之介入的影響。之後，一導電材料，通常為一金屬，例如銅，被沉積至該型樣化介電層上以填充形成於該介電層中的通孔及溝渠。然後，藉由化學機械拋光(CMP)移除過量金屬，藉此形成一包括經暴露之銅及低k介電質區域的平坦表面，諸如一介電質阻障的其它層被沉積於其上。該CMP製程一般會損傷該低k介電質，導致碳損失及水吸收。這係因為該低k介電質的k增大，因此降低該低k材料可能提供之RC改良。
此外，暴露金屬(尤其係銅)之區域在一介電質阻障或之後之層形成於該晶圓表面上之前經受氧化。CMP漿料之抗腐蝕組分之有機殘留物，例如苯并三唑(BTA)，可在一CMP製程之後停留於一晶圓表面上。氧化銅及有機殘留物的存在引起將介電質阻障黏接於該晶圓表面上的問題。因此，各種清潔製程可被使用以便將此氧化物及殘留物(製程引起之損傷的另一個形式)移除。在一個具體實施例中，此一晶圓可在向一電漿增強化學氣相沉積(PECVD)處理室導入化學蒸汽之前在該處理室中暴露於一直流式電漿一段時間。一諸如氨或氫電漿之還原電漿的使用可減少該表面上的氧化銅及碳氫化合物，藉此清潔該表面。然而，取決於處理條件，此等直流式電漿亦可影響一圍繞該銅的低k介電質，因為該低k介電質係藉由離子轟擊或因為經由化學活動之鍵結碳移除而在該表面被局部增大密度。一些藉由諸如CMP而引起的對該低k材料的k損傷可藉由在上述預處理及蝕刻終止沉積之前進行一較短的退火而被回復，但該回復極為微小。
本發明提供一種利用一還原劑及紫外光(UV)輻射處理含碳低k介電質，例如但不限於摻碳氧化物(CDO)以修復製程引起之損傷的方法，該介電質可能包含一金屬特徵。在另一個態樣中，利用一還原劑及紫外光(UV)輻射可藉由移除(還原)金屬氧化物(例如氧化銅)及/或來自一經處理晶圓之平坦化表面的CMP漿料的有機殘留物而有效清理一經處理晶圓表面。本發明之該等方法尤其可應用於鑲嵌處理背景下以回復一在處理過程中被損傷的介電質所損失的低k屬性，不管係在金屬化之前、金屬化之後或兩者皆可，及/或提供有效的平滑化後表面清潔以改善之後應用之介電質阻障及/或其它層的黏接。
在一個實施例中，本發明包含將一型樣化金屬(例如銅)互連晶圓(CMP之後及蝕刻終止沉積之前)暴露至一具有足夠光通量的紫外光(UV)輻射及一還原劑，例如NH3 ，引起金屬氧化物(例如氧化銅)還原及在CMP之後剩餘的吸附有機殘留物之移除而對該暴露介電質(其可為諸如ULK的低k，例如一含碳介電質，如CDO；或者其它低k或非低k介電質)之介電常數具有最小的影響。其中之預處理及其本身亦可回復一些傳遞至該基板表面之一低k介電質的損傷(例如歸因於吸收水的k降低)。還有一些根據本發明的其它可行方式，例如使用一短暫退火(例如1分鐘或更少)，其包含在一大約400℃之溫度下將該介電質表面暴露至一還原劑，然後在一諸如氦氣的惰性氣體中短暫暴露至一UV光。在另一個實施例中，該晶圓在一還原氣體例如NH3 中暴露至UV以清潔該金屬(例如銅)表面，然後在一惰性氣體中暴露至UV以回復k損傷。在任一情況下，經測量的介電常數之回復大於一退火本身可實現的效果。
雖然氧化銅之還原係一尤為有用及例示實施例，但在其它實施例中此相同方法亦可在介電質及/或金屬阻障沉積、接觸形成或相似的沉積製程之前應用於氧化鎳、氧化鎢、氧化鈷或其它金屬氧化物之還原。
此製程可包含於一適當設計的負載鎖之上或作為一PECVD半導體晶圓處理系統之一模組，舉例來說該處理系統可為一可從CA，San Jose之Novellus System,Inc.購得的Vector Extreme組態之PECVD系統。
在另一個態樣中，本發明係關於一種形成一半導體裝置的方法。該方法包括在一處理室中接收一包括一含碳低k介電層之半導體裝置基板，該介電層具有一形成於其中的特徵，該特徵具有側壁及一底部；及將該特徵暴露至一還原劑及UV輻射。該特徵中該製程引起的低k介電質損傷被修復。
在另一個態樣中，本發明係關於一種形成一半導體裝置的方法，其包含在一處理室中接收一包括一平坦化表面的半導體裝置基板，該平坦化表面具有在一介電層中的導電特徵；及將該平坦化表面暴露至UV輻射及一還原劑。在該表面上的平坦化引起之損傷被修復。
本發明亦可更廣泛地應用於其它半導體處理背景下。舉例來說，在一處理室中接收一半導體裝置基板及將該半導體裝置基板暴露至UV輻射及一還原劑使得處理引起的對該半導體裝置基板的損傷被修復。
本發明的這些及其它特徵以及優點將參考該等相關圖式而被更詳細地描述。
本發明之實施例主要在此描述處理鑲嵌處理中之含碳低k介電質修復的背景。一般技術者將理解本發明之如下詳細描述僅具說明性而非限制性。本發明之其它實施例對於獲得此說明之利益的技術熟練者來說係顯而易見的。現在將詳細參考顯示於所附之圖式中的本發明之各種實施方式。
使用於此之術語「半導體裝置」涉及任何形成於一半導體基板上的裝置或任何處理一半導體材料的裝置。在許多情況下，一半導體裝置參與電子邏輯或記憶體或者能量轉換。術語「半導體裝置」包括部份製造之裝置(例如部份製造的積體電路)以及可用於銷售或安裝於特定設備中的完整裝置。簡言之，一半導體裝置可存在於任何使用本發明之一方法或擁有本發明之一結構的製造狀態中。
如上述，本發明提供一種製造半導體裝置的方法，其包含暴露於一還原劑及UV輻射。根據本發明的處理可有效修復製程引起之對該介電質之損傷，例如源自電漿溝渠蝕刻或氧化金屬化或源自CMP之有機殘留物的含碳低k介電質(例如CDO)之斷裂Si-CH3 鍵。可應用的含碳介電質一般具有摻有碳的SiO基主鏈，尤其係CDO(例如由八甲基環四矽氧烷(OMCTS)、四甲基環四矽氧烷(TMCTS)、二甲基二甲氧基矽烷(DMDMOS)及甲基二乙氧基矽烷(DEMS)形成的CDO以及其它熟知的CDO前驅體)，但亦可包含合併有C、Si及該主鏈中之O兩者的複合聚合物。本發明至少在其後平坦化損傷修復(例如表面清潔)態樣中可應用於具有非含碳低k介電質甚至非低k介電質的半導體基板，因為該等金屬氧化物還原劑及有機CMP殘留物移除態樣獨立於本發明之低k介電質修復及k回復態樣。本發明之方法尤其可應用於鑲嵌處理之背景下。
在一個態樣中，本發明係關於一種形成一半導體裝置的方法，該方法係藉由同時或連續地暴露一形成於一含碳低k介電層中之特徵至一還原劑及UV輻射以修復舉例來說在該特徵形成製程中包含的電漿蝕刻、乾式光阻剝離、濕式清潔及乾式清潔引起的對該特徵側壁及底部之製程引起低k介電質損傷(例如懸浮鍵或高度應變鍵，例如由有機(一般而言-CH3 )基團之移除引起的Si-O-Si或Si-CH2 -Si。然後經修復之特徵可填充有一導電材料，尤其係一金屬擴散阻障，之後填充銅(或其它適當的互連金屬)。然後該半導體裝置之頂面可通常藉由化學機械拋光(CMP)而被平坦化。如上述，除預金屬化介電質修復之外或獨立於其之平坦化引起的介電質損傷的後平坦化修復為本發明之態樣。
圖1之處理流程圖描繪可以各種根據本發明之實施例之方法執行的操作。本發明可被有利地應用於一鑲嵌處理背景下，但其應用不受限於此。應理解在至少一些態樣中，本發明僅需一諸如在圖1所示之實施例之操作104及/或110中所述之可應用之半導體裝置基板在UV輻射及還原劑中的暴露。本發明的其它態樣可包含附加處理操作，例如描述於此的鑲嵌處理操作。但本發明不限於這些附加處理操作在其所有態樣中的執行。一雙鑲嵌技術之一概括版本參考圖2A到2D而被描述於下，該等圖式顯示一在此製程之各個階段中的部份形成之半導體裝置。本發明亦可併同其它半導體處理技術而使用。
現參考圖1，在並不必為本發明之部份但將本發明之一實施例置於一有利應用之背景下的操作中，一含碳低k介電層在100處被沉積於一基板上。導電特徵之型樣在102被形成於該介電層中，通常係藉由電漿蝕刻。電漿蝕刻通常引起對該等型樣邊緣，通常係溝渠側壁及底部的損傷，如上述。諸如乾式光阻剝離、濕式清潔及乾式清潔的其它製程操作亦可引起或造成低k介電質的損傷。該等導電特徵一般，雖然並不一定，係金屬線路及通孔。在一個實例中，該等金屬特徵為一由銅形成之金屬化層之互連件。技術熟練者所熟知的係，可使用各種技術以形成此等層。
然後該等被形成的特徵(例如蝕刻溝渠)在104暴露於一還原劑及紫外光(UV)輻射。雖然本發明不限於任何特定的操作理論，但據信根據本發明之此態樣的受損介電質表面對UV的暴露將交聯該等表面Si基團以填充來自離去之甲基(-CH3 )基團的間隙。此外，該UV能量可光激發該還原劑以產生氫或類氫(例如氘)基，該等基轉而揮發並移除或反應掉某些懸浮鍵或非結構形成碳組分，否則其將提高該基質之極化率，因此增大該介電常數。在一些實施例中，該低k介電質修復之此還原劑調節態樣可包含在UV暴露之前或在UV暴露期間該介電質對一甲矽烷基化劑例如六甲基二矽氮烷(HMDS)的暴露，如下所進一步描述。
該還原劑一般為一還原氣體，且可單獨或與存在於該處理室中之其它化學物種組合時具有光活性。還原劑之適當實例包含NH3 或類NH3 複合物，其中H被以下替代：氘(例如NH2 D、NHD2 、ND3 )、H2 ；肼(N2 H4 )或其它可產生一諸如四甲基矽烷(4MS)或三甲基矽烷(3MS)之H基團、胺(例如甲基、二甲基或三甲基-胺或乙胺)、諸如乙烯或丙烯之烯烴或諸如乙炔之炔、或者這些與彼此及/或諸如He、N2 或Ar之惰性氣體之組合的光活性氣體。在具體實例中，該還原氣體可為NH3 或H2 。一具體實例為NH3 。
根據本發明之各種實施例，該特徵可在存在該還原劑的前提下向UV輻射暴露。在其它實施例中，該特徵可在向該還原劑暴露後向UV暴露，例如該特徵利用一還原氣體(例如NH3 )之一初始退火或浸泡，例如在一低於目標熱預算的溫度下，例如大約400℃，暴露大約30秒，然後在一惰性氣體(例如He)中向UV暴露例如大約30秒。在其它實施例中，首先在存在該還原劑的情況下向UV輻射暴露，然後可在沒有該還原劑的情況下在一惰性氣體(例如He)中進一步向UV輻射暴露；或者逆向操作(即在沒有還原劑的情況下在一惰性氣體(例如He)中向UV輻射暴露)，然後在有該還原劑的情況下進一步向UV輻射暴露。
在另一個實施例中，損傷的介電質可在例如一大約400℃(退火)的溫度下向一諸如HMDS的矽烷化劑暴露，之後或同時在存在一諸如NH3 或一例如He、Ar或N2 之惰性氣體的情況下向UV暴露，其中，舉例來說，該基板先前已向一還原劑暴露。
在該處理後，一阻障層可在該半導體裝置之後的處理之前被沉積於該低k介電層之上。
適當的還原劑分壓可在大約1到700托耳之間，例如50-600托耳。一具代表性的還原劑流速為大約15 slm。通常而言適當的係小於1分鐘，例如30秒或25秒的暴露時間。在較低的分壓下，通常需要一更長的暴露時間。
該UV輻射可獲取自任何適當的UV源。UV波長、總暴露時間及強度等之選擇取決於一些因素，包含該介電膜之厚度及該介電膜之成份。適當的UV處理參數在大約1 mw-20 W/cm2 的功率強度範圍內，較佳的係大約500 mW-5 W/cm2 ；波長為大約150-500 nm，較佳的係大約200-400 nm；時間上至1分鐘，例如大約15、30或45秒；晶圓溫度為室溫到大約450℃，較佳的係大約200-400℃。一根據本發明之此態樣的典型UV暴露之功率密度為大約1-3 W/cm2 ，晶圓溫度為大約400℃，時間為大約30秒。該UV源可為一單波長準分子燈或具有電弧或微波激發的寬譜源。該製程壓力可在大約1毫托耳到760托耳之間，較佳的係大約5托耳到700托耳。
在一可從Novellus System,Inc.購得之SOLA UV熱處理系統之一特定實施方式中，UV強度可在10%-100%中任一者。更低的強度一般需要更長的暴露時間，尤其係對於清潔。溫度被設定為低於目標熱預算(例如350-400℃)。壓力可如上述。被使用之UV波長可為一利用具有低於230 nm之波長之H+燈泡的寬頻源，因為NH3 在此區域中吸收。亦可使用其它產生此等諸如172 nm準分子之短波長源。
該UV處理之製程參數，包含強度、波長、溫度、壓力、時間及氣流，可被獨立控制並改變，且該等製程條件之任一者或全部可隨站臺改變，其中本發明被實施於一多站臺處理設備中。特定而言，可獨立控制溫度、還原劑及UV輻射。舉例來說，該晶圓可處於一溫度T下一時間t、暴露至一還原劑一時間t1、暴露至UV輻射及一還原劑一時間t2、暴露至UV輻射僅一時間t3，然後被移動至一多站臺處理設備之另一個站臺中，其中包含溫度、UV輻射強度、壓力、波長、氣流及時間的條件可在所描述之參數內獨立改變。
用以實施本發明的設備可具有一個或多個UV源。在一些描述於此的實施例中，該設備將具有一單一UV源。適當的裝置被更詳細描述於下。
在此UV處理之後，在並不必為本發明之部份但為上述一實施例之背景的操作中，該等溝渠可在106用一導電材料填充，該材料一般為銅(Cu)，但其它金屬亦可被使用。在填充該等特徵時，過量材料將須從該介電層之頂部(暴露表面)移除。該過量材料可藉由一平坦化製程移除以便在108處形成該介電質中之導電特徵之一暴露型樣。如上述，一廣泛使用的平坦化製程為化學機械拋光(CMP)。
CMP漿料在平坦化期間氧化該導電材料之表面。有利的係在平坦化製程之後從該導電材料移除氧化物。如上述，來自CMP的漿料亦可從該介電質化學移除碳基團。此外，CMP漿料之抗腐蝕組分的有機殘留物，例如苯并三唑(BTA)，可在一CMP製程後停留於一晶圓表面上。氧化銅及有機殘留物的存在可干擾之後應用的層例如一介電質阻障在該晶圓表面的黏接。
根據本發明之另一態樣，為修復該介電質並移除該金屬氧化物及/或CMP漿料有機殘留物，該介電質表面可在110暴露至另一個還原劑及UV輻射。該處理可在與上述後溝渠蝕刻處理相同的條件下進行。本發明之UV及還原劑暴露亦可有效移除金屬氧化物及CMP有機殘留物。雖然本發明不限於任何特定操作理論，但據信根據本發明之此態樣的平坦化表面之UV暴露交聯該等表面Si基團以填充該低k介電質中源自離去之甲基(-CH3)基團的間隙。此外，該UV能量可光激勵該還原劑以產生氫(或類氫)基，該等基轉而揮發並移除或反應掉某些懸浮鍵或非結構性碳組分，否則該等懸浮鍵或碳組分將增大該基質之極化率，因此增大該介電常數，同時亦揮發並移除或反應掉CMP有機殘留物。此外，所產生的氫(或類氫)基亦可轉而驅動氧化銅至純銅的還原。
在根據本發明的鑲嵌處理之後，一擴散阻障膜，例如一銅擴散阻障膜，可被沉積於該部份形成之半導體裝置之平坦化表面上。此層可用於除了一擴散阻障之外的其它目的。舉例來說，該擴散阻障膜亦可充當一蝕刻終止層。
根據本發明之各種實施方式，一如上述的還原劑及UV暴露處理可進行於一半導體處理操作之前金屬化(例如溝渠填充)或後金屬化階段或二者皆可。該操作可包含任一或兩個處理操作。在該還原劑及UV暴露處理未執行於一包含前金屬化處理及後金屬化處理兩者的半導體處理操作之兩個階段的實施例中，其它處理技術亦可在一個階段或另一個階段與該還原劑及UV暴露處理組合。舉例來說，一不具有還原劑暴露的UV暴露可在一個階段或另一個階段使用。
此外，其它處理操作可在一給定的處理階段與該還原劑及UV暴露處理組合。舉例來說，本發明之一實施例包含基板209上之一金屬層211之上的蝕刻終止層210。
應注意前述僅為本發明可被實施的一個雙鑲嵌製程之一實例。一種通孔最先雙鑲嵌製程已被描述。在其它實施例中，一通孔最先製程可包含在該等線路溝渠之蝕刻之前完整的通孔蝕刻。或者可使用一溝渠最先製程，其中該等線路溝渠之蝕刻先於該通孔蝕刻。這些各種鑲嵌處理技術及其其它變體熟知於技術中並代表本發明之實施例的替代實施背景。本發明亦可應用於一單鑲嵌處理、更習知的金屬沉積及蝕刻、觸件清潔及基本上任何使用含碳低k介電質(用於本發明之低k修復態樣)的半導體處理背景以及/或任何需要金屬氧化物之還原或有機CMP殘留物之移除(表面清潔)的半導體背景(用於至少本發明之後平坦化態樣)。在觸件清潔的情況下，應理解本發明之金屬氧化物還原態樣在一觸件清潔製程中具有兩個變體，其任一者或兩者皆可根據本發明而被執行：在金屬沉積之前的蝕刻接觸通孔之清潔劑在化學機械拋光(CMP)之後的經填充之金屬觸件之清潔。在第一個情況下，該UV及還原劑處理將在一諸如NiSi之矽化物中產生的氧化物還原。在第二個情況下，該處理將生長於該金屬觸件之頂部，通常在諸如W或Cu之金屬上的金屬氧化物還原。
此外，在這點上，在鑲嵌處理背景下的術語「溝渠」通常被理解為描述一形成於介電質中且之後被填充以便在一介電層中形成一導電線路的特徵。在一更廣泛的半導體處理背景下，該術語已被理解為描述一種形成於介電質中且一兩步驟後CMP階段製程，其包含用於k回復、利用UV在一惰性(例如He)氣體中固化的介電質修復，然後為用於表面清潔、利用一還原劑(例如NH3 )的UV固化；或者該等步驟可被顛倒。根據這些實施例，在NH3 中的UV固化之前或之後一短退火(例如30秒，400℃)可致能一單一處理中的表面清潔及k回復兩者。
現參考圖2A-2D，其顯示一種包含本發明之處理引起之損傷修復製程的典型雙鑲嵌製程。如上述，應理解本發明之一在一有利應用之背景下的實施例被顯示。在至少一些態樣中，本發明僅需該半導體裝置基板的UV輻射及還原劑暴露，如上述。本發明的其它態樣可包含附加處理操作，例如描述於此之鑲嵌處理操作。但本發明不限於這些附加處理操作在所有態樣中的執行。
參考圖2A，第一及第二介電層203及205被連續沉積，可能藉由一蝕刻終止層例如一氮化矽層之沉積分開。技術中熟知的係，根據替代鑲嵌處理技術，一更厚的單一介電層可被使用代替分開的第一及第二介電層。
在第二介電層205之沉積後，一具有若干開口的通孔遮罩211被形成，之後通孔將被形成於該等開口中。然後，該等通孔被部份向下蝕刻穿過該第二介電層205之高度。然後通孔遮罩211被剝離並用一線路遮罩213替代，如圖2B所示。一第二蝕刻操作被執行以移除足夠數量的介電質以便在第二介電層205中界定線路徑215。該蝕刻操作亦可延伸通孔洞217通過該第一介電層203、向下接觸一在該下伏之後經填充以形成一半導體裝置之一元件(例如通孔、線路、STI等)的特徵，並可包含一鑲嵌溝渠或一組合式鑲嵌結構。除非於文中另有描述，否則當被使用於此時，該術語應被理解為具有其廣泛的意義。
在溝渠蝕刻後，光阻在另一個電漿製程中移除，之後進行一濕式或乾式清潔然後該低k介電質表面上的損傷被修復，如上述。
其後，導電阻障層材料219之一薄層被形成於介電層203及205之暴露表面(包含側壁)上。導電阻障層材料219可由例如鉭或氮化鉭形成。一般可利用一CVD或PVD操作以沉積導電阻障層材料219。在該阻障材料沉積前，一般使用一電漿製程以清潔該等溝渠之底部以便從該下伏層上的暴露銅表面移除氧化物及污染物。技術熟練者所熟知的係，此阻障「預清潔」電漿製程可僅為一惰性電漿或一諸如氫氣之氣體的反應性電漿。該預清潔電漿製程亦可損傷一低k介電膜。一如上述用以修復經損傷之低k膜的還原劑及UV處理可在Ta或TaN之PVD操作之前使用。
在該阻障層之頂部，一導電金屬(一般為銅)被沉積於該溝渠及線路徑217及215中。習知此沉積以兩個步驟執行：一導電種層之一初始沉積，然後銅藉由電鍍整體沉積(bulk deposition)。該種層可藉由實體氣相沉積、化學氣相沉積、無電電鍍等沉積。注意銅之整體沉積不僅填充線路徑215，並且，為確保完整沉積，亦覆蓋在第二介電層205之頂部上的所有暴露區域。
因此，必要的係平坦化該結構並從該裝置移除過量的銅。平坦化移除下至介電層205之頂部高度的材料。這引起導電線路221在介電層205中之一暴露型樣及介電層203中的通孔。(見圖2C之截面圖及圖2D之簡化俯視圖。)
平坦化可藉由各種技術完成。一般來說，該製程包含一些數量的CMP。其亦可包含電拋光之一組合，用以移除多數的過量整體銅，之後為CMP以便將剩餘的銅向下移除至該介電層205之頂面的高度。如上述，來自CMP的漿料可化學移除碳基團，且基於一般用於在該平坦化製程後從該等導電線路移除氧化物之製程的處於原位之電漿亦可移除在低k介電膜表面上留有矽懸浮鍵的碳基團。這些類型的損傷之各者亦可引起極大的水吸附，導致介電質k之增大。
如前述，本發明之另一態樣係關於在鑲嵌處理中產生的後平坦化(例如CMP)損傷修復。根據此態樣，在藉由CMP平坦化後，Si-OH(矽烷醇)鍵(藉由CMP漿料移除有機(一般而言-CH3 )基團以及該漿料中水之處理及與產生之懸浮Si-鍵的反應而產生)或其它含碳低k介電膜損傷(例如高度應變鍵)或者金屬氧化物或CMP漿料有機殘留物污染藉由將該表面向一還原劑及UV輻射暴露而被修復，如上述。
本發明可被實施於許多不同類型的設備中。在一些實施例中，該設備包含一個或多個封覆一個或多個晶圓並適於晶圓處理的室(有時被稱為處理模組)。至少一個室將包含一UV源。一單一室可具有一個或多個站臺並可被用於本發明的一個、一些或所有操作。各個室可封覆一個或多個晶圓(基板)以便處理。該一個或多個室在本發明的過程中將該晶圓維持於一界定位置或若干位置(在該位置內具有或不具有動作，例如旋轉、振動或其它搖動)。對於某些該晶圓溫度將被控制的操作來說，該設備可包含一溫控晶圓支撐件，其可被加熱、冷卻或兩者皆可。該晶圓支撐件亦可受控制以便在一處理模組內提供經界定的晶圓位置。該晶圓支撐件可相對於該UV源旋轉、振動或搖動該晶圓。
圖3顯示一適於實施本發明的UV光源之配置。在此實施例中，一冷光鏡反射器嘗試減少IR輻射在該晶圓上的照射，同時允許UV輻射可用於處理。為了簡潔，此圖式僅顯示可用於本發明之一設備中的多個可行處理站臺之一者。此外，為了簡潔，此圖式省略該晶圓之顯示，並顯示一泛光式(flood-type)反射器。對技術熟練者來說顯而易見的係顯示於圖3中的該等原理亦可應用於一聚焦反射器。
參考圖3，底座303被嵌入於一處理室301之一站臺中。視窗305被適當定位於底座303之上以允許該晶圓(未顯示)利用來自UV燈309及319之具有理想波長的UV輸出進行輻射。用於UV光源的適用燈可包含但不限於汞氣燈或氙氣燈。其它適當的光源包含氙燈、準分子燈或雷射(例如準分子雷射及各種雷射之可調節變體)。該等兩個燈309及319皆裝備有將其輸出呈現為泛光照明的反射器307及317。反射器307及317自身可由「冷光鏡」材料製成，即其亦可被設計以透射IR並反射UV輻射。
直接源自燈309及319以及反射自反射器307及317的輻射進一步入射於一組反射器311上。這些反射器亦為經設計以便僅反射目的為固化該晶圓上之薄膜的該等UV波長的冷光鏡。包含可見光及尤其係IR的所有其它輻射被此組冷光鏡透射。因此該晶圓僅被在該薄膜上引起理想效果的該等波長輻射。對於技術熟練者來說顯而易見的係該等冷光鏡反射器311相對於該等燈309及319的特定角度、距離及定向可被優化以最大化入射於該晶圓上的UV強度並優化其照射之均勻性。
該室301能在高於大氣壓力的壓力保持一真空狀態及/或包含氣體。為了簡潔，僅顯示一個室301之一站臺。應注意在一些實施例中，室301為一多室設備中之一室，但室301亦可為一獨立單室設備之一部份。在任一情況下，該(等)室可具有一個或不止一個站臺。在本發明的一些實施例中，該UV處理模組具有一個站臺。用於實施本發明的適當設備可包含描述於此的來自加利福尼亞州San Jose市之Novellus System,Inc.的INOVA、Sequel、Vector及SOLA系統及來自加利福尼亞州Santa Clara市之Applied Materials的Endura、Centura、Producer及Nanocure系統組態。在一特定實例中，本發明可被實施於一來自加利福尼亞州San Jose市之Novellus System,Inc.的Vector Extreme工具上。
注意圖3之UV光源組態僅為一適當組態之一實例。總體而言，較佳的係該等燈經配置以便向該晶圓提供統一的UV輻射。舉例來說，其它適當的燈組態可包含同心配置或以其它方式配置之圓形燈陣列，或者可使用彼此相對成90度或180度配置的更小長度之燈。該(等)光源可為固定或可移動以便在該晶圓之適當位置提供光。或者，一光學系統，包含例如一系列可移動透鏡、濾光器及/或鏡，可被控制以便在不同時間從不同光源將光導向該基板。
該UV光強度可藉由光源之類型或藉由施加至該光源或光源陣列的功率而被直接控制。影響所施加之功率之強度的因素包含例如光源(例如一光源陣列中)之數量及該等光源類型(例如燈類型或雷射類型)。其它控制該UV光在該晶圓樣本上之強度的方法包含使用可阻止部份光達到該晶圓樣本的濾光器。對於光的方向，該晶圓處的光強度可利用諸如鏡、透鏡、散射器及濾光器的各種光學組件調變。個別光源的頻譜分佈可藉由光源之選擇(例如汞氣燈對氙氣燈對氙燈對準分子燈等)以及調整頻譜分佈的濾光器的使用而被控制。此外，一些燈的頻譜分佈可藉由將諸如鐵、鎵等的特定摻雜劑與該燈中的氣體混合物摻雜而被調節。
該裝置亦包含一還原氣體320之來源，例如NH3 或H2 ，如上述的其它氣體。
在一些實施例中，一系統控制器325被使用以便在根據本發明利用還原劑進行UV處理的製程中控制製程條件。該控制器一般包含一個或多個記憶體裝置及一個或多個處理器。該處理器可包含一CPU或電腦、類比及/或數位輸入/輸出連接、步進馬達控制器板等。
在某些實施例中，該控制器控制該設備之所有活動。該系統控制器執行系統控制軟體，包含控制時間、氣體(例如還原劑氣體)供應、室壓力、室溫度、晶圓溫度、UV波長、強度及暴露時間的指令集以及一特定製程的其它參數。其它儲存於與該控制器相關之記憶體裝置上的電腦程式可在一些實施例中使用。
一般存在一與控制器625關聯的使用者介面。該使用者介面可包含一顯示器螢幕、該設備及/或製程條件之圖形軟體顯示器以及使用者輸入裝置，例如指針裝置、鍵盤、觸控螢幕、麥克風等。
用於控制該等製程的電腦程式碼可以任何習知的電腦可讀之程式語言寫入：例如，組合語言、C、C++、帕斯卡、福傳語言或其它。編譯目標碼或腳本可被該處理器執行以便執行在該程式中識別的任務。
用於監測該製程的信號可藉由該系統控制器之類比及/或數位輸入連接提供。用於控制該製程的該等信號在該沉積設備之類比及數位輸出連結上輸出。
該系統軟體可以許多不同方式設計或組態。舉例來說，各種室組件副程式或控制目標可被寫入以控制執行該等發明之製程所需的室組件操作。用於此目的的程式或程式段之實例包含基板定位碼、還原氣體控制碼、壓力控制碼、加熱器控制碼及UV輻射控制碼。在一個實施例中，該控制器包含用於執行根據上述方法執行本發明之製程的指令。
應理解圖3所示之設備僅為一適當UV處理模組之一實例且其它設計亦可被使用。該半導體裝置應在無空氣斷開的情況下從該UV模組轉移至該阻障層沉積模組。這可在多個單一工具上完成。
實例
如下描述提供本發明之具體實施方式及執行數據之實例以便更好理解本發明。然而，本發明不限於此等具體實施方式。
後CMP處理
在本發明之一實施例中，NH3 被用作該還原劑。NH3 在該UV範圍中吸附，並可能產生可還原金屬氧化物的H基。該等H基及向UV輻射的暴露兩者皆可能移除殘留的CMP有機殘留物(C移除)。在此實例中，極高的固化壓力(大約600T)被使用以便增加H基的產生，但較低的壓力亦可能被使用，取決於需被還原之金屬氧化物之量。
為評估金屬氧化物(在此情況下為CuOx )之移除，大約130的CuO利用一氧化電漿生長於PVD Cu上。不同固化時間的影響以及具有及不具有UV暴露的影響被評估。數據被標出於圖4中。130的CuO之完整還原在NH3 氣體環境中在小於30秒的UV固化下實現。(稍低的10秒及20秒固化係歸因於在該晶圓之邊緣的不完整移除，在該處CuO明顯更厚。)藉由對比，一僅(無UV暴露)30秒的NH3 浸泡僅移除三分之一的CuO(大約40)。
為評估CMP碳氫殘留物移除，已通過該CMP製程的Cu晶圓被測試。晶圓被覆蓋有SiN然後藉由SIMS分析。所有結果將與直接電漿製程(在此情況下為基於NH3 的原位預處理)對比。數據在圖5中標出。對於表面清潔製程，一在NH3 (作為一簡單還原劑)中的UV固化可能以多種方式實施：NH3 中的單步驟UV固化；NH3 中的UV固化，然後在一如He之惰性氣體中的UV固化；及NH3 浸泡(無UV)，然後在一惰性氣體環境中的UV固化。如該數據所指示，在包含一還原劑及UV固化的所有測試中的C移除優於直接電漿製程(原位NH3 預處理)。
呈現於上的該等結果皆係在400℃下固化30秒。實際的所需時間及固化溫度取決於要求。舉例來說，在C移除為主要要求的情況下，可使用更短的時間。在無C且僅需極少O還原的情況下，可使用更短時間及溫度。
該數據被呈現於圖6及7中。為評估由該清潔製程引起的k損傷，在一還原氣體中基於UV的製程與一原位電漿製程對比。如圖6所示，k損傷對於利用一還原劑及UV固化處理的膜來說係最小的。與5%的直接電漿製程相比，利用基於NH3 之30秒UV固化的k損傷係最小的(大約1.5%)。此外，如呈現於下表中的FTIR數據所示，利用基於UV之預處理，僅可觀察極少的碳損失，這說明了較低的k損傷：
為評估介電質損傷修復(用於k回復)，一2.55 ULK膜被測試。在此實例中該處理包含在大約400℃下利用NH3 對經損傷之低k膜退火一更短時間(小於1分鐘)，然後進行一更短的UV固化(小於1分鐘，在大約400℃)。如圖7所示，這導致最大的k回復(經由退火的回復僅需些微退火時間)。
後溝渠蝕刻製程
上述相同技術亦可用於從後蝕刻(預金屬化)損傷中回復至少一些k。根據本發明的後溝渠蝕刻處理之數據被標出於圖8中。如該數據所示，k回復對於利用一還原劑及UV固化處理的膜來說係最好的。
結論
雖然前述發明為了清晰理解而被詳細描述，但顯而易見的係一些改變及變形可在所附之申請專利範圍的範圍內做出。應注意存在許多實施該製程及本發明之合成物兩者的替代方式。因此，本發明將被視為具有說明性而非限制性，且本發明不限於描述於此之該等細節。
203．．．第一介電層
205．．．第二介電層
209．．．基板
210．．．蝕刻終止層
211．．．通孔遮罩
213．．．線路遮罩
215．．．線路徑
217．．．通孔洞
219．．．阻障層材料
221．．．導電線路
301．．．處理室
303．．．底座
305．．．窗口
307．．．反射器
309．．．UV燈
311．．．反射器
320．．．還原氣體
325．．．系統控制器
圖1之製程流程圖描繪一種根據本發明之一實施例的方法；
圖2A-2D之截面圖顯示一半導體裝置藉由根據本發明之一實施例之雙鑲嵌製程的形成；
圖3為一適於實施本發明的示例室之一示意圖；及
圖4-8提供顯示本發明之優點的數據圖。
(無元件符號說明)

Claims (40)

  1. 一種形成一半導體裝置的方法，其包括：在一處理室中接收一半導體裝置基板，該基板包括一含碳低k介電層，該介電層中形成有一特徵，該特徵具有若干側壁及一底部；將該特徵暴露於一還原劑及UV輻射而不暴露該特徵至一電漿；藉此修復該特徵中由製程引起的低k介電質損傷。
  2. 如請求項1的方法，其中該還原劑為一還原氣體。
  3. 如請求項2的方法，其中該還原氣體包括一選自由以下所組成群組的複合物：NH3 、NH2 D、NHD2 、ND3 、H2 、N2 H4 、四甲基矽烷、三甲基矽烷、甲基-、二甲基-或三甲基-胺、乙胺、乙烯、丙烯、乙炔及其與彼此及/或惰性氣體之組合。
  4. 如請求項3的方法，其中該還原氣體基本上由一選自由NH3 、H2 及其組合所組成之群組的複合物組成。
  5. 如請求項1的方法，其中該還原氣體為NH3 。
  6. 如請求項1的方法，其中該特徵在存在該還原劑的情況下暴露於UV輻射。
  7. 如請求項6的方法，其中該還原氣體為NH3 。
  8. 如請求項1的方法，其中該特徵在暴露於該還原劑後暴露於UV輻射。
  9. 如請求項8的方法，其中該還原劑為NH3 氣體，該暴露於該還原劑係在一大約400℃之溫度下進行小於1分鐘，且 該UV輻射暴露係在一惰性氣氛中進行。
  10. 如請求項1的方法，其中該特徵為一在一鑲嵌處理操作中蝕刻的溝渠。
  11. 如請求項1的方法，其進一步包括在該低k介電層上沉積一阻障層。
  12. 如請求項10的方法，其中該裝置基板進一步包括一填充該溝渠的金屬，且該裝置基板之一頂面已被平坦化使得該低k介電質及該溝渠中之該金屬兩者皆在該表面處暴露。
  13. 如請求項12的方法，其中該金屬為銅。
  14. 如請求項13的方法，其進一步包括將該平坦化表面暴露於一還原劑及UV輻射使得氧化銅及有機平坦化漿體殘留物之至少一者從該表面移除。
  15. 如請求項14的方法，其進一步包括其中在該低k介電質中實現至少一些k回復。
  16. 如請求項15的方法，其中該特徵在存在該還原劑的情況下暴露於UV輻射。
  17. 如請求項15的方法，其中該特徵在暴露於該還原劑後暴露於UV輻射。
  18. 如請求項17的方法，其中該特徵在存在該還原劑的情況下暴露於UV輻射之前，在一惰性氣氛中暴露於UV輻射。
  19. 如請求項17的方法，其中該特徵在存在該還原劑的情況下暴露於UV輻射後，在一惰性氣氛中暴露於UV輻射。
  20. 如請求項1的方法，其中該含碳低k介電質包括CDO。
  21. 如請求項15的方法，其進一步包括在該平坦化表面上沉積一阻障層。
  22. 如請求項12的方法，其中一金屬氧化物及一有機殘留物之至少一者從該基板表面移除。
  23. 如請求項1的方法，其中該特徵形成包括：在一基板上沉積一含碳低k介電層；及在該介電層中蝕刻該特徵。
  24. 如請求項1的方法，其進一步包括：在UV暴露之前或之時將該介電質暴露於一矽烷化劑(silylating agent)。
  25. 一種形成一半導體裝置的方法，其包括：在一處理室中接收一半導體裝置基板，該基板包括一平坦化表面，該表面具有在一介電層中的導電特徵；將該平坦化表面暴露於一UV輻射及一還原劑而不暴露該平坦化表面至一電漿；藉此修復該表面上平坦化引起的損傷。
  26. 如請求項25的方法，其中該介電質包括一含碳低k介電層。
  27. 如請求項25的方法，其中該等導電特徵包括一金屬。
  28. 如請求項27的方法，其中氧化物從該金屬移除。
  29. 如請求項28的方法，其中該金屬為銅。
  30. 如請求項26的方法，其中該含碳低k介電質包括CDO。
  31. 如請求項25的方法，其中一殘留物從該基板表面移除。
  32. 如請求項25的方法，其進一步包括：在一基板上之一含碳低k介電層中形成導電特徵；及平坦化該低k介電層之一頂面及導電材料。
  33. 一種形成一半導體裝置的方法，其包括：在一處理室中接收一半導體裝置基板；將該半導體裝置基板暴露於一還原劑及UV輻射而不暴露該半導體裝置基板至一電漿，使得由處理引起之對該半導體裝置基板的損傷被修復。
  34. 如請求項33的方法，其中該基板在存在該還原劑的情況下暴露於UV輻射。
  35. 如請求項34的方法，其進一步包括在之後在無該還原劑的情況下將該基板暴露於UV輻射。
  36. 如請求項33的方法，其中該基板在暴露於該還原劑後暴露於UV輻射。
  37. 如請求項33的方法，其中該半導體裝置基板進一步包括一金屬。
  38. 如請求項33的方法，其中該UV及還原劑暴露減少在一諸如NiSi之通孔矽化物中產生的氧化物。
  39. 如請求項33的方法，其中該UV及還原劑暴露減少氧化物並從一平坦化金屬觸件移除有機CMP殘留物。
  40. 一種用於修復一半導體裝置基板上由製程引起之損傷的設備，其包括：(a)一具有一UV輻射源及一還原劑之一來源的處理室；及 (b)一控制器，其包括用於進行一根據請求項33之製程的程式指令。
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US10037905B2 (en) 2018-07-31
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