TWI430371B - 具有空腔界定閘之裝置及其製造方法 - Google Patents

具有空腔界定閘之裝置及其製造方法 Download PDF

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TWI430371B
TWI430371B TW098107482A TW98107482A TWI430371B TW I430371 B TWI430371 B TW I430371B TW 098107482 A TW098107482 A TW 098107482A TW 98107482 A TW98107482 A TW 98107482A TW I430371 B TWI430371 B TW I430371B
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Werner Juengling
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Micron Technology Inc
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

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Description

具有空腔界定閘之裝置及其製造方法
本發明之實施例大體係關於電子裝置，且更具體言之，在特定實施例中，係關於鰭式場效電晶體。
鰭式場效電晶體(finFET)經常建置於自基板整體垂直地上升之鰭片(例如，高薄半導電構件)周圍。通常，閘極藉由保形地沿著鰭片之一側向上、越過頂部且沿著鰭片之另一側向下而橫越鰭片。在一些情況下，閘極經安置成與鰭片之側相抵且不越過頂部而延伸。通常，源極與汲極位於閘極之在鰭片之末端附近之相對側上。在操作中，穿過源極與汲極之間的鰭片的電流係藉由選擇性地激發閘極而加以控制。
一些finFET包括藉由側壁隔片製程而形成之閘極。在此製程之一些型式中，藉由以保形導電薄膜來覆蓋鰭片且接著各向異性地蝕刻導電薄膜而形成閘極。在蝕刻期間，導電材料自水平表面比自垂直表面更快速地被移除。因此，導電材料之一部分保持與鰭片之垂直側壁相抵，藉此形成閘極。此製程之優點在於：相對於藉由經常經受對準及解析度約束之光微影而圖案化之閘極，可形成相對較窄閘極。
儘管藉由側壁隔片製程而形成閘極會避免一些製程問題，但其可引入其他故障機制。經常，由於鰭片係藉由為較不完全地各向異性之蝕刻步驟而形成，故鰭片之側壁成角度而非垂直。此等成角度側壁可使用於側壁隔片製程之製程窗口變窄，且在一些狀況下可將其關閉。該等角度將相鄰鰭片之基底置放成更接近於彼此，且當保形薄膜沈積於此較窄間隙中時，薄膜之覆蓋相鄰側壁之部分可接合，從而在間隙中形成具有較大垂直厚度之薄膜。薄膜可在間隙中變得如此厚，以致於側壁隔片蝕刻未移除相鄰閘極之間的所有導電薄膜。所得導電殘餘物形成使相鄰finFET短路且降低產率之縱樑(stringer)。
以上所論述之一些問題可藉由新製造製程之特定實施例而得以減輕。在以下所描述之一實施例中，閘極係沿著鰭片之側而形成於絕緣孔洞中。此實施例之孔洞係藉由形成呈閘極之形狀的碳質模具、藉由絕緣體而覆蓋碳質模具且接著藉由燃燒模具而自絕緣體下方移除碳質模具進行建構。所得空腔接著至少部分地填充有閘極絕緣體及導電閘極材料以形成電晶體。由於空腔係在閘極形成之前彼此絕緣，故閘極被認為係不太可能對其他閘極造成短路。以下參考圖1至圖24來描述此製程及其他製程。
如由圖1所說明，製造製程藉由提供基板110而開始。基板110可包括半導電材料，諸如，單晶矽或多晶矽、砷化鎵、磷化銦，或具有半導體性質之其他材料。或者，或另外，基板110可包括可建構有電子裝置之非半導體表面，諸如，塑料或陶瓷工作表面。術語「基板」涵蓋在各種製造階段中之主體，包括未經處理之全晶圓、經部分處理之全晶圓、經完全處理之全晶圓、經分割晶圓之一部分，或已封裝電子裝置中之經分割晶圓之一部分。
在此實施例中，基板110包括上部摻雜區域112及下部摻雜區域114。上部摻雜區域112與下部摻雜區域114可經不同地摻雜。舉例而言，上部摻雜區域112可包括n+材料且下部摻雜區域114可包括p-材料。上部摻雜區域112之深度可在基板110之一實質部分上(諸如，貫穿(例如)記憶體裝置之陣列區域之一實質部分)為整體均一的。上部摻雜區域112及下部摻雜區域114可藉由植入摻雜物材料或使摻雜物材料擴散而形成。或者，或另外，此等區域112及/或114中之一者或兩者可在基板110之全部或一部分之生長或沈積期間(諸如，在半導電材料之磊晶沈積期間或在晶圓可被切割自之半導電鑄錠之生長期間)被摻雜。如以下所解釋，上部摻雜區域112可提供用以形成電晶體之源極及汲極的材料，且下部摻雜區域114可提供用以形成電晶體之通道的材料。
緊接著，如由圖2所說明，形成深溝槽光罩116，且如由圖3所說明，蝕刻深隔離溝槽118。深溝槽光罩116可為光阻或硬式光罩，且深溝槽光罩116可藉由光微影設備或其他類型之微影設備(諸如，奈米壓印系統或電子束系統)而進行圖案化。深溝槽光罩116包括具有通常等於或小於1/4 F、1/2 F或F之寬度120的整體線性且整體平行之經曝光區域，及具有通常等於或小於3/4 F、3/2 F或3 F之寬度122的經遮蔽區域，其中F為用以使深溝槽光罩116圖案化之系統的解析度。
在一些實施例中，深溝槽光罩116係藉由對光罩(未圖示)進行雙間距而形成。在該製程之一實例中，深溝槽光罩116係首先藉由遮蔽每隔一對經曝光區域之間的區域且接著在對應於經曝光區域中之每一者之區域上在光罩之側上形成多晶矽側壁隔片而形成。接著，初始光罩可經移除且諸如氧化物之硬式光罩材料可沈積於剩餘多晶矽側壁隔片上，且硬式光罩材料可經回蝕或藉由化學機械拋光(CMP)而進行平坦化以曝光多晶矽。緊接著，多晶矽可經選擇性地蝕刻以形成經曝光區域(由圖2所說明之氧化物硬式光罩)。由於經曝光區域之寬度122通常係由側壁隔片之寬度界定，故在一些實施例中，寬度122可小於F。
如由圖3所說明，可蝕刻基板110之由光罩116所曝光之區域以形成深隔離溝槽118。在此實施例中，蝕刻為整體各向異性乾式蝕刻。深隔離溝槽118可在Y方向上整體橫向地延伸且在Z方向上向下延伸。深隔離溝槽118可具有整體矩形或梯形橫截面，且在一些實施例中，其橫截面經由在Y方向上之某一距離而可為整體均一的。
緊接著，在本實施例中，移除深溝槽光罩116，且使深隔離溝槽118填充有介電質，如由圖4所說明。深溝槽光罩116可藉由各種技術(諸如，使光阻與氧在熔爐中或在電漿蝕刻室中進行反應或選擇性地濕式蝕刻光罩材料)而被移除。在一些實施例中，在填充深隔離溝槽118之後移除深溝槽光罩116。在其他實施例中，可在填充深隔離溝槽118之前移除深溝槽光罩116。舉例而言，介電覆蓋層(overburden)可皆沈積於深溝槽光罩116上及深隔離溝槽118中，且深溝槽光罩116可在化學機械拋光(CMP)期間充當終止區域以移除覆蓋層。深隔離溝槽118可部分地或全部地填充有各種介電材料(諸如，高密度電漿(HDP)氧化物、旋塗式玻璃(SOG)或正矽酸四乙酯(TEOS))以電隔離特徵。為了進一步隔離特徵，在一些實施例中，可在填充溝槽118之前藉由經選擇以增強隔離之摻雜物而植入深隔離溝槽118之底部。另外，深隔離溝槽118可包括諸如氮化矽之各種襯墊材料，以消除薄膜應力、改良黏著力或充當障壁材料。
在填充深隔離溝槽118之後，將淺溝槽光罩124形成於基板110上，如由圖5所說明。如同深溝槽光罩116一樣，淺溝槽光罩124可為光阻或硬式光罩，且其可藉由諸如以上所論述之微影系統的各種微影系統而進行圖案化。在一些實施例中，淺溝槽光罩124為藉由類似於以上針對隔離溝槽光罩116所描述之製程的雙間距光罩製程而形成之硬式光罩，除了此光罩在X方向上移位1/2間距之外。所說明之淺溝槽光罩124包括具有可具有通常等於或小於1/4 F、1/2 F或F之寬度之空間126的經曝光區域，及具有可通常等於或小於3/4 F、3/2 F或3 F之寬度128的經覆蓋區域。經曝光區域可為整體線性的、整體平行的，且整體等距地插入於深隔離溝槽118之間。
緊接著，如由圖6所說明，可蝕刻基板110之經曝光區域以形成淺溝槽130。淺溝槽130可為整體線性的、整體平行的、整體在Y方向上整體橫向地延伸，且在Z方向上整體向下延伸，且因此，可整體平行於深隔離溝槽118。在此實施例中，淺溝槽130係藉由整體各向異性乾式蝕刻而形成且深於上部摻雜區域112，但不與深隔離溝槽118一樣深。淺溝槽130可具有整體矩形或整體梯形輪廓，其在Y方向上在一實質距離內為整體均一的。
如由圖7所說明，使淺溝槽130填充有諸如氮化物之犧牲材料。在此實施例中，淺溝槽130填充有與填充深隔離溝槽118之材料不同的材料，使得可在後續步驟中在未自深隔離溝槽118移除材料之實質量的情況下選擇性地蝕刻淺溝槽130。然而，在其他實施例中，此等溝槽118及130可包括相同材料。
緊接著，如由圖8所說明，形成鰭片光罩132。鰭片光罩132可由光阻製成，或其可為硬式光罩。鰭片光罩132可藉由以上所描述之微影系統中之任一者或其他微影系統而進行圖案化。在此實施例中，鰭片光罩132界定具有寬度134之經遮蔽區域及具有寬度136之經曝光區域。寬度134可通常等於或小於F，且寬度136可通常等於或小於3/2 F。經遮蔽區域可為整體直線的、彼此整體平行，且整體垂直於深隔離溝槽118及淺溝槽130兩者，且在X方向上整體延伸。
在一些實施例中，對鰭片光罩132進行雙間距。如由圖9所說明，可與鰭片光罩132之側壁相抵而形成側壁隔片138。側壁隔片138可藉由將保形薄膜沈積於基板110上且各向異性地蝕刻保形薄膜以將其自水平表面移除而形成。側壁隔片138可由與鰭片光罩132之材料不同的材料製成以促進在後續步驟中選擇性地移除鰭片光罩132。側壁隔片138可具有通常等於或小於1/4F、1/2F或F之寬度140。
緊接著，如由圖10所說明，移除鰭片光罩132，且如由圖11所說明，形成鰭片列142。鰭片光罩132可藉由蝕刻或其他製程而被移除，該其他製程以大體上高於移除基板110之其他材料之速率的速率而選擇性地移除鰭片光罩材料。經曝光側壁隔片138中之每一者可遮蔽通常與鰭片列142之頂部對應的區域。在此實施例中，鰭片列142係藉由整體各向異性蝕刻而蝕刻至深度144，深度144通常大於淺溝槽130之深度，但不與深隔離溝槽118一樣深。鰭片列142可具有整體梯形橫截面，其在X方向上在一實質距離內整體均一地延伸。在其他實施例中，鰭片列142可具有其他輪廓，諸如，整體矩形或彎曲輪廓。
緊接著，如由圖12所說明，可移除隔片138，或在一些實施例中，隔片138可留於鰭片列142上且在後續步驟期間被移除。
圖13及圖14說明可與鰭片列142之側壁相抵而形成之犧牲材料146(其在此實施例中充當模具且可被稱作模具)。犧牲材料146可藉由側壁隔片製程而形成。犧牲材料146可由可在隨後參考圖18而描述之處理傳導(procession conduction)下變得可流動(例如，其可變成諸如氣體或液體之流體)之材料形成。拋棄式模具材料之實例包括碳及特定聚合物，其皆可藉由將其與氧在熔爐中進行反應而作為氣體自基板110被移除。保形薄膜可沈積於基板110上，從而覆蓋上部摻雜區域112及下部摻雜區域114，且隨後經各向異性地蝕刻。側壁隔片蝕刻可移除下部摻雜區域114之一部分以形成凹部148。凹部148可具有通常等於或小於1 F、1/2 F或1/4 F之寬度150。如以下所解釋，繼續側壁隔片蝕刻直至其形成凹部148被認為係用以減少藉由模具146而形成之閘極對彼此造成短路之可能性。在此實施例中，犧牲材料146在上部摻雜區域112之底部上方延伸且具有可小於或通常等於1 F、1/2 F或1/4 F之寬度152。
在形成犧牲材料146之後，可將介電區域154形成於犧牲材料146上，如由圖15所說明。在一些實施例中，介電區域154可為藉由諸如原子層沈積(ALD)之低溫製程而沈積之氧化物。所說明之介電質154大體上或全部地包封犧牲材料146且包括覆蓋層156。
在由圖16所說明之平坦化步驟中消耗覆蓋層156。基板110可藉由回蝕、CMP或其他製程而進行平坦化。在一些實施例中，可移除覆蓋層156，直至曝光上部摻雜區域112之頂部、深隔離溝槽118及淺溝槽130。介電區域154與此等結構112、118及130之間的轉變可產生向用以對基板110進行平坦化之製程觸發端點的現象。舉例而言，此轉變可得到基板110之光學性質(諸如，顏色)的改變、離開基板110之廢料之化學性質(諸如，蝕刻室中之廢氣或漿料pH值)的改變，或基板110之機械性質(諸如，滑動摩擦)的改變。
緊接著，如由圖17所說明，可移除淺溝槽130中之材料的至少一部分。在一些實施例中，此材料為氮化物，且其係藉由相對於矽及氧化物為選擇性以避免損失此等材料之實質量的乾式蝕刻而被移除。清除淺溝槽130之至少一部分會打開通向犧牲材料146之側壁158的通路，且此通路可促進移除犧牲材料146。
如由圖18所說明，可藉由經由淺隔離溝槽130之打開通路而移除犧牲材料146。為了移除犧牲材料146，可將基板110在(例如)電漿蝕刻室中曝光至氧電漿或在熔爐中曝光至氧。電漿或其他反應物經由淺隔離溝槽130而流入且(例如)藉由燃燒犧牲材料146而與犧牲材料146之側壁158進行反應。在一些實施例中，反應之副產物為氣體，例如，蒸汽、一氧化碳及二氧化碳，且氣體經由淺隔離溝槽130而回流出。在一些實施例中，繼續燃燒，直至燃盡實質部分或大體上整個犧牲材料146且形成空腔160。所得空腔160在一側上係由介電質154界限且在另一側上係由鰭片列142界限。
空腔160之形狀係由圖19說明，圖19說明在不具有基板110之其他部分之情況下的空腔160。空腔160中之每一者可包括兩個整體反射對稱、整體線性且整體平行之空隙162及164以及複數個溝槽區段166。所說明之溝槽區段166安置於空隙162及164之頂部部分中且將空隙162與164彼此接合。相鄰空腔160可藉由介電質154(圖18)而彼此大體上或全部地分離。
緊接著，如由圖20所說明，可將閘極介電質166形成於空腔160內。閘極介電質166可(例如)藉由CVD而沈積或藉由將基板110曝光至氧而生長。在所說明實施例中，閘極介電質166係藉由將基板110之矽部分與氧進行反應而生長，因此，閘極介電質166安置於鰭片列142之經曝光表面(包括淺溝槽130之表面)上。進行反應以形成閘極介電質166之氧或其他化學品經由溝槽區段166而流入至空腔160中且與線性空隙162及164(圖19)內之表面進行反應。在各種實施例中，閘極介電質166可由各種材料製成，包括氧化物、氮氧化物、鉿基高k介電質，或其他適當材料。
一旦形成閘極介電質166，便可將閘極材料沈積於空腔166內以形成閘極168，如由圖21、圖22及圖23所說明。所說明之閘極168可藉由沈積氮化鈦或其他適當導電材料而形成。閘極材料可藉由氣相反應物而輸送至基板110且輸送至空腔166中。反應物可經由淺溝槽130而流入至空腔166中且在空腔166之表面上進行反應。在一些實施例中，閘極材料在填充空腔166之前關閉淺溝槽130，藉此留下空隙170。閘極材料之覆蓋層可形成於基板110之表面上，且覆蓋層可藉由濕式蝕刻、乾式蝕刻或CMP製程而被移除。
圖24為藉由以上所描述製程而形成之電晶體171之實例的分解透視圖。然而，應注意，本技術不限於電晶體，且可用以形成諸如電容器或浮動閘極電晶體之其他裝置。所說明之電晶體171包括鰭片172、閘極介電質166及閘極168。所說明之鰭片172包括藉由與淺溝槽130對應之整體U形狹槽178而分離之兩個支柱174及176。鰭片172之遠端部分係由上部摻雜區域112製成，且鰭片172之下部部分係由下部摻雜區域114製成。邊緣180及182通常係由深隔離溝槽118界定且可長於鰭片172之側184及185。所說明之閘極166經安置成與側184及185以及狹槽178之表面皆相鄰。
在所說明實施例中，閘極168包括兩個側閘極186及188以及頂部閘極190。兩個側閘極186及188為整體反射對稱的且皆整體在X方向上延伸，其在一實質距離內具有整體均一橫截面。除了空隙170之外，側閘極186及188之形狀與犧牲材料146之形狀整體互補。所說明之頂部閘極190在Y方向上具有整體均一橫截面且其將側閘極186與188彼此接合。頂部閘極190可通常為固體、不具有空隙，或在一些實施例中，頂部閘極190亦可包括空隙。側閘極186經安置成與鰭片172之側185至少部分地相鄰，頂部閘極190經安置成至少部分地在狹槽178內，且側閘極188經安置成與鰭片172之側184至少部分地相鄰。由於閘極168經安置成與鰭片172之兩個側及頂部部分相鄰，故所說明之電晶體171可經特性化為三閘極電晶體。
在操作中，兩個支柱174及176可充當源極及汲極，且電晶體171可根據閘極168之電壓而選擇性地控制電流在源極與汲極之間的流動。所說明之電晶體171包括三個通道：由箭頭192所表示之整體水平通道，及由箭頭194所表示之兩個整體垂直通道。可藉由自頂部閘極190發散之電場而建立整體水平通道192，且可藉由自兩個側閘極186及188發散之電場而建立整體垂直通道194。
雖然本發明可易受各種修改及替代形式，但已在圖式中藉由實例而展示特定實施例且本文中已詳細地描述特定實施例。然而，應理解，本發明不意欲限於所揭示之特定形式。更確切而言，本發明將涵蓋屬於如由以下隨附申請專利範圍所界定之本發明之精神及範疇的所有修改、均等物及替代物。
110．．．基板
112．．．上部摻雜區域
114．．．下部摻雜區域
116．．．深溝槽光罩
118．．．深隔離溝槽
120．．．寬度
122．．．寬度
124．．．淺溝槽光罩
126．．．空間
128．．．寬度
130．．．淺隔離溝槽
132．．．鰭片光罩
134．．．寬度
136．．．寬度
138．．．側壁隔片
140．．．寬度
142．．．鰭片列
144．．．深度
146．．．犧牲材料/模具
148．．．凹部
150．．．寬度
152．．．寬度
154．．．介電區域/介電質
156．．．覆蓋層
158．．．側壁
160．．．空腔
162．．．空隙
164．．．空隙
166．．．溝槽區段/閘極介電質/空腔
168．．．閘極
170．．．空隙
171．．．電晶體
172．．．鰭片
174．．．支柱
176．．．支柱
178．．．U形狹槽
180．．．邊緣
182．．．邊緣
184．．．側
185．．．側
186．．．側閘極
188．．．側閘極
190．．．頂部閘極
192．．．整體水平通道
194．．．整體垂直通道
X．．．方向
Y．．．方向
Z．．．方向
圖1至圖24說明根據本技術之一實施例之製造製程的實例。
112．．．上部摻雜區域
114．．．下部摻雜區域
166．．．溝槽區段/閘極介電質/空腔
168．．．閘極
170．．．空隙
172．．．鰭片
174．．．支柱
176．．．支柱
178．．．U形狹槽
180．．．邊緣
182．．．邊緣
184．．．側
185．．．側
186．．．側閘極
188．．．側閘極
190．．．頂部閘極
192．．．整體水平通道
194．．．整體垂直通道
X．．．方向
Y．．．方向
Z．．．方向

Claims (25)

  1. 一種製造具有空腔界定閘之裝置之方法，其包含：形成一溝槽於一基底中；形成一第一犧牲材料於該溝槽中；形成一半導體鰭片，其中該半導體鰭片垂直於該溝槽；形成一與該半導體鰭片相鄰之第二犧牲材料；藉由一介電材料而覆蓋該第二犧牲材料；藉由移除該第一犧牲材料之至少一部分以形成一通路至該第二犧牲材料；不藉由通過該通路實質上移除該介電材質而藉由自該介電材料下方移除該第二犧牲材料以形成一空腔；及在該空腔中形成一閘極。
  2. 如請求項1之方法，其中形成該第二犧牲材料包含：形成一與該半導體鰭片相鄰之側壁隔片。
  3. 如請求項2之方法，其中形成該側壁隔片包含：形成一碳側壁隔片。
  4. 如請求項1之方法，其中移除該第二犧牲材料包含：通過該通路曝光該第二犧牲材料之至少一部分；及將該第二犧牲材料之至少一部分轉換成一流體。
  5. 如請求項1之方法，其中形成該通路包含：藉由化學機械拋光而移除安置於該第一犧牲材料上之該介電材料中之一些而非全部。
  6. 如請求項1之方法，其中形成該通路包含：移除該介電 材料，直至至少部分地曝光該第一犧牲材料之一部分。
  7. 如請求項4之方法，其中將該第二犧牲材料之至少一部分轉換成該流體包含：燃燒該第二犧牲材料之至少一實質部分。
  8. 如請求項1之方法，其中形成該空腔包含：在該半導體鰭片之任一側上形成整體線性空隙；及形成在該等整體線性空隙之間延伸之溝槽區段。
  9. 如請求項1之方法，其中在該空腔中形成該閘極包含：藉由將一反應物氣體流入至複數個開口中而進入該空腔中而形成一橫越該半導體鰭片之至少三個側的閘極。
  10. 一種具有空腔界定閘之裝置，其包含：一鰭片列，其包含複數個鰭式場效電晶體；一閘極，其經安置成與該鰭片列相鄰，其中該閘極包含：沿著該鰭片之一第一側形成之一第一中空側閘極；沿著該鰭片之一第二側形成之一第二中空側閘極，該第二側係相對於該第一側。
  11. 如請求項10之裝置，其中該閘極包含複數個溝槽區段，該等溝槽區段橫越複數個該等鰭式場效電晶體之一遠端部分。
  12. 如請求項10之裝置，其中該複數個鰭式場效電晶體當中之每一鰭式場效電晶體包含三個通道。
  13. 如請求項10之裝置，其中該複數個鰭式場效電晶體當中之每一鰭式場效電晶體包含一整體U形遠端部分。
  14. 如請求項10之裝置，其中該複數個鰭式場效電晶體當中之每一鰭式場效電晶體之一鰭片寬度小於光微影解析度極限。
  15. 一種於一裝置中形成空腔之方法，其包含：形成一第一犧牲材料於一半導體鰭片上之一溝槽中；形成一第二犧牲材料，其中該第二犧牲材料安置於相鄰該半導體鰭片；藉由一介電材料而覆蓋該第二犧牲材料；不藉由實質上移除該介電材料而藉由移除該第一犧牲材料以致能接近並移除該第二犧牲材料。
  16. 如請求項15之方法，其中該第二犧牲材料包含非晶碳、光阻或此兩者。
  17. 如請求項15之方法，其中該第二犧牲材料包含：一第一側壁隔片，該第一側壁隔片經安置成與該半導體鰭片之一側相抵；及一第二側壁隔片，該第二側壁隔片經安置成與該半導體鰭片之另一側相抵。
  18. 如請求項17之方法，其中該第一犧牲材料包含一安置於自該半導體鰭片延伸之兩個支柱之間的溝槽區段。
  19. 如請求項18之方法，其中該第一側壁隔片係藉由該溝槽區段而耦接至該第二側壁隔片。
  20. 如請求項15之方法，其包含：藉由移除該第二犧牲材料以於該介電材料下方形成一空腔並於該空腔中形成一閘極以界定與該半導體鰭片相鄰之該閘極。
  21. 一種具有空腔界定閘之裝置，其包含： 複數個三閘極電晶體，其各自包含一頂部閘極及兩個側閘極；複數個介電構件，其各自安置於相鄰三閘極電晶體之該等側閘極之間，其中該等介電構件延伸至深於該等側閘極之凹部中。
  22. 如請求項21之裝置，其中該等凹部為側壁隔片過度蝕刻之凹部。
  23. 如請求項21之裝置，其中該等凹部窄於光微影解析度極限。
  24. 如請求項21之裝置，其中該頂部閘極或該兩個側閘極中之至少一者形成於一空腔內。
  25. 如請求項24之裝置，其中該頂部閘極及該兩個側閘極中之每一者形成於一空腔內。
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JP2011514677A (ja) 2011-05-06
US7915659B2 (en) 2011-03-29
KR20100131478A (ko) 2010-12-15
CN101960572A (zh) 2011-01-26
US20090224357A1 (en) 2009-09-10
TW200947565A (en) 2009-11-16
US9331203B2 (en) 2016-05-03
KR101547375B1 (ko) 2015-08-25

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