TWI481030B - 具有鰭式電晶體之系統及裝置以及其使用、製造和運作方法 - Google Patents

具有鰭式電晶體之系統及裝置以及其使用、製造和運作方法 Download PDF

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TWI481030B
TWI481030B TW098104199A TW98104199A TWI481030B TW I481030 B TWI481030 B TW I481030B TW 098104199 A TW098104199 A TW 098104199A TW 98104199 A TW98104199 A TW 98104199A TW I481030 B TWI481030 B TW I481030B
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transistor
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Werner Juengling
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Micron Technology Inc
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET

Description

具有鰭式電晶體之系統及裝置以及其使用、製造和運作方法
本發明之實施例一般而言係關於電子裝置，且更具體而言，在某些實施例中係關於鰭式電晶體。
鰭式場效電晶體(finFET)經常圍繞一自一基板大體上垂直延伸之鰭(例如，一高且薄之半導電部件)構建。一般而言，一閘極藉由沿鰭之一個側等形地向上行進翻越頂部並沿鰭之另一側向下行進而跨越該鰭。在某些實例中，該閘極經安置倚靠該鰭之側且並不延伸翻越頂部。一般而言，一源極及一汲極位於閘極之相對側上，靠近鰭之兩端。在作業中，一穿過源極與汲極之間的鰭之電流係藉由選擇性地供電給閘極來控制。
某些finFET包含藉助一側壁間隔件過程形成之閘極。在此過程之某些版本中，藉由用一等形、導電膜覆蓋一鰭且然後各向異性蝕刻該導電膜來形成該等閘極。在該蝕刻期間，比自垂直表面快地自水平表面移除該導電材料。因此，該導電材料之一部分殘留倚靠鰭之垂直側壁。此過程之一優點係相對於經常經受對準及解析度約束之藉助光微影圖案化之閘極可形成相對狹窄閘極。
儘管藉助一側壁間隔件過程形成閘極避免了某些過程問題，但其可引入其他失效機制。鰭之側壁經常成一角度而非垂直，此乃因該等鰭係藉助一小於完全各向異性之蝕刻步驟而形成。該等成一角度之側壁可使側壁間隔件過程之窗口變窄，且在某些情況下使其閉合。該等角度使毗鄰鰭之基底彼此更靠近地放置，且當等形膜沈積於此較狹窄間隙中時，該膜之覆蓋該等毗鄰側壁之部分可聯合，從而在該間隙中形成一具有一較大垂直厚度之膜。在該間隙中該膜可變得如此厚以至於側壁間隔件蝕刻不會移除毗鄰閘極之間的所有導電膜。所得導電殘餘物形成使毗鄰finFET短路且降低良率之條紋。
上文論述之若干問題可藉由隨後所述實施例中之某些實施例得到緩解。在該等實施例之中係在毗鄰閘極之間形成絕緣鰭之製作過程之一實例。如下文所闡釋，在某些實施例中，絕緣鰭及半導體鰭兩者皆藉由一界定絕緣鰭與半導體鰭之間的溝之單個蝕刻來形成。該等溝又可界定形成於該等溝中之閘極之形狀及位置。由於該等閘極形成於藉由絕緣鰭分離之溝中，因此在某些實施例中，認為該等閘極比藉助習用技術形成之閘極彼此更可靠地隔離。下文參照圖1-22闡述此製作過程及其某些變形。
如圖1所圖解說明，該製作過程以提供一基板102開始。基板102可包含半導電材料，例如單晶或多晶矽、砷化鎵、磷化銦或具有半導體特性之其他材料。另一選擇為或額外地，基板102可包含一電子裝置可構造於其上之一非半導體本體，例如，諸如一塑膠或陶瓷工作表面等結構。措詞"基板"囊括處於各種製作階段之本體，包含一未處理之整個晶圓、一部分處理之整個晶圓、一完全處理之整個晶圓、一經切割晶圓之一部分或一經封裝電子裝置中一經切割晶圓之一部分。
在此實施例中，基板102包含一上部摻雜區104及一下部摻雜區106。上部摻雜區104及下部摻雜區106可係經不同摻雜。例如，上部摻雜區104可包含一n+材料且下部摻雜區106可包含一p-材料。上部摻雜區104之深度在基板102之一相當大部分上可係大體上均勻，例如(舉例而言)遍及一記憶體裝置之一陣列區域之一相當大部分。可藉由植入或擴散摻雜劑材料摻雜上部摻雜區104及下部摻雜區106。另一選擇為，或額外地，可在生長或沈積基板102之全部或一部分期間摻雜該等區104或106中之一者或兩者，例如在磊晶沈積一半導電材料期間或在生長一自其切下晶圓之半導電晶碇期間。如下文所闡釋，上部摻雜區104可提供用於形成一電晶體之一源極及一汲極之材料且下部摻雜區106可提供用於形成該電晶體之一通道之材料。
可在基板102中形成深隔離渠溝108及淺渠溝110。該等渠溝108及110可大體上沿Y方向延伸，如圖1中所指示。一個或多個淺渠溝110可插在若干對深隔離渠溝108之間。在某些實施例中，淺渠溝110可深於上部摻雜區104以分離隨後形成之源極及汲極。額外地，深隔離渠溝108可深於淺渠溝110以隔離隨後形成之電晶體。
深隔離渠溝108及淺渠溝110可界定基板102之若干尺寸。淺渠溝110具有一小於F之寬度112，其中F為圖案化深隔離渠溝所藉助之設備之解析度。類似地，深隔離渠溝108可具有一小於F之寬度114，且深隔離渠溝108可與淺渠溝110以一小於F之寬度116間隔開。在某些實施例中，該等寬度112、114及116中之一者或多者或全部小於或大體上等於3/4F、1/2F或1/4F。渠溝108及110以一週期118重複，在某些實施例中，該週期小於或大體上等於4F、2F或1F。在其他實施例中，可以該圖案中之其他結構或變化遮斷該圖案。深隔離渠溝108及/或淺渠溝110可具有一大體上矩形或梯形之橫截面，且在某些實施例中，其橫截面在通過沿Y方向之某些距離上可大體上均勻，例如在通過一大於一個、兩個、五個或更多個電晶體長度之距離上。
可使用各種流程來形成深隔離渠溝108及淺渠溝110。在某些實施例中，該等渠溝各自藉助一雙間距遮罩按順序形成。在此一過程之一個實例中，首先藉由遮蔽掉每隔一對深隔離渠溝108之間的區域且然後在對應於深隔離渠溝108中之每一者之區域上方在該遮罩之側上形成一多晶矽側壁間隔件來形成深隔離渠溝108。然後，可移除該遮罩且一硬遮罩材料(例如，氧化物)可沈積於殘留多晶矽側壁間隔件上方，且可藉助化學機械平坦化(CMP)回蝕或平坦化該硬遮罩材料以曝露該多晶矽。接下來，可選擇性地蝕刻該多晶矽以在該氧化物硬遮罩中形成開口，藉由該等開口可蝕刻深隔離渠溝108。可藉助一類似流程形成淺渠溝110，除將初始遮罩移位達某段距離(例如，寬度116)及一較淺蝕刻以外。在其他實施例中，該等結構108及110(如本文中所論述之諸多其他結構)可藉助若干流程來形成。
可用各種介電材料(例如(舉例而言)高密度電漿(HDP)氧化物、原矽酸四乙酯(TEOS)或旋塗玻璃(SOG))部分地或全部地填充深隔離渠溝108及淺渠溝110以電隔離特徵。額外地，深隔離渠溝108或淺渠溝110可包含各種襯裡材料(例如(舉例而言)氮化矽)以釋放膜應力、改良黏附力或用作一障壁材料。在某些實施例中，在填充之前，用選定以進一步隔離電晶體之摻雜劑植入深隔離渠溝108之底部。
接下來，在此實施例中，在基板102上形成三個不同膜，如圖2所圖解說明。首先圖解說明之膜為一下部終止區120。在此實施例中，下部終止區120為一氧化物層，部分端視基板102之大部分半導體材料是否容易形成一原生氧化物(如矽等材料發生的)，生長或者沈積該氧化物層。例如，可藉由在一爐中使基板102之矽部分之表面與氧反應在矽上生長下部終止區120或可在具有各種類性之半導體材料(包含矽及化合物半導體兩者)之基板上藉助化學氣相沈積(CVD)沈積下部終止區120。下部終止區120可係在20與200之間厚，例如大體上接近80厚。
下部終止區120可由一不同於下一區之材料製成：一上部終止區122。在此實施例中，上部終止區122由藉助CVD沈積之氮化物製成。上部終止區122可係在30與300之間厚，例如大體上接近100厚。如下文所闡釋，在某些實施例中，上部終止區122與下部終止區120之間的過渡可藉由發出停止蝕刻之適合時間之信號或藉由在穿透上部摻雜區104之間減慢蝕刻速率來減少過度蝕刻。
接下來，在所圖解說明之實施例中，形成一犧牲遮罩區124，如圖2所圖解說明。犧牲遮罩區124可由藉助一CVD系統沈積之多晶矽製成，且其可具有一在500與5000之間的厚度，例如大體上接近1500厚。犧牲遮罩區124之厚度可基於一所需半導體鰭高度來選擇。如下文所闡釋，在此實施例中，犧牲遮罩區124形成用於界定半導體鰭之蝕刻步驟之硬遮罩。在鰭蝕刻期間消耗該硬遮罩之一部分，因此，半導體鰭越長，且鰭蝕刻得越深，則犧牲遮罩區124可越厚。
在形成如圖2所圖解說明之膜之後，圖案化基板102，如圖3及4所圖解說明。圖3圖解說明一前驅鰭遮罩126，且圖4圖解說明藉由蝕刻藉由前驅鰭遮罩126曝露之區所形成之前驅鰭128。前驅鰭遮罩126可由光阻劑製成或遮罩126可係藉由沈積並圖案化一遮蔽材料所形成之硬遮罩。前驅鰭遮罩126可藉助各種微影系統來圖案化，例如一光微影系統、一奈米壓印系統、一電子束系統或其他適合圖案化裝置。所圖解說明之前驅鰭遮罩126包含一系列遮蔽區130及曝露區132，兩者皆大體上沿X方向延伸。遮蔽區130及曝露區132兩者可具有一大體上等於1F之寬度，且其遵循前驅鰭遮罩126可具有一接近2F之週期134。
在某些實施例中，與某些習用過程相比，前驅鰭遮罩126具有一相對大的對準限度。在此實施例中，基板102上之諸多現有結構(例如深隔離渠溝108及淺渠溝110)沿Y方向大體上均勻。因此，在此實施例中，遮罩126可沿Y方向稍微移位，或錯位，此對電晶體之最終形狀沒有明顯影響。類似地，由於遮罩126沿X方向大體上均勻，因此渠溝108及110沿X方向之某些錯位在某些實施例中可係可接受。
在形成前驅鰭遮罩126之後，可蝕刻前驅鰭128，如圖4所圖解說明。在某些實施例中，此蝕刻可係一大體上各向異性乾式蝕刻。前驅鰭128可具有與前驅鰭遮罩126之尺寸大體上互補之尺寸。該蝕刻可形成沿Z軸大體上延伸一距離136進入基板102中之空洞。距離136可經選擇以使得該等空洞底部138比淺渠溝110深得多，但不如深隔離渠溝108那麼深。
接下來，如圖5及6所圖解說明，可底切前驅鰭128之犧牲遮蔽區部分124。可將基板102放置於一濕式蝕刻浴槽中，其對製成犧牲遮蔽區124之材料有選擇性，例如一優先蝕刻多晶矽但以一慢得多之速率移除基板102上之其他材料之濕式蝕刻。由於濕式蝕刻為大體上各向同性，且由於犧牲遮蔽區124之頂部及底部被其他區126及122覆蓋，因此該濕式蝕刻可主要自犧牲遮蔽區124之垂直表面沿X及Y方向移除材料，藉此使其寬度140變窄。在某些實施例中，寬度140可大體上等於或小於1/4F、1/2F、3/4F或1F。可以一大體上等於或大於3/8F、1/4F、1/8F之距離142或某一其他距離來底切犧牲遮蔽區124。在某些實施例中，距離142可大體上等於或大於15nm。如下文所述，較狹窄犧牲遮蔽區124可界定較狹窄半導體鰭。在某些實施例中，可在形成前驅鰭128之蝕刻期間對犧牲遮蔽區124進行底切。
接下來，移除前驅鰭遮罩126，如圖7所圖解說明。前驅鰭遮罩126可藉助一對前驅鰭遮罩126有選擇性之濕式蝕刻來移除或前驅鰭遮罩126可藉由在一爐中或一電漿蝕刻室中使前驅鰭遮罩126與氧反應來移除。
如圖8所圖解說明，可在基板102上形成一襯裡142。在此實施例中，襯裡142為一藉助化學氣相沈積或其他類型之沈積所沈積之大體上等形氮化物膜。在某些實施例中，襯裡142由例如與上部終止區122相同之材料或其他適合材料製成。襯裡142可具有一大體上等於或小於犧牲遮蔽區124(圖6)之底切寬度142之厚度144。所圖解說明之襯裡142包含界定一具有兩個大體上90度之方向改變之複合曲線之肩部143。如下文所闡釋，在某些實施例中，當蝕刻襯裡142之高於肩部143之部分時，該等肩部143保護襯裡142之低於肩部143之部分。因此，在某些實施例中，肩部143用作一終止區。
接下來，形成一閘極間電介質146，如圖9所圖解說明。在此實施例中，閘極間電介質146係一經施加具有一覆蓋層148之旋塗電介質(SOD)。在其他實施例中，其可係一藉助一不同過程，例如CVD或ALD施加之不同材料。該旋塗電介質可係一旋塗玻璃，例如氧化物，且在某些實施例中，該旋塗電介質可藉由將基板102放置在一爐中以自該旋塗電介質驅動揮發性化合物而稠密化。在某些實施例中，襯裡142可保護基板102之其他部分免於在稠密化期間產生之膜應力。
在形成閘極間電介質146之後，可借助化學機械平坦化(CMP)來大體上平坦化基板102，如圖10所圖解說明。該CMP過程可移除覆蓋層148、襯裡142之一終止部分且在犧牲遮蔽區124上或其附近停止。閘極間電介質146與襯裡142之間的過渡可產生一觸發CMP過程之結束之可偵測現象，例如基板光學特性(例如，色彩)之改變、化學特性(例如，廢漿pH)或機械特性(例如，滑動摩擦)。襯裡142與犧牲遮蔽區124之間的過渡亦可產生用於指示該過程之結束之類似可偵測現象。在某些實施例中，該CMP過程在襯裡142上或其附近停止且不曝露犧牲遮蔽區124。
接下來，移除襯裡142之高於肩部143之部分，如圖11及12所圖解說明。襯裡142可藉助一乾式蝕刻移除，該乾式蝕刻一般而言對襯裡142有選擇性以使得蝕刻襯裡142而不移除犧牲遮蔽區124或閘極間電介質146之一相當大部分。在此實施例中，該蝕刻在肩部143上或其附近停止，且襯裡142之低於肩部143之一相當大部分或全部殘留在適當位置。在某些實施例中，該蝕刻可穿透進入上部終止區122且在下部終止區120上停止。移除襯裡142之上部部分在交替之犧牲遮蔽區124及閘極間電介質146部件之間敞開若干間隙150。在此實施例中，該等間隙150曝露用於下一過程步驟之閘極間電解質146側壁。
在形成間隙150之後，可對其進行加寬，如圖13及14所圖解說明。在此實施例中，藉由濕式蝕刻基板102來加寬間隙150。蝕刻劑穿透間隙150且與閘極間電介質146之側壁進行反應。該濕式蝕刻係一大體上各向同性且一般而言對閘極間電介質146有選擇性以使得移除相對少之犧牲遮蔽區124。在某些實施例中，該濕式蝕刻底切犧牲遮蔽區124下方之上部終止區122之一部分。可將間隙150加寬至一寬度152，且可將閘極間電介質146變窄至一寬度156。在某些實施例中，寬度156及寬度152兩者可小於F，例如大體上等於或小於3/4F、1/2F或1/4F。如下文所闡釋，寬度152可大體上界定若干電晶體中之每一者之閘極寬度。
接下來，在當前所述之實施例中，各向異性地蝕刻基板102，如圖15及16所圖解說明。在此實施例中，各向異性蝕刻優先地沿Z方向移除材料且一般而言對基板102之若干曝露材料中之諸多或全部材料沒有選擇性。例如，該蝕刻可大體上以大體上相同速率蝕刻閘極間電介質146、犧牲遮蔽區124、上部摻雜區104及下部摻雜區106。此蝕刻可係此項技術中稱作"鱷皮蝕刻"之蝕刻類性。
如圖15及16所圖解說明，當前所述蝕刻改變基板102之眾多特徵。可移除犧牲遮蔽區124之一相當大部分或全部，且可在上部摻雜區104及下部摻雜區106兩者中敞開溝158。所圖解說明之溝158亦可消耗襯裡142之一部分。溝158在上部摻雜區104之頂部以下可具有一深於淺渠溝110但不如深隔離渠溝108或者前驅鰭128(圖4)之間的空間之底部138深之深度160。溝158之側壁可大體上平行於Z方向，或其可傾斜或彎曲。該蝕刻亦可減少閘極間電介質146之厚度且大體上界定絕緣鰭154。絕緣鰭154可具有一界定溝158之一底部部分之基底155。如下文所闡釋，絕緣鰭154可分離毗鄰列之電晶體之閘極。
在此階段，基板102可大體上界定半導體鰭162之尺寸。為圖解說明該等尺寸，圖17繪示移除其他特徵之基板102之上部摻雜區104及下部摻雜區106。如所圖解說明，基板102包含複數個半導體鰭162。所圖解說明之鰭162配製成大體上沿X方向延伸之若干個列164及大體上沿Y方向延伸之若干個行166。在此實施例中，半導體鰭162中之每一者皆藉由一深渠溝168與同一列164中之其他半導體鰭162隔離且藉由一中間渠溝170與同一行166中之其他半導體鰭162隔離。中間渠溝170可包含一較寬上部部分172及一較狹窄下部部分174。所圖解說明之半導體鰭162中之每一者皆包含一具有兩個支柱176及178之大體上U形末端部分，該等支柱藉由一淺渠溝180分離。如下文所闡釋，該等支柱176及178中之每一者可形成一電晶體之一源極或者一汲極。
圖18圖解說明當前所述實施例中之下一步驟。在形成間隙158之後，可形成一閘極電介質182。在某些實施例中，可藉助化學氣相沈積或原子層沈積來沈積閘極電介質182或在其他實施例中可藉由在一爐中(例如)使基板102曝露於氧來生長閘極電介質182。所圖解說明之閘極電介質182為經生長所得，且因此，其通常安置於上部摻雜區104及下部摻雜區106兩者之曝露部分上。閘極電介質182可由各種介電材料製成，例如氧化物、氧氮化物或高介電常數材料，如二氧化鉿、二氧化鋯及二氧化鈦。
接下來，可在基板102上形成一閘極材料184，如圖19所繪示。所圖解說明之閘極材料184為一導電材料，例如藉助一濺射過程沈積之氮化鈦，但在其他實施例中，閘極材料184可包含其他導電膜，例如經摻雜多晶矽或各種金屬。在此實施例中，閘極材料184經沈積而具有一覆蓋層185以平坦化基板102且大致或完全地填充溝158。
在所圖解說明之實施例中，然後對閘極材料184進行回蝕以在半導體鰭162之列164之任一側上形成隔離之閘極186及188，如圖20所圖解說明。閘極材料184可經凹陷低於隔離鰭154之頂部，但並非如此深以至於閘極186及188之頂部低於上部摻雜區104之底部。亦即，閘極186及188可與上部摻雜區104至少部分地重疊。
在某些實施例中，即使半導體鰭162之側壁傾斜，閘極186及188亦藉由絕緣鰭154彼此隔離。在此實施例中，在溝158中藉助一回蝕過程而非一側壁間隔件過程界定閘極186及188。因此，在某些實施例中，傾斜之鰭側壁未必使過程窗口變窄。
接下來，可移除犧牲遮蔽區124、上部終止區122及下部終止區120之殘留部分以曝露電晶體190之端子，如圖21及22所圖解說明。所圖解說明之電晶體190中之每一者皆包含一源極192、一汲極194及一由箭頭196所圖解說明之通道，該箭頭196繪示自源極192至汲極194之電流流動。電晶體190可消耗一大體上等於或小於4F2 之區域，包含閘極186及188及與每一電晶體190相關聯之隔離。
為導通電晶體190，可在閘極186及188上斷定一電壓，且源極192與汲極194之間的電壓可驅動電流196穿過通道。所圖解說明之電晶體190可稱作雙閘極電晶體或多閘極電晶體，此乃因其在毗鄰每一側壁處具有一閘極。可根據各種形式供電給閘極186及188：通常可同時供電給閘極186及188兩者；可供電給一個閘極186或188，而不供電給另一個；或可彼此獨立地供電給閘極186及188。在某些實施例中，閘極186及188可部分地或完全地圍繞若干個列164，例如閘極186及188可連接在列164之一個端或兩個端處。
各種裝置可連接至電晶體190。例如，電晶體190可連接至其他電晶體190以形成一處理器、一專用積體電路(ASIC)或靜態隨機存取記憶體(SRAM)或電晶體190可連接至一經組態以主要儲存資料之裝置，例如一電容器、相位改變記憶體、鐵電記憶體或一可程式化金屬化單元。
雖然本發明可容許有各種修改及替代形式，但具體實施例以舉例說明形式顯示於圖式中並詳細闡述於本文中。然而，應理解，並非意欲將本發明限定於所揭示之特定形式。相反，本發明將涵蓋屬於下文隨附申請專利範圍所界定之本發明之精神及範圍內之所有修改、等效形式及替代方案。
102．．．基板
104．．．上部摻雜區
106．．．下部摻雜區
108．．．深隔離渠溝
110．．．淺渠溝
112．．．寬度
114．．．寬度
116．．．寬度
118．．．週期
120．．．下部終止區
122．．．上部終止區
124．．．犧牲遮蔽區
126．．．前驅鰭遮罩
128．．．前驅鰭
138．．．空洞底部
142．．．襯裡
143．．．肩部
146．．．閘極間電介質
150．．．間隙
154．．．絕緣鰭
155．．．基底
158．．．溝
162．．．半導體鰭
166．．．行
164．．．列
168．．．深渠溝
170．．．中間渠溝
172．．．較寬上部部分
174．．．較狹窄下部部分
176．．．支柱
178．．．支柱
180．．．淺渠溝
182．．．閘極電介質
184．．．閘極材料
185．．．覆蓋層
186．．．閘極
188．．．閘極
190．．．電晶體
192．．．源極(端子)
194．．．汲極(端子)
196．．．電流/箭頭
圖1-22係一基板在根據本發明實施例之一製作過程的按順序階段期間之剖視圖。
102．．．基板
122．．．上部終止區
164．．．列
186．．．閘極
188．．．閘極
190．．．電晶體
192．．．源極(端子)
194．．．汲極(端子)
196．．．電流/箭頭

Claims (24)

  1. 一種包含鰭式電晶體的裝置，其包括：複數個鰭式場效電晶體，其安置成若干個列；複數個絕緣鰭，其每一者安置於該等列之間；及複數個記憶體元件，其每一者耦合至該複數個鰭式場效電晶體中之一鰭式場效電晶體之一端子。
  2. 如請求項1之裝置，其中該複數個絕緣鰭至少部分地界定該等鰭式場效電晶體之閘極安置於其中之若干個溝。
  3. 如請求項2之裝置，其中該絕緣鰭之至少一部分安置於該等閘極下方。
  4. 如請求項1之裝置，其中該複數個鰭式場效電晶體中之該等鰭式場效電晶體之每一者包括一大體上為U形的末端部分。
  5. 如請求項1之裝置，其中該複數個鰭式場效電晶體包括複數個雙閘極鰭式場效電晶體。
  6. 一種包含鰭式電晶體的裝置，其包括：複數個電晶體列，每一電晶體皆包括：一半導體鰭；及一閘極，其至少一部分經安置而毗鄰該半導體鰭；及複數個絕緣鰭，其每一者安置於該複數個電晶體列中之一對電晶體列之間。
  7. 如請求項6之裝置，其中該複數個絕緣鰭中之每一絕緣鰭皆包括一基底，且其中該基底至少部分地安置於閘極中之至少一者下方。
  8. 如請求項6之裝置，其中該等絕緣鰭沿該等電晶體列之一長度之至少一相當大部分延伸。
  9. 如請求項6之裝置，其中該複數個絕緣鰭中之每一絕緣鰭皆包括一安置於該絕緣鰭與一基板之間的襯裡。
  10. 如請求項6之裝置，其中該複數個電晶體列中之每一電晶體列皆包括一對安置於該電晶體列之相對側上之閘極(186、188)。
  11. 如請求項6之裝置，其中該等絕緣鰭之每一者皆小於1F寬。
  12. 一種包含鰭式電晶體的裝置，其包括：一第一電晶體及一第二電晶體，其每一者包括：一半導體鰭，其自一基板大體上垂直延伸且沿一平行於該基板之方向大體上線性延伸；及一對閘極，其形成於該半導體鰭之任一側上且大體上平行於該半導體鰭延伸；及一絕緣鰭，其安置於該第一電晶體與該第二電晶體之間且大體上平行於該第一及該第二電晶體中之每一者之該半導體鰭延伸。
  13. 如請求項12之裝置，其中該絕緣鰭、該第一電晶體之該半導體鰭及該第二電晶體之該半導體鰭界定該絕緣鰭之任一側上之一對溝，其中該第一電晶體之該對閘極中之一閘極安置於該對溝中之一溝中且該第二電晶體之該對閘極中之一閘極安置於該對溝中之另一溝中。
  14. 如請求項12之裝置，其中該等半導體鰭每一者包括一對 藉由一渠溝分離之支柱。
  15. 如請求項12之裝置，其包括一至少部分地安置於該絕緣鰭下方之襯裡。
  16. 如請求項12之裝置，其中該第一電晶體及該第二電晶體每一者包括一上部摻雜區)及一下部摻雜區，其中該上部摻雜區經摻雜而不同於該下部摻雜區。
  17. 一種製造包含鰭式電晶體的一裝置之方法，其包括：在一基板上形成一前驅鰭；在該基板上形成一襯裡膜；用一閘極間電介質至少部分地填充毗鄰該前驅鰭之一空洞；移除該襯裡膜之至少一部分；移除該閘極間電介質中藉由移除該襯裡膜之該部分所曝露之一部分；在該基板中形成一溝，其中該溝安置於一自該基板形成之半導體鰭與一自該閘極間電介質形成之絕緣鰭之間。
  18. 如請求項17之方法，其中該前驅鰭、該閘極間電介質及該溝窄於光微影解析度限制。
  19. 如請求項17之方法，其包括藉助一濕式蝕刻底切該前驅鰭。
  20. 如請求項17之方法，其中該形成該襯裡膜包括在該前驅鰭之任一側上形成襯裡膜之一肩部。
  21. 如請求項17之方法，其包括在形成該前驅鰭之前在該基 板中形成若干隔離渠溝，其中該等隔離渠溝大體上垂直於該前驅鰭延伸。
  22. 如請求項21之方法，其包括在形成該前驅鰭之前在該基板中形成若干淺渠溝，其中該等淺渠溝淺於該等隔離渠溝。
  23. 如請求項17之方法，其中形成該溝包括藉助一鱷皮蝕刻蝕刻該基板。
  24. 如請求項23之方法，其中該等隔離渠溝在深度上不同。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7915659B2 (en) 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
US8546876B2 (en) 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8334196B2 (en) 2010-11-01 2012-12-18 Micron Technology, Inc. Methods of forming conductive contacts in the fabrication of integrated circuitry
US8921899B2 (en) 2010-11-19 2014-12-30 Micron Technology, Inc. Double gated 4F2 dram CHC cell and methods of fabricating the same
US8293602B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Method of fabricating a finFET having cross-hair cells
US8294511B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same
US9553193B2 (en) 2010-11-19 2017-01-24 Micron Technology, Inc. Double gated fin transistors and methods of fabricating and operating the same
CN102646599B (zh) 2012-04-09 2014-11-26 北京大学 一种大规模集成电路中FinFET的制备方法
US9136397B2 (en) 2013-05-31 2015-09-15 Infineon Technologies Ag Field-effect semiconductor device
US9953975B2 (en) * 2013-07-19 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming STI regions in integrated circuits
CN104425371B (zh) * 2013-08-28 2017-09-22 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9184281B2 (en) 2013-10-30 2015-11-10 Infineon Technologies Ag Method for manufacturing a vertical semiconductor device and vertical semiconductor device
CN104900521B (zh) * 2014-03-04 2018-08-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
US9385123B2 (en) 2014-05-20 2016-07-05 International Business Machines Corporation STI region for small fin pitch in FinFET devices
CN105448917B (zh) * 2014-09-01 2019-03-29 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
KR102291571B1 (ko) * 2015-01-13 2021-08-18 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102166238B1 (ko) * 2016-04-01 2020-10-15 인텔 코포레이션 강화된 온 상태 및 오프 상태 성능을 위한 임계 전압 스위칭이 있는 강유전체 기반 전계 효과 트랜지스터
US10014391B2 (en) * 2016-06-28 2018-07-03 International Business Machines Corporation Vertical transport field effect transistor with precise gate length definition
US11469323B2 (en) 2018-09-25 2022-10-11 Intel Corporation Ferroelectric gate stack for band-to-band tunneling reduction
US10790286B2 (en) 2018-12-06 2020-09-29 Micron Technology, Inc. Apparatuses including 3D memory arrays, methods of forming the apparatuses, and related electronic systems
US10629615B1 (en) * 2019-01-04 2020-04-21 Macronix International Co., Ltd. Semiconductor structure having doped active pillars in trenches
CN112670180A (zh) * 2019-10-16 2021-04-16 长鑫存储技术有限公司 存储器、半导体器件及其制造方法
US20230299213A1 (en) * 2022-03-21 2023-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods for increased capacitance

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040106267A1 (en) * 2001-05-23 2004-06-03 International Business Machines Corporation Oxynitride shallow trench isolation and method of formation
US20060189078A1 (en) * 2004-05-26 2006-08-24 Werner Juengling Semiconductor structures and memory device constructions

Family Cites Families (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3885861A (en) 1972-10-02 1975-05-27 Hughes Aircraft Co Liquid crystal digital reticle
US5196910A (en) 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
US5160987A (en) 1989-10-26 1992-11-03 International Business Machines Corporation Three-dimensional semiconductor structures formed from planar layers
US5109256A (en) 1990-08-17 1992-04-28 National Semiconductor Corporation Schottky barrier diodes and Schottky barrier diode-clamped transistors and method of fabrication
US6791131B1 (en) 1993-04-02 2004-09-14 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
JPH07263576A (ja) 1994-03-25 1995-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6831322B2 (en) 1995-06-05 2004-12-14 Fujitsu Limited Semiconductor memory device and method for fabricating the same
JP3853406B2 (ja) 1995-10-27 2006-12-06 エルピーダメモリ株式会社 半導体集積回路装置及び当該装置の製造方法
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
WO1997028532A1 (en) 1996-02-01 1997-08-07 Micron Technology, Inc. Digit line architecture for dynamic memory
US5688709A (en) 1996-02-14 1997-11-18 Lsi Logic Corporation Method for forming composite trench-fin capacitors for DRAMS
US5793033A (en) 1996-03-29 1998-08-11 Metanetics Corporation Portable data collection device with viewing assembly
US7064376B2 (en) 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5821513A (en) 1996-06-26 1998-10-13 Telxon Corporation Shopping cart mounted portable data collection device with tethered dataform reader
TW347558B (en) 1996-07-10 1998-12-11 Fujitsu Ltd Semiconductor device with self-aligned contact and its manufacture
JP3941133B2 (ja) 1996-07-18 2007-07-04 富士通株式会社 半導体装置およびその製造方法
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US5925918A (en) 1997-07-30 1999-07-20 Micron, Technology, Inc. Gate stack with improved sidewall integrity
US6130551A (en) 1998-01-19 2000-10-10 Vantis Corporation Synthesis-friendly FPGA architecture with variable length and variable timing interconnect
US6097212A (en) 1997-10-09 2000-08-01 Lattice Semiconductor Corporation Variable grain architecture for FPGA integrated circuits
US6137128A (en) 1998-06-09 2000-10-24 International Business Machines Corporation Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
US5858829A (en) 1998-06-29 1999-01-12 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) cells with minimum active cell areas using sidewall-spacer bit lines
TW388125B (en) 1998-08-19 2000-04-21 Vanguard Int Semiconduct Corp Method for fabricating dynamic random access memory (DRAM) cells with minimum active cell areas
DE19842704C2 (de) 1998-09-17 2002-03-28 Infineon Technologies Ag Herstellverfahren für einen Kondensator mit einem Hoch-epsilon-Dielektrikum oder einem Ferroelektrikum nach dem Fin-Stack-Prinzip unter Einsatz einer Negativform
TW380316B (en) 1998-10-15 2000-01-21 Worldwide Semiconductor Mfg Manufacturing method for fin-trench-structure capacitor of DRAM
US6100129A (en) 1998-11-09 2000-08-08 Worldwide Semiconductor Manufacturing Corporation Method for making fin-trench structured DRAM capacitor
US6426175B2 (en) 1999-02-22 2002-07-30 International Business Machines Corporation Fabrication of a high density long channel DRAM gate with or without a grooved gate
KR100325472B1 (ko) 1999-04-15 2002-03-04 박종섭 디램 메모리 셀의 제조 방법
JP4074051B2 (ja) 1999-08-31 2008-04-09 株式会社東芝 半導体基板およびその製造方法
US6282113B1 (en) 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
DE19946719A1 (de) 1999-09-29 2001-04-19 Infineon Technologies Ag Grabenkondensator und Verfahren zu seiner Herstellung
JP3457236B2 (ja) 1999-11-05 2003-10-14 茂徳科技股▲ふん▼有限公司 深いトレンチキャパシター蓄積電極の製造方法
WO2001061738A1 (en) 2000-02-15 2001-08-23 Steag Cvd Systems Ltd. Dram capacitor with ultra-thin nitride layer
JP3983960B2 (ja) 2000-07-14 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法および半導体集積回路装置
KR100466689B1 (ko) 2000-08-28 2005-01-24 인터내셔널 비지네스 머신즈 코포레이션 콤팩트형 이중 포트 동적 랜덤 액세스 메모리 아키텍쳐 시스템 및 그 제조 방법
US6509226B1 (en) 2000-09-27 2003-01-21 International Business Machines Corporation Process for protecting array top oxide
US6967147B1 (en) 2000-11-16 2005-11-22 Infineon Technologies Ag Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor
US6258659B1 (en) 2000-11-29 2001-07-10 International Business Machines Corporation Embedded vertical DRAM cells and dual workfunction logic gates
US6576944B2 (en) 2000-12-14 2003-06-10 Infineon Technologies Ag Self-aligned nitride pattern for improved process window
CA2340985A1 (en) 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6809368B2 (en) 2001-04-11 2004-10-26 International Business Machines Corporation TTO nitride liner for improved collar protection and TTO reliability
US7190060B1 (en) 2002-01-09 2007-03-13 Bridge Semiconductor Corporation Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
TW580732B (en) 2002-05-23 2004-03-21 Taiwan Semiconductor Mfg FET having necking channel and method for making the same
US7019353B2 (en) 2002-07-26 2006-03-28 Micron Technology, Inc. Three dimensional flash cell
US6865100B2 (en) 2002-08-12 2005-03-08 Micron Technology, Inc. 6F2 architecture ROM embedded DRAM
US6927462B2 (en) 2002-08-28 2005-08-09 Infineon Technologes Richmond, Lp Method of forming a gate contact in a semiconductor device
US6670682B1 (en) 2002-08-29 2003-12-30 Micron Technology, Inc. Multilayered doped conductor
DE10248722A1 (de) 2002-10-18 2004-05-06 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Kondensator und Herstellungsverfahren
DE10302128B3 (de) 2003-01-21 2004-09-09 Infineon Technologies Ag Pufferverstärkeranordnung
US6845033B2 (en) 2003-03-05 2005-01-18 International Business Machines Corporation Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology
JP2004281782A (ja) 2003-03-17 2004-10-07 Toshiba Corp 半導体装置及びその製造方法
US6794254B1 (en) 2003-05-15 2004-09-21 Taiwan Semiconductor Manufacturing Company Embedded dual-port DRAM process
US7099216B2 (en) 2003-09-05 2006-08-29 International Business Machines Corporation Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing
US6844591B1 (en) 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
KR100518602B1 (ko) * 2003-12-03 2005-10-04 삼성전자주식회사 돌출된 형태의 채널을 갖는 모스 트랜지스터 및 그 제조방법
DE10361695B3 (de) 2003-12-30 2005-02-03 Infineon Technologies Ag Transistorstruktur mit gekrümmtem Kanal, Speicherzelle und Speicherzellenfeld für DRAMs sowie Verfahren zur Herstellung eines DRAMs
US6998666B2 (en) 2004-01-09 2006-02-14 International Business Machines Corporation Nitrided STI liner oxide for reduced corner device impact on vertical device performance
DE102004006520B4 (de) 2004-02-10 2010-05-12 Qimonda Ag Verfahren zur Herstellung einer DRAM-Speicherzellenanordnung mit Trenchkondensatoren und Stegfeldeffekttransistoren (FinFET) sowie DRAM-Speicherzellenanordnung
DE102004021052B3 (de) 2004-04-29 2005-12-29 Infineon Technologies Ag Verfahren zur Herstellung von Trench-DRAM-Speicherzellen und Trench-DRAM-Speicherzellenfeld mit Stegfeldeffekttransistoren mit gekrümmtem Kanal (CFET)
JP2006054431A (ja) 2004-06-29 2006-02-23 Infineon Technologies Ag トランジスタ、メモリセルアレイ、および、トランジスタ製造方法
US7132333B2 (en) 2004-09-10 2006-11-07 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
DE102004031385B4 (de) 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
DE102004043857B3 (de) 2004-09-10 2006-03-30 Infineon Technologies Ag DRAM-Zellenpaar und DRAM-Speicherzellenfeld mit Stack- und Trench-Speicherzellen sowie Verfahren zur Herstellung eines DRAM-Speicherzellenfeldes
DE102004043858A1 (de) 2004-09-10 2006-03-16 Infineon Technologies Ag Verfahren zur Herstellung einer Speicherzelle, einer Speicherzellenanordnung und Speicherzellenanordnung
KR100585161B1 (ko) 2004-10-02 2006-05-30 삼성전자주식회사 다중채널 트랜지스터 소자 제조 방법 및 이에 의한 소자
US7476920B2 (en) 2004-12-15 2009-01-13 Infineon Technologies Ag 6F2 access transistor arrangement and semiconductor memory device
US7254074B2 (en) 2005-03-07 2007-08-07 Micron Technology, Inc. Open digit line array architecture for a memory array
KR100618893B1 (ko) * 2005-04-14 2006-09-01 삼성전자주식회사 반도체 소자 및 그 제조방법
KR100630746B1 (ko) * 2005-05-06 2006-10-02 삼성전자주식회사 멀티-비트 및 멀티-레벨 비휘발성 메모리 소자 및 그 동작및 제조 방법
US7316953B2 (en) 2005-05-31 2008-01-08 Nanya Technology Corporation Method for forming a recessed gate with word lines
KR100608380B1 (ko) 2005-06-01 2006-08-08 주식회사 하이닉스반도체 메모리 소자의 트랜지스터 및 그 제조방법
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
KR100707200B1 (ko) * 2005-07-22 2007-04-13 삼성전자주식회사 핀-타입 채널 영역을 갖는 비휘발성 메모리 소자 및 그제조 방법
US7776715B2 (en) 2005-07-26 2010-08-17 Micron Technology, Inc. Reverse construction memory cell
US7151023B1 (en) 2005-08-01 2006-12-19 International Business Machines Corporation Metal gate MOSFET by full semiconductor metal alloy conversion
US20070058468A1 (en) 2005-09-12 2007-03-15 Promos Technologies Pte.Ltd. Singapore Shielded bitline architecture for dynamic random access memory (DRAM) arrays
KR100653712B1 (ko) 2005-11-14 2006-12-05 삼성전자주식회사 핀펫에서 활성영역과 실질적으로 동일한 상면을 갖는소자분리막이 배치된 반도체 장치들 및 그 형성방법들
US7402856B2 (en) 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US8716772B2 (en) 2005-12-28 2014-05-06 Micron Technology, Inc. DRAM cell design with folded digitline sense amplifier
KR100734304B1 (ko) 2006-01-16 2007-07-02 삼성전자주식회사 트랜지스터의 제조방법
KR100720238B1 (ko) 2006-01-23 2007-05-23 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US20070176253A1 (en) 2006-01-31 2007-08-02 Peng-Fei Wang Transistor, memory cell and method of manufacturing a transistor
TWI294640B (en) 2006-02-16 2008-03-11 Nanya Technology Corp Alignment mark and alignment method for the fabrication of trench-capacitor dram devices
US7573108B2 (en) * 2006-05-12 2009-08-11 Micron Technology, Inc Non-planar transistor and techniques for fabricating the same
US20080012067A1 (en) 2006-07-14 2008-01-17 Dongping Wu Transistor and memory cell array and methods of making the same
US7816216B2 (en) * 2007-07-09 2010-10-19 Micron Technology, Inc. Semiconductor device comprising transistor structures and methods for forming same
US8129763B2 (en) * 2008-02-07 2012-03-06 International Business Machines Corporation Metal-oxide-semiconductor device including a multiple-layer energy filter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040106267A1 (en) * 2001-05-23 2004-06-03 International Business Machines Corporation Oxynitride shallow trench isolation and method of formation
US20060189078A1 (en) * 2004-05-26 2006-08-24 Werner Juengling Semiconductor structures and memory device constructions

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