WO2001061738A1 - Dram capacitor with ultra-thin nitride layer - Google Patents

Dram capacitor with ultra-thin nitride layer Download PDF

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Publication number
WO2001061738A1
WO2001061738A1 PCT/IB2001/000131 IB0100131W WO0161738A1 WO 2001061738 A1 WO2001061738 A1 WO 2001061738A1 IB 0100131 W IB0100131 W IB 0100131W WO 0161738 A1 WO0161738 A1 WO 0161738A1
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WO
WIPO (PCT)
Prior art keywords
nitride layer
layer
method according
forming
seed layer
Prior art date
Application number
PCT/IB2001/000131
Other languages
French (fr)
Inventor
Avishai Kepten
Eli Ishckevitz
Hedri Shpilgberg
Sagy Levy
Yaozhi Hu
Original Assignee
Steag Cvd Systems Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US18268300P priority Critical
Priority to US60/182,683 priority
Application filed by Steag Cvd Systems Ltd. filed Critical Steag Cvd Systems Ltd.
Publication of WO2001061738A1 publication Critical patent/WO2001061738A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

Abstract

A thin nitride layer (thickness below 50Å) is formed by chemical vapor deposition (CVD) over a seed layer on a base structure comprising storage nodes for stack capacitors in the memory cells of a semiconductor device, such as a dynamic random access memory (DRAM) device. Preferably, the DRAM device comprises a stack capacitor structure comprising hemispherical grain silicon covered by the ultra-thin nitride layer. Alternatively, the capacitor may comprise a trench capacitor structure. The CVD process produces the ultra-thin nitride layer, while maintaining goods step coverage and low leakage current.

Description

DRAM CAPACITOR WITH ULTRA-THIN NITRIDE LAYER FIELD OF THE INVENTION

The present invention relates generally to fabrication of semiconductor devices, and specifically to high-density DRAM devices.

BACKGROUND OF THE INVENTION

The density of dynamic random-access memory (DRAM) continues to increase, thanks to advances in memory cell structure and production technology. Gigabit DRAM d vices are expected to enter the market within the next few years, based on feature sizes of 0.15 μm and below.

One of the key challenges associated with increasing DRAM cell density is to maximize the charge storage capacity of the cells, while minimizing leakage current. A typical DRAM cell contains a capacitor made up of a storage node, acting as a lower conductive plate, and a conductive upper plate. The plates are separated by a dielectric layer. In order to increase the capacitance, it is necessary to maximize the effective areas of the plates, while minimizing the thickness of the dielectric layer. A variety of cell designs have been developed to meet these criteria. The most common designs are categorized generally as trench capacitor (TRC) and stack capacitor (STC) types. These designs are surveyed in an article by Nitayama, et al., entitled "Future Directions for DRAM Memory Cell Technology," in IEDM Technical Digest (IEEE, 1998), pp. 355-

358, which is incorporated herein by reference.

State-of-the-art STC devices use hemispherical grain silicon (HSG) storage nodes, covered by a relatively thick (>50A) dielectric layer of nitride or tantalum oxide (TA2O5). A scheme of this sort with 0.15 μm feat ire size is described, for example, by Chum, et al., in an article entitled "A New DR-. -M Cell Technology Using Merged Process with Storag . Node and Memory Cell Contact for 4Gb DRAM and Beyond," in IEDM Technical Dige st (IEEE, 1998), pp. 351-54, which is incorporated herein by reference. Looking ahead to future generations, with feature sizes of 0.13 μm and below, the dielectric material used in stack capacitors must meet the requirements of high dielectric constant and low leakage current (<108 A/cm2), with good step coverage over the HSG and other elements of the capacitor structure. The thickness of the dielectric layer should be less than 5θA. Nitride dielectric cannot be made to meet these requirements using current furnace technology. New materials, such as TA2O5 and BST, may offer an alternative, but will require substantial further development before they can be used in production.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved method for production of thin dielectric layers.

It is a further object of some aspects of the present invention to provide an improved process for producing stack and trench capacitors used in DRAM devices.

In preferred embodiments of the present invention, a DRAM device comprises a capacitor, preferably a stack capacitor (STC) structure, most preferably comprising

HSG, which is covered by an ultra-thin nitride layer. Alternatively, the capacitor may comprise a trench capacitor structure. The nitride layer is formed by chemical vapor deposition (CVD), using a novel process implemented in a single-wafer CVD chamber.

The process enables the layer to be formed with a thickness below 5θA, while maintaining good step coverage and low leakage current. It thus meets the needs of gigabit DRAM devices with feature sizes of 0.15 μm and below. The present invention will be more fully understood from the following detailed

description of the preferred embodiment thereof, taken together with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic, sectional illustration of a DRAM cell, in accordance with a preferred embodiment of the present invention; and

FIG. 2 is a flow chart that schematically illustrates a process for producing a thin dielectric layer in a DRAM device, in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 is a schematic, sectional illustration of a DRAM cell 20, in accordance with a preferred embodiment of the present invention. The cell comprises a silicon substrate 22, on which a storage node 24 is formed. Preferably, the storage node comprises hemispherical grain silicon (HSG), as described, for instance, in the above- mentioned article by Chun, et al. The shape of storage node 24 in the FIG. 1 is shown only by way of example, and substantially any suitable shape known in the art may be used. The storage node is covered by an ultra-thin nitride layer 30, preferably less than 5θA thick, which is formed using a process described hereinbelow. A conductive plate 28 is formed over layer 30. Plate 28 and storage node 24 thus constitute the plates of a stack capacitor (STC), which are separated by the dielectric nitride layer 30. The capacitor is charged and discharged via a word line 26, as is known in the art.

FIG. 2 is a flow chart that schematically illustrates a process for producing ultra- thin nitride layers, such as layer 30, in accordance with a preferred embodiment of the present invention. At an initial step 40, STC storage nodes, such as node 24, are formed on a silicon wafer using processes known in the art. The nodes preferably comprise HSG, as noted above. The wafer is then transferred to a CND chamber in a single-wafer cluster tool, such as IΝTEGRAPRO, produced by STEAG CND Systems, in order to produce the nitride layer. The same cluster tool can also be used to form the storage nodes at step 40. In this case, the wafer can be transferred directly within the cluster tool from the node formation stage to the nitride layer formation stage, either under vacuum or in an atmospheric environment.

At a cleaning step 42, the wafer is optionally cleaned in situ. Any suitable method known in the art can be used for this purpose, including either dry or wet cleaning, or a combination of the two.

A seed layer is formed on the surface of node 24, at a seed formation step 44. This step is carried out using one or more of the following techniques:

• High- vacuum reactive gas seed flow. • Reactive gas flow, using chlorine gas, for example, under ultraviolet

(UV) illumination. This technique can be carried out either in the CND chamber or in a separate, dedicated surface conditioning chamber.

• Growth of a very thin layer of silicon nitride, with high step coverage, using dichlorosilane (DCS) and/or disilane chemistry and ΝH3, using CVD or, in particular, rapid thermal CVD (RTCVD).

• Plasma-enhanced growth of a thin nitride layer of N2 and/or atomic N*", using a remote or local plasma.

The seed layer is used as a base for CVD growth of a thin nitride layer, to serve as the bulk nitride layer 30, at a nitride layer growth step 46. The layer is preferably grown using silane, disilane or DCS chemistry, in a RTCVD and or CVD process with susceptor heating.

Optionally, at an annealing step 48, thin nitride layer 30 is annealed at high temperature under NH3 or N2, preferably using a rapid thermal processing (RTP) technique, in order to harden the layer. At a further optional post-treatment step 50, the wafer is treated under high temperature using NO and/or N2O gas. The DRAM production process then continues with the formation of upper plate 28 and other steps, as are known in the art.

It will be appreciated that the preferred embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

CLAIM:
1. A method for producing a thin nitride layer in a semiconductor device, comprising: providing a base structure; forming a seed layer on the base structure; and growing a nitride layer having a thickness less than 50A on the seed layer by chemical vapor deposition.
2. A method according to claim 1 , wherein the semiconductor device comprises a dynamic random access memory device having multiple memory cells, and wherein providing the base structure comprises forming storage nodes for stack capacitors in the cells.
3. A method according to claim 2. wherein the storage nodes comprise hemispherical grain silicon.
4. A method according to claim 1. wherein forming the seed layer comprises flowing a reactive gas over the base structure.
5. A method according to claim 4, wherein flowing the reactive gas comprises flowing the gas under high vacuum.
6. A method according to claim 4, wherein forming the seed layer comprises illuminating the structure with ultraviolet radiation while flowing the gas.
7. A method according to claim 1 , wherein forming the seed layer comprises growing a thin layer with high step coverage by chemical vapor deposition.
8. A method according to claim 1. wherein forming the seed layer comprises forming a thin nitride layer on the base structure using plasma enhancement.
9. A method according to claim 1 , wherein growing the nitride layer comprises growing the layer in the presence of a gas selected from a group consisting of silane. disilane and dichlorosilane.
10. A method according to claim 1. and comprising annealing the nitride layer at high temperature.
1 1. A method according to claim 1. and comprising treating the nitride layer at high temperature in the presence of a nitrogen-containing gas.
12. A dynamic random access memory device comprising a plurality of memory cells, each cell comprising: a stroage node; a nitride layer deposited on the storage node, the layer having a thickness less than 50A; and a plate deposited over the nitride layer, so that the node and the plate together define a capacitor in which charge is stored.
13. A device according to claim 12. wherein the storage node comprises hemispherical grain silicon.
14. A device according to claim 12. wherein the nitride layer is deposited on the storage node by first forming a seed layer on the node and then growing a nitride bulk layer on the seed layer by chemical vapor deposition.
15. A device according to claim 12, wherein the capacitor has a leakage current less than 10"s A/cm2.
PCT/IB2001/000131 2000-02-15 2001-02-02 Dram capacitor with ultra-thin nitride layer WO2001061738A1 (en)

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US18268300P true 2000-02-15 2000-02-15
US60/182,683 2000-02-15

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Cited By (11)

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Publication number Priority date Publication date Assignee Title
US7742324B2 (en) 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
US7808042B2 (en) 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
US7915659B2 (en) 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8076229B2 (en) 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
US8148776B2 (en) 2008-09-15 2012-04-03 Micron Technology, Inc. Transistor with a passive gate
US8546876B2 (en) 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US8810310B2 (en) 2010-11-19 2014-08-19 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US9190494B2 (en) 2008-02-19 2015-11-17 Micron Technology, Inc. Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US9087721B2 (en) 2008-02-19 2015-07-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US7742324B2 (en) 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
US9190494B2 (en) 2008-02-19 2015-11-17 Micron Technology, Inc. Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin
US9331203B2 (en) 2008-03-06 2016-05-03 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US7915659B2 (en) 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US8669159B2 (en) 2008-03-06 2014-03-11 Micron Technologies, Inc. Devices with cavity-defined gates and methods of making the same
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
US7981736B2 (en) 2008-03-20 2011-07-19 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7808042B2 (en) 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US8450785B2 (en) 2008-03-20 2013-05-28 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US8759889B2 (en) 2008-03-20 2014-06-24 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US8546876B2 (en) 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US9449652B2 (en) 2008-03-20 2016-09-20 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8076229B2 (en) 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
US8148776B2 (en) 2008-09-15 2012-04-03 Micron Technology, Inc. Transistor with a passive gate
US8810310B2 (en) 2010-11-19 2014-08-19 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same

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