TWI413705B - 經原子層沈積之鋇鍶鈦氧化物膜 - Google Patents

經原子層沈積之鋇鍶鈦氧化物膜 Download PDF

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Publication number
TWI413705B
TWI413705B TW096131531A TW96131531A TWI413705B TW I413705 B TWI413705 B TW I413705B TW 096131531 A TW096131531 A TW 096131531A TW 96131531 A TW96131531 A TW 96131531A TW I413705 B TWI413705 B TW I413705B
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Taiwan
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titanium oxide
layer
forming
tantalum
oxide layer
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TW096131531A
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English (en)
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TW200827479A (en
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Kie Y Ahn
Leonard Forbes
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Micron Technology Inc
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Description

經原子層沈積之鋇鍶鈦氧化物膜
本申請案大體而言係關於半導體裝置及裝置製造。
半導體裝置工業具有減小諸如處理器晶片、行動電話及記憶體裝置(諸如動態隨機存取記憶體(DRAM))之產品中所用裝置之大小的市場需要。目前，半導體工業依賴於減小或按比例縮放其基本裝置尺寸之能力。此裝置之按比例縮放包括諸如電容及主要使用二氧化矽製造的以矽為主之金屬氧化物半導體場效電晶體(MOSFET)及其變體之裝置中的介電層之按比例縮放。熱生長非晶形SiO2 層提供電穩定且熱力學穩定之材料，其中SiO2 層與底層矽之介面提供一高品質介面以及優良電隔離特性。然而，微電子裝置中按比例縮放及其他要求增加需要將其他材料用作多種電子結構中之介電區。
以下詳細說明乃參考以例示說明的方式來展示可實踐本發明之各種實施例的附圖。充分詳細描述該等實施例以使熟習此項技術者能實踐本發明之實施例。可利用其他實施例且可作出與結構、邏輯及電有關之變化。多個實施例不必相互排斥，可將一些實施例與一或多個其他實施例組合形成新實施例。
以下描述中所用之術語基板包括具有一用於形成諸如積體電路(IC)結構之結構的暴露表面之任何基板。應瞭解，術語基板包括半導體晶圓。術語基板亦用於指稱加工期間之半導體結構，且可包括已製造於其上之其他層。基板包括經摻雜及未經摻雜之半導體、由一基底半導體或絕緣體支撐之磊晶半導體層以及熟習此項技術者已知之其他半導體結構。應瞭解，術語導體一般包括n型半導體及p型半導體，且術語絕緣體或介電質經定義包括導電性不及稱作導體之材料的任何材料。因此，以下實施方式不應具有限制意義。
在一實施例中，使用原子層沈積(ALD)形成鋇鍶鈦氧化物膜。在一實施例中，使用原子層沈積形成摻鉺之鋇鍶鈦氧化物膜。可使用各種形式之ALD，包括自由基增強之原子層沈積。實施例包括用於具有構造為一或多個單層之鋇鍶鈦氧化物膜、摻鉺之鋇鍶鈦氧化物膜或其組合之電容、電晶體、記憶體裝置、光電子裝置及系統的結構，及形成該等結構之方法。使用原子層沈積形成該介電膜可控制材料層之間的過渡。由於該控制，經原子層沈積之鋇鍶鈦氧化物介電膜及經原子層沈積之摻鉺之鋇鍶鈦氧化物介電膜可使其上經組態之材料表面具有經設計之過渡。
亦稱作原子層磊晶(ALE)之ALD為化學氣相沈積(CVD)之變型且亦稱作"交替脈衝CVD"。在ALD中，一次將一種氣態前驅體引入安放於反應室(或反應器)內之基板表面。此氣態前驅體引入係採用各氣態前驅體之脈衝形式。在前驅體氣體之脈衝中，使該前驅體氣體在較短時段內流入特定範圍或區域中。在脈衝之間，可使用氣體淨化反應室，其中該淨化氣可為惰性氣體。在脈衝之間，可將反應室排空。在脈衝之間，可將反應室以氣體淨化且排空。
在化學吸附飽和ALD(CS－ALD)方法中，在第一脈衝輸送期內，基板與飽和化學吸附於基板表面之前驅體發生反應。隨後脈衝輸送淨化氣自反應室移除過量前驅體。
第二脈衝輸送期將另一前驅體引入發生所要膜之生長反應的基板上。在膜生長反應後，自反應室淨化反應副產物及過量前驅體。在前驅體吸附於基板上且於其上彼此積極反應之良好前驅體化學作用下，可在經適當設計之流式反應室中在不到一秒內進行一次ALD循環。通常，前驅體脈衝時間在約0.5秒至約2秒至3秒範圍內。淨化氣之脈衝時間可顯著更長，例如脈衝時間為約5秒至約30秒。
在ALD中，所有反應及淨化期之飽和使生長具有自我限制性。此自我限制式生長產生大範圍之均一性及保形性，此在諸如平坦基板、深溝槽及加工多孔矽及大表面積二氧化矽及氧化鋁粉末的狀況下具有重要應用。原子層沈積藉由控制生長循環數來以直接方式對膜厚度加以控制。
ALD方法中所用之前驅體可為氣態、液態或固態。然而，液態或固態前驅體應具有揮發性。蒸氣壓應足夠高以便達成有效質量輸送。同樣，固態前驅體及某些液態前驅體可能需要在反應室內加熱且經由熱管引至基板。應在低於基板溫度之溫度下達到必需蒸氣壓以避免前驅體在基板上冷凝。儘管在製程期間蒸發速率可能因表面積變化而略有變化，但由於ALD之自我限制式生長機制，可使用蒸氣壓相對低之固態前驅體。
ALD中所用之前驅體具有若干其他特徵。因為前驅體分解可能會破壞表面控制且因此破壞依賴於基板表面上之前驅體反應之ALD方法的優勢，所以前驅體在基板溫度下應具有熱穩定性。若與ALD生長相比分解較為緩慢，則可容許略微分解。
儘管前驅體與表面之間的相互作用以及吸附機制對於不同前驅體而言為不同的，但前驅體應化學吸附於表面上或與其反應。基板表面上之分子應與第二前驅體積極反應以形成所要固體膜。另外，前驅體應不與膜反應引起蝕刻，且前驅體應不溶解於膜中。ALD中高反應性前驅體之使用與習知CVD之前驅體選擇形成對比。
反應之副產物應為氣態以便容易地將其自反應室移除。此外，副產物應不與表面反應或吸附於其上。
在反應序列ALD(RS－ALD)方法中，自我限制製程序列涉及依序表面化學反應。RS－ALD依賴於反應性表面與反應性分子前驅體之間的化學作用。在RS－ALD方法中，將分子前驅體獨立地脈衝輸送至ALD反應室中。基板上之金屬前驅體反應後通常為用於自反應室移除過量前驅體及副產物之惰性氣體脈衝，隨後脈衝輸送製造序列之下一前驅體。
藉由RS－ALD可以化學動力學、每次循環之沈積、組成及厚度可能均相同之等計量序列使膜層化。RS－ALD序列一般每次循環沈積不到一整層。通常，可實現每次RS－ALD循環約0.25至約2.00之沈積或生長速率。
RS－ALD加工由於其逐層沈積技術、使用低溫及溫和氧化製程、不依賴於反應室、生長厚度僅依賴於所進行之循環數及以溶解一或兩個單層來加工多層層合膜之能力而提供避免化學氣相沈積(<20)及物理氣相沈積(<50)中常見之不良界定之成核區的介面連續性，多個基板拓撲之保形性。RS－ALD方法允許對單層之順序加以沈積控制及沈積非晶形膜單層之能力。
在本文中，序列係指基於前驅體與其反應物前驅體之ALD反應的ALD材料形成。金屬氧化物之ALD序列可能涉及金屬及氧。舉例而言，可使用包括Er(thd)3 (thd＝2,2,6,6四甲基－3,5－庚酮)及作為其反應物前驅體之臭氧之序列形成氧化鉺，其中該序列可稱作鉺/氧序列或鉺序列。在形成氧化物或含氧化合物之各種ALD方法中，使用含氧反應物前驅體提供氧。在本文中，含氧且提供待併入所形成之ALD組合物(其可與提供ALD化合物中之其他元素的前驅體一起用於ALD方法中)中之氧的前驅體稱作氧反應物前驅體。對於使用Er(thd)3 及臭氧之ALD方法而言，臭氧為氧反應物前驅體。ALD循環可包括脈衝輸送前驅體、脈衝輸送前驅體之淨化氣、脈衝輸送反應物前驅體及脈衝輸送反應物前驅體之淨化氣。ALD循環可包括脈衝輸送前驅體、將反應物室排空、脈衝輸送反應物前驅體及將反應物室排空。ALD循環可包括脈衝輸送前驅體、脈衝輸送前驅體之淨化氣及將反應物室排空、脈衝輸送反應物前驅體及脈衝輸送反應物前驅體之淨化氣及將反應物室排空。
在形成金屬物質之層時，ALD序列可將反應物前驅體脈衝輸送至已吸附有含金屬物質之基板表面，使得反應物前驅體與含金屬物質反應產生金屬及可在隨後之淨化/排空製程期間移除的氣態副產物。或者，在形成金屬物質之層時，ALD序列可使含有該金屬物質之前驅體與基板表面反應。該金屬形成序列之循環可包括在脈衝輸送含有金屬物質之前驅體後脈衝輸送淨化氣以使金屬沈積。此外，若半導體材料之前驅體適當，則可以與形成金屬層類似之方式實現半導體材料之沈積。
在具有兩種以上元素之材料組合物的ALD形成中，一循環可包括一定數目之序列以提供組合物之元素。舉例而言，用於ALD形成ABOx 組合物之循環可包括依序脈衝輸送第一前驅體/第一前驅體之淨化氣/第一反應物前驅體/第一反應物前驅體之淨化氣/第二前驅體/第二前驅體之淨化氣/第二反應物前驅體/第二反應物前驅體之淨化氣，可將此視為具有兩個序列之循環。在一實施例中，一循環可包括一定數目之元素A序列及不同數目之元素B序列。可能存在使用一種含有元素A及元素B之前驅體來ALD形成ABOx 組合物之狀況，因此將含有AB之前驅體接著將其反應物前驅體脈衝輸送至基板上可包括在基板上形成ABOx 以提供AB/氧序列之反應。AB/氧序列之循環可包括脈衝輸送含有A及B之前驅體、脈衝輸送前驅體之淨化氣、將氧反應物前驅體脈衝輸送至A/B前驅體及脈衝輸送反應物前驅體之淨化氣。可將循環重複若干次以提供所要厚度之組合物。在一實施例中，用於ALD形成鋇鍶鈦氧化物之組合物的循環可包括一定數目之鋇、鍶及鈦序列，可將該循環視為具有多個序列之循環。在一實施例中，用於ALD形成摻鉺之鋇鍶鈦氧化物之組合物的循環可包括在一定數目之鋇、鍶及鈦序列中散布鉺序列。在一實施例中，使用ALD在重複鋇/鍶/鈦序列中使用個別地脈衝輸送至反應室之前驅體氣體在安放於反應室中之基板上形成大體上為鋇鍶鈦氧化物之層。在一實施例中，使用ALD在具有有限數目鉺序列之重複鋇/鍶/鈦序列中使用個別地脈衝輸送至反應室之前驅體氣體在安放於反應室中之基板上形成大體上為摻鉺之鋇鍶鈦氧化物之層。可在經適當設計之反應室中使用固態或液態前驅體。
在一實施例中，可將鋇鍶鈦氧化物層構造為一或多個單層。構造為一或多個單層之鋇鍶鈦氧化物膜之厚度可在一單層至數千埃或更高之範圍內。在一實施例中，可將摻鉺之鋇鍶鈦氧化物層構造為一或多個單層。構造為一或多個單層之摻鉺之鋇鍶鈦氧化物膜之厚度可在一單層至數千埃或更高之範圍內。鋇鍶鈦氧化物膜與摻鉺之鋇鍶鈦氧化物膜均可使用原子層沈積來加工。經原子層沈積之鋇鍶鈦氧化物層、經原子層沈積之摻鉺之鋇鍶鈦氧化物或其組合之實施例的介電常數大於二氧化矽之介電常數。該等介電層與具有相同物理厚度之二氧化矽層相比提供顯著較薄之等效氧化物厚度。就代表性物理厚度而言，等效氧化物厚度teq 使閘極介電質之電學特性(諸如電容)量化。teq 定義為與給定介電質具有相同電容密度(不計漏電流及安全性因素)所需之理論SiO2 層厚度。或者，該等介電層與具有相同等效氧化物厚度之二氧化矽層相比提供顯著較厚之物理厚度。此物理厚度增加有助於降低漏電流。
本文所用之術語鋇鍶鈦氧化物係關於基本上由鋇、鍶、鈦及氧組成之組合物。本文所用之術語摻鉺之鋇鍶鈦氧化物係關於基本上由鉺、鋇、鍶、鈦及氧組成之組合物，其中該形式之組合物具有相對於鋇、鍶及鈦有限量之鉺。可將鋇鍶鈦氧化物構造為可為化學計量、非化學計量或其組合之膜或其他形式。可將摻鉺之鋇鍶鈦氧化物構造為可為近化學計量、非化學計量或其組合之膜或其他形式。在本文中，鋇鍶鈦氧化物組合物可表示為BaSrTiO、BaSrTiOx 、BST或其他等效形式。在本文中，摻鉺之鋇鍶鈦氧化物組合物可表示為摻Er之 BaSrTiO、摻Er之BaSrTiOx 、摻Er之BST、BST：Er或其他等效形式。本文所用之術語鋇氧化物係關於基本上由鋇及氧組成之組合物。本文所用之術語鍶氧化物係關於基本上由鍶及氧組成之組合物。本文所用之術語鈦氧化物係關於基本上由鈦及氧組成之組合物。本文所用之術語鉺氧化物係關於基本上由鉺及氧組成之組合物。表述BaOu 層可用於包括大體上為化學計量、非化學計量或其組合之鋇氧化物層。表述SrOv 、TiOr 及ErOw 可以與BaOu 相同之方式使用。在多個實施例中，鋇鍶鈦氧化物膜可摻有除鋇、鍶、鈦及氧以外之元素或化合物。在多個實施例中，摻鉺之鋇鍶鈦氧化物膜可摻有除鉺、鋇、鍶、鈦及氧以外之元素或化合物。
在使用ALD形成BaSrTiOx 膜或摻Er之BaSrTiOx 膜前，其上待沈積BaSrTiOx 膜或摻Er之BaSrTiOx 膜之表面可經歷預備階段。該表面可為諸如積體電路或光電子裝置之電子裝置的基板表面。在一實施例中，用於形成電晶體之基板可包括矽或含矽材料。在其他實施例中，可使用鍺、砷化鎵、磷化銦、藍寶石上矽基板或其他合適基板。預備製程可包括清潔基板及形成基板之層及區(諸如汲極及源極)，隨後在形成金屬氧化物半導體(MOS)電晶體時形成閘極介電質。或者，視所實施之整個製造方法而定，可在形成介電層之後形成活性區。在一實施例中，清潔基板以提供耗盡其自生氧化物之初始基板。在一實施例中，亦清潔初始基板以提供氫端面。在一實施例中，在ALD加工之前矽基板經歷最終氟化氫(HF)沖洗以提供具有氫端面而無自生二氧化矽層之矽基板。
在即將進行原子層沈積之前進行清潔有助於減少自生氧化物成為基板與使用原子層沈積法形成之BaSrTiO介電質或摻Er之BaSrTiO介電質之間的介面的發生。介面層之材料組成及其特性通常視製程條件及形成介電層之前的基板狀態而定。儘管介面層之存在可有效降低與介電層及其基板有關之介電常數，但諸如自生氧化物介面層、SiO2 介面層或其他組合物介面層之介面層可改良介面密度、固定電荷密度及具有此介面層之裝置的通道遷移率。
所加工之諸如電晶體之電子裝置的區形成之排序可遵循熟習此項技術者熟知之該等裝置製造中一般所進行之典型排序。如半導體製造中通常所進行，在形成介電質之前的加工中可包括對在介電質形成期間待保護之基板區加以遮蔽。在一實施例中，未遮蔽區包括電晶體之主體區；然而熟習此項技術者應理解其他半導體裝置結構可利用此方法。
在多個實施例中，在原子層沈積法中所用之各前驅體脈衝輸送之間，可將淨化氣脈衝輸送至ALD反應室中。在各前驅體脈衝輸送之間，可使用熟習此項技術者已知之真空技術將ALD反應室排空。在各前驅體脈衝輸送之間，可將淨化氣脈衝輸送至ALD反應室中且可將該ALD反應室排空。
在一實施例中，藉由原子層沈積在原子層沈積所形成之鍶鈦氧化物(SrTiOz )層中形成鋇鈦氧化物(BaTiOy )層。可使BaTiOy 層及SrTiOz 層退火形成BaSrTiOx 層。可視所要應用選擇BaTiOy 層及SrTiOz 層之形成順序。在一實施例中，可將由原子層沈積形成之ErOw 層散布於由原子層沈積形成之BaTiOy 層及由原子層沈積形成之SrTiOz 層中。可使ErOw 層、BaTiOy 層及SrTiOz 氧化物層退火形成摻Er之BaSrTiOx 層。可視所要應用選擇ErOw 層、BaTiOy 層及SrTiOz 層之形成順序。
在一實施例中，將含鋇前驅體脈衝輸送至ALD反應室中之基板上從而藉由原子層沈積形成鋇鈦氧化物。可使用多種含鋇前驅體向基板提供鋇。在一實施例中，含鋇前驅體可包括雙(五甲基環戊二烯基)鋇，[Ba(C5 Me5 )2 ，其中Me＝CH3 ]。可將水蒸氣用作使用Ba(C5 Me5 )2 之ALD序列中的氧反應物前驅體。在一實施例中，可將基板溫度保持在約275℃之溫度下。在鈦序列中使用含鈦前驅體且可在鋇序列之後將其脈衝輸送至基板。可使用多種含鈦前驅體向基板提供鈦。在一實施例中，所脈衝輸送之鈦前驅體可為四異丙醇鈦，亦寫作Ti(O i －Pr)4 ，其中Pr＝CH2 CH2 CH3 。在一實施例中，可將基板溫度保持在250℃以下至約325℃範圍內之溫度下。可用於ALD方法中之其他鈦前驅體包括鈦鹵化物(諸如TiCl4 或TiI4 )及Ti(NO3 )4 。在一實施例中，在BaTiOy 膜形成期間，可將基板保持在約275℃之溫度下。在一實施例中，在BaTiOy 膜形成期間，可將基板保持在約250℃至約500℃範圍內之溫度下。個別前驅體之使用不限於上述實施例之溫度範圍內。此外，藉由原子層沈積形成鋇鈦氧化物不限於上述前驅體。在ALD形成BaTiOy 之多個實施例中，不同序列中所用之反應物前驅體可為包括(但不限於)水蒸氣、原子氧、分子氧、臭氧、過氧化氫、水－過氧化氫混合物、醇或氧化亞氮中之一或多者的氧反應物前驅體。此外，序列中個別前驅體之脈衝輸送可使用在給定序列中提供單層在表面上之均一覆蓋的脈衝輸送週期或可使用在給定序列中提供單層在表面上之均一部分覆蓋的脈衝輸送週期。
藉由原子層沈積形成BaTiOy 膜之實施例可包括形成BaTiOy 膜之鋇序列及鈦序列的眾多變更。在一實施例中，在鋇序列之前進行鈦序列。在一實施例中，在鈦序列之前進行鋇序列。在一實施例中，鋇/鈦循環可包一定數目(n)之鋇序列及一定數目(p)之鈦序列。可選擇序列數n及p以設計鈦與鋇之相對量。所形成之BaTiOy 膜之電容率可基於鋇序列與鈦序列之比率而設計。在一實施例中，可與序列數n及p一起選擇ALD序列之有關脈衝輸送週期及時間從而形成經設計之鋇鈦氧化物膜。
由原子層沈積形成之鋇鈦氧化物層的厚度可由對於脈衝輸送週期及所用前驅體固定之生長速率(設定為諸如每循環N nm之值，視鋇/鈦序列循環數而定)決定。確定ALD循環之後，即可確定每循環之生長速率。如熟習此項技術者可瞭解，可在對用於加工供給定應用之鋇鈦氧化物介電膜之ALD系統進行常規起始測試期間確定特定生長速率而無需過度實驗。為達成應用中之所要鋇鈦氧化物層厚度(t)，將ALD方法重複t/N次總循環。在t/N次循環完成後，可能不需要對鋇鈦氧化物層進行進一步ALD加工。在重複若干次ALD循環後，可判斷鋇/鈦循環數是否等於形成所要鋇鈦氧化物層之預定數目。若未完成形成所要厚度之循環總數，則可重複若干次鋇及鈦序列之循環。
在一實施例中，將含鍶前驅體脈衝輸送至ALD反應室中之基板上從而藉由原子層沈積形成鍶鈦氧化物。可使用多種含鍶前驅體向基板提供鍶。在一實施例中，含鍶前驅體可包括雙(三異丙基環戊二烯基)鍶[Sr(C5 －i －Pr3 H2 )，其中Pr＝CH2 CH2 CH3 ]。可將水蒸氣用作使用Sr(C5 －i －Pr3 H2 )之ALD序列中的氧反應物前驅體。在一實施例中，可將基板溫度保持在約275℃之溫度下。在鈦序列中使用含鈦前驅體且可在鋇序列之後將其脈衝輸送至基板。可使用多種含鈦前驅體向基板提供鈦。在一實施例中，所脈衝輸送之鈦前驅體可為四異丙醇鈦，亦寫作Ti(O i －Pr)4 。在一實施例中，在SrTiOz 膜形成期間，可將基板保持在約325℃之溫度下。在一實施例中，可將基板溫度保持在250℃以下至約325℃範圍內之溫度下。可用於ALD方法中之其他鈦前驅體包括鈦鹵化物(諸如TiCl4 或TiI4 )及Ti(NO3 )4 。在一實施例中，在SrTiOz 膜形成期間，可將基板保持在約325℃之溫度下。在一實施例中，在SrTiOz 膜形成期間，可將基板保持在約250℃至約500℃範圍內之溫度下。個別前驅體之使用不限於上述實施例之溫度範圍。此外，藉由原子層沈積形成鍶鈦氧化物不限於上述前驅體。在ALD形成SrTiOz 之多個實施例中，不同序列中所用之反應物前驅體可為包括(但不限於)水蒸氣、原子氧、分子氧、臭氧、過氧化氫、水－過氧化氫混合物、醇或氧化亞氮中之一或多者的氧反應物前驅體。此外，序列中個別前驅體之脈衝輸送可使用在給定序列期間提供單層在表面上之均一覆蓋的脈衝輸送週期或可使用在給定序列期間提供單層在表面上之均一部分覆蓋的脈衝輸送週期。
藉由原子層沈積形成SrTiOz 膜之實施例可包括形成SrTiOz 膜之鍶序列及鈦序列的眾多變更。在一實施例中，在鍶序列之前進行鈦序列。在一實施例中，在鈦序列之前進行鍶序列。在一實施例中，鍶/鈦循環可包括一定數目(m)之鍶序列及一定數目(q)之鈦序列。可選擇序列數m及q以設計鈦與鍶之相對量。所形成之SrTiOy 膜之電容率可基於鍶序列與鈦序列之比率而設計。在一實施例中，可與序列數m及q一起選擇ALD序列之有關脈衝輸送週期及時間從而形成經設計之鍶鈦氧化物膜。
由原子層沈積形成之鍶鈦氧化物層的厚度可由對於脈衝輸送週期及所用前驅體固定之生長速率(設定為諸如每循環M nm之值，視鍶/鈦序列循環數而定)決定。確定ALD循環之後，即可確定每循環之生長速率。如熟習此項技術者可瞭解，可在對用於加工供給定應用之鍶鈦氧化物介電膜之ALD系統進行常規起始測試期間確定特定生長速率而無需過度實驗。為達成應用中之所要鍶鈦氧化物層厚度(d)，將ALD方法重複d/M次總循環。在d/M次循環完成後，可能不需要對鍶鈦氧化物層進行進一步ALD加工。在重複若干次ALD循環後，可判斷鍶/鈦循環數是否等於形成所要鍶鈦氧化物層之預定數目。若未完成形成所要厚度之循環總數，則可重複若干次鍶及鈦序列之循環。
可將經原子層沈積之SrTiOz 層及經原子層沈積之BaTiOy 層退火形成BaSrTiOx 層。在一實施例中，可將ALD BaTiOy 與ALD SrTiOz 之交替層退火形成BaSrTiOx 層。可使用若干不同準則設計BaSrTiOx 層以使其具有選定量之鋇、鍶及鈦。該準則可包括相對於BaTiOy 層數選擇SrTiOz 層數，且相對於BaTiOy 層厚度選擇SrTiOz 層厚度。可使用SrTiOz 層厚度之眾多變更及BaTiOy 層厚度之眾多變更來形成BaSrTiOx 層。可調節各SrTiOz 層內Sr與Ti之比率。可調節各BaTiOy 層內Ba與Ti之比率。使用該等眾多準則可將BaSrTiOx 層設計為具有所要介電常數。在一實施例中，BaSrTiOx 層之電容率可在165至180範圍內。在多個實施例中，使用原子層沈積形成之BaSrTiOx 層可摻有適當元素。可藉由若干不同方法(包括離子植入)實現摻雜。在一實施例中，BaSrTiOx 層摻有鉺。
或者，在一實施例中，可藉由重複包括原子層沈積BaOu 、SrOv 、TiOr 層，接著退火之方法來使BaSrTiO膜生長至所要厚度。在一實施例中，可根據多個實施例形成基本厚度，以便可藉由形成一定數目之具有基本厚度之層來形成預定厚度之BaSrTiO膜。如熟習此項技術者可瞭解，基本厚度之確定視應用而定且可在起始加工期間確定而無需過度實驗。可藉由調節所形成之個別BaOx 、SrOy 、TiOz 層的相對厚度來控制BaSrTiO膜中鋇、鍶及鈦之相對量。此外，BaSrTiO膜中鋇、鍶及鈦之相對量可藉由形成作為具有不同基本厚度之多層的BaSrTiO層及藉由調節各基本層中所形成之個別BaOu 、SrOv 、TiOr 層之相對厚度來控制。在多個實施例中，使用原子層沈積形成之BaSrTiO層可摻有適當元素。可藉由若干不同方法(包括離子植入)實現摻雜。在一實施例中，BaSrTiO層摻有鉺。
在一替代實施例中，形成BaSrTiO之ALD循環可包括按鋇、鍶及鈦之順序將含金屬前驅體進行排序，其中獲得單層在基板表面上之部分覆蓋用以脈衝輸送含金屬之前驅體。藉由原子層沈積形成鋇鍶鈦氧化物膜之實施例可包括形成鋇鍶鈦氧化物膜之鋇序列、鍶序列及鈦序列的眾多變更。在一實施例中，鋇/鍶/鈦循環可包括一定數目(nx)之鋇序列、一定數目(ny)之鍶序列及一定數目(nz)之鈦序列數，其中與各金屬有關之反應物前驅體應用於有關序列。可選擇序列數nx、ny及nz以設計鋇、鍶及鈦之相對量。在一實施例中，選擇序列數nx、ny及nz以形成富含鋇之鋇鍶鈦氧化物。或者，選擇序列數nx、ny及nz以形成富含鍶之鋇鍶鈦氧化物。此外，選擇序列數nx、ny及nz以形成富含鈦之鋇鍶鈦氧化物。
在重複選定次數之ALD循環後，可判斷鋇/鍶/鈦循環數是否等於形成所要鋇鍶鈦氧化物層之預定數目。若未完成形成所要厚度之總循環數，則可重複若干次鋇、鍶及鈦序列之循環。由原子層沈積形成之鋇鍶鈦氧化物層的厚度可由對於脈衝輸送週期及所用前驅體固定之生長速率(視鋇/鍶/鈦序列之循環數而定)決定。視BaSrTiO膜之ALD形成所用之前驅體而定，該方法可在ALD窗口中進行，ALD窗口為生長速率大體上恆定之溫度範圍。若該ALD窗口不可得，則ALD方法可在該方法中各ALD序列之相同溫度設定下進行。在與原子層沈積有關之相對低溫下加工之鋇鍶鈦氧化物層可提供一非晶形層。
在一實施例中，可藉由原子層沈積形成散布於由原子層沈積形成之鋇鈦氧化物層及由原子層沈積形成之鍶鈦氧化物層中之鉺氧化物層來構造摻鉺之BaSrTiOx 層。在一實施例中，將含鉺前驅體脈衝輸送至ALD反應室中之基板上從而藉由原子層沈積形成鉺氧化物。可使用多種含鉺前驅體向基板提供鉺。在一實施例中，含鉺前驅體可包括Er(thd)3 。在使用Er(thd)3 之ALD序列中可將臭氧用作氧反應物前驅體。在一實施例中，在ErOw 膜形成期間，可將基板保持在約250℃至約450℃範圍內之溫度下。鉺氧化物膜在325℃以下可能為非晶形的。可使多晶鉺氧化物膜在較高溫度下生長，其中在325℃以上之沈積溫度下方位自(4 0 0)變化至(2 2 2)。個別前驅體之使用不限於上述實施例之溫度範圍內。在使用不同含鉺前驅體ALD形成ErOw 之多個實施例中，不同序列中所用之反應物前驅體可為包括(但不限於)水蒸氣、原子氧、分子氧、臭氧、過氧化氫、水－過氧化氫混合物、醇或氧化亞氮中之一或多者的氧反應物前驅體。在多個實施例中，藉由原子層沈積形成鉺氧化物不限於上述前驅體且個別含鉺前驅體之使用不限於上述實例實施例之溫度範圍。此外，序列中個別前驅體之脈衝輸送可使用在鉺序列期間提供單層在表面上之均一覆蓋的脈衝輸送週期或可使用在鉺序列期間提供單層在表面上之均一部分覆蓋的脈衝輸送週期。
在一實施例中，可藉由原子層沈積形成一定數目之ErOw 層、一定數目之BaTiOy 層及一定數目之SrTiOz 層，其中選擇顯著小於BaTiOy 層數及SrTiOz 層數之ErOw 層數。可使ErOw 層、BaTiOy 層及SrTiOz 層退火形成摻鉺之BaSrTiOx 。在一實施例中，使散布有ALD Er2 O3 層之ALD SrTiO3 與ALD BaTiO3 之交替層的層合結構退火產生摻Er之Ba0.7 Sr0.3 TiO3 膜。在一實施例中，選擇ErOw 層數使得ErOw 層、BaTiOy 層及SrTiOz 層之總數中的ErOw 百分比小於或等於10%。在一實施例中，選擇ErOw 層數使得所形成之摻Er之BaSrTiOx 中之鉺原子濃度小於或等於10%。在一實施例中，可在退火前將該等數目之ErOw 層散布於預定排列之該等數目之ErOw 層中。在一實施例中，可在退火前將該等數目之ErOw 層散布於隨機順序之該等數目之BaTiOy 層及SrTiOz 層中。在多個實施例中，可變更BaTiOy 、SrTiOz 及ErOw 層之形成順序。可在氮氣環境中進行退火。在一實施例中，可在具有少量氧之氮氣環境中進行退火。然而，退火不限於該等環境條件。可在約600℃或更高之溫度下進行退火。可進行退火歷時約60分鐘或更短時間。在一實施例中，進行退火歷時不到1分鐘。可在其他溫度下及以其他退火時間進行退火。可基於摻Er之BaSrTiOx 層之所要結構選擇退火溫度及退火時段。
在一實施例中，藉由原子層沈積使BaTiOy 層、SrTiOz 層及ErOw 層各自生長至一定厚度，使得該等層在適當溫度下之退火基本上將該等層轉化為一摻Er之BaSrTiOx 層。在一實施例中，可藉由重複包括原子層沈積BaTiOy 、SrTiOz 層及ErOw 層隨後退火之方法來使摻Er之BaSrTiOx 膜生長至所要厚度。在一實施例中，可根據多個實施例形成基本厚度，以便可藉由形成一定數目之具有基本厚度之層來形成預定厚度之摻Er之BaSrTiOx 膜。如熟習此項技術者可瞭解，基本厚度之確定視應用而定且可在起始加工期間確定而無需過度實驗。可藉由調節所形成之個別氧化物層的相對厚度來控制摻Er之BaSrTiOx 膜中之鉺、鋇、鍶、鈦及氧的相對量。此外，可藉由形成作為具有不同基本厚度之多層的摻Er之BaSrTiOx 層及藉由調節各基本層中所形成之個別氧化物層的相對厚度隨後退火來控制摻Er之BaSrTiOx 膜中之鉺、鋇、鍶、鈦及氧的相對量。如熟習此項技術者可瞭解，可在對用於給定應用之ALD系統進行常規起始測試期間確定經設計之摻Er之BaSrTiOx 膜的特定有效生長速率而無需過度實驗。
在一替代實施例中，形成摻Er之BaSrTiO的ALD循環可包括鋇、鍶及鈦之含金屬前驅體之重複排序，其中以鉺序列取代主序列中之一或多者或向ALD循環之主序列中添加一或多個鉺序列，其中獲得單層在基板表面上之部分覆蓋用於脈衝輸送含金屬之前驅體。藉由原子層沈積形成摻鉺之鋇鍶鈦氧化物膜之實施例可包括散布於ALD循環之主序列鋇序列、鍶序列及鈦序列中的鉺序列的眾多變更。在一實施例中，鋇/鍶/鈦/鉺循環可包括一定數目(mx)之鋇序列、一定數目(my)之鍶序列、一定數目(mz)之鈦序列及一定數目(mr)之鉺序列，其中與各金屬有關之反應物前驅體應用於有關序列。可選擇序列數mx、my、mz及mr以設計鋇、鍶、鈦及鉺之相對量。在一實施例中，選擇序列數mx、my、mz及mr以形成富含鋇之摻鉺之鋇鍶鈦氧化物。或者，選擇序列數mx、my、mz及mr以形成富含鍶之摻鉺之鋇鍶鈦氧化物。此外，選擇序列數mx、my、mz及mr以形成富含鈦之摻鉺之鋇鍶鈦氧化物。可選擇序列數mx、my、mz及mr以限制摻入BaSrTiOx 膜中之鉺的量。
在重複選定次數之ALD循環後，可判斷鋇/鍶/鈦/鉺循環數是否等於形成所要摻鉺之鋇鍶鈦氧化物層之預定數目。若未完成形成所要厚度之循環總數，則可重複若干次鋇、鍶、鈦及鉺序列之循環。由原子層沈積形成之摻鉺之鋇鍶鈦氧化物層的厚度可由對脈衝輸送週期及所用前驅體固定之生長速率(設定為諸如每循環P nm之值，視鋇/鍶/鈦/鉺序列循環數而定)決定。視ALD形成BaSrTiO膜所用之前驅體而定，該方法可在ALD窗口中進行。若該ALD窗口不可得，則ALD方法可在該方法中各ALD序列之相同溫度設定下進行。為達成應用中之所要摻鉺之鋇鍶鈦氧化物層厚度(l)，將ALD方法重複l/P次總循環。在完成l/P次循環後，無需對摻鉺之鋇鍶鈦氧化物層進行進一步ALD加工。在與原子層沈積有關之相對低溫下加工之摻鉺之鋇鍶鈦氧化物層可提供一非晶形層。
在多個實施例中，可將氮氣用作形成BaOu 、SrOv 、TiOr 、BaTiOy 、SrTiOz 、ErOw 及BaSrTiOx 之一或多個序列之淨化氣及載氣。或者，可將氫氣、氬氣或其他惰性氣體用作淨化氣。可由淨化氣移除過量前驅體氣體及反應副產物。可藉由使用各種真空技術排空反應室來移除過量前驅體氣體及反應副產物。可由淨化氣及藉由排空反應室來移除過量前驅體氣體及反應副產物。
個別組份或層之原子層沈積允許個別控制脈衝輸送至反應室中之各前驅體。因此，將各前驅體脈衝輸送至反應室歷時預定時期，其中各前驅體之預定時期可單獨設定。此外對各種ALD形成而言，可在單獨環境條件下將各前驅體脈衝輸送至反應室中。對於各前驅體之脈衝輸送而言，可獨立地將基板維持於選定溫度下且將反應室維持於選定壓力下。無論前驅體為單一前驅體或前驅體混合物均可維持適當溫度及壓力。
在根據任何實施例形成BaSrTiO膜之前或之後，可形成諸如氮化物層、介電金屬矽酸鹽、絕緣金屬氧化物或其組合之其他介電層作為介電層或介電堆疊之一部分。該或該等其他介電材料層可提供為化學計量形式、非化學計量形式或其組合。視應用而定，含有BaSrTiOx 膜之介電堆疊可包括二氧化矽層。在一實施例中，可將介電層形成為奈米合層。或者，可將介電層大體上形成為鋇鍶鈦氧化物膜或摻鉺之鋇鍶鈦氧化物膜。
在多個實施例中，控制介電層與安置該介電層之基板之間的介面結構以限制自生氧化物之納入。諸如矽上之二氧化矽層之自生氧化物會降低介電層之有效介電常數。介面層之材料組成及特性可視製程條件及形成介電層之前的基板狀態而定。儘管介面層之存在可有效降低與介電層及其基板有關之介電常數，但諸如二氧化矽介面層或其他材料介面層之介面層可改良介面密度、固定電荷密度及具有此介面層之裝置的通道遷移率。
圖1展示一電晶體100之實施例，該電晶體具有一含有一BaSrTiOx 膜之介電層140。該BaSrTiOx 膜可摻有鉺。電晶體100可在一以矽為主之基板110中包括一源極區120及一汲極區130，其中源極區120及汲極區130係由一主體區132隔開。主體區132界定一具有一通道長度134之通道。閘極介電質140可安置於基板110上，其中閘極介電質140形成為含有BaSrTiOx 之介電層。閘極介電質140可實現為大體上由BaSrTiOx 形成之介電層。閘極介電質140可構造為含有至少一個BaSrTiOx 膜及一或多個除鋇鍶鈦氧化物膜外之絕緣材料層之多個介電層(亦即介電堆疊)。BaSrTiOx 膜可構造為一或多個單層。可使用原子層沈積形成BaSrTiOx 膜或摻Er之BaSrTiOx 膜之實施例。閘極150可形成於閘極介電質140上方且與其接觸。
可在主體區132與閘極介電質140之間形成一介面層133。在一實施例中，介面層133可限於相較於閘極介電質140相對小之厚度或限於顯著小於閘極介電質140厚度之厚度以達成有效消除之目的。可使用熟習此項技術者已知之標準方法形成基板及源極區及汲極區。此外，可使用熟習此項技術者已知之製造方法進行形成電晶體之方法的各種元素之排序。在一實施例中，閘極介電質140可實現為矽互補金屬氧化物半導體(CMOS)電晶體中之閘極絕緣體。含有鋇鍶鈦氧化物膜、摻鉺之鋇鍶鈦氧化物膜或其組合之閘極介電質之使用不限於以矽為主之基板，而可與多種半導體基板一起使用。
圖2展示一浮動閘極電晶體200之實施例，該電晶體具有一含有BaSrTiOx 膜之介電層。該BaSrTiOx 膜可摻有鉺。BaSrTiOx 膜可構造為一或多個單層。可使用原子層沈積技術形成BaSrTiOx 膜或摻Er之BaSrTiOx 膜。電晶體200可包括一以矽為主之基板210，其中源極220與汲極230由主體區232隔開。介於源極220與汲極230之間的主體區232界定一具有一通道長度234之通道區。位於主體區232上方者為一堆疊255，該堆疊包括一閘極介電質240、一浮動閘極252、一浮動閘極介電質242及一控制閘極250。可在主體區232與閘極介電質240之間形成一介面層233。在一實施例中，介面層233可限於相較於閘極介電質240相對小之厚度或限於顯著小於閘極介電質240厚度之厚度以達成有效消除之目的。
在一實施例中，閘極介電質240包括一含有一經原子層沈積之BaSrTiOx 膜的介電質。閘極介電質240可實現為大體上由BaSrTiOx 形成之介電層。閘極介電質240可為一含有至少一個BaSrTiOx 膜或摻Er之BaSrTiOx 膜及一或多個其他絕緣材料層之介電堆疊。在一實施例中，浮動閘極252可形成於閘極介電質240上方且與其接觸。
在一實施例中，浮動閘極介電質242包括一含有一BaSrTiOx 膜的介電質。該BaSrTiOx 膜可摻有鉺。BaSrTiOx 膜可構造為一或多個單層。在一實施例中，可使用原子層沈積技術形成BaSrTiOx 膜或摻Er之BaSrTiOx 膜。浮動閘極介電質242可實現為大體上由BaSrTiOx 形成之介電層。浮動閘極介電質242可為一含有至少一個BaSrTiOx 膜及一或多個其他絕緣材料層之介電堆疊。在一實施例中，控制閘極250可形成於浮動閘極介電質242上方且與其接觸。
或者，閘極介電質240與浮動閘極介電質242兩者均可形成為含有一構造為一或多個單層之BaSrTiOx 膜的介電層。該BaSrTiOx 膜可摻有鉺。閘極介電質240及浮動閘極介電質242可藉由與本文中描述之彼等實施例類似之實施例實現，電晶體200之其餘元件使用熟習此項技術者已知之方法形成。在一實施例中，在快閃記憶體裝置中，閘極介電質240形成一穿隧閘極絕緣體且浮動閘極介電質242形成一閘極間絕緣體，其中閘極介電質240及浮動閘極介電質242可包括構造為一或多個單層的一摻鉺之鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合。該等結構不限於以矽為主之基板，而可與多種半導體基板一起使用。
構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合之實施例亦可應用於多種積體電路、記憶體裝置及電子系統中之電容。在圖3所說明之電容300之實施例中，一種方法包括形成一第一導電層310、在第一導電層310上形成一含有一構造為一或多個單層之鋇鍶鈦氧化物膜之介電層320，及在介電層320上形成一第二導電層330。該BaSrTiOx 膜可摻有鉺。介電層320可為一含有至少一個BaSrTiOx 膜或摻Er之BaSrTiOx 膜及一或多個其他絕緣材料層之介電堆疊。可在第一導電層310與介電層320之間形成一介面層315。在一實施例中，介面層315可限於相較於介電層320相對小之厚度或限於顯著小於介電層320厚度之厚度以達成有效消除之目的。
構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合之實施例可包括(但不限於)DRAM中之電容及類比、射頻(RF)及混合信號積體電路中之電容。混合信號積體電路為可以數位及類比信號操作之積體電路。
圖4描繪一介電結構400之實施例，該介電結構具有多個介電層405－1、405－2、...405－N，其中至少一層為鋇鍶鈦氧化物層。該BaSrTiOx 膜可摻有鉺。層410及420可提供與介電層405－1、405－2、...405－N接觸之構件。層410及420可為形成一電容之電極。層410可為電晶體之主體區，而層420為閘極。層410可為浮動閘極電極，而層420為控制閘極。
在一實施例中，介電結構400包括一或多個層405－1、405－2...405－N作為除一BaSrTiO層以外之介電層，其中至少一層為BaSrTiO層。BaSrTiOx 膜可摻有鉺。介電層405－1、405－2...405－N可包括一絕緣金屬氧化物層。介電層405－1、405－2、...405－N可包括一絕緣氮化物層。介電層405－1、405－2、...405－N可包括一絕緣氮氧化物層。介電層405－1、405－2、...405－N可包括一氮化矽層。介電層405－1、405－2、...405－N可包括一絕緣矽酸鹽層。介電層405－1、405－2、...405－N可包括一二氧化矽層。
含有構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合的多個實施例可藉由為裝置提供減少之漏電流來提供增強之裝置效能。可藉由形成與其他金屬氧化物、不含金屬之介電層或其組合呈奈米合層結構的一或多個鋇鍶鈦氧化物層來獲得該等漏電流特徵改良。一或多個BaSrTiOx 層可摻有鉺。自奈米合層之一層至奈米合層之另一層的轉變破壞奈米合層堆疊中之有序結構之趨勢。術語"奈米合層"意謂一具有呈一層化堆疊形式之兩種或兩種以上材料之超薄層複合膜。通常，奈米合層中之各層的厚度為奈米範圍內之數量級。此外，奈米合層之每一個別材料層之厚度可低至該材料之單層之厚度或高達20奈米。
在一實施例中，介電結構400可構造為一包括一構造為一或多個單層之BaSrTiOx 膜的奈米合層結構400。該BaSrTiOx 膜可摻有鉺。奈米合層結構400包括複數個層405－1、405－2至405－N，其中至少一層含有一構造為一或多個單層之BaSrTiOx 膜。其他層可為絕緣氮化物、絕緣氮氧化物及諸如絕緣金屬氧化物之其他介電材料。層之排序視應用而定。與奈米合層結構400有關之有效介電常數可歸於串聯之N個電容，其中各電容之厚度係由相應層之厚度及組成界定。藉由選擇各層之各厚度及組成，可將奈米合層結構設計為具有預定介電常數。諸如奈米合層結構400之結構的實施例可用作非揮發性唯讀記憶體(NROM)快閃記憶體裝置以及其他積體電路中之奈米合層介電質。在一實施例中，奈米合層結構400之層係用於儲存NROM裝置中之電荷。NROM裝置中之奈米合層結構400之電荷儲存層可為二氧化矽層。
摻稀土之材料在基於該等材料之發光特性的光電子裝置及顯示器中具有多種應用。摻鉺氧化物之應用可針對其在1.54 μm下之特徵發光的使用。1.54 μm波長亦對應於以二氧化矽為主之纖維中的最小損失。此外，裝置可利用藍色、綠色及紅色光譜區中之Er＋3 躍遷。儘管主基質影響光致發光之相對強度、化學穩定性及對操作環境之敏感性，但摻鉺材料之躍遷能與其主基質及環境溫度相對獨立。就典型硫化物發光磷光體而言，氧化物膜磷光體提供大氣穩定性、抗腐蝕特性及在外加電壓下減少之降級。在多個實施例中，可在光電子裝置中使用ALD摻Er之BaSrTiOx 替代發光磷光體。可使用原子層沈積將Er＋3 離子併入鋇鍶鈦中以形成擴充溶液。可將ALD摻Er之Ba0.7 Sr0.3 TiO3 膜用於電致發光裝置(諸如顯示器及平板顯示器)中，且替代光電子裝置中之發光磷光體。
圖5說明一具有一摻鉺之鋇鍶鈦氧化物膜520之平板顯示器500之實施例的圖示。平板顯示器500可包括由一介電層530與一透明導電氧化物(TCO)層510隔開且由一介電層540與一導電層550隔開之BST：Er膜520。導電層550可為一金屬層。TCO層510及導電層550經組態以接觸適當電壓源，該電壓源可在TCO層510與導電層550之間施加電壓V外加 。可使用各種類型或組態之電壓源提供V外加 。可使用用於具有摻鉺之鋇鍶鈦氧化物膜之平板顯示器或其他顯示器的其他組態。
圖6描繪一具有一電光區620之光電子設備600之實施例之圖示，電光區620包括一ALD BST膜、一ALD BST：Er膜或其組合。在一實施例中，光電子設備600包括一基板605、一底部包覆層610、一頂部包覆層630及介於底部包覆層610與頂部包覆層630之間的電光材料層620。電光材料層620為用於傳播光及/或改變光傳播之光學層。基板605可為矽基板、矽－鍺基板、玻璃基板、GaAs基板、InP基板或其他III－V組合物之基板。基板605不限於該等材料。基板605可經組態以與包覆層610組合。包覆材料可包括二氧化矽或其他適當介電材料。可提供電極以調節光電子設備600從而利用電光材料620之光學有關特性。可將電極連接至安置於電光材料620頂部及底部之TCO層。亦可以不干擾光電子設備600之光學操作的其他組態連接該等電極。可基於應用之特徵(諸如所關注之波長)選擇基板605、包覆層610、包覆層630及電光材料層620所選用之材料。可將光電子設備600構造為積體光學裝置。光電子設備600可組態於多種裝置及系統中。
電晶體、電容、顯示器、波導結構及其他電子及光電子裝置可包括含有一構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜、或其組合之層的介電膜。可藉由原子層沈積形成摻鉺之鋇鍶鈦氧化物層。可將含有一鋇鍶鈦氧化物層、一摻鉺之鋇鍶鈦氧化物層或其組合之介電膜建構於記憶體裝置及包括資訊處理裝置之電子系統中。可構造鋇鍶鈦氧化物層以在電子裝置中提供高電容率及低漏電流。此外，電子裝置及光電子設備之實施例可實現為積體電路。資訊處理裝置之實施例可包括無線系統、電信系統及電腦。
圖7說明一具有一或多個裝置之電子系統700之方塊圖，該(等)裝置具有一包括構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合之介電結構。該BaSrTiOx 層之厚度可在一單層至數千埃或更高之範圍內，且其可使用原子層沈積加工。電子系統700包括一控制器705、一匯流排715及一電子裝置725，其中匯流排715在控制器705與電子裝置725之間提供導電性。電子裝置725可為一光電子裝置。在多個實施例中，控制器705可包括一BaSrTiOx 膜之實施例。該BaSrTiOx 膜可摻有鉺。在多個實施例中，電子裝置725可包括一BaSrTiOx 膜之實施例。該BaSrTiOx 膜可摻有鉺。在多個實施例中，控制器705及電子裝置725可包括一BaSrTiOx 膜之實施例。該BaSrTiOx 膜可摻有鉺。電子系統700可包括(但不限於)光纖系統、電－光系統及資訊處理系統(諸如無線系統、電信系統及電腦)。
圖8描繪一具有一或多個裝置之系統800之實施例的示意圖，該(等)裝置含有構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合。系統800亦包括一控制器805、一記憶體825、一電子設備835及一匯流排815，其中匯流排815在控制器805與電子設備835之間且在控制器805與記憶體825之間提供導電性。匯流排815可包括各自獨立地經組態之一位址匯流排、一資料匯流排及一控制匯流排。或者，匯流排815可使用通用導線提供位址、資料或控制中之一或多者，其用途受控制器805調節。在一實施例中，設備835可為以與記憶體825類似之方式組態之額外記憶體。在一實施例中，系統800可包括與匯流排815耦合之額外周邊裝置845。周邊裝置845可包括顯示器、額外儲存記憶體或可與控制器805結合操作之其他控制裝置。或者，周邊裝置845可包括顯示器、額外儲存記憶體或可與記憶體825或控制器805及記憶體825結合操作之其他控制裝置。在一實施例中，控制器805為處理器。控制器805、記憶體825、匯流排815、設備835或周邊裝置845中之一或多者可包括一具有構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合之介電層的實施例。該BaSrTiOx 結構之厚度可在一單層至數千埃或更高之範圍內，且其可使用原子層沈積加工。
記憶體825可實現為一含有構造為一或多個單層之一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合之記憶體裝置。可在記憶體陣列之記憶體單元中形成BaSrTiOx 結構。可在記憶體陣列之記憶體單元中的電容中形成BaSrTiOx 結構。可在記憶體陣列之記憶體單元中的電晶體中形成BaSrTiOx 結構。應瞭解實施例可等效應用於任何大小及類型之記憶體電路且不欲限於特定類型之記憶體裝置。記憶體類型包括DRAM、SRAM(靜態隨機存取記憶體)或快閃記憶體。此外，DRAM可為通常稱作SGRAM(同步圖形隨機存取記憶體)、SDRAM(同步動態隨機存取記憶體)、SDRAM II及DDR SDRAM(雙倍資料速率SDRAM)之同步DRAM以及其他新興DRAM技術。系統800可包括(但不限於)光纖系統、電－光系統及資訊處理系統(包括無線裝置、無線系統及電腦)。
儘管本文已說明及描述特定實施例，但一般熟習此項技術者應瞭解經計算以達成相同目的之任何配置可取代所展示之特定實施例。應瞭解上文所述意欲為說明性而非限制性的，且本文所採用之措辭或術語係用於說明而非限制之目的。在研究上文描述後，上述實施例與其他實施例之組合對熟習此項技術者而言為顯而易見的。
100．．．電晶體
110．．．基板
120．．．源極區
130．．．汲極區
132．．．主體區
133．．．介面層
134．．．通道長度
140．．．介電層/閘極介電質
150．．．閘極
200．．．浮動閘極電晶體/電晶體
210．．．基板
220．．．源極
230．．．汲極
232．．．主體區
233．．．介面層
234．．．通道長度
240．．．閘極介電質
242．．．浮動閘極介電質
250．．．控制閘極
252．．．浮動閘極
255．．．堆疊
300．．．電容
310．．．第一導電層
315．．．介面層
320．．．介電層
330．．．第二導電層
400．．．介電結構/奈米合層結構
405－1、405－2、......、405－N．．．介電層
410．．．層
420．．．層
500．．．平板顯示器
510．．．透明導電氧化物層/TCO層
520．．．摻鉺之鋇鍶鈦氧化物膜/BST：Er膜
530．．．介電層
540．．．介電層
550．．．導電層
600．．．光電子設備
605．．．基板
610．．．底部包覆層/包覆層
620．．．電光材料層/電光區/電光材料
630．．．頂部包覆層/包覆層
700．．．電子系統
705．．．控制器
715．．．匯流排
725．．．電子裝置
800．．．系統
805．．．控制器
815．．．匯流排
825．．．記憶體
835．．．電子設備/設備
845．．．周邊裝置/裝置
圖1展示一具有一介電層之電晶體實施例的圖示，其中該介電層含有一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合。
圖2展示一具有一介電層之浮動閘極電晶體實施例的圖示，其中該介電層含有一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合。
圖3展示一具有一介電層之電容實施例的圖示，其中該介電層含有一鋇鍶鈦氧化物膜、一摻鉺之鋇鍶鈦氧化物膜或其組合。
圖4描繪一具有多個層之介電層實施例之圖示，該等層包括一鋇鍶鈦氧化物層、一摻鉺之鋇鍶鈦氧化物層或其組合。
圖5說明一具有一摻鉺之鋇鍶鈦氧化物膜的平板顯示器實施例之圖示。
圖6描繪一具有一電光區之光電子設備實施例之圖示，該電光區包括一鋇鍶鈦氧化物層、一摻鉺之鋇鍶鈦氧化物層或其組合。
圖7描繪一與一電子裝置耦合之控制器實施例之簡圖的圖示，該電子裝置具有一含有一鋇鍶鈦氧化物層、一摻鉺之鋇鍶鈦氧化物層或其組合之介電層。
圖8說明一具有裝置之電子系統實施例之方塊圖的圖示，該等裝置具有一含有一鋇鍶鈦氧化物層、一摻鉺之鋇鍶鈦氧化物層或其組合之介電膜。
100．．．電晶體
110．．．基板
120．．．源極區
130．．．汲極區
132．．．主體區
133．．．介面層
134．．．通道長度
140．．．介電層/閘極介電質
150．．．閘極

Claims (46)

  1. 一種形成鋇鍶鈦氧化物層的方法，該方法包含：藉由原子層沈積形成一鍶鈦氧化物層；藉由原子層沈積形成一鋇鈦氧化物層；及在一經選擇的氣體環境中以一經選擇的退火溫度及時間期間退火，使得該等個別鍶鈦氧化物層及鋇鈦氧化物層一起轉換以形成一鋇鍶鈦氧化物層。
  2. 如請求項1之方法，其中該方法包括以鉺摻雜該鋇鍶鈦氧化物。
  3. 如請求項1之方法，其中該方法包括在退火前形成鍶鈦氧化物與鋇鈦氧化物之交替層。
  4. 如請求項1之方法，其中該方法包括形成一非晶形鋇鍶鈦氧化物層。
  5. 如請求項1之方法，其中該方法包括形成一Ba0.7 Sr0.3 TiO3 層。
  6. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層乃包括形成該鋇鍶鈦氧化物層作為積體電路中一電容內之電容介電質。
  7. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為一記憶體中之介電層。
  8. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為一電晶體中之閘極絕緣體。
  9. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為一以矽為主之互補金屬氧化物 半導體電晶體中之閘極絕緣體。
  10. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為一快閃記憶體裝置中之穿隧閘極絕緣體。
  11. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為一快閘記憶體裝置中之閘極間絕緣體。
  12. 如請求項1之方法，其中形成該鋇鍶鈦氧化物層包括形成該鋇鍶鈦氧化物層作為NROM快閃記憶體之一奈米合層中之介電區。
  13. 如請求項1之方法，其中該方法包括在形成該鋇鍶鈦氧化物層期間以鉺摻雜該鋇鍶鈦氧化物層以形成一電致發光裝置中之發光元件。
  14. 如請求項1之方法，其中該方法包括在形成該鋇鍶鈦氧化物層期間以鉺摻雜該鋇鍶鈦氧化物層作為一光電子裝置中之膜。
  15. 如請求項1之方法，其中該在該經選擇的氣體環境中退火包括在沒有氧氣之一氮氣環境中退火，以將該等個別鍶鈦氧化物層及鋇鈦氧化物層轉換成該鋇鍶鈦氧化物層。
  16. 一種形成摻鉺之鋇鍶鈦氧化物層的方法，該方法包含：藉由原子層沈積形成一鍶鈦氧化物層；藉由原子層沈積形成一鋇鈦氧化物層；藉由原子層沈積形成一鉺氧化物層，該鉺氧化物層介 於該鍶鈦氧化物層與該鋇鈦氧化物層之間；及在一經選擇的氣體環境中以一經選擇的退火溫度及時間期間退火，使得該等個別鍶鈦氧化物層、鋇鈦氧化物層及鉺氧化物層一起轉換形成一摻鉺之鋇鍶鈦氧化物層。
  17. 如請求項16之方法，其中該方法包括形成一非晶形摻Er之鋇鍶鈦氧化物層。
  18. 如請求項16之方法，其中該方法包括形成組成因該鉺摻雜而偏離Ba0.7 Sr0.3 TiO3 之該摻鉺之鋇鍶鈦氧化物。
  19. 如請求項16之方法，其中形成該摻鉺之鋇鍶鈦氧化物層包括形成該摻鉺之鋇鍶鈦氧化物層作為一電晶體中之閘極絕緣體。
  20. 如請求項16之方法，其中形成該摻鉺之鋇鍶鈦氧化物層包括於一記憶體中形成該摻鉺之鋇鍶鈦氧化物層。
  21. 如請求項16之方法，其中該方法包括形成該摻鉺之鋇鍶鈦氧化物層作為一電致發光顯示器中之膜。
  22. 如請求項16之方法，其中該方法包括形成該摻鉺之鋇鍶鈦氧化物層作為一平板顯示器中之膜。
  23. 如請求項16之方法，其中該方法包括形成該摻鉺之鋇鍶鈦氧化物層作為一光電子裝置中之膜。
  24. 一種在陣列之記憶體單元中形成介電層的方法，該方法包含：形成一記憶體單元陣列；及在該陣列之一記憶體單元中形成一介電層，其中形成 該介電層包括由以下步驟形成一鋇鍶鈦氧化物膜：藉由原子層沈積形成一鍶鈦氧化物層；藉由原子層沈積形成一鋇鈦氧化物層；及在一經選擇的氣體環境中以一經選擇的退火溫度及時間期間退火，使得該等個別鍶鈦氧化物層及鋇鈦氧化物層一起轉換形成鋇鍶鈦氧化物。
  25. 如請求項24之方法，其中形成一介電層包括形成大體上為該鋇鍶鈦氧化物膜之該介電層。
  26. 如請求項24之方法，其中形成該介電層包括形成該介電層作為一動態隨機存取記憶體之一電容中之一電容介電質。
  27. 如請求項24之方法，其中形成該介電層包括形成該介電層作為一快閃記憶體裝置中之穿隧閘極絕緣體。
  28. 如請求項24之方法，其中形成該介電層包括形成該介電層作為一快閃記憶體裝置中之閘極間絕緣體。
  29. 如請求項24之方法，其中形成該介電層包括形成該介電層作為一介電區以儲存一NROM快閃記憶體中之電荷。
  30. 一種在陣列之記憶體單元中形成介電層的方法，該方法包含：形成一單元陣列；在該陣列之一單元中形成一介電層，其中形成該介電層包括由以下步驟形成一摻鉺之鋇鍶鈦氧化物膜：藉由原子層沈積形成一鍶鈦氧化物層；藉由原子層沈積形成一鋇鈦氧化物層； 藉由原子層沈積形成一鉺氧化物層，該鉺氧化物層介於該鍶鈦氧化物層與該鋇鈦氧化物層之間；及在一經選擇的氣體環境中以一經選擇的退火溫度及時間期間退火，使得該等個別鍶鈦氧化物層、鋇鈦氧化物層及鉺氧化物層一起轉換形成摻鉺之鋇鍶鈦氧化物。
  31. 如請求項30之方法，其中該方法包括形成鋇鈦氧化物與鍶鈦氧化物之交替層，在該等呈一介電堆疊之鋇鈦氧化物層及鍶鈦氧化物層中散布有一或多個鉺氧化物層，隨後退火形成摻鉺之鋇鍶鈦氧化物。
  32. 如請求項30之方法，其中形成該介電層包括形成該介電層作為一記憶體中之一發光層。
  33. 如請求項30之方法，其中形成該介電層包括於一平板顯示器中形成該介電層。
  34. 如請求項30之方法，其中形成該介電層包括形成該介電層作為一電光裝置中之一介電層。
  35. 一種製造與積體電路耦合之控制器的方法，該方法包含：提供一控制器；將一積體電路耦合至該控制器，該積體電路具有一含有一鋇鍶鈦氧化物膜之介電層，該鋇鍶鈦氧化物膜係由以下步驟形成：藉由原子層沈積形成一鍶鈦氧化物層；藉由原子層沈積形成一鋇鈦氧化物層；及在一經選擇的氣體環境中以一經選擇的退火溫度及 時間期間退火，使得該等個別鍶鈦氧化物層及鋇鈦氧化物層一起轉換形成鋇鍶鈦氧化物。
  36. 如請求項35之方法，其中將一積體電路耦合至該控制器包括耦合一具有該含有該鋇鍶鈦氧化物膜之介電層的記憶體裝置。
  37. 如請求項35之方法，其中提供一控制器包括提供一處理器。
  38. 如請求項35之方法，其中將一積體電路耦合至該控制器包括耦合一混合信號積體電路，其形成為具有該含有該鋇鍶鈦氧化物膜之介電層之積體電路。
  39. 如請求項35之方法，其中該方法包括形成一資訊處理系統。
  40. 如請求項35之方法，其中該方法包括形成一無線系統。
  41. 一種製造與裝置耦合之控制器的方法，該方法包含：提供一控制器；將一裝置耦合至該控制器，該裝置具有一含有一摻鉺之鋇鍶鈦氧化物膜之介電層，該摻鉺之鋇鍶鈦氧化物膜係由以下步驟形成：藉由原子層沈積形成一鋇氧化物層；藉由原子層沈積形成一鍶氧化物層；藉由原子層沈積形成一鈦氧化物層；及在一經選擇的氣體環境中以一經選擇的退火溫度及時間期間退火，使得該等個別鋇氧化物層、鍶氧化物層及鈦氧化物層一起轉換形成鋇鍶鈦氧化物膜；及 加入鉺至該鋇鍶鈦氧化物膜以形成該摻鉺之鋇鍶鈦氧化物膜。
  42. 如請求項41之方法，其中將一裝置耦合至該控制器包括耦合一具有該含有該摻鉺之鋇鍶鈦氧化物膜之介電層的顯示器。
  43. 如請求項41之方法，其中將一裝置耦合至該控制器包括耦合一具有該含有該摻鉺之鋇鍶鈦氧化物膜之介電層的發光裝置。
  44. 如請求項41之方法，其中提供一控制器包括提供一處理器。
  45. 如請求項41之方法，其中該方法包括形成一多媒體系統。
  46. 如請求項41之方法，其中形成一資訊處理系統包括形成一無線裝置。
TW096131531A 2006-08-25 2007-08-24 經原子層沈積之鋇鍶鈦氧化物膜 TWI413705B (zh)

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