TW546841B - Semiconductor device and fabrication process thereof - Google Patents

Semiconductor device and fabrication process thereof Download PDF

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Publication number
TW546841B
TW546841B TW091114197A TW91114197A TW546841B TW 546841 B TW546841 B TW 546841B TW 091114197 A TW091114197 A TW 091114197A TW 91114197 A TW91114197 A TW 91114197A TW 546841 B TW546841 B TW 546841B
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Taiwan
Prior art keywords
electrode
film
pad
semiconductor device
pattern
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TW091114197A
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English (en)
Inventor
Shuichi Chiba
Masahiko Ishiguri
Koichi Murata
Eiji Watanabe
Michiaki Tamagawa
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Fujitsu Ltd
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Publication of TW546841B publication Critical patent/TW546841B/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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Description

546841 A7 B7 五、發明説明 [技術領域] 本發明-般係有關於-種半導體裝置，特収有關於一 種半導體裝置之墊整（pa(J )電極構造。 在半導體I置中’―般若欲將已形成於半導體基板上半 導體零件内部之墊整電極，α通電方式及機械方式連接至 用於裝配半導體零件的基板（承載基板（inte_er)等） 時，必須在塾整電極上形成凸塊作為連接外部用之突起電 才虽° [習知背景] 一般而言，在製造半導體裝置之際，於半導體製程結束 時，必須確認半導體零件在電氣狀態時是否呈現正常運 作。因此，會於已形成於半導體基板表面上的墊整電極上 接上揲針’進行電性動作測試。 由於該動作測試過程中，須於A1或Cu所構成之墊整 電極上按探針，所以塾整電極表面會殘留探針的尖銳頂 端造成之呈凹凸狀變形之損痕（以下稱之為探針痕）。 第1圖係顯示在業已有探針痕形成的墊整電極之上形 成凸塊的半導體裝置者。 參照第1圖，半導體基板1〇上形成有墊整電極2〇，進 而在露出該塾整電極20之狀態下形成有鈍化膜30。且， 前述墊整電極20上形成有動作測試結果下的探針痕4〇。 精濺鍍法以於如此之墊整電極2〇上分別形成有厚度 3 00nm的丁！層6〇作為密接層，與厚度25〇1^的層61 作為導電層，進而以該導電層61為電極進行電解鑛敷，分 本紙張尺度ϋ用中國國家t^(CNS) Α4規格⑵
訂 .............線-. (請先閲讀背面之注意事項再填寫本頁) C, -4- 546841 五、發明説明（2 別形成厚度40〇〇nm的Ni層8〇盥 '、予！ 200nm 的 Au 層 而該如層90係作為州層80㈣β 90 R θ更進二^ Μ Ag系等無錯焊劑，或Sn-pb系等有 錯焊齊j於削述_ Au層90之y、、 之上形成凸塊電極1〇〇。 然而第1圖之形態中，如先前 乃匕况明過，在動作測钟 結果下，將於雨述塾整電極2〇上形成探針痕Μ， 痕現凹凸狀，所以即使進行機錢，有時亦無法均句 形成月ί述岔接層60或Cu層61。因為前if 一 口冷刖逃丁丨層60或Cu 2 61係非常之薄，僅具有約2〇〇~3〇〇nm之厚度，所以如 前述狀態’其底部若存有凹凸不平，將無法均勾成膜。° 因此，藉以以層61為電極的電解鍍敷形成Ni層80 與Aii層90時，這些層膜亦無法在探針痕4〇上成長，從 而，在Au層90上形成凸塊電極1〇〇之際，有時在對應於 前述孩針痕40的位置，塾整電極2〇與凸塊刚之間會產 生空洞110。 若凸塊電極ί⑽之下有如此的空洞110存在時，將讓使 用凸塊電極接合的電氣性或機械性之品質趨劣，降低半導 體裝置之可信賴度。又，經由如此未有Ti層及Cu層形成 之領域，為凸塊電極100材料之Sn、Ag、Pb、Ni等金屬 元素會擴散至墊整電極20中，或構成墊整電極2〇之A1 會擴散至&塊電極1〇〇，而有接觸阻抗增加之問題發生。 戶斤以，按習知技術，無法使探針直接接上電極墊表面， 而須於半導體裝置上另設一作為探針檢查用之測試用電極 墊，違行電性動作測試。依這種方法除用以形成凸塊電極 __ —— _ " ------------ 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公复）
(才先閲讀背面之注意事¾再填寫本頁) i------訂- 線：丨： 五、發明説明（3 ) 塾正電極外，运必須設有探針檢查用之另一墊整電極， 因此使半導體裝置之面積增加。 [發明之揭示j 在此，本發明之具體課題係於提供一種解決上述課題、 新穎且有用之半導體裝置之製造方法。 本發明更具體課題係於提供一種半導體裝置，其係可於 已接上探針之墊整電極上直接形成凸塊電極者。 本發明之另一課題係於提供一種半導體裝置，其係具有 土板形成於"亥基板上之墊整電極及形成於該墊整電極上 之凸塊電極者， 其中該墊整電極係具有凹凸狀損痕； 且前述墊整電極與前述凸塊電極之間設有用以覆蓋前 述凹凸狀損痕之圖案。 本i明之另-課題係於提供一種半導體裝置之製造方 法，其特徵在於包含有以下步驟，即·· 於基板上形成墊整電極； 於該墊整電極接上探針進行測試； 於兩述塾整電極表面之_ //V ΤΤ/ 、，” 口Η刀形成圖案，以覆蓋經由接 上前述探針時所產生之凹凸痕； 於如述塾整電極表面形成導雷 、〜^ ^ ^膜，以覆蓋該圖案； 以該導電膜為電極，用雷能 用^解鍍敷方式於前述墊整電極上 形成導電性底膜；及 於該‘電性底膜上形成凸塊電極。 本發明之另 一課題係於提供_ 種半導體裝置之製造方
發明説明 去，其特徵在於包含有以下步驟，即： 於基板上形成墊整電極； 於該塾整電極接上探針進行測試； 將經由接上該探針時產 座玍之凹凸部分平坦化； 於前述墊整電極表面形成導 成¥電膜，以覆蓋業已平坦化的 凹凸部分； 以w亥‘笔為電極，用雷能供敷+ ,, 也解錢敷方式於前述墊整電極上 形成導電性底膜；及 於該導電性底膜上形成凸塊電極。 本發明之另一課題传於蔣 哽係於獒供一種半導體裝置之製造方 法，其特徵在於包含有以下步驟，即： 於基板上形成墊整電極； 於該墊整電極接上探針以進行測試； 於前述墊整電極前面形成電極膜，以覆蓋經由接上前述 探針時所產生的凹凸痕； 以該電極膜為電極’用電解錢敷方式於前述塾整電極上 形成導電性底膜；及 於該導電性底膜上形成凸塊電極； 而前述電極膜其厚度係超過前述凹凸痕所產生的落差。 依據本發明，藉於有探針檢查時使用的探針所造成之凹 凸狀損痕（以下稱探針痕）之塾整電極上形成保護膜，或 將之平坦化，可於前述電極塾上形成包含有該探針痕部分 之導電層’再以該導電層為電極進行電解錢敷形成導電圖 案，遂可在前述墊整電極上形成凸塊電極。此時，本發明 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)
546841 A7 B7 5 五、發明説明 無須另設測試用墊整雷極，w 士， 正电位可有效利用基板表面，以及使 半導體裝置微細化。 (請先閲讀背面之注意事項再填寫本頁) 本舍明之其他特徵與優點，應可藉參照圖示下進行本發 明之較佳實施例之詳細說明而明白。 [圖式之簡單說明] 弟1圖係顯示在p^ 仕匕有知針痕形成之墊整電極上形成凸 塊之半導體裝置者。 弟2圖係顯示藉本私明货 精尽^明之弟1實施型態在墊整電極上之 凸塊形成過程者。 第3圖係顯示另—拉太旅 力猎本^明之第1實施型態在墊整電極 上之凸塊形成過程者。 -、ν一口 . 弟4圖係顯示另一藉本發明之第1實施型態在墊整電極 上之凸塊形成過程者。 第5圖係顯示另一拉太 力精本發明之第1實施型態在墊整電極 上之凸塊形成過程者。 :線丨 弟6圖係顯示另一藉本發明之第1實施型態在塾整電極 上之凸塊形成過程者。 第7圖係顯不另一藉本發明之第1實施型態在塾整電極 上之凸塊开> 成過程者。 第8圖係顯+ v 頌不另一猎本發明之第1實施型態在墊整電極 上之凸塊形成過程者。 电位 第9圖係盈翼+ 2 〜’、另一猎本發明之第1實施型態在墊整電極 上之凸塊形成過程者。 弟1 0圖1 系盈5 - rr ，、”、、員不另一藉本發明之第1實施型態在墊整電 本紙張尺度適用中國國 546841
極上之凸塊形成過程者。 (請先閲讀背面之注意事項再填寫本頁) 第π圖係顯不藉本發明之第2實施型態在墊整電極上 之凸塊形成過程者。 第12圖係顯示另一藉本發明之第2實施型態在墊整電 極上之凸塊形成過程者。 第13圖係顯不另一藉本發明之第2實施型態在墊整電 極上之凸塊形成過程者。 第14圖係顯示另一藉本發明之第2實施型態在墊整電 極上之凸塊形成過程者。 第15圖係顯示藉本發明之第3實施型態在墊整電極上 之凸塊形成過程者。 第16圖係顯示另一藉本發明之第3實施型態在墊整電 極上之凸塊形成過程者。 [發明之實施形態] (第1實施命J ) 第2至1 0圖係顯示藉本發明第1實施型態之半導體裝 置之製程者。 A ·墊整電極與基板保護膜之形成步驟 茶照第2圖，藉電子束蒸鍍法或濺鍍法而於業已形成有 電晶體及多層配線（圖上未顯示）之半導體基板21〇的表 面周緣部形成銘膜，再經由將其圖案化形成墊整電極 220。接著，於該墊整電極220上形成為保護膜之氮化矽膜 230以包覆塾整電極220’進而在露出該墊整電極220之狀 態下於前述保護膜230中形成開口部。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 7 五、發明說明 β。半導體裝置之探針檢查之步驟 探針:成 ::確？:示之構造後，在第3圖之步驟中，進行 侦宜以確涊電性信號。 將殘邊由於按壓探針所造成之凹 240 (以下稱之為探針痕)。 、廈之仏針痕 C.於塾整電極表面之探針損痕上形成氮化補之步驟 進而在弟」圖之步驟中，於第3圖之構造上形成氮化矽 、、骐以覆盍探針痕240,再進而對應該探針痕24〇，將其 膜圖案化形成覆蓋該探針痕24〇之氮化石夕膜圖案25〇。、 〇· Τι層與Cu層之形成步驟 訂 接著’在第5圖之步驟中，藉濺鍍法於第4圖之構造上 分別侬次形成厚度300咖之Ti層260與厚度200nm之Cu 層261以覆蓋岫述墊整電極22〇及氮化矽膜圖案25〇。 E •抗鍅膜270之圖案化步驟 接著’在第6圖之步驟中，於第5圖之構造上形成抗蝕 膜270 ’將其圖案化以覆蓋墊整電極220以外之領域。 F · Νι層與Au層之形成步驟 接著’在第7圖之步驟中，使用電解鍍敷法於第6圖之 構造上形成厚度4〇〇〇nm之Ni層280，進而於Ni層280 上形成厚度20〇nm之Au層290作為防氧化膜。 G·抗蝕膜之去除步驟 接著’在第8圖之步驟中進行灰化，去除第7圖中之抗 蝕膜270。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） -10- 546841 五 、發明説明（ 8 H· Τι層與Cu層之蝕刻步驟 接著’在第9圖之步驟中，以已形成於塾整電極220 上之如層28〇與⑽29G作紐膜，藉㈣或離子銳除 去形成於墊整電極220以外領域之乃層26〇及“層％卜 1 ·凸塊之形成步驟 進而在第H)圖之步驟中，於^層29〇上藉印刷法、 ㈣法及電解鑛敷法中任一方法形成由⑽系合金構成 ，热錯焊劑’或Sn_Pb系合金構成之有錯焊劑。之後，對 該焊劑進行熱處理，形成凸塊電極3〇〇。 但是’本實施例中，由於透過形成保護膜，例如為益機 膜之氮化石夕膜圖案250以覆蓋塾整電極22〇表面之探針痕 24〇’可以於塾整電極220上連續形成71層26〇盘a層 :以覆蓋該氮切膜圖案跡因此可以藉電解鍍敷㈣ 玉電極220上連續形成Ni圖案28〇或Au圖案29〇,即， 均勻覆蓋於對應該塾整電極220之領域，如此結果下即使 形成凸塊電極300，在其下也將不合 个曰有如習知之空洞形 成。於前述密接層260、261盥墊馨蕾化1 電極22〇之間形成氮化 石夕膜250，在墊整電極220上有損# ^ 時，是非常有效。 、…例如，有探針痕 又’本實施例中，係以氮切膜等絕緣膜為前述保護膜 250 ’但’本^明亚不偏限於此’亦可以氧化石夕膜等其他絕 緣膜’或聚酉迪亞胺樹脂等有機膜，咬公 、 —孟屬、合金等導電腺 作為保護膜圖案250之用。例如，犯丄 、 形成為導電膜之糊狀 …、Pd、Cu中任一者以取代前述保護膜圖案25〇,亦 五、發明説明（9 ) 可收相同之效果。 (弟2貫施你j ) f之弟制=14圖係顯示藉本發明第2實施型態之半導« ，程者。不過，對應先前業已說明過部分，賦予同一 參照標號，而說明省略。 A·半導體裝置之探針檢查步驟 如弟11圖所示，於半導體其4 土板210上形成墊整電極22丨 及基才反保遵膜2 3 〇之德推 <千j 军私认尤 <俊進订铋針檢查的結果下，墊整電極 22〇表面將殘留為凹凸狀損痕之探針痕24〇。 B ·藉乾姓刻將探針痕平坦化步驟 接著，如第12圖所示，於前述墊整電極22〇表面，包 含探針痕240，進行乾式㈣，將探針痕24〇平坦化。 C · Τι層與Cu層之形成步驟 接著，在第13圖之步驟中，使用濺鍍法於第12圖之構 造上分別依次形成厚度300nm之Tl層26〇與厚度2〇〇· 之Cii層261以覆蓋前述基板保護膜23〇及墊整電極22〇。 D ·凸塊之形成步驟 之後，經歷第1實施例之第6 $ Q同& ^ ^ κ< 乐主y圖所不步驟，如第 14圖所示，於墊整電極22〇上之〇11層261之上，形成厚 度4000nm之Ni層280，和厚度2〇〇nm之—層29〇，進 而形成SrwVg系無錯合金焊劑，或Sn-pb系鉛合金焊劑， 藉將其熱處理形成凸塊電極300。 如上所述，本實施型態中，藉由平坦化探針痕24〇減少 其凹凸落差，可於墊整電極220上連續均勻形成Ti層26〇 546841 五、發明説明（丨〇 ) 及Cu層261，可形成凸塊電極则而不產生空洞。 又’本實施例中是藉乾式則進行探針痕24〇之平班 化’不過使用濕式餘刻取代之，亦可收相同效果。又，亦 可將墊整電極220以6〇〇〜8〇。 > 〇〇 C進订炫解平坦化探針痕 240 ’以取代乾蝕刻。進而可對探針痕24〇施加機械性壓 力，物理性平坦化探針痕24〇，以取代乾式㈣，亦可收 相同效果。 (第3實施你J ) 第15至16圖係顯示藉本發明第3實施型態之半導體裝 置之製程者。不過，對應先前業已說明過部分，賦予同一 參照標號，而說明省略。 參照第15圖，本實施例中，探針檢查之後，藉濺鍍法 依次形成比前實施例更厚之Ti層262與Cu層263，例如 5〇〇nm之膜厚，以覆蓋已形成有探針痕24〇之墊整電極22〇 及純化膜230。 之後，經歷先前第6至9圖所示步驟，如第16圖所示， 於墊整電極220上之Cu層263之上，藉電解鍍敷形成厚 度4000nm之Ni層280和厚度200nm之Au層，進而形成 Sn-Ag系合金構成之無鉛焊劑，或Sn_Pb系合金構成之有 鉛焊劑。之後，對該合金焊劑進行熱處理形成凸塊電極 300 ° 本實施型態中，如上所述，將Ti層262與Cu層263 形成較厚，而以形成與前述探針痕240之落差相等或，超 過其厚度為佳，諸如1 μηι程度者，以使探針痕240之凹凸 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填窝本頁) 訂| ;線- 13 - 546841 A7 11 五、發明説明 形狀落差相對地變小或可忽視，而可以於前述墊整電極 220上連續形成前述Ti層262與Cll層263。 又’以上各實施例中，密接層260並不侷限於Ti層， 可以由Ti、Cr、TiW、Mo、Ta、W、Nb、V中任一者構成。 又 $述電極層261並不侷限於〇\1，可以由1\[卜（311、？(1、 Pt Au、Ag中任一者形成。進而，形成前述膜層之製程並 不偈限於濺鍍法，亦可藉蒸鍍法或m〇cVD( Metal organic chemical vapor dep〇siti〇I1 ;有機金屬化學氣相磊晶法）法 形成。 又’為前述凸塊之底層（UBM層：under bump metal ) 之‘電層280並不侷限於Ni層，亦可由包含Ni、Cu之合 金構成。進而，前述防氧化膜29〇並不侷限於All，可以由 An、Pt'Pd、Pt、In 中任一者形成。 進而，前述凸塊電極300並不侷限於Sn_Ag合金或
Pb-Sn合金，亦可為pd、川、Cu、〜及外之合金，或可 為 Au、Ag。 以上，針對本發明之較佳實施例詳加說明，然而本發明 並=侷限於如此特定實施型態，在申請專利範圍之本發明 要曰之範圍内，可作各種變形及變更。 [產業可利用性] 依本發明，即使形成於基板上之墊整電極有凹凸狀損 1、亦可於其上女定連續地形成導電膜，藉以如此之導電 腰為電極進行電解錢敷，即可於塾整電極之全面形成導電 曰…果，可於如此之導電層上穩定地形成凸塊電極且而 本紙張尺度適用中__(_ Μ規格⑵_7錢） (請先閲讀背面之注意事項再填寫本頁) •”訂· .線- -14- 546841 A7 ^____B7___五、發明説明（12 ) 無空洞形成。 接本發明，由於亦可於接上探針電極之墊整電極上形成 凸塊電極’所以無須形成另一測試用墊整電極，可有效利 用基板表面，以及使半導體裝置微細化。 [圖中標號說明] 10.··半導體基板 20·.·塾整電極 3 0…鈍化膜 40…探針痕 60."Ti 層 61…Cu層 80…Ni層 90".Au 層 1 〇〇··.凸塊電極 110…空洞 210·..半導體基板 220··.塾整電極 230…氮化石夕膜 240…探針痕 250…氮化矽膜圖案 260...Ti 層 261".Cu 層 270…抗名虫膜 280·..Ni 層 290".Au 層 300···凸塊電極 (請先閱讀背面之注意事項再填寫本頁) ，裝_ 訂| :線丨 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公楚）

Claims (1)

  1. 的841 A8 B8 C8 D8 ' _請專利範圍 種半導體裝置，係具有基板、形成於該基板上之墊整 包極及形成於該墊整電極上之凸塊電極者， 其中該墊整電極係具有凹凸狀損痕； 且别述塾整電極與前述凸塊電極之間設有用以覆蓋 月;J述凹凸狀損痕之圖案。 2 如申凊專利範圍第1項之半導體裝置 無機膜所構成者。 3 > •如申請專利範圍第1項之半導體裝置 有機膜所構成者。 4·如申請專利範圍第1項之半導體裝置 導電性膜所構成者。 5 ·如申請專利範圍第1項之半導體裝置 其中該圖案係由 其中該圖案係由 其中該圖案是由 (請先閲誇背面<注意事項再填寫本頁) 6, 其中該圖案是由 組合無機膜、有機膜或導電性膜而成之積層膜所構成 者。 —種半導體震置之製造方法，其特徵在於包含有以下步 驟，即： 於基板上形成墊整電極； 於該墊整電極接上探針進行測試； 於前^塾整電極表面之一部份形成圖案，以覆蓋經 由接上别述探針時所產生的凹凸痕； 於前述塾整電極表面形成導電臈1覆蓋該圖案； 以'導電膜為電極’用電解鍍敷方式於前述墊整電 極上形成導電性底膜；及 於該導電性底膜上形成凸塊電極。 本紙張尺度適用中_標準（_Α4祕⑽__ 訂· ~ 16 - 546841
    、申請專利範園 7·如申請專利範圍第6項 該圖幸是由為盎播腊 製造方法’其中 8. 如申請專利範圍第6項之半 f:料成者。 該圖案是由為有機膜之5 ^ 衣&方法，其中 ^ M之聚醯亞胺樹脂所形成者。 9. 如申請專利範圍第& .,π ^ ^ 體裝置之製造方法，其中 珂述圖案是由為導雷wu di ^ T 者。 生賊之糊狀^，、^〜所構成 ι〇·—種半導體裝置之勢；生古、土仕a 驟，即： …法，其特徵在於包含有以下步 於基板上形成墊整電極； 於該墊整電極接上探針進行測試； 將經由接上該探針時產生之凹凸部分平坦化· 於前述塾整電'極表面形成導電膜，以覆蓋業已 化的凹凸部分； — 以該導電臈為電極’用電解鍍敷方式於前述塾 極上形成導電性底膜；及 正电 於名^電性底膜上形成凸塊電極。 11·^申請孚利範圍第10項之半導體裝置之製造方法，复 前述平坦化步驟具有一將前述凹凸狀損痕進行= 刻之步驟。 L八蚀 12·如申請專利範圍第10項之半導體裝置之製造方法，其中 刖述平坦化步驟具有一將前述凹凸狀損痕進行濕 刻之步驟。 ’·、、、式餘 13.如中請專利範圍第丨〇項之半導體裝置之製造方法，其 本紙張尺度適用中國國家標準（CNS) A4規格⑵〇><297公楚） (請先閲誨背面之•注意事項再填寫本頁)
    -17- 546841 A8 B8 C8 D8 、申請專利範圍 'J述平坦化步驟具有一將前述墊整電極以6⑻〜8⑼。c 進行熔解之步驟。 14·:申请專利範圍第1〇項之半導體裝置之製造方法，其中 則述平坦化步驟是對前述凹凸狀損痕施加機械性壓力 使其平坦者。 15-種半導體裝置之製造方法，其特徵在於包含有以下步 驟，即： 於基板上形成墊整電極； 於該墊整電極接上探針以進行測試； 於前述墊整電極前面形成雷 义、、 〜^电極膑，以覆蓋經由接上 月·J述探針時所產生的凹凸痕； 以該電極膜為電極，用電解鑛敷方式於前述塾整電 極上形成導電性底膜；及 於該導電性底膜上形成凸塊電極； 而前述電極膜其厚度係超過前述 < U凸痕所產生的落 差0 本紙張尺度適用中國國家標準（CNS) A4規格⑵狀撕公奢） (請先閲#背面、心注意事項再填寫本頁)
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