1269422 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於半導體電鍍製程改善方法，特別是指 一種在電鍍製程進行前，利用光阻塗佈、曝光、顯影來製 5 造出電極接觸點’以改善電鑛品質之半導體製程之圖案電 鍍接觸點產生方法。 【先前技術】 金屬化製程（metallization process)，可以利用諸如蒸錢 、濺鍍、化學氣相沈積，以及電鍍等製程來達成，並已是 〇 半導體製程技術中極為重要的一環。其中，由於電鍍製程 設備成本低廉與膜厚沈積速度較快等特性，故已被廣泛地 應用於半導體產業上。特別是在要求高集積度、短傳輸路 徑下所衍生的覆晶構裝技術中，利用電鍍法來製作金屬凸 塊已成為關鍵的製程技術。 5 參閱圖1 ,半導體製程在晶圓7上完成各層線路元件製 作後，在輸入/輸出埠8的金屬焊墊四周及焊墊以外的線路 區，或稱主動區，會覆蓋一層氮化矽、氧化矽保護層71。 金屬凸塊製程首純在焊塾8及護層71上方的晶圓表面賤 鍍一層金屬薄膜72(通稱為UBM層，Under Bump 〇 MetallUrgy)，以及一電鍍核種層（Plating seed layer)73，並 在電鍍核種層73上塗佈光阻層75 $時開出導孔， 以便進行後續的電鍵處理與凸塊76形成作業（亦有在保護層 71與UBM層72間再加上一介電層者）。 其中，UBM層72是用來提供黏著與擴散障礙之用，電 1269422 鍍核種層73則是用作後續電鍍處理的初始層。在以電鑛製 程製作浸潤（wetting)及UBM保護層74(通常為銅或鎳金屬） 後，再以電鍍製程將鉛-錫合金76鍍上，並除去光阻層75 與其它不必要的金屬層後，經由迴焊（refl〇w)處理，使得鋅 5 錫轉變為球形的凸塊76即告完成，如圖2所示。 在以在電鍛處理的過程中，如圖3所示，是利用一連 接於電鍍電源供應裝置（圖未示）之陰極金屬針9，以其尖銳 前端刺入光阻層75中，並以陰極金屬針9本身的彈性或治 具彈簧來維持陰極金屬針9與電鍍核種層73間的緊密接觸 10 ，故在晶圓7被置入電鍍液中後，將陰極金屬針9與電鍍 槽的陰極相連，就能使電鍍液中的金屬離子漸次附著於裸 露於導孔中的電鍍核種層73上，完成電鍍製程。 然而，上述的電鍍方式卻會產生幾個問題： (1) 當尖針9刺穿光阻層75時，會產生光阻碎屑，此光 15 阻碎屑落入電鍍液中後，可能隨著電鍍液的流動而進入導 孔81内，形成電鍍缺陷。 (2) 大針9與電鑛核種層73的接觸面積小，當通入較大 電鑛電流時’會使朗點附近電龍種層73局部過熱燒毀 而使電流供應中斷。為了增加尖針9與電㈣㈣73的接 2〇 觸面積，亦有採斜角方式刺入光阻層75者，並利用晶圓上 方蓋板90之重量來壓迫陰極金屬針9變形，如圖4所示， 但依然無法避免上述缺點（丨）的產生。 (3) 若電鑛核種層73下方尚有—層介電層”時，尖針9 極易刺穿電錄核種層73及介電層77到達晶圓7表面，易 1269422 73間之電性連接不良，無 造成陰極金屬針9與電鍍核種層 法進行電鍍反應，如圖5所示。 【發明内容】 5 10 15 20 因此，本發明之目的即在於提供—種能夠產 陰極金屬針之針頭相接觸的__ _ 鍍製程中的諸多缺點。 乂解决以彺電 於疋在第—較佳實施例中，本 圖案電鑛陰極接觸點產生方法 Μ體^之 疋在一具有一電鍍核種層 之硬質基板上進行，包含步驟 Α)$成一介電層於該電鍍核 種層上。B)形成至少二窗口於八 、為；丨電層上，以分別曝露該 電鍍核種層之表面的一第一區只 昂 &域與一第二區域，該第一區 域是供-陰極祕針頭㈣，該第二區域是心進行電鍵 化學反應之位置。 在-第二較佳實施例中，本發明半導體製程之圖案電 鍍陰極接觸點產生方法，是在_具有_第一介電層之硬質 基板上進行，其步驟為：a)形成至少—第—窗口與—第二窗 口於該第-介電層±，以分別曝露出該基板表面之一第一 區域與-第二區域。b)形成-電鍍核種層於該第—介電層及 該第一、第二區域上。c)形成一第二介電層於該電鍍核種層 上。以及步驟d)形成複數第三與第四窗口於該第二介電層 上，以分別曝露出位於該第一區域與該第二區域上方之該 電鍍核種層表面的至少一部分，以分別供一陰極電鍍針頭 接觸與供進行電鍍化學反應。 上述實施例中，由於產生了供該陰極電鍍針頭相接觸 6 1269422 之區域，因此不會有碎屑的問題發生，特別是，該陰極電 鍛針頭是採用具有平滑前端之針頭，因此除了能夠與該電 鑛核種層進行良好的電性連接以外，更不會刺穿該軟質介 電層等’因此能夠提高電鍍品質。 5 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在. 以下配合參考圖式之一第一與一第二較佳實施例的詳細說 明中，將可清楚的明白。 參閱圖6，本發明半導體製程之圖案電鍍陰極接觸 φ 1〇 生方法的第-較佳實施例是在一具有一電鍍核種層u之硬 質基板1上進行。本實施例中，基板1是指一具有一硬質 表面的晶圓，例如表面為一裸晶或是金屬層等，其表面下 方可能已經過許多半導體製程步驟而依次形成有許多金屬 層、介電層#，然為了簡化說明起見，圖示中並不特別將 15 每一層結構載明，僅就本發明之相關步驟加以闡明。 如圖6與圖7所示，當基板i上方已依次濺鍍有一電 鍍核種層11後，此電鍍核種層11可以分別是銅、金、銀，馨 或其它不易在光阻顯影製程時受顯影劑侵蝕之金屬。本發 明首先是形成一介電層12於電鍍核種層n上，本實施例中 2〇 ，介電層12是指一以聚亞醯胺(PI)為材質之光阻層，因此、 疋以叙轉塗佈等方式將介電層形成於電鍍核種層丨1上。 · 接著，如圖7與圖8所示，以一第一光罩21轉移複數 窗口 31之圖案至介電層12上，並再以一第二光罩22轉移 複數窗口 32之圖案之介電層12上。此處若以單一光罩亦 7 5 10 15 分為第-區域m與第二區域112，其中，第一區域⑴指 的是對應於基W之無效區上，而第二區域ιΐ2較指各晶 片之主動區與主動㈣之間隔處，就是欲進行钱製程的 區域。 1269422 能同時形成窗口31、32，此乃本例之一簡單變化而已。-隨後經過顯影製程’使介電層12上形成出該些窗口 31 與窗口 32,以曝露出電鑛核種層u之表面，如圖9所示。 微影（⑽祕啊㈣製程之其它㈣步驟例如塗佈〜軟 烤:曝光、顯料，及其更進—步說明，當為熟習此技者 所月b輕易了解者，本例中並不再一一贅述。 配合圖1〇 ’在此曝露出的電鍍核種層11表面上，可以 因此如圖11所示’當吾人將已形成好供一陰極電鑛 針頭10接觸之接觸點（第一區域⑴）後，將基板i置入電鑛 液中’再利用電鍍電源供應裝置(圖未示)之陰極供電給陰極 電鑛針頭10’就能夠使得第二區域112產生電鑛化學反應 ’即以第二區㉟U2之電鑛核種層η作為電鑛之初始層， 漸次產生電鍍反應而增加金屬層之厚度。 特別是，由於提供第一區域U1來供陰極電鍍針頭1〇 接觸，故毋需大銳的頭端來進行刺入的動作，而能改採平 滑之針頭，以便於增加接觸面積、減少接觸電阻，因此不 會有以往產生光阻碎屑以及接觸面積不足等缺點發生。 另一方面，電鍍液雖會進入第一區域lu之窗口 31中 ，造成第一區域111亦產生電鍍化學反應，然由於第一區域 111乃是對應於晶圓之無效區，故對後續製程並未產生重大 20 5 10 15 1269422 曰或為免上述情形發生，亦能讓電鍵針頭ι〇與第一區 域接觸後，以膠封或其它隔絕方式密封住第一區域⑴ 之自口，以免電鍍液流入於其中進而產生電鍍化學反應。 ^ >閱圖12，本發明半導體電鍍接觸點產生方法之第二 車又佳實知例疋在一具有一第一介電層42之硬質基板上 進订’例如應用在覆晶構裝中的凸塊製作，該第-介電層 通⑦為有機尚分子聚合物，如聚亞醯胺（ρι)、矽酮 (Slhc〇nes)、環氧樹脂（eP〇xy)、雙苯基環丁烯 (b1Sbe_cyclobutene，BCB)等，其熟化後之薄膜硬度較氮 化石夕、氧化石夕等玻璃材質為低，，因此極易為以往的尖銳 電極針頭刺穿。 本例中第一介電層42特別是指一感光型或非感光型聚 亞醯胺，除了可作為機械緩衝（mechanical hffer)，在構裝 ^程中保4其下方之電路層，避免遭受刮傷或壓傷外，亦 可作為一介電層，以改善覆晶構裝時晶粒與構裝基板上線 路間的交談（crosstalk)效應而產生雜訊等。 首先，如圖13、14所示，分別以一第一光罩2〇1及一 第二光罩202對第一介電層42依次進行曝光動作，並隨後 進行顯影、熟化等製程，使第一介電層42上形成有與該等 光罩201、202相對應之圖樣，即形成複數個第一窗口 5〇1 與第二窗口 502於該第一介電層42上，以分別曝露出基板 41表面上之一第一區域411與一第二區域412，其中，第一 區域411乃為基板上之無效區，第二區域412乃為基板41 上主動區與主動區間之間隔處，即晶片與晶片間供切割道（ 20 1269422 圖未示）、焊墊（圖未示）等設置處，以便進行後續例如凸塊 製造'或焊墊重配置等製程。 惟上述以兩光罩201、202依次進行並非侷限本發明之 步驟，亦能以單一光罩一次形成上述窗口 5〇1、502圖樣， 5 以曝露出基板之第一與第二區域411、412，其形成後之晶 圓正視圖如圖16所示，其中，第一窗口 501之數目端視電 鑛治具之設計而定。 接者’如圖17所示，以錢鍛方式形成一均勻之電鏟核 種層43於基板41上，使其覆蓋於前述介電層42以及第一 10 、第二區域411、412上，以防止氧化並作為後續電鍍製程 之初始層，此電鍍核種層43 —般之材質是採金或銅。當然 ，熟習此技者應知，若是為了避免後續製程中，凸塊（圖未 示）與焊墊（圖未示）等產生相互擴散或者形成易脆的介金屬 化物，則在電鍍核種層43形成前，理應濺鍍一可能為鈦、 15 鉻或者鈦鎢混鑄金屬（TiW)的UBM層，來作為黏著與擴散 阻礙層。 如圖18所示，緊接著再塗佈一第二介電層44於電鍍 核種層43上，其亦與前述第一介電層42相同，是以感光 型光阻作為其材質，並如圖19、20所示，再經一第三與一 20 第四光罩203、204分別曝光、顯影等製程，以依序形成第 三與第四窗口 503、504，第三窗口 503之位置應與第一窗 口 501之位置重疊，即曝露出第一區域411上方的電鍍核種 層43,如圖21。圖中許多小凸柱所在處5〇4即為後續凸塊 形成所在位置，即位於各晶粒主動區周緣，並是本例中欲 10 1269422 加以進行電鍍化學反應的地方，如圖22所示。 參閱圖23，與第一實施例相同，本實施例採取具有平 滑前端的電鍍針頭10接觸於第一區域411上方的電鍍核種 層43，並當基板41置入電鍍液中後，以電鍍裝置（圖未示） 施予電流後，使由第四窗口 5〇4曝露出之電鍍核種層43表 面進行電鍍化學反應，並當電鍍完成後，再接續去除光阻 及钱刻丨賤鍍金屬層之製程。 本例中雖有第一介電層42的存在，然經由適當地曝光 顯衫等製私，使得第一區域411上方之電鍍核種層43能 直接與基板41相接觸，即陰極電鍍針頭1〇所接觸之區域 乃疋一硬質表面，故必然不會有刺穿第一介電層42的問題 存在，消除了以往易於產生電連接不良的問題。 由上述兩實施例可以得知，本發明並不侷限於先前技 術中所述的凸塊製作中，其亦廣泛地適用於欲以電錢法來 形成一圖案金屬層之前置步驟，即先利用光阻塗佈、曝光 、顯影等微影製程，製造出供陰極電鍍針頭1G相接觸之接 觸點’因此毋需利用陰極電鍍針頭1G刺人光阻層中，故免 去了產生光阻碎屑等問題，更佳的是，由於採用平滑頭端 的陰極電鍍針1員10，因此能夠有效地加大接觸面積、改善 電鍍品質，確實達到本發明之目的。 【圓式簡單說明】 圖1〜圖2是剖視圖，說明以往凸塊製作的流程； 圖3是一示意圖，說明以往電鍍製程時，一陰極金屬 針與一電鍍核種層相接觸； 11 1269422 圖4是一示意圖，說明該陰極金屬針以斜角刺入一光 阻層後與該電鍍核種層相接觸； 圖5是一示意圖，說明該陰極金屬針刺穿該電鍍核種 層下方之介電層’到達晶圓表面； 圖6〜10圖是示意圖，說明本發明半導體製程之圖案 電鍍陰極接觸點產生方法的一第一較佳實施例的流程； 圖11是一示意圖，說明以一具有平滑頭端的電鍍針頭 與一電鍍核種層相接觸的情形； 圖12〜22圖是示意圖，說明本發明半導體電鍍接觸點 H 產生方法的一第二較佳實施例的流程；以及 圖23是一示意圖，說明以一具有平滑頭端的電鍍針頭 與一電鍍核種層相接觸的情形。1269422 玖, the invention description: [Technical field of the invention] The present invention relates to a semiconductor electroplating process improvement method, in particular to a method for making an electrode contact by photoresist coating, exposure, and development before the electroplating process is performed. Point 'patterning contact point generation method for semiconductor process to improve the quality of electric ore. [Prior Art] The metallization process can be achieved by processes such as steaming, sputtering, chemical vapor deposition, and electroplating, and is an extremely important part of semiconductor process technology. Among them, the electroplating process equipment has been widely used in the semiconductor industry due to its low cost and fast film deposition speed. Especially in the flip chip fabrication technology which is required to have a high accumulation degree and a short transmission path, the use of electroplating to form metal bumps has become a key process technology. 5 Referring to FIG. 1, after the semiconductor process is completed on the wafer 7, each layer of the circuit component is fabricated, and a layer of tantalum nitride is covered around the metal pad of the input/output port 8 and the line region other than the pad, or the active region. The ruthenium oxide protective layer 71. The metal bump process is firstly coated with a metal film 72 (known as UBM layer, Under Bump 〇MetallUrgy) on the surface of the wafer above the solder bump 8 and the cap layer 71, and a plating seed layer 73, and When the photoresist layer 75 is coated on the plating core layer 73, a via hole is opened for subsequent key processing and bump 76 formation (and a dielectric layer is also provided between the protective layer 71 and the UBM layer 72). By). Among them, the UBM layer 72 is used to provide adhesion and diffusion barriers, and the electric 1269422 nucleation layer 73 is used as an initial layer for subsequent plating treatment. After the wetting and UBM protective layer 74 (usually copper or nickel metal) is fabricated by an electric ore process, the lead-tin alloy 76 is plated by an electroplating process, and the photoresist layer 75 and other unnecessary metals are removed. After the layer is processed by reflow (refl〇w), the zinc 5 tin is converted into a spherical bump 76, as shown in FIG. In the process of electric forging, as shown in FIG. 3, a cathode metal pin 9 connected to a plating power supply device (not shown) is used to pierce the photoresist layer 75 with its sharp front end, and The elasticity of the cathode metal needle 9 itself or the fixture spring maintains the close contact 10 between the cathode metal needle 9 and the plating core layer 73, so after the wafer 7 is placed in the plating solution, the cathode metal needle 9 and the plating tank are placed. When the cathodes are connected, the metal ions in the plating solution are gradually attached to the plating core layer 73 exposed in the via holes to complete the electroplating process. However, the above plating method has several problems: (1) When the sharp needle 9 pierces the photoresist layer 75, photoresist debris is generated, and the light 15 may hinder the debris from falling into the plating solution, possibly following The flow of the plating solution enters the via hole 81 to form a plating defect. (2) The contact area between the large needle 9 and the electric nucleus seed layer 73 is small. When a large electric current is introduced, the local electric charge layer 73 near the spur point will be partially overheated and burned to interrupt the current supply. In order to increase the contact area between the sharp needle 9 and the electric (four) (four) 73, the photoresist layer 75 is also obliquely penetrated, and the weight of the upper cover 90 of the wafer is used to compress the cathode metal needle 9 to deform, as shown in FIG. As shown, but the above disadvantages (丨) are still unavoidable. (3) If there is a dielectric layer below the electro-minening nucleus layer 73, the sharp needle 9 can easily pierce the electro-recorded nuclear layer 73 and the dielectric layer 77 to reach the surface of the wafer 7, and the electrical property of the 1268422 Poor connection, no causing electroplating reaction between the cathode metal needle 9 and the electroplating core layer method, as shown in Fig. 5. [Invention] 5 10 15 20 Therefore, the object of the present invention is to provide a needle capable of producing a cathode metal needle. Many disadvantages in the __ _ plating process of the contact 。 乂 乂 乂 疋 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Performing on the hard substrate, comprising the steps of: forming a dielectric layer on the electroplated core layer; B) forming at least two windows on the erbium layer; respectively, exposing the surface of the electroplated nucleation layer a region only & a region and a second region, the first region being a donor-cathode needle (four), the second region being the location where the heart performs a chemical reaction of the bond. In the second preferred embodiment, the invention Pattern plating cathode contact point generation method for semiconductor process And performing on the hard substrate having the first dielectric layer, the steps of: a) forming at least a first window and a second window on the first dielectric layer ± to expose the surface of the substrate respectively a first region and a second region. b) forming a plating core layer on the first dielectric layer and the first and second regions, c) forming a second dielectric layer on the plating core layer And step d) forming a plurality of third and fourth windows on the second dielectric layer to expose at least a portion of the surface of the plating core layer above the first region and the second region, respectively, for respectively A cathode electroplating needle contacts and is subjected to electroplating chemical reaction. In the above embodiment, since the region where the cathode electroplating needle contacts 6 1269422 is generated, there is no problem of chipping, in particular, the cathode electric forging needle Since a needle having a smooth front end is used, in addition to being electrically connected to the electroless core layer, the soft dielectric layer or the like is not pierced. Therefore, the plating quality can be improved. hair The foregoing and other technical contents, features, and functions will be apparent from the following detailed description of the first and second preferred embodiments of the accompanying drawings. Referring to Figure 6, the semiconductor process of the present invention The first preferred embodiment of the pattern plating cathode contact φ 1 generation method is performed on a hard substrate 1 having a plating core layer u. In this embodiment, the substrate 1 refers to a wafer having a hard surface. For example, if the surface is a bare crystal or a metal layer, there may be many semiconductor processing steps under the surface and a plurality of metal layers and dielectric layers # are sequentially formed. However, for the sake of simplicity of explanation, the illustration is not particularly limited. Each layer structure is illustrated, and only the relevant steps of the present invention are clarified. As shown in FIG. 6 and FIG. 7, after a plating core layer 11 has been sequentially sputtered on the substrate i, the plating core layer 11 may be copper, Gold, silver, enamel or other metals that are not easily attacked by the developer during the photoresist development process. The present invention firstly forms a dielectric layer 12 on the electroplated core layer n. In the present embodiment, the dielectric layer 12 refers to a photoresist layer made of polyamidamine (PI). A dielectric layer is formed on the plating core layer 1 by means of transfer coating or the like. Then, as shown in FIG. 7 and FIG. 8, the pattern of the plurality of windows 31 is transferred to the dielectric layer 12 by a first mask 21, and the dielectric of the pattern of the plurality of windows 32 is transferred by a second mask 22. On layer 12. Here, if the single mask is also divided into the first region m and the second region 112, wherein the first region (1) refers to the ineffective region corresponding to the base W, and the second region ι2 refers to each The area between the active area of the chip and the active (four) is the area where the money process is to be performed. 1269422 can form windows 31, 32 at the same time, which is a simple change of this example. The window 31 and the window 32 are formed on the dielectric layer 12 by a developing process to expose the surface of the electrodeposited layer u, as shown in FIG. Lithography ((10) secret ah (four) process other (four) steps such as coating ~ soft bake: exposure, material, and further step-by-step instructions, when it is easy to understand for those who are familiar with this technique, this example is not Further, in conjunction with Fig. 1 'on the surface of the electroplated core layer 11 exposed here, it can be as shown in Fig. 11 'When we have formed a contact point for contacting a cathodic electro-mine needle 10 (first After the region (1)), the substrate i is placed in the electro-mineral solution. 'The cathode of the electroplating power supply device (not shown) is supplied to the cathodic electro-chemical needle 10' to enable the second region 112 to generate an electro-mineral chemical reaction. Taking the electroless ore nucleation layer η of the second region 35U2 as the initial layer of the electric ore, the electroplating reaction is gradually generated to increase the thickness of the metal layer. In particular, since the first region U1 is provided for the contact of the cathodic electroplating needle, it is necessary The sharp end of the sharp end is used for the piercing action, and the smooth needle can be changed to increase the contact area and reduce the contact resistance, so that there is no disadvantage such as the occurrence of photoresist debris and insufficient contact area. Aspect, plating solution It will enter the window 31 of the first region lu, causing the first region 111 to also generate a plating chemical reaction. However, since the first region 111 corresponds to the ineffective region of the wafer, it does not generate significant 20 5 10 15 for the subsequent process. 1269422 曰In order to avoid the above situation, the button needle ι〇 can also be contacted with the first area, and the first area (1) is sealed by a seal or other insulation to prevent the plating solution from flowing therein to generate electroplating chemistry. The second car of the method for producing a semiconductor plated contact point of the present invention is preferably exemplified by a predetermined substrate on a hard substrate having a first dielectric layer 42, for example, applied to a flip-chip structure. In the case of the bumps in the package, the first dielectric layer 7 is an organic molecular polymer, such as poly(imide), fluorenone (Slhc〇nes), epoxy resin (eP〇xy), bisbenzene. The hardness of the film after curing is lower than that of glass materials such as nitrite and oxidized stone, so it is easy to pierce the conventional sharp electrode needle. Electrical layer 42 refers in particular to a photosensitive type or Photosensitive polyamidoline, in addition to being used as a mechanical buffer, protects the circuit layer underneath it from scratches or crushes, and acts as a dielectric layer to improve flip chip During the assembly, the crosstalk effect between the die and the line on the substrate is generated to generate noise, etc. First, as shown in FIGS. 13 and 14, a first photomask 2〇1 and a second photomask are respectively used. 202, the first dielectric layer 42 is sequentially exposed, and then subjected to development, curing, etc., so that the first dielectric layer 42 is formed with a pattern corresponding to the masks 201, 202, thereby forming a plurality of a window 5〇1 and a second window 502 are disposed on the first dielectric layer 42 to expose a first region 411 and a second region 412 on the surface of the substrate 41, wherein the first region 411 is a substrate In the upper inactive area, the second area 412 is a space between the active area and the active area on the substrate 41, that is, a scribe line between the wafer and the wafer (not shown in FIG. 20 1269422) and a pad (not shown). For subsequent processes such as bump fabrication or pad reconfigurationHowever, the above steps of the two masks 201 and 202 are not limited to the steps of the present invention, and the windows 5〇1 and 502 can be formed at a time by a single mask to expose the first and second regions 411 and 412 of the substrate. The front view of the formed wafer is as shown in FIG. 16, wherein the number of the first windows 501 depends on the design of the electric ore fixture. As shown in FIG. 17, a uniform electric shovel core layer 43 is formed on the substrate 41 by money forging to cover the dielectric layer 42 and the first 10 and second regions 411 and 412. To prevent oxidation and as an initial layer of the subsequent electroplating process, the electroplated core layer 43 is generally made of gold or copper. Of course, those skilled in the art should know that if the bumps (not shown) and the pads (not shown) are interdiffused or form a brittle metalkate in the subsequent process, the plating layer 43 is formed. Prior to formation, a UBM layer, possibly titanium, 15 chrome or titanium-tungsten mixed metal (TiW), should be sputtered as an adhesion and diffusion barrier. As shown in FIG. 18, a second dielectric layer 44 is applied to the electroplated core layer 43, which is also the same as the first dielectric layer 42, and is made of a photosensitive photoresist as shown in FIG. 19 and 20, and then through a third and a 20 fourth masks 203, 204 respectively exposure, development and other processes, in order to form third and fourth windows 503, 504, the position of the third window 503 should be The positions of the first window 501 overlap, that is, the plated core layer 43 above the first region 411 is exposed, as shown in FIG. In the figure, many small studs are located at 5〇4, which is where the subsequent bumps are formed, that is, at the periphery of each active region of the die, and is the place where 10 1269422 is used for electroplating chemical reaction in this example, as shown in Fig. 22. . Referring to FIG. 23, in the same manner as the first embodiment, the present embodiment adopts a plating needle 10 having a smooth front end to contact the plating core layer 43 above the first region 411, and after the substrate 41 is placed in the plating solution, the plating device is used ( After the current is applied, the surface of the plating core layer 43 exposed by the fourth window 5〇4 is subjected to a plating chemical reaction, and after the plating is completed, the photoresist and the metallized layer are successively removed. Process. In this example, although the first dielectric layer 42 is present, the plating core layer 43 above the first region 411 can be directly contacted with the substrate 41 by appropriately exposing the blank or the like, that is, the cathode plating needle 1〇 The area to be contacted is a hard surface, so that there is no problem of piercing the first dielectric layer 42, and the problem of easy electrical connection failure in the past is eliminated. It can be seen from the above two embodiments that the present invention is not limited to the fabrication of the bumps described in the prior art, and is also widely applicable to the pre-step of forming a patterned metal layer by the method of electricity, that is, Using a lithography process such as photoresist coating, exposure, development, etc., a contact point for contacting the cathode plating needle 1G is manufactured. Therefore, it is not necessary to use a cathode plating needle 1G to pierce the photoresist layer, thereby eliminating the occurrence of photo-resistance. More preferably, since the cathode plating needle 1 member 10 having a smooth tip end is used, the contact area can be effectively increased and the plating quality can be improved, and the object of the present invention can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 2 are cross-sectional views illustrating a flow of conventional bump fabrication. FIG. 3 is a schematic view showing a cathode metal needle in contact with a plating core layer in a conventional electroplating process; 11 1269422 FIG. Is a schematic diagram showing that the cathode metal needle is in contact with the plating core layer after being obliquely inserted into a photoresist layer; FIG. 5 is a schematic view showing the cathode metal needle piercing the dielectric layer under the plating core layer' FIG. 6 to FIG. 10 are schematic diagrams showing the flow of a first preferred embodiment of the pattern plating cathode contact point generating method of the semiconductor process of the present invention; FIG. 11 is a schematic view showing a smooth head end FIG. 12 to FIG. 22 are schematic views showing the flow of a second preferred embodiment of the method for producing a semiconductor plating contact point H of the present invention; and FIG. 23 is a schematic view showing A case where a plated needle having a smooth tip is in contact with a plated core layer.
12 1269422 【圖式之主要元件代表符號說明】 1 基板 202 第二光罩 11 電鍍核種層 203 第三光罩 12 介電層 204 第四光罩 31 窗口 501 第一窗口 32 窗口 502 第二窗口 21 第一光罩 503 第三窗口 22 第二光罩 504 第四窗口 111 第一區域 411 第一區域 112 第二區域 412 第二區域 10 陰極電鍍針頭 43 電鍍核種層 41 基板 44 第二介電層 42 第一介電層 201 第一光罩 1312 1269422 [Description of main components of the drawings] 1 substrate 202 second mask 11 electroplated core layer 203 third mask 12 dielectric layer 204 fourth mask 31 window 501 first window 32 window 502 second window 21 First mask 503 third window 22 second mask 504 fourth window 111 first region 411 first region 112 second region 412 second region 10 cathode plating needle 43 plating core layer 41 substrate 44 second dielectric layer 42 First dielectric layer 201 first mask 13