CN101145533A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN101145533A
CN101145533A CNA2007101807338A CN200710180733A CN101145533A CN 101145533 A CN101145533 A CN 101145533A CN A2007101807338 A CNA2007101807338 A CN A2007101807338A CN 200710180733 A CN200710180733 A CN 200710180733A CN 101145533 A CN101145533 A CN 101145533A
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pad electrode
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CN100536103C (zh
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千叶修一
石栗雅彦
村田浩一
渡边英二
玉川道昭
佐藤明
户井田安司
三泽和博
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Socionext Inc
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Abstract

半导体装置包括基板、形成在前述基板上的衬垫电极和形成在前述衬垫电极上的凸块电极，前述衬垫电极具有凹凸状的压痕，在前述衬垫电极和前述凸块电极之间设置有覆盖前述凹凸压痕的图案。

Description

半导体装置的制造方法
本申请是申请日为2002年6月21日、申请号为02829105.0、发明名称为“半导体装置及其制造方法”的申请的分案申请。
技术领域
本发明一般与半导体装置有关，特别是涉及半导体装置的衬垫电极结构。
半导体装置中，一般为了将半导体基板上的半导体元件内部所形成的衬垫电极，与半导体元件安装用的基板(内插板等)电气或机械连接，需要在衬垫电极上形成作为外部连接用的突起电极的凸块。
背景技术
一般地，半导体装置的制造的时候，在半导体装置的制造工序结束时，有必要确认示出各半导体元件在电气方面正常动作的情况。为此，在半导体基板的表面上形成的衬垫电极上接触探针，进行电气方面的动作试验。
前述动作试验中，由于有必要将探针按压到由Al或Cu形成的衬垫电极上，所以在衬垫电极表面上由前端尖利的探针变形为凹凸状的压痕(以下称为探针痕)残留下来。
图1是表示形成探针痕的衬垫电极上形成有凸块的情况下的半导体装置的图。
参照图1，半导体基板10上形成有衬垫电极20，进而为使前述的衬垫电极20露出来，形成有钝化膜30。此外，前述衬垫电极20上，动作试验的结果，形成有探针痕40。
这样的衬垫电极20上，Ti层60和Cu层61分别作为粘合层和导电层，利用喷溅法，各自形成为300nm和250nm的厚度，进而，将前述导电层61作为电极进行电镀，而分别形成4000nm和200nm厚度的Ni层80和Au层90。前述Au层90是作为Ni层80的氧化防止膜而起作用的。
进而，前述Au层90上，利用Sn-Ag系等的无铅焊锡，或Sn-Pb系等的铅焊锡，形成凸块电极100。
然而，图1的例子中，如前面所说的那样动作试验的结果，虽然在前述衬垫电极20上形成探针痕40，但由于探针痕40是以凹凸状的，所以即使进行喷溅处理，也存在前述粘合层60或者Cu层61也不能均一地形成的情况。前述Ti层60或者Cu层61非常薄，只有200～300nm程度的厚度，所以如这样地在基底上存在凹凸的情况下，要形成一样的膜是不可能的。
因此，通过以Cu层61为电极的电镀而形成Ni层80和Au层90的情况下，这些层也不能在探针痕40上成长，从而，凸块100在前述Au层90上形成的情况下，存在与前述探针痕40对应地，在衬垫电极20和凸块电极100之间形成空洞110的情况。
在凸块电极100的下面有这样的空洞110的情况下，利用凸块电极连接的电气的或者机械的特性劣化，半导体装置的可靠性降低。此外，经由这些Ti层和Cu层没有形成的区域，作为凸块电极100的材料的Sn、Ag、Pb、Ni等金属元素扩散到衬垫电极20中，或者构成衬垫电极20的Al扩散到凸块电极10中，并发生连接电阻上升的问题。
因此，现有技术中，在电极衬垫表面上不能直接接触探针，在半导体装置上设置作为探针检查用的另外的电极衬垫而用于试验用，进行电气的动作试验。如这样的方法中，除了形成凸块电极的衬垫电极之外，因为设置作为探针检查用的另外的衬垫电极，所以导致半导体装置的面积增大。
发明内容
在此，本发明解决了上述的课题，以提供一种新颖、有用的半导体装置制造方法作为具体的课题。
本发明的更具体的课题是提供一种半导体装置，其在接触到探针的衬垫电极上，能够直接形成凸块电极。
本发明的其它的课题是提供一种半导体装置，其包括基板、在前述基板上形成的衬垫电极和在前述衬垫电极上形成的凸块电极，其特征在于：
前述衬垫电极具有凹凸状的压痕；
在前述衬垫电极和前述凸块电极之间，设置有覆盖前述凹凸状的压痕的图案。
本发明的其它的课题是提供一种半导体装置的制造方法，其特征在于包括：
在基板上形成衬垫电极的工序；
在前述衬垫电极上接触探针而进行试验的工序；
在前述衬垫电极表面的一部分，按照覆盖由前述探针的接触而产生的凹凸的方式形成图案的工序；
在前述衬垫电极表面上，按照覆盖前述图案的方式形成导电膜的工序，
利用电镀法，在电极上形成前述导电膜，在前述衬垫电极上形成导电性基底膜的工序；
在前述导电性基底膜上形成凸块电极的工序。
本发明的其它的课题是提供一种半导体装置的制造方法，其特征在于包括：
在基板上形成衬垫电极的工序；
在前述衬垫电极上接触探针而进行试验的工序；
将由前述探针的接触而产生的凹凸状的压痕平坦化的工序；
在前述衬垫电极表面，按照覆盖前述被平坦化了的凹凸状的压痕的方式，形成导电膜的工序；
将前述导电膜作为电极，并利用电镀法，在前述衬垫电极上的前述导电膜上形成导电性基底膜的工序；
在前述导电性基底膜上形成凸块电极的工序。
本发明的其它的课题是提供一种半导体装置的制造方法，其特征在于包括：
在基板上形成多个衬垫电极的工序；
在前述多个衬垫电极的每一个上分别接触探针而进行试验的工序；
在前述基板的整个面上，在前述多个衬垫电极的每一个中，分别按照覆盖由前述探针的接触而产生的凹凸的方式形成导电膜的工序；
在前述多个衬垫电极的每一个中，将前述导电膜作为电极，并分别利用电镀法，在前述衬垫电极上的前述导电膜上形成导电性基底膜的工序；
在前述多个衬垫电极的每一个中，分别在前述导电性基底膜上形成凸块电极的工序，
在前述多个衬垫电极的每一个中，前述导电膜具有超过由前述凹凸形成的阶差的厚度。
根据本发明，探针检查时由于使用探针而具有凹凸状的压痕(以下称为探针痕)的衬垫电极上，形成保护膜或进行平坦化处理，从而在前述电极衬垫上，能够包括前述探针痕的部分而形成导电层，将该导电层对电极进行电镀处理而形成导电图案，从而前述衬垫电极上的凸块电极的形成成为可能。此时，本发明中，无需配置另外测试用的衬垫电极，能够有效地利用基板表面，此外，可将半导体装置微细化。
本发明的其它的特征和优点，通过下面参照附图进行的对发明的优选实施例的详细说明而会变得更清楚。
附图说明
图1是表示形成探针痕的衬垫电极上形成有凸块时的半导体装置的图；
图2是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的图；
图3是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图4是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图5是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图6是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图7是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图8是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图9是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图10是表示根据本发明的第1实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图11是表示根据本发明的第2实施方式的向衬垫电极上的凸块形成的过程的图；
图12是表示根据本发明的第2实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图13是表示根据本发明的第2实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图14是表示根据本发明的第2实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图15是表示根据本发明的第3实施方式的向衬垫电极上的凸块形成的过程的其它的图；
图16是表示根据本发明的第3实施方式的向衬垫电极上的凸块形成的过程的其它的图。
具体实施方式
[第1实施例]
图2～10是表示根据本发明的第1实施方式的半导体装置的制造工序的图。
A.衬垫电极和基板保护膜的形成工序
参照图2，在形成晶体管以及多层布线(图中未示出)的半导体基板210的表面的周边缘部，用电子束蒸镀法或喷溅法形成铝膜，通过将其制作成图案而形成衬垫电极220。然后，在前述衬垫电极220上，按照覆盖衬垫电极220的方式，形成成为保护膜的氮化硅膜230，并且，在前述保护膜230中，按照露出前述衬垫电极220的方式，形成开口部。
B.半导体装置的探针检查工序
形成图2所示的结构之后，图3的工序中，为确认电气信号，进行探针检查。
其结果，如图3所示，在前述探针检查之后，在衬垫电极220上，由于探针碰压而残留凹凸状的压痕的探针痕240(以下称为探针痕)。
C.衬垫电极表面的探针痕上形成氮化硅膜的工序
进而，图4的工序中，在图3的结构上，按照覆盖探针痕240的方式，形成氮化硅膜等的膜，进一步，将其形成图案，并与前述探针痕240对应地形成覆盖前述探针痕240的氮化硅膜250。
D：Ti层和Cu层的形成工序
接下来，图5的工序中，在图4的结构之上，按照覆盖前述衬垫电极220和氮化硅膜250的方式，利用喷溅法，依次形成厚度分别为300nm和200nm的Ti层260和Cu层261。
E.抗蚀膜的形成图案工序
接着，图6的工序中，在图5的结构上形成抗蚀膜270，将其按照覆盖衬垫电极220以外的区域的方式形成图案。
F.Ni层和Au层的形成工序
然后，图7的工序中，在图6的结构上，利用电镀法形成4000nm厚度的Ni层280，进一步，在Ni层280上作为氧化防止膜形成200nm厚度的Au层290。
G.抗蚀膜的除去工序
接着，图8工序中，执行灰化处理，除去图7的抗蚀膜270。
H.Ti层和Cu层的蚀刻工序
下面，图9的工序中，将衬垫电极220上形成的Ni层280和Au层290用掩模盖住，将衬垫电极220以外的区域所形成的Ti层260和Cu层261通过蚀刻或者离子蚀刻而除去。
I.凸块的形成工序
进而，图10的工序中，在Au层290上，通过印刷法、复制法、电镀法之中的任意一个方法，形成由Sn-Ag系合金形成的无铅焊锡或者由Sn-Pb系合金形成的铅焊锡。之后，对前述焊锡进行热处理，而形成凸块电极300。
然而，本实施例子中，按照覆盖衬垫电极220表面的探针痕240的方式，形成保护膜、例如无机膜的氮化硅膜图案250，由此在衬垫电极220上，按照覆盖前述氮化硅膜图案250的方式，能够连续地形成Ti层260和Cu层261，所以在前述衬垫电极220上，通过电镀法连续地形成Ni图案280或者Au图案290，使得与前述衬垫电极220对应的区域能够一样地被覆盖，其结果即使形成了凸块电极300，在其下面不会形成如现有的空洞。在前述粘合层260、261和衬垫电极220之间形成氮化硅膜250，对于衬垫电极220上有压痕的情况，例如存在探针痕的情况，是非常有效的。
此外，本实施例中，前述保护膜图案250是氮化硅膜等的绝缘膜，但本发明并不限定于此，也可以将氧化硅膜等的其它绝缘膜，或者聚酰亚胺树脂等的有机膜，或者金属或合金等的导电膜作为保护膜图案250而使用。例如，替代前述保护膜图案250，而形成作为导电性的膜的糊状的Ag、Pt、Pd、Cu之中任意一种也都能得到同样的效果。
[第2实施例]
图11～14是表示根据本发明的第2实施方式的半导体装置的制造工序的图。但是，图中与先前说明过的部分对应的部分，赋予同一的参照符号，省略说明。
A.半导体装置的探针检查工序
如图11所示，在半导体基板210上，形成衬垫电极220和基板保护膜230以后进行的探针检查的结果，衬垫电极220表面的凹凸状的压痕作为探针痕240而残留。
B.利用干刻法的探针痕的平坦化工序
接下来，如图12所示，以前述衬垫电极220的表面上包含探针痕240的方式进行干刻，平坦化探针痕240。
C.Ti层和Cu层的形成工序
下面，图13的工序中，在图12的结构上，利用喷溅法，按照覆盖前述基板保护膜230及衬垫电极220的方式，依次形成厚度分别为300nm和200nm的Ti层260和Cu层261。
D.凸块的形成工序
之后，经过实施例1的图6～9所示的工序后，如图14所示，在衬垫电极220上的Cu层261的上面，Ni层280以4000nm的厚度，此外Au层290以200nm的厚度形成，进而，通过形成Sn-Ag系无铅合金焊锡或者是Sn-Pb系的铅合金焊锡，并进行热处理，而形成凸块电极300。
这样，本实施方式中，将探针痕240的凹凸阶差通过平坦化而减小，从而能够使Ti层260以及Cu层261在衬垫电极220上连续地、一样地形成，在不产生空洞的情况下能够形成凸块电极300。
此外，本实施例中，探针痕240的平坦化是利用干刻法进行的，但用湿刻法来代替也能得到同样的效果。另外，代替干刻法，也可以将衬垫电极220在600～800℃的温度下熔解来进行探针痕240的平坦化处理。进一步，代替干刻法，对于探针痕240施加机械压力，使用物理方法将探针痕240平坦化，也能得到同样的效果。
[第3实施例]
图15～16是表示根据本发明的第3实施方式的半导体装置的制造工序的图。但在图中，与先前说明过的部分对应的部分赋予同一参照符号，省略说明。
参照图15，本实施例中，在探针检查之后，按照覆盖探针痕240的形成后的衬垫电极220以及钝化膜230的方式，利用喷溅法，以比先前的实施例更厚的，例如500nm的膜厚依次形成Ti层262和Cu层263。
然后，经过先前图6～9所示的工序后，如图16所示，在衬垫电极220上的Cu层263的上面，Ni层280以4000nm的厚度，此外Au层以200nm的厚度通过电镀法形成，进而，形成由Sn-Ag系合金形成的无铅焊锡，或者由Sn-Pb系合金形成的铅焊锡。之后，对前述合金焊锡进行热处理，形成凸块300电极。
本实施方式中，这样地，使Ti层262和Cu层263厚些，最好与前述探针痕240的阶差相等，或者超过此的例如1um的程度的厚度来形成，从而探针痕240的凹凸状的阶差相对就变小，或者变得能够无视了，能够将前述Ti层262和Cu层263在前述衬垫电极220上连续形成。
此外，以上的各实施方式中，粘合层260并不限定于Ti层，也可以由Ti、Cr、TiW、Mo、Ta、W、Nb、V之中的任意一种来构成。另外，前述电极层261并不限定于Cu，也可以是Ni、Cu、Pd、Pt、Au、Ag之中的任意一种来构成。进一步，形成这些的过程并不限定于喷溅法，也能由蒸镀法或者MOCVD法来形成。
另外，成为前述凸块的基底层(UBM层：under bump metal)的导电层280并不限定于Ni层，也可以由含有Ni、Cu的合金来构成。此外，前述氧化防止膜290并不限定于Au，也可以由Pt、Pd、In之中的任意一种来形成。
并且，前述凸块电极300并不限定于Sn-Ag合金或者Pb-Sn合金，也可以是Pd、Ni、Cu、Sn及Pb的合金，或者是Au、Ag。
以上详细记述了本发明的优选实施例，但本发明并不限定于相关的特定的实施方式，在权力要求书所述的本发明的要旨的范围内的各种变形、变更也是可能的。
根据本发明，基板上形成的衬垫电极即使有凹凸状的压痕，也可以在其上面稳定地连续形成导电膜，通过将这样的导电膜对电极进行电镀，可在衬垫电极的整个面形成导电层。其结果，在这样的导电层上，稳定地不产生空洞的形成而形成凸块电极。
根据本发明，探针电极所接触的衬垫电极上也可以形成凸块电极，因此不需要另外形成测试用的凸块电极，可有效地利用基板表面，从而可将半导体装置微细化。

Claims (6)

1.一种半导体装置的制造方法，其特征在于包括：
在基板上形成衬垫电极的工序；
在前述衬垫电极上接触探针而进行试验的工序；
将由前述探针的接触而产生的凹凸状的压痕平坦化的工序；
在前述衬垫电极表面，按照覆盖前述被平坦化了的凹凸状的压痕的方式，形成导电膜的工序；
将前述导电膜作为电极，并利用电镀法，在前述衬垫电极上的前述导电膜上形成导电性基底膜的工序；
在前述导电性基底膜上形成凸块电极的工序。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，前述平坦化工序包含对前述凹凸状的压痕进行干刻的工序。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于，前述平坦化工序包含对前述凹凸状的压痕进行湿刻的工序。
4.根据权利要求1所述的半导体装置的制造方法，其特征在于，前述平坦化工序包含在600～800℃下熔解前述衬垫电极的工序。
5.根据权利要求1所述的半导体装置的制造方法，其特征在于，前述平坦化工序是对前述凹凸状的压痕施加机械压力的工序。
6.一种半导体装置的制造方法，其特征在于包括：
在基板上形成多个衬垫电极的工序；
在前述多个衬垫电极的每一个上分别接触探针而进行试验的工序；
在前述基板的整个面上，在前述多个衬垫电极的每一个中，分别按照覆盖由前述探针的接触而产生的凹凸的方式形成导电膜的工序；
在前述多个衬垫电极的每一个中，将前述导电膜作为电极，并分别利用电镀法，在前述衬垫电极上的前述导电膜上形成导电性基底膜的工序；
在前述多个衬垫电极的每一个中，分别在前述导电性基底膜上形成凸块电极的工序，
在前述多个衬垫电极的每一个中，前述导电膜具有超过由前述凹凸形成的阶差的厚度。
CNB2007101807338A 2002-06-21 2002-06-21 半导体装置的制造方法 Expired - Fee Related CN100536103C (zh)

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EP1517364B1 (en) 2011-03-16
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EP1517364A1 (en) 2005-03-23
CN100382262C (zh) 2008-04-16
TW546841B (en) 2003-08-11
WO2004001839A1 (ja) 2003-12-31
CN1628379A (zh) 2005-06-15
DE60239493D1 (de) 2011-04-28
US7095045B2 (en) 2006-08-22
CN100536103C (zh) 2009-09-02
EP1517364A4 (en) 2006-06-07
KR20040111695A (ko) 2004-12-31
JP3978449B2 (ja) 2007-09-19

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