TW202403895A - 低溫接合結構 - Google Patents

低溫接合結構 Download PDF

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TW202403895A
TW202403895A TW112137842A TW112137842A TW202403895A TW 202403895 A TW202403895 A TW 202403895A TW 112137842 A TW112137842 A TW 112137842A TW 112137842 A TW112137842 A TW 112137842A TW 202403895 A TW202403895 A TW 202403895A
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Taiwan
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conductive
metallic
substrate
metal
feature
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TW112137842A
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English (en)
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賽普里恩 艾米卡 烏佐
傑瑞米 提爾
亮 王
拉杰詡 卡特卡
桂蓮 高
蘿拉 威爾 麥卡雷米
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美商艾德亞半導體接合科技有限公司
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Publication of TW202403895A publication Critical patent/TW202403895A/zh

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Abstract

本發明提供裝置及技術，其包括利用導電互連結構中之凹槽以形成可靠的低溫金屬接合之程序步驟。在接合之前，將填充層沉積至這些凹槽中。使用直接接合技術將第一導電互連結構在環境溫度下接合至第二金屬互連結構，此利用該第一互連結構及該第二互連結構中之一者或兩者中之這些凹槽中的這些填充層。

Description

低溫接合結構
以下描述係關於積體電路（IC）。更特定而言，以下描述係關於製造IC晶粒及晶圓。 優先權要求及對相關申請案之交叉參考
本申請案根據35 U.S.C. § 119(e)(1)主張2019年3月25日申請之美國非臨時申請案第16/363,894號及2018年4月11日申請之美國臨時申請案第62/656,264的權益，這些申請案以全文引用之方式併入本文中。
微電子元件通常包含諸如矽或砷化鎵之半導體材料的薄厚塊，其通常被稱為半導體晶圓。晶片可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個積體晶片或晶粒。與晶圓分開之晶粒通常經提供為個別預封裝單元。在一些封裝設計中，晶粒經安裝至基板或晶片載體，該基板或晶片載體又安裝在諸如印刷電路板（printed circuit board；PCB）之電路面板上。舉例而言，許多晶粒係提供於適合表面安裝之封裝中。
亦可以「堆疊」配置來提供經封裝半導體晶粒，其中一個封裝係提供於例如電路板或其他載體上，且另一封裝安裝於第一封裝之頂部上。此等配置可允許將數個不同晶粒安裝於電路板上之單個佔據區內，且可進一步藉由在封裝之間提供短互連件來促進高速操作。此互連距離通常可僅略大於晶粒自身之厚度。對於待在晶粒封裝之堆疊內達成的互連，用於機械及電連接之互連結構可提供於每一晶粒封裝（除了最頂封裝）以外之兩側（例如，面）上。
另外，晶粒或晶圓可以三維配置堆疊作為各種微電子封裝方案之部分。此可包括在較大基底晶粒、裝置、晶圓、基板或其類似者上堆疊一或多個晶粒、裝置及/或晶圓之層，以豎直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。可使用各種接合技術以堆疊配置來接合晶粒或晶圓，這些接合技術包括直接介電質接合、無黏著劑技術（諸如，ZiBond®）或混合接合技術（諸如，DBI®），兩者均可自Invensas接合技術公司（先前係Ziptronix公司）、Xperi公司購得（例如，參見美國專利第6,864,585號及第7,485,968號，這些專利之全文併入本文中）。
對於實施堆疊晶粒及晶圓配置可存在多種挑戰。當使用直接接合或混合接合技術來接合堆疊晶粒時，通常需要待接合之晶粒的表面極平坦、光滑且潔淨。舉例而言，這些表面一般應具有極低的表面拓樸變化（亦即，奈米尺度變化）使得這些表面可緊密配合以形成持續接合。
然而，用以製備接合表面之諸如化學機械拋光（chemical-mechanical polishing；CMP）及其類似者的一些處理技術亦可有助於形成不均勻接合表面，特別係在接合表面包括不同密度之不同材料時。舉例而言，接合表面處之嵌入式金屬結構可在接合表面拋光期間過度凹入，且當金屬結構具有大的曝露表面積時在較大程度上凹入。
另外，可能需要接合鄰近堆疊晶粒之嵌入式金屬結構以在晶粒之間形成導電互連件。通常，使用加熱退火技術來接合金屬結構以形成擴散接合。然而，用以執行退火技術之溫度對於一些所需封裝方案或組件或封裝中之至少一或多種材料而言通常可能過高，因此限制可利用此等技術之方案及組件之類型或材料之組合。
揭示代表性技術及裝置，包括用於利用互連結構中之凹槽以形成可靠的低溫金屬（例如，混合）接合的程序步驟。在各種實施方案中，可使用直接接合技術將第一金屬互連結構在環境溫度下接合至第二金屬互連結構，此利用第一互連結構及第二互連結構中之一者或兩者中的凹槽。出於此目的，凹槽可形成於互連結構中，或可運用此創新技術來補救由CMP（及其類似者）產生之凹槽。具有較大表面積之互連襯墊及具有較深凹陷之其他襯墊可特別有益。
在各種實施方案中，一種用於形成一微電子組裝件之方法包括：平坦化一第一基板之一接合表面，其中該第一基板包括嵌入至該第一基板之該接合表面中的一第一金屬襯墊；及將一第一金屬材料沉積至該第一金屬襯墊之一表面上。又，平坦化一第二基板之一接合表面，其中該第二基板包括嵌入至該第二基底之該接合表面中的一第二金屬襯墊；及將一第二金屬材料沉積至該第二金屬襯墊之一表面上。接著，經由直接接合而無黏著劑來將該第二基板之該接合表面接合至該第一基板之該接合表面。
在一實施方案中，該方法包括經由浸漬無電極金屬沉積或類似技術來沉積該第一金屬材料及/或該第二金屬材料。在另一實施方案中，該方法包括在該第一金屬襯墊與該第二金屬襯墊之間形成一共晶合金塊（alloy mass），其中該共晶合金塊或接近共晶組成物合金塊包含該第一金屬材料及該第二金屬材料之一合金。
該方法可包括：在該第一金屬襯墊之一表面中形成一第一凹入部分及在該第二金屬襯墊之一表面中形成一第二凹入部分；及用該第一金屬材料至少部分地填充該第一凹入部分及用該第二金屬材料至少部分地填充該第二凹入部分。在一些具體實例中，該方法包括在沉積該第一金屬材料或該第二金屬材料之前分別將一導電障壁層沉積至該第一金屬襯墊之該表面及/或該第二金屬襯墊之該表面上。
在額外實施方案中，技術及方法包括形成一微電子組裝件，該微電子組裝件包含：一第一基板，其具有具一平坦化形貌(topography)之一接合表面及在該第一基板之該接合表面處的第一複數個金屬襯墊或跡線或其組合；及一第二基板，其具有具一平坦化形貌之一接合表面，該接合表面接合至該第一基板之該接合表面。該第二基板之該接合表面處的第二複數個金屬襯墊接合至該第一複數個金屬襯墊。該第一複數個金屬襯墊及/或該第二複數個金屬襯墊包含兩種或多於兩種導電材料。
在一些實施方案中，一第一凹入部分安置於該第一複數個金屬襯墊之一表面中，該第一凹入部分在該第一複數個金屬襯墊之該表面下方延伸一預選深度，或在該第一基板之該接合表面下方延伸一預選深度。該第一凹入部分至少部分地填充有不同於該第一複數個金屬襯墊之一導電材料的一第一導電材料。另外，一第二凹入部分可安置於該第二複數個金屬襯墊之一表面中，該第二凹入部分在該第二複數個金屬襯墊之該表面下方延伸一預選深度，或在該第二基板之該接合表面下方延伸一預選深度。該第二凹入部分至少部分地填充有不同於該第二複數個金屬襯墊之一導電材料的一第二導電材料。
在一替代實施方案中，一障壁層安置於該第一凹入部分及/或該第二凹入部分內。該障壁層包含一第三導電材料，該第三導電材料不同於該第一導電材料或該第二導電材料且不同於該第一複數個金屬襯墊或第二複數個金屬襯墊之該導電材料。
在一些實施方案中，一合金塊（例如，一共晶合金塊）安置於該第一複數個金屬襯墊與該第二複數個金屬襯墊之間，其中該合金塊包含該第一導電材料及該第二導電材料之一合金。在一些實例中，該第一複數個金屬襯墊或該第二複數個金屬襯墊與該合金塊之間的區係非線性的。
參考電組件及電子組件以及變化之載體來論述各種實施方案及配置。雖然提及特定組件（亦即，晶粒、晶圓、積體電路（IC）晶片晶粒、基板等），但此並不意欲為限制性的且係為了易於論述及便於說明。參考晶圓、晶粒、基板或其類似者論述之技術及裝置適用於任何類型或數目之電組件、電路（例如，積體電路（IC）、混合電路、ASIC、記憶體裝置、處理器等）、組件群組、封裝式組件、結構（例如，晶圓、面板、板、PCB等）及其類似者，其可經耦接以彼此介接，與外部電路、系統、載體及其類似者介接。此等不同組件、電路、群組、封裝、結構及其類似者中之每一者可一般被稱作「微電子組件」。為簡單起見，除非另外指定，否則接合至另一組件之組件將在本文中被稱作「晶粒」。
此概述並不意欲給出完整描述。在下文使用複數個實例更詳細地解釋實施方案。儘管在此處且在下文論述各種實施方案及實例，但其他實施方案及實例可藉由組合個別實施及實例之特徵及元件而成為可能。
綜述
圖1至圖6說明用於形成及製備用於接合（諸如，用於直接接合而無黏著劑）之各種微電子組件（諸如，晶粒102及組裝件118）的代表性裝置以及程序100及300至600。程序100及300至600包括：在微電子組件上提供一接合表面（諸如，接合表面108）或在一些實例中提供兩個接合表面（圖中未示）；提供嵌入至接合表面中之導電互連結構；修復或緩解接合表面中由於處理或缺陷之侵蝕、凹陷及其類似者；藉由在接合表面處直接接合微電子組件來形成微電子組裝件；等等。
描述程序100及300至600之次序並不意欲解釋為限制性的，且可按任何次序組合程序100及300至600中之任一者中的任何數目個所描述程序區塊以實施這些程序或替代程序。另外，可自程序中之任一者刪除個別區塊而不脫離本文中所描述之主題之精神及範圍。此外，程序100及300至600可以任何合適之硬體、軟體、韌體或其組合實施，而不脫離本文中所描述之主題之範圍。在替代實施方案中，其他技術可以各種組合包括於程序100及300至600中，且保持在本發明之範圍內。
參看圖1，可使用各種技術形成代表性「晶粒」 102以包括基底基板104及絕緣或介電層106。基底基板104可包含矽、鍺、玻璃、石英、介電性表面、直接或間接能隙半導體材料或層或另一合適材料。絕緣層106沉積或形成於基板104上方，且可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、類金剛石材料、玻璃、陶瓷、玻璃陶瓷及其類似者。
晶粒102之接合表面108可包括導電特徵110，諸如嵌入至絕緣層106中且經配置使得來自各別接合表面108之導電特徵110可在接合期間視需要配合及接合的互連結構。接合的互連特徵110可形成堆疊晶粒102之間的連續導電互連件（用於信號、電力等）。
鑲嵌製程（或其類似者）可用以在絕緣層106中形成嵌入式導電特徵110。導電特徵110可包含金屬（例如，銅等）或其他導電材料或材料組合，且包括結構、跡線、襯墊、圖案等。導電特徵110可包括於絕緣層106中以提供電及/或熱路徑，或可替代地經組態以經由使用額外襯墊或所謂的虛設襯墊、跡線、圖案或其類似者來平衡接合表面108之金屬化。在形成導電特徵110之後，可平坦化包括絕緣層106及導電特徵110之晶粒102的曝露表面以形成平坦接合表面108。
如圖1中所展示，在區塊A處，可平坦化（使用化學機械拋光（chemical-mechanical polishing；CMP）或其類似者）包括嵌入式互連結構110之晶粒102的一或多個接合表面108以製備表面108用於接合。形成接合表面108包括修整表面108以符合介電粗糙度規格及金屬層（例如，銅等）凹槽規格，以製備表面108用於直接接合。換言之，接合表面108經形成為儘可能平坦及光滑的，且具有極小表面拓樸變化。諸如化學機械拋光（CMP）之各種習知製程可用以達成低表面粗糙度。此製程提供平坦光滑表面108，其導致晶粒102之間的可靠接合。在一些狀況下，導電特徵110之曝露表面可有意地凹入，以允許材料膨脹，特別係在加熱退火期間（若應執行加熱退火）。
如圖1中所展示，在區塊B處，由於互連特徵110之材料（例如，金屬等）及絕緣層106之介電材料的性質（機械性質、拋光速率等之差異）之不連續性以及其與拋光墊之各別相互作用、其硬度、拋光漿液及其他製程參數，平坦化可在接合表面108上具有高金屬圖案密度之區域中產生介電質侵蝕（圖中未示）及在金屬特徵110之曝露表面中產生凹陷（亦即，凹槽112）。一般而言，表面108上之金屬圖案密度愈高，侵蝕愈大，且類似地，金屬特徵110之表面的面積愈大，凹槽112愈大（亦即，愈深）。如在區塊B處所展示，特徵110之凹陷可在晶粒102之整個表面拓樸中產生顯著的變化（例如，具有深度（「d1」））。在一些狀況下，拓樸變化可足夠大以使晶粒102之間的直接接合變弱或降低表面變化（例如，凹槽112）之部位處的接合可靠性。
在互連特徵110之曝露表面上的過度凹槽112之結果當中，互連特徵110之表面的平坦度不良且相比通常需要的低溫，典型地需要高得多的溫度以在晶粒102之金屬特徵110之間形成連續導電互連。在導電特徵110具有極大面積襯墊之情況下，相對於相對互連特徵，凹槽112可能太深而無法在無不合需要的空隙缺陷之情況下緊密配合，此係因為金屬在退火溫度下可能不會充分膨脹以形成接合的連續導電層。因此，當導電特徵110之表面接合或附接至其他裝置或基板時，該表面上之不良平坦度通常產生有缺陷的接合。
然而，在各種具體實例中，具有預選深度（「d1」）之凹陷或凹槽112可有意地形成於導電特徵110之表面中，以製備用於低溫（例如，環境溫度、室溫、低於100℃）接合技術之導電特徵110，如本文中所揭示。凹槽112在預選深度（「d1」）處之有意形成可在形成導電特徵110時實現，或可在形成導電特徵之後藉由平坦化、蝕刻或其類似者實現。在一些具體實例中，凹槽112之預選深度（「d1」）可取決於導電特徵110之曝露部分之表面積。舉例而言，具有較大表面積及/或較厚導電層之導電特徵110可具有或具備較深凹槽112，且具有較小表面積及/或較薄導電層之導電特徵110可具有或具備較淺凹槽112。 實例具體實例
技術及裝置包括利用互連特徵110中之凹槽112以形成可靠的低溫金屬接合之程序步驟。在實施方案中，可使用直接接合技術將第一晶粒102處之第一金屬互連特徵110在環境溫度（例如，低於100℃）下接合至第二晶粒102處之第二金屬互連特徵110，此利用第一及第二互連特徵110中之一者或兩者中的凹槽112。出於此目的，凹槽112可形成於互連特徵110中，或可運用此創新技術來補救由CMP（及其類似者）產生之凹槽112。具有較大表面積之互連特徵110及具有較深凹陷之其他特徵可特別有益。
參看圖1、區塊C及D，在一實施方案中，用一或多個導電（例如，金屬等）填充層114及/或116填充金屬互連特徵110中之凹槽112，這些導電填充層在將具有填充層114、116之互連特徵110按壓在一起時形成導電合金塊202（參見圖2）。換言之，在一些具體實例中，第一及第二互連特徵110中之每一者中的一或多個額外金屬填充層114、116在緊密接觸後熔融在一起以形成導電合金塊202，該導電合金塊亦熔融至各別的第一及第二互連特徵110，從而形成低溫接合的導電互連件204。在一些具體實例中，導電合金塊202包含共晶合金塊或接近共晶合金塊之組成物。
在一具體實例中，各別的第一及第二互連特徵110處之金屬填充層114及116在相比熔融第一及第二互連特徵110（藉由退火等）所需之溫度相對較低的溫度下熔融在一起以形成導電合金塊202。包含導電合金塊202之層（包括填充層114及116）的接合溫度低於包含無填充層114或116之互連特徵110之相對層的接合溫度。在一些具體實例中，填充層114及/或填充層116之熔點低於第一及第二互連特徵110中之一者或兩者的材料之熔點。可選擇一或多個金屬填充層114、116之材料，使得材料之組合形成熔點高於填充層114及116中之任一者及第一及/或第二互連特徵110之金屬的合金。
舉例而言，如在區塊C處所展示，將第一金屬填充層114形成、添加、沉積、塗佈或其類似者於第一晶粒102之第一互連特徵110的曝露表面上。以預選厚度形成填充層114以將凹槽112自較大深度（「d1」）減少至較小深度（「d2」）。舉例而言，深度（「d2」）可係針對材料膨脹而選擇且允許可靠直接接合之所要或預選深度。在各種具體實例中，深度（「d2」）可取決於第一互連特徵110之材料、第一填充層114之材料、第一互連特徵110之大小或面積、待發生之退火製程之溫度及持續時間，以及其類似者。
儘管在區塊B處僅展示一個深度（「d1」），從而僅指示一個凹槽深度，但取決於第一互連特徵110之襯墊的大小或如先前所提及之其他原因，兩個或多於兩個此等深度在同一晶粒102上亦係可能的。添加填充層114及116亦可在同一晶粒102處形成兩個或多於兩個對應深度（「d2」）。
在一實施方案中，第一填充層114可藉由原子層沉積方法（或其類似者）選擇性地無電極鍍敷、氣相塗佈或沉積至第一互連特徵110之表面上。又，第一填充層114可連續（如在區塊C處以114展示）或不連續（如在區塊C處以114'展示）。在一具體實例中，第一填充層114可包含銦、銦合金或類似金屬或材料。不連續填充層114'不大可能降低包括填充層114'（係極薄層）之接合結構之材料的導電性，同時仍加強互連結構110之間的接合材料。
如在區塊D處所展示，將第二金屬填充層116形成、添加、沉積或其類似者於第二晶粒102之第二互連特徵110的曝露表面上。如前所述，可以預選厚度形成填充層116以將凹槽112減少至所要深度（d2或未必相同於如區塊C處所展示之深度「d2」的深度d2'）。在一具體實例中，第二填充層116可藉由原子層沉積方法（或其類似者）選擇性地無電極鍍敷、氣相塗佈或沉積至第二互連特徵110之表面上。亦類似地，第二晶粒102或基板之互連特徵110上的第二填充層116可連續（如在區塊D處以116展示）或不連續（如在區塊D處以116'展示）。在一具體實例中，第二填充層116可包含鎵、錫、其各別合金或類似金屬或材料。
在一些具體實例中，第一填充層114及第二填充層116包含不同材料。然而，在一替代具體實例中，第一填充層114及第二填充層116包含相同材料。在一些替代具體實例中，可將額外填充層（圖中未示）添加至第一填充層114及/或第二填充層116（在沉積第一填充層114及/或第二填充層116之前或之後）。儘管填充層114及116在本文中論述為金屬層，但其各自可為兩種或多於兩種金屬、兩種或多於兩種合金或其類似者之組合。
在不同實施方案中，第一填充層114及第二填充層116可藉由各種手段而沉積於凹入的互連特徵110上。在一個實施方案中，諸如直接置換反應或自催化金屬沉積製程之無電極製程用於以精確控制選擇性地在凹入的互連特徵110（例如，銅）上方沉積填充層114、116。在一個實例中，可使用無電極浸漬沉積製程。在各種具體實例中，此製程可用以沉積金、銀、鈀、鎳、銦、鎵、鈷、鍺或任何其他金屬或其組合或其類似者之第一填充層114及第二填充層116。在這些具體實例中，該製程維持低成本，此係因為其不使用微影、真空、加熱且在沉積之後不需要額外CMP。
在另一具體實例中，可對晶粒102（或晶圓）中之一者或兩者執行額外CMP步驟。由於取決於襯墊110之不同直徑，兩個或多於兩個凹槽112可能在晶粒102（或晶圓）上，因此拋光或CMP步驟可自一些襯墊110而不自其他者移除材料。
如在區塊E處所展示，在環境溫度（例如，低於100℃）下使用直接介電質至介電質接合（無黏著劑）來接合第一及第二晶粒102。此包括使每一晶粒102之製備好的接合表面108之非金屬區接合一起使得接合表面108彼此接觸且接合。第一及第二晶粒102之接合形成微電子組裝件118。在替代具體實例中，晶粒102之絕緣層106直接接合至另一晶粒102上之相同或類似材料的另一絕緣層106，或在一些實例中，另一晶粒102可能不具有分開的絕緣層106且接合發生於晶粒102之絕緣層106（例如，氧化矽）與例如另一晶粒102上之矽層之間。
在該程序中，將第一填充層114及第二填充層116按壓在一起，以在低於200℃且較佳低於170℃或100℃之後續溫度下將互連特徵110接合成固體互連結構204。在一個具體實例中，第一填充層114及/或第二填充層116之組成物小於接合的導電特徵204之25%且較佳小於10%。在一些具體實例中，第一填充層114及第二填充層116之緊密配合可包含填充層114及/或填充層116之熱變形。在其他應用中，包含互連特徵110之材料及第一晶粒102之填充層114之材料的導電複合物可藉由熱變形及晶界擴散製程與包含互連特徵110之材料及第二晶粒102之填充層116之材料的導電複合物接合。
如在圖2、區塊F處所展示，第一填充層114及第二填充層116組合以形成合金塊202，該合金塊實體地且電接合各別互連特徵110以形成互連結構204。在各種具體實例中，合金塊202包含在第一與第二互連特徵110之間的區（藉由接合第一及第二互連特徵110而形成之接合的互連件204之區），其具有非線性材料濃度。換言之，第一填充層114及第二填充層116組合以形成合金塊202，但第一填充層114至第二填充層116之濃度貫穿接合的互連結構204內之合金塊202係非線性的。
在一具體實例中，合金塊202包含結合至第一及第二導電互連特徵110之導電合金塊202，其中導電合金塊202包括：第一材料，其包含（第一晶粒102之）第一互連特徵110的材料；第二材料，其包含（第二晶粒102之）第二互連特徵110的材料；及至少第三材料，其包含第一填充物114及第二填充物116中之任一者或兩者的材料。在一具體實例中，可選擇第三材料以提高包括第三材料及第一材料或第二材料中之至少一者的合金之熔點。在各種具體實例中，導電合金塊202包括：第三材料，其包含至少第一填充物114；及第四材料，其包含至少第二填充物116。
在另一具體實例中，共晶合金塊202包含結合至第一及第二導電互連特徵110之導電合金塊202，其中導電合金塊202包括：第一材料，其包含第一填充物114之材料；第二材料，其包含第二填充物116之材料；及至少第三材料，其包含第一填充物114及第二填充物116之材料的合金或化合物。在該具體實例中，可藉由選擇第一填充物114及第二填充物116來選擇第三材料以提高包括第三材料及第一材料或第二材料中之至少一者的合金之熔點。在各種具體實例中，除第一填充物114及第二填充物116之材料以外，導電合金塊202亦包括一或多個層或材料（例如，金屬或其他導電材料）。
在這些具體實例中，第一材料之濃度可自朝向第一互連特徵110（或第一晶粒102）安置之位置處的相對較高量變化至朝向第二互連特徵110（或第二晶粒102）的相對較低量，且第二材料之濃度可在濃度上自朝向第二互連特徵110（或第二晶粒102）安置之位置處的相對較高量變化至朝向第一互連特徵110（或第一晶粒102）的相對較低量。在一具體實例中，第三材料在第一材料之第一最高濃度與第二材料之第二最高濃度之間的位置處具有最高濃度。
在其他應用中，接合的導電特徵204中之第一填充層114或第二填充層116的濃度小於接合的導電特徵204之25%且較佳小於10%。又，在一些具體實例中，在初始接合操作之後，第一填充層114或第二填充層116之材料可在後續處理步驟期間或在現場使用期間擴散及/或相互擴散至第一或第二導電特徵110中。因此，由第一填充層114及第二填充層116形成之合金塊202可包含接合的導電特徵204中之相異區。在如較早所論述的其他情形中，第一填充層114或第二填充層116可擴散至第一或第二導電特徵110中，且其濃度可更擴散，其中第一填充層114或第二填充層116之局部濃度小於周圍導電材料（例如，互連件110之材料）的5%且較佳小於1%。
在各種實施方案中，合金塊202係在低溫（例如，環境溫度、室溫、低於100℃）下形成且提供具有可靠強度及導電性之接合而無需較高溫度退火。舉例而言，包括合金塊202之低溫接合的強度及可靠性可等效於或實質上類似於經由較高溫度退火形成之接合。
儘管可使用低溫合金塊202來形成接合晶粒102之間的互連件204，但在一些具體實例中，可使用來自第一晶粒102之一個互連件110之金屬材料（例如，銅）至來自第二晶粒102之另一互連件110之金屬材料（例如，銅）的混合接合來形成接合晶粒102之間的至少一或多個互連件204。舉例而言，雖然一些互連件204形成為在互連件204內具有合金202，但可存在互連件204內不具有合金202之其他互連件204。在一些其他具體實例中，接合的互連件110之間的接觸區可部分地由合金202、銅銅接合部之組合形成，或甚至包括一些空隙。
實務上，，底部及頂部基板104之幾何比例可類似或相同。如在圖2、區塊G處所展示，接合晶粒102（例如，微電子組裝件118）之基板104中之一或多者可視需要薄化以供進一步處理或封裝。在其他應用中，底部基板104可顯著大於頂部基板104。舉例而言，底部基板104可包含200或300 mm矽晶圓或其類似者，而頂部基板104可包含顯著小於底部基板104之晶粒102。多個晶粒102可接合至底部基板104之平坦化接合表面108。可處理接合晶粒102以供額外接合操作，例如將其他潔淨晶粒102堆疊至最初接合晶粒102，等等。又，可進一步處理底部較大基板104，例如薄化或單體化操作或其兩者，以將各種接合晶粒102分開以供後續操作。
在各種具體實例中，本文中所描述之技術可用以補救或緩解待接合之微電子組件之表面中的無意凹入之互連結構的效應。用一或多個額外金屬填充層（114、116）至少部分地填充互連特徵110中之過度凹槽112提供改良之接合表面（例如，較少表面拓樸變化）。與改良之表面平坦度的直接及混合接合可導致微電子組件（例如，晶粒102）之間的改良且更可靠的接合。另外，由於在接合結合部處形成之合金塊202，可在低溫下達成各別晶粒102之互連特徵110之間的改良接合。
如上文所提及，在其他具體實例中，凹槽112可有意地形成於待接合之互連特徵110中之一或多者的曝露表面中，以應用所描述技術。舉例而言，可關於圖3之程序300來說明此等情境中之任一者。如在區塊A處所展示，在一實施方案中，程序300包含使用例如金屬鑲嵌製程在絕緣層106中形成導電特徵110。具有預定大小及形狀（例如，面積及深度「d1」）之凹槽112可無意或有意地形成於待接合之兩個晶粒102中之一者或兩者的互連特徵110中之一或多者的表面中。在一個具體實例中，可藉由蝕刻方法或其類似者將導電特徵110之部分相對於介電質106之接合表面選擇性地部分移除至預定深度。
在各種實施方案中，可例如藉由圖案化及蝕刻特徵110有意地產生凹槽112。可將光阻塗覆（圖中未示）至特徵110之表面以圖案化特徵110以用於預定凹槽112之位置。可曝光抗蝕劑且接著蝕刻特徵110之表面以形成所要凹槽112。在各種實施方案中，預定凹槽112可具有數十奈米至數百奈米（例如，50至500 nm）或視需要甚至更深之深度「d1」。
在替代實施方案中，例如當凹槽112在平坦化期間形成於大的金屬特徵110上時，可藉由CMP或其類似者產生凹槽112，如上文所描述。在一實例中，凹槽112之深度「d1」可大於15 nm。
如在區塊B處所展示，接合兩個晶粒102以形成微電子組裝件118而不緩解凹槽112可在特徵110之間留下空隙或間隙302。間隙302包含接合部中之大量缺陷，且可防止形成互連結構204或由各別特徵110可靠地形成互連結構。來自間隙302之大量缺陷可導致過早失效或低裝置良率。
在一具體實例中，程序300包括添加如上文所描述之一或多個填充層114、116以緩解凹槽112及間隙302。舉例而言，如在區塊C處所展示，將第一金屬填充層114形成、添加、沉積、塗佈或其類似者於第一晶粒102之第一互連特徵110的曝露表面上，如上文所描述。如在區塊D處所展示，將第二金屬填充層116形成、添加、沉積或其類似者於第二晶粒102之第二互連特徵110的曝露表面上，如上文所描述。
如在區塊E處所展示，在室溫（例如，低於100℃）下使用直接介電質至介電質接合（無黏著劑）來接合第一及第二晶粒102。第一及第二晶粒102之接合形成微電子組裝件118。在該程序中，將第一填充層114及第二填充層116按壓在一起以將互連特徵110接合成固體互連結構204，其中第一填充層114及第二填充層116組合以形成合金塊202，該合金塊實體地且電接合各別互連特徵110以形成互連結構204。在一些具體實例中，合金塊202之組成物可包含共晶合金或接近共晶合金塊之組成物。
在一些具體實例中，在接合之後，合金塊202內可仍留有小的間隙（圖中未示）。若間隙較小，則其可為無關緊要的。然而，若間隙較大，則其可導致失效。在彼狀況下，第一填充層114及/或第二填充層116中之一者或兩者的厚度可在接合之前增加。替代地，可在接合之前添加一或多個額外填充層（添加第一填充層114及第二填充層116）以減小或消除間隙。
在各種具體實例中，合金塊202具有非線性材料濃度，如上文所描述。舉例而言，在合金塊202內，第一填充物114之材料濃度可自朝向第一互連特徵110（或第一晶粒102）安置之位置處的相對較高量變化至朝向第二互連特徵110（或第二晶粒102）的相對較低量，且第二填充物之材料濃度可在濃度上自朝向第二互連特徵110（或第二晶粒102）安置之位置處的相對較高量變化至朝向第一互連特徵110（或第一晶粒102）的相對較低量。在一具體實例中，包含第一材料114及第二材料116之合金或化合物的第三材料在第一材料之第一最高濃度與第二材料之第二最高濃度之間的位置處在合金塊202內具有最高濃度。
在各種實施方案中，合金塊202係在低溫（例如，環境溫度、室溫、低於150℃）下形成且提供具有可靠強度及足夠導電性之接合。舉例而言，包括合金塊202之低溫接合的強度等效於或實質上類似於經由較高溫度退火形成之接合。
參看圖4，程序400經展示為程序300之替代實施方案。舉例而言，可插入區塊C1、D1及E1作為程序300之額外或替代程序步驟。在區塊C1及D1處，在第一填充層114及/或第二填充層116之前將障壁層402及/或404（諸如，鎳、鎳合金或其類似者）沉積至一個或兩個晶粒102之凹槽112上。當晶粒102接合在一起時，如在區塊E1處所展示，第一填充層114與第二填充層116緊密配合，且形成如上文所描述之合金塊202。在替代具體實例中，障壁層402及/或404可能與或可能不與填充層114、116及/或特徵110材料組合以變成合金塊202之部分。
圖5展示程序500，其說明使用無電極金屬沉積作為用於形成第一填充層114及/或第二填充層116之技術。程序500可特別適用於凹槽112可特別深（例如，「d1」＞50 nm）之狀況。區塊A說明有意或無意地（例如，CMP平坦化）具有過深凹槽112之晶粒102。在一具體實例中，過深凹槽112可能係由於例如凹槽112之尺寸中之一者（例如，大於0.05 mm），或特徵110之大的表面積大小。
在區塊B處，諸如直接置換反應或自催化金屬沉積之無電極製程例如用於以精確控制將填充層114選擇性地沉積至導電特徵110之曝露表面上。以預選厚度沉積填充層114以視需要將凹槽112減少至預定深度（「d2」），從而符合直接接合要求。
在一實施方案中，無電極製程包含浸漬銀、銅或金製程。在另一實施方案中，鈀之晶種沉積之後例如係鎳或其類似者之沉積。舉例而言，在沉積晶種層之後，可藉由基於次磷酸鹽之浸漬製程進行鎳沉積。在各種具體實例中，用於浸漬製程之還原劑包括次磷酸鈉、硼氫化鈉、二甲胺硼烷、肼或其類似者中之一或多者。
在區塊C處，具有填充層114之晶粒102中之兩者接合在一起以形成微電子組裝件118。如上所述，填充層114形成合金塊202，該合金塊接合（在低溫下）導電特徵110以形成固體互連結構204。
無電極沉積技術具有若干優點，包括不需要微影，不使用真空或熱，及在沉積之後不需要額外CMP。其他優點對於熟習此項技術者亦將為顯而易見的。
圖6係說明根據具體實例之用於形成及接合微電子組件（諸如，晶粒102）的實例程序600之流程圖。舉例而言，在區塊602處，程序包括平坦化第一基板（諸如，第一晶粒102）之接合表面（諸如，接合表面108）。在該具體實例中，第一基板包括嵌入至第一基板之接合表面中的第一金屬襯墊（諸如，導電特徵110）。
在區塊604處，該程序包括將第一金屬材料（諸如，第一填充層114）沉積至第一金屬襯墊之表面上。在一實施方案中，該程序包括在第一金屬襯墊之表面中形成第一凹入部分（諸如，凹槽112）及用第一金屬材料至少部分地填充第一凹入部分。在各種具體實例中，凹槽係一或多個程序步驟之產品，且可係有意或無意的。
在一實施方案中，該程序包括在沉積第一金屬材料之前將導電障壁層（諸如，障壁402）沉積至第一金屬襯墊之表面上。在一替代具體實例中，該程序包括沉積多個填充層、障壁層或其組合。
在區塊606處，該程序包括平坦化第二基板（諸如，第二晶粒102）之接合表面。該第二基板包括嵌入至第二基板之接合表面中的第二金屬襯墊。
在區塊608處，該程序包括將第二金屬材料（諸如，第二填充層116）沉積至第二金屬襯墊之表面上。在一實施方案中，該程序包括在第二金屬襯墊之表面中形成第二凹入部分及用第二金屬材料至少部分地填充第二凹入部分。在各種具體實例中，若存在，則凹槽係一或多個程序步驟之產品，且可係有意或無意的。
在一實施方案中，該程序包括在沉積第二金屬材料之前將導電障壁層（諸如，障壁404）沉積至第二金屬襯墊之表面上。在一替代具體實例中，該程序包括沉積多個填充層、障壁層或其組合。
在一實施方案中，該程序包括經由浸漬無電極金屬沉積來沉積第一金屬材料及/或第二金屬材料。在一些具體實例中，第一填充層及/或第二填充層之熔點可高於導電特徵110之熔點。舉例而言，第一填充層及/或第二填充層可包含鎳、鈷或錳或其各種合金之極薄層，而導電特徵可包含例如銅或銅合金。
所沉積之第一填充層及/或第二填充層可連續或不連續，且第一填充層及/或第二填充層之厚度的範圍可介於0.5至500 nm之間，且較佳介於1至小於50 nm之間。在一些具體實例中，第一填充層及/或第二填充層可包含至少一種較高溫度熔點金屬及至少一種較低溫度熔點金屬之合金，例如鈷錫或鈷銦合金或其類似者，或具有相對較低濃度之一或多種雜質的元素。合金或元件之組成物可包括一定比例之填充材料（雜質），該比例小於組合的互連襯墊之總組成物的2%，或小於5000 ppm，或小於500 ppm。
在一個具體實例中，第一填充層及/或第二填充層比各別導電特徵薄。在一個應用中，第一填充層及/或第二填充層比各別導電特徵之厚度薄至少5倍。
在區塊610處，該程序包括經由直接的介電質至介電質接合而無黏著劑來將第二基板之接合表面接合至第一基板之接合表面。在一實施方案中，該程序包括在接合期間將第一金屬襯墊按壓至第二金屬襯墊，及在第一金屬襯墊與第二金屬襯墊之間形成合金塊（諸如，合金塊204）。在該實施方案中，該合金塊包含第一金屬材料及第二金屬材料之合金。在一具體實例中，該程序包括經由合金塊將第二金屬襯墊接合至第一金屬襯墊以形成單個固體互連結構（諸如，互連結構204）。在另一具體實例中，合金塊的第一金屬材料之濃度及第二金屬材料之濃度在整個合金塊中係非線性的。
在接合製程期間，頂部基板之導電特徵及底部基板之複合導電特徵（包含較低熔點導電特徵及較高熔點填充層）熱變形以緊密配合，且來自導電特徵（例如，銅）之原子擴散至填充層（例如，鈷）中。在此組態中，接合的基板可包括具有主要包含例如銅之導電互連結構的一部分，及具有包括合金塊（例如，銅鈷合金塊）之互連結構的另一部分，該合金塊包含導電特徵（例如，銅）及填充層（例如，鈷）。
在各種具體實例中，相較於本文中所描述之程序步驟，可修改或消除一些程序步驟。
本文中所描述之技術、組件及裝置不限於圖1至圖6之說明，且可在不脫離本發明之範圍的情況下應用於包括其他電組件之其他設計、類型、配置及構造。在一些狀況下，額外或替代組件、技術、序列或程序可用以實施本文中所描述之技術。另外，組件及/或技術可以各種組合配置及/或組合，同時產生類似或大致相同之結果。 結論
儘管已以特定於結構特徵及/或方法動作之語言描述本發明之實施方案，但應理解，實施方案未必限於所描述之特定特徵或動作。確切而言，將特定特徵及動作揭示為實施實例裝置及技術之代表性形式。
100:程序 102:晶粒 104:基底基板 106:絕緣層/介電層/介電質 108:接合表面 110:嵌入式導電特徵/嵌入式互連結構/金屬互連特徵/互連件 112:凹陷或凹槽 114:第一填充物/第一金屬填充層/第一材料/導電填充層 114':不連續填充層 116:第二填充物/第二金屬填充層/第二材料/導電填充層 116':不連續填充層 118:微電子組裝件 202:導電合金塊/合金 204:固體互連結構/導電互連件/接合的導電特徵 300:程序 302:空隙或間隙 400:程序 402:障壁層 404:障壁層 500:程序 600:程序 602:區塊 604:區塊 606:區塊 608:區塊 610:區塊 A:區塊 B:區塊 C:區塊 C1:區塊 D:區塊 D1:區塊 E1:區塊 F:區塊 d1:深度 d2:深度
參看隨附圖式闡述實施方式。在這些圖式中，參考數字之最左側數位識別首次出現該參考數字之圖。在不同圖中使用相同參考數字指示類似或相同物件。
對於此論述，圖式中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置及/或系統之各種實施方案可包括更少組件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施方案可包括額外組件或所描述組件之各種組合，且保持在本發明之範圍內。
[圖1]及[圖2]包括說明根據具體實例之用於形成及接合晶粒的一實例程序之圖形流程圖。
[圖3]係說明根據具體實例之用於形成及接合晶粒的另一實例程序之圖形流程圖。
[圖4]係說明根據具體實例之用於形成及接合晶粒的一替代實例程序之圖形流程圖。
[圖5]係說明根據具體實例之用於形成及接合晶粒的另一實例程序之圖形流程圖。
[圖6]係說明根據具體實例之用於形成及接合晶粒的一實例程序之流程圖。
600:程序
602:區塊
604:區塊
606:區塊
608:區塊
610:區塊

Claims (33)

  1. 一種方法，其包含： 形成第一基板的接合表面，所述第一基板包括嵌入到所述第一基板的所述接合表面中的第一金屬特徵； 將第一金屬材料沉積到所述第一金屬特徵的表面上； 形成第二基板的接合表面，所述第二基板包括嵌入到所述第二基板的所述接合表面中的第二金屬特徵； 將第二金屬材料沉積到所述第二金屬特徵的表面上； 在所述第一金屬特徵的至少一部分和所述第二金屬特徵的至少一部分之間形成合金塊，所述合金塊包括所述第一金屬材料和所述第二金屬材料的合金，其中所述合金塊之所述第一金屬材料的濃度和所述第二金屬材料的濃度在整個所述合金塊中變化；以及 經由直接接合且無需使用黏著劑而將所述第二基板的所述接合表面接合至所述第一基板的所述接合表面。
  2. 如請求項1所述之方法，其中所述合金塊包括共晶合金塊。
  3. 如請求項1所述之方法，其進一步包括經由所述合金塊將所述第二金屬特徵接合到所述第一金屬特徵，以形成單一固體互連結構。
  4. 如請求項1所述之方法，其進一步包括： 在所述第一金屬特徵的表面中形成第一凹入部分以及在所述第二金屬特徵的表面中形成第二凹入部分；以及 用所述第一金屬材料至少部分地填充所述第一凹入部分，並且用所述第二金屬材料至少部分地填充所述第二凹入部分。
  5. 如請求項1所述之方法，其進一步包括在分別沉積所述第一金屬材料或所述第二金屬材料之前，將導電障壁層沉積到所述第一金屬特徵的所述表面及/或所述第二金屬特徵的所述表面上。
  6. 如請求項1所述之方法，其進一步包括經由浸漬無電極金屬沉積來沉積所述第一金屬材料及/或所述第二金屬材料。
  7. 一種方法，其包含： 形成第一基板的接合表面，所述第一基板包括嵌入到所述第一基板的所述接合表面中的第一金屬特徵； 形成第二基板的接合表面，所述第二基板包括嵌入到所述第二基板的所述接合表面中的第二金屬特徵； 在所述第一金屬特徵及/或所述第二金屬特徵的表面上形成第一金屬材料的不連續層，所述第一金屬材料不同於所述第一金屬特徵或所述第二金屬特徵的材料；以及 透過直接接合將所述第二基板的所述接合表面接合至所述第一基板的所述接合表面，並且將所述第一金屬特徵機械地或電性耦接至所述第二金屬特徵。
  8. 如請求項7所述之方法，其中所述第一金屬特徵透過熱變形直接接合至所述第二金屬特徵。
  9. 如請求項7所述之方法，其中所述第一金屬材料包括鈷、鎳或錳。
  10. 如請求項7所述之方法，其中所述第一金屬材料的熔點高於所述第一金屬特徵的材料或所述第二金屬特徵的材料的部分的熔點。
  11. 一種方法，其包含： 形成第一基板的接合表面，所述第一基板包括嵌入到所述第一基板的所述接合表面中的第一金屬特徵； 將與所述第一金屬特徵的材料不同的第一金屬材料沉積到所述第一金屬特徵的表面上； 形成第二基板的接合表面，所述第二基板包括嵌入到所述第二基板的所述接合表面中的第二金屬特徵； 將與所述第二金屬特徵的材料不同且與所述第一金屬材料不同的第二金屬材料沉積到所述第二金屬特徵的表面上； 經由直接接合且無需使用黏著劑而將所述第二基板的所述接合表面接合至所述第一基板的所述接合表面；以及 經由所述第一金屬材料和所述第二金屬材料將所述第一金屬特徵機械地和電性耦接至所述第二金屬特徵。
  12. 如請求項11所述之方法，其進一步包括在所述第一金屬特徵的至少一部分和所述第二金屬特徵的至少一部分之間形成合金塊，所述合金塊包括所述第一金屬材料和所述第二金屬材料的合金，並且透過所述合金塊將所述第一金屬特徵接合至所述第二金屬特徵。
  13. 如請求項12所述之方法，其中所述合金體的所述第一金屬材料的濃度和所述第二金屬材料的濃度在整個所述合金體中變化。
  14. 一種微電子組裝件，包括： 第一基板，其具有接合表面，所述第一基板的所述接合表面具有平坦化的形貌； 第一多個金屬特徵，其位於所述第一基板的所述接合表面處； 第一凹入部分，其設置在所述第一多個金屬特徵中的一個或多個的表面中並且在所述第一基板的所述接合表面下方延伸預選深度，所述第一凹入部分以與所述第一多個金屬特徵的導電材料不同的第一導電材料至少部分地填充； 第二基板，其具有接合表面，所述第二基板的所述接合表面具有平坦化的形貌並且接合至所述第一基板的所述接合表面；以及 第二多個金屬特徵，其位於所述第二基板的接合表面處並且接合至所述第一多個金屬特徵，所述第一多個金屬特徵及/或所述第二多個金屬特徵除了如果存在的任何障壁層之外還包括兩個或更多個導電材料。
  15. 如請求項14所述之微電子組裝件，其進一步包括第二凹入部分，所述第二凹入部分設置在所述第二多個金屬特徵中的一個或多個的表面中並且在所述第二基板的所述接合表面下方延伸預選深度，所述第二凹入部分以與所述第二多個金屬特徵的導電材料不同的第二導電材料至少部分地填充。
  16. 如請求項15所述之微電子組裝件，其進一步包括設置在所述第一凹入部分及/或所述第二凹入部分內、在所述第一多個金屬特徵的所述導電材料與所述第一導電材料之間及/或在所述第二多個金屬特徵的所述導電材料與所述第二導電材料之間的障壁層，所述障壁層包括與所述第一導電材料或所述第二導電材料不同並且與所述第一多個金屬特徵或所述第二多個金屬特徵的所述導電材料不同的第三導電材料。
  17. 如請求項15所述之微電子組裝件，其進一步包括佈置在所述第一多個金屬特徵和所述第二多個金屬特徵的至少一部分之間的合金塊，所述合金塊包括所述第一導電材料和所述第二導電材料的合金。
  18. 如請求項17所述之微電子組裝件，其中所述合金塊的熔點高於所述第一金屬特徵和所述第二金屬特徵各自的熔點。
  19. 如請求項17所述之微電子組裝件，其中所述合金塊的熔點低於所述第一金屬特徵和所述第二金屬特徵各自的熔點。
  20. 如請求項17所述之微電子組裝件，其中所述第一導電材料的濃度和所述第二導電材料的濃度在整個所述合金塊中變化。
  21. 如請求項14所述之微電子組裝件，其中所述第二基板的所述接合表面經由直接接合且無需使用黏著劑而接合到所述第一基板的所述接合表面。
  22. 一種微電子組裝件，包括： 第一基板，其具有表面，所述第一基板的所述表面具有第一導電互連結構； 第二基板，其具有表面，所述第二基板的所述表面具有第二導電互連結構，所述第一基板接合到所述第二基板，且所述第一導電互連結構接合到所述第二導電互連結構；以及 導電合金塊，所述導電合金塊將所述第一導電互連結構耦接到所述第二導電互連結構，其中所述導電合金塊包括第一導電材料、第二導電材料和第三導電材料，所述第三導電材料被選擇以提高包括所述第一導電材料或所述第二導電材料中的至少一個以及所述第三導電材料的合金的熔點，其中所述第一導電材料的濃度從朝向所述第一導電互連結構的位置處的第一量變化為朝向所述第二導電互連結構的位置處的第二量，其中所述第二導電材料的濃度從朝向所述第二導電互連結構設置的位置處的第三量變化到朝向所述第一導電互連結構的位置處的第四量，其中所述第一量高於所述第二量且所述第三量高於所述第四量，且其中所述第三導電材料在所述第一導電互連結構和所述第二導電互連結構之間的位置處具有最高濃度。
  23. 如請求項22所述之微電子組裝件，其進一步包括設置在所述第一導電互連結構的表面中的第一凹入部分和設置在所述第二導電互連結構的表面中的第二凹入部分，所述第一凹入部分以所述第一導電材料至少部分地填充並且所述第二凹入部分以所述第二導電材料至少部分地填充。
  24. 如請求項23所述之微電子組裝件，其進一步包括設置在所述第一凹入部分及/或所述第二凹入部分內的導電障壁層。
  25. 一種微電子組裝件，包括： 第一基板，其具有凹入於所述第一基板的第一接合表面下方的第一多個金屬特徵，所述第一多個金屬特徵包括兩個或更多個不同的金屬材料； 第一非金屬區域，其位於所述第一接合表面處，所述第一非金屬區域圍繞所述第一多個金屬特徵； 第二基板，其具有凹陷到所述第二基板的第二接合表面下方的第二多個金屬特徵，所述第二多個金屬特徵包括兩個或更多個不同的金屬材料； 第二非金屬區域，其位於所述第二接合表面處，所述第二非金屬區域圍繞所述第二多個金屬特徵，所述第二非金屬區域至少部分接觸並且直接接合至所述第一非金屬區域；以及 合金塊，其設置在所述第一多個金屬特徵和所述第二多個金屬特徵之間，該合金塊具有所述第一多個金屬特徵的所述不同金屬材料中的一個或多個之可變濃度並且具有所述第二多個金屬特徵的所述不同金屬材料中的一個或多個之可變濃度。
  26. 如請求項25所述之微電子組裝件，其進一步包括設置在所述第一多個金屬特徵的表面上的第一凹入部分和設置在所述第二多個金屬特徵的表面上的第二凹入部分。
  27. 如請求項26所述之微電子組裝件，其中所述第一凹入部分以與所述第一多個金屬特徵的所述金屬材料不同的一個或多個導電材料至少部分地填充，並且其中所述第二凹入部分以與所述第二多個金屬特徵的所述金屬材料不同的一個或多個導電材料至少部分地填充。
  28. 如請求項26所述之微電子組裝件，其進一步包括設置在所述第一凹入部分及/或所述第二凹入部分內的導電障壁層。
  29. 如請求項25所述之微電子組裝件，其中所述第一非金屬區域和所述第二非金屬區域中的至少一個包括非黏著材料。
  30. 一種微電子組裝件，包括： 第一基板，其具有表面和第一導電結構，所述第一導電結構包括第一元件； 第二基板，其具有表面和第二導電結構，所述第一基板的所述表面緊密接合到所述第二基板的所述表面，所述第一導電結構接合到所述第二導電結構；以及 導電合金區，其將所述第一導電結構耦接到所述第二導電結構，其中所述導電合金區包括熔點高於所述第一導電結構或所述第二導電結構中的一部分的熔點之所述第一元件。
  31. 如請求項30所述之微電子組裝件，其中所述導電合金區域包括鈷、鎳及/或錳。
  32. 如請求項30所述之微電子組裝件，其中所述導電合金區域的厚度比所述第一導電結構或所述第二導電結構的厚度薄。
  33. 一種微電子組裝件，包括： 第一基板，其具有表面和第一導電結構，所述第一導電結構包括第一元件； 第二基板，其具有表面和第二導電結構，所述第一基板的所述表面緊密接合到所述第二基板的所述表面，所述第一導電結構接合到所述第二導電結構；以及 導電合金區，其將所述第一導電結構耦接到所述第二導電結構，其中所述導電合金區包括熔點低於所述第一導電結構或所述第二導電結構中的一部分的熔點之所述第一元件。
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US20230268307A1 (en) 2023-08-24
US20200381389A1 (en) 2020-12-03
US10790262B2 (en) 2020-09-29
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