WO2023272942A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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WO2023272942A1
WO2023272942A1 PCT/CN2021/117500 CN2021117500W WO2023272942A1 WO 2023272942 A1 WO2023272942 A1 WO 2023272942A1 CN 2021117500 W CN2021117500 W CN 2021117500W WO 2023272942 A1 WO2023272942 A1 WO 2023272942A1
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conductive
conductor group
contact pad
chip
contact surface
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PCT/CN2021/117500
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English (en)
French (fr)
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庄凌艺
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长鑫存储技术有限公司
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Priority to US17/648,309 priority Critical patent/US11984417B2/en
Publication of WO2023272942A1 publication Critical patent/WO2023272942A1/zh

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Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • the bonding between the chips is realized by connecting the metal pads on the chips.
  • the stacked chips need to be transported before bonding. If there is vibration or external force, the alignment of the stacked chips will be affected by slippage, which increases the difficulty of the process.
  • the disclosure provides a semiconductor structure and a manufacturing method of the semiconductor structure to improve the performance of the semiconductor structure.
  • a semiconductor structure comprising:
  • the first chip includes a first substrate, a first conductive connection and a first conductive contact pad, the first conductive contact pad is connected to the first conductive connection, and the first conductive contact pad includes a first conductor group and a second set of electrical conductors, the melting point of the first set of electrical conductors being greater than the melting point of the second set of electrical conductors;
  • the second chip includes a second substrate, a second conductive connection and a second conductive contact pad, the second conductive contact pad is connected to the second conductive connection, and the second conductive contact pad includes a third conductor group and the fourth conductor group, the melting point of the third conductor group is higher than the melting point of the fourth conductor group, the first conductor group is directly opposite to the third conductor group, and the second conductor group is directly opposite to the fourth conductor group , to form a bonding structure between the first conductive contact pad and the second conductive contact pad;
  • one end of the first conductive contact pad facing the second conductive contact pad is the first contact surface
  • one end of the second conductive contact pad facing the first contact surface is the second contact surface
  • the first conductor group occupies a portion of the first contact surface.
  • the area is smaller than the area occupied by the second electrical conductor group on the first contact surface
  • the area occupied by the third electrical conductor group on the second contact surface is smaller than the area occupied by the fourth electrical conductor group on the second contact surface.
  • a method for fabricating a semiconductor structure including:
  • a first chip is provided, the first chip includes a first substrate, a first conductive connection and a first conductive contact pad, the first conductive contact pad is connected to the first conductive connection, and the first conductive contact pad includes a first conductor group and a second group of electrical conductors, the melting point of the first group of electrical conductors is greater than the melting point of the second group of electrical conductors;
  • a second chip is provided, the second chip includes a second substrate, a second conductive connection and a second conductive contact pad, the second conductive contact pad is connected to the second conductive connection, and the second conductive contact pad includes a third conductor group and a fourth conductor group, the melting point of the third conductor group is greater than the melting point of the fourth conductor group;
  • one end of the first conductive contact pad facing the second conductive contact pad is the first contact surface
  • one end of the second conductive contact pad facing the first contact surface is the second contact surface
  • the first conductor group occupies a portion of the first contact surface.
  • the area is smaller than the area occupied by the second electrical conductor group on the first contact surface
  • the area occupied by the third electrical conductor group on the second contact surface is smaller than the area occupied by the fourth electrical conductor group on the second contact surface.
  • Fig. 1 is a schematic diagram showing an exploded structure of a first chip and a second chip of a semiconductor structure according to an exemplary embodiment
  • Fig. 2 is a schematic diagram of a partial connection structure between a first chip and a second chip of a semiconductor structure shown according to an exemplary embodiment
  • Fig. 3 is a schematic structural diagram of a first contact surface and a first contact surface of a semiconductor structure shown according to an exemplary embodiment
  • Fig. 4 is a schematic structural diagram of a first contact surface and a first contact surface of a semiconductor structure according to another exemplary embodiment
  • Fig. 5 is a schematic flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • the first chip 11. The first substrate; 12. The first conductive connection; 13. The first conductive contact pad; 131. The first conductor group; 132. The second conductor group; 1321. The first child Conductive section; 14. The first contact surface;
  • An embodiment of the present disclosure provides a semiconductor structure. Please refer to FIG. 1 and FIG.
  • Conductive contact pad 13, the first conductive contact pad 13 is connected with the first conductive wire 12, the first conductive contact pad 13 includes a first conductor group 131 and a second conductor group 132, the melting point of the first conductor group 131 Greater than the melting point of the second conductor group 132; the second chip 20, the second chip 20 includes a second substrate 21, a second conductive connection 22 and a second conductive contact pad 23, the second conductive contact pad 23 is connected to the second conductive The connecting wires 22 are connected.
  • the second conductive contact pad 23 includes a third conductor group 231 and a fourth conductor group 232.
  • the melting point of the third conductor group 231 is greater than the melting point of the fourth conductor group 232.
  • the first conductor group 131 is directly opposite to the third conductor group 231, and the second conductor group 132 is directly opposite to the fourth conductor group 232, so as to form a bonding structure between the first conductive contact pad 13 and the second conductive contact pad 23; wherein One end of the first conductive contact pad 13 facing the second conductive contact pad 23 is the first contact surface 14, and one end of the second conductive contact pad 23 facing the first contact surface 14 is the second contact surface 24, and the first conductor group 131
  • the area occupied by the first contact surface 14 is smaller than the area occupied by the second conductor group 132 on the first contact surface 14, and the area occupied by the third conductor group 231 on the second contact surface 24 is smaller than that occupied by the fourth conductor group 232. 24 area.
  • the semiconductor structure of an embodiment of the present disclosure includes a first chip 10 and a second chip 20, the first conductive wire 12 of the first chip 10 is connected to the first conductive contact pad 13, and the second conductive wire 22 of the second chip 20 is connected to The second conductive contact pad 23 , and the first conductive contact pad 13 includes a first conductive body group 131 and a second conductive body group 132 , and the second conductive contact pad 23 includes a third conductive body group 231 and a fourth conductive body group 232 .
  • the first conductor group 131 is directly opposite to the third conductor group 231
  • the second conductor group 132 is directly opposite to the fourth conductor group 232
  • the melting point of the first conductor group 131 is higher than that of the second conductor group 132.
  • the melting point of the third conductor group 231 is greater than the melting point of the fourth conductor group 232, so the second conductor group 132 and the fourth conductor group 232 can be melted and connected at the first temperature, that is, the first The pre-connection of the conductive contact pad 13 and the second conductive contact pad 23, and then the pre-connected first chip 10 and the second chip 20 are transferred to the second temperature annealing condition for bonding, so as to realize the first conductive contact pad 13 and the second chip 20.
  • the second conductor group 132 and the fourth conductor group 232 melt, but the first conductor group 131 and the third conductor group 231 do not melt.
  • the second conductor group The group 132 and the fourth conductor group 232 can be connected, and the various metal materials of the first conductive contact pad 13 and the second conductive contact pad 23 are mutually infiltrated and fused, as shown in FIG. 2 , thus forming a metal compound, thereby realizing Pre-connection of the first conductive contact pad 13 and the second conductive contact pad 23 .
  • first conductive contact pad 13 and the second conductive contact pad 23 have completed the pre-connection, there will be no relative opposition between the first chip 10 and the second chip 20 during the subsequent transfer of the first chip 10 and the second chip 20. Slip, so as to ensure that the first chip 10 and the second chip 20 are under the connection condition of reliable alignment, and the first chip 10 and the second chip 20 are bonded to each other under the second temperature annealing condition, thus realizing the first
  • the reliable bonding of the first conductive contact pad 13 and the second conductive contact pad 23 forms a reliable bonding structure between the first conductive contact pad 13 and the second conductive contact pad 23 .
  • the first chip 10 and the second chip 20 need to be directly placed in a high-temperature environment for bonding, and the alignment is affected by slip during the transfer process, thus affecting the performance of the semiconductor structure.
  • the semiconductor structure in this embodiment The alignment problem in the related art can be improved to improve the performance of the semiconductor structure.
  • the first conductor group 131 is directly opposite to the third conductor group 231, and the second conductor group 132 is directly opposite to the fourth conductor group 232, which actually illustrates the position of the first chip 10 and the second chip 20 before bonding.
  • the above-mentioned positional relationship does not necessarily exist, and the corresponding position of the conductive material may not be determined due to fusion. Positional relationship, but the above positional relationship can be judged from the material configuration.
  • both the first conductive wiring 12 and the first conductive contact pad 13 are located in the first substrate 11
  • the second conductive wiring 22 and the second conductive contact pad 23 are both located in the second substrate 21 .
  • first conductive wiring 12 and the first conductive contact pad 13 may be partly located in the first substrate 11, and the first conductive wiring 12 and the first conductive contact pad 13 may also be entirely located in the first substrate 11.
  • second conductive wiring 22 and the second conductive contact pad 23 may be partially located in the second substrate 21 , or may be completely located in the second substrate 21 .
  • the first conductive contact pad 13 may be located on the surface of the first substrate 11 .
  • the second conductive contact pad 23 may be located on the surface of the second substrate 21 .
  • the first substrate 11 includes a silicon substrate and an insulating layer formed above the silicon substrate, a part of the first conductive wiring 12 is located in the insulating layer, and a first conductive contact pad 13 is formed in the insulating layer.
  • the second substrate 21 includes a silicon substrate and an insulating layer formed above the silicon substrate, part of the second conductive wiring 22 is located in the insulating layer, and the second conductive contact pad 23 is formed in the insulating layer.
  • the insulating layer of the first chip 10 is disposed adjacent to the second conductor group 132
  • the insulating layer of the second chip 20 is disposed adjacent to the fourth conductor group 232
  • the expansion coefficient of the second conductor group 132 is much larger than that of the second conductor group 132.
  • the expansion coefficient of the first conductor group 131 is smaller than the expansion coefficient of the first conductor group 131, correspondingly, the expansion coefficient of the fourth conductor group 232 is much smaller than the expansion coefficient of the third conductor group 231, therefore, the first conductive contact pad 13 and the second conductive contact
  • the expansion of the second conductor group 132 and the fourth conductor group 232 will be relatively low, so the insulating layer of the bonded first chip 10 and the second chip 20 will not be excessively squeezed.
  • the insulating layer thus avoiding the problem of cracks forming between the insulating layers.
  • copper is directly adjacent to the insulating layer, and it is easy to stretch the bonded insulating layer around to form cracks during the bonding process, but this embodiment can solve the above problem.
  • the silicon substrate may be formed of a silicon-containing material.
  • the silicon substrate may be formed of any suitable material, including, for example, at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the insulating layer may include silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbonitride (SiCN) and other related integrated circuit insulating materials.
  • the first conductive wire 12 is a first silicon through
  • the second conductive wiring 22 is a second TSV.
  • the first TSV and the second TSV are connected through the first conductive contact pad 13 and the second conductive contact pad 23 .
  • the thickness of the second conductor group 132 is less than 1 um, and the thickness of the fourth conductor group 232 is less than 1 um.
  • one end of the first conductive contact pad 13 towards the second conductive contact pad 23 is the first contact surface 14, and the end of the second conductive contact pad 23 towards the first contact surface 14 is the second contact surface 24; wherein , the first conductor group 131 and the second conductor group 132 occupy part of the first contact surface 14 respectively, the third conductor group 231 and the fourth conductor group 232 respectively occupy part of the second contact surface 24, and the first The area occupied by the conductor group 131 on the first contact surface 14 is smaller than the area occupied by the second conductor group 132 on the first contact surface 14, and the area occupied by the third conductor group 231 on the second contact surface 24 is smaller than that occupied by the fourth conductor group 232.
  • the area of the second contact surface 24 is The area of the second contact surface 24 .
  • the first contact surface 14 and the second contact surface 24 are in contact with each other, so as to realize the electrical connection between the first conductive contact pad 13 and the second conductive contact pad 23 .
  • the first conductor group 131, the second conductor group 132, the third conductor group 231 and the fourth conductor group 232 are all conductors, the first conductive contact pad 13 and the second conductive contact pad A large-area electrical connection contact surface can be formed between the pads 23 .
  • the area that the first conductor group 131 occupies the first contact surface 14 is smaller than the area that the second conductor group 132 occupies the first contact surface 14, and the area that the third conductor group 231 occupies the second contact surface 24 is smaller than the fourth conductor group 231.
  • the body group 232 occupies the area of the second contact surface 24, that is, the second conductor group 132 and the fourth conductor group 232 are melted at the first temperature, so that a larger pre-connection surface can be formed to ensure subsequent connection stability.
  • part of the first contact surface 14 occupied by the first conductor group 131 and the second conductor group 132 may also include other conductors.
  • the third conductor group 231 and the fourth conductor group 232 occupy part of the second contact surface 24 , and the second conductive contact pad 23 may also include other conductors.
  • the melting points of other conductors of the first conductive contact pad 13 and the second conductive contact pad 23 are not limited. The relationship between the melting points of the four-conductor group 232 reflects that the first chip 10 and the second chip 20 can be pre-connected at a relatively low temperature.
  • the first conductor group 131 and the second conductor group 132 occupy the entire first contact surface 14, that is, the first conductive contact pad 13 may only include the first conductor group 131 and the second conductor group 132, Or the first conductive contact pad 13 may include other electrical conductors, but this electrical conductor is not located at the end of the first conductive contact pad 13 away from the first conductive wire 12 .
  • the third conductor group 231 and the fourth conductor group 232 occupy the entire second contact surface 24, that is, the second conductive contact pad 23 may only include the third conductor group 231 and the fourth conductor group 232, or The second conductive contact pad 23 may include other electrical conductors, but this electrical conductor is not located at the end of the second conductive contact pad 23 away from the second conductive wire 22 .
  • the first conductor group 131 may include multiple conductive materials, that is, the first conductor group 131 may be composed of a plurality of different types of conductive materials, where the multiple types of conductive materials are distinguished from A metal compound, that is, the first conductor group 131 may include multiple single metal materials, or multiple metal compounds, or a single metal material and metal compounds.
  • the second conductor group 132 , the third conductor group 231 and the fourth conductor group 232 can all refer to this embodiment, and details are not repeated here.
  • the first conductor group 131 only includes the first conductor
  • the second conductor group 132 only includes the second conductor
  • the third conductor group 231 only includes the third conductor
  • the fourth conductor group 232 includes only the fourth electrical conductor. That is, the first conductor group 131 , the second conductor group 132 , the third conductor group 231 and the fourth conductor group 232 are all a single metal material or metal compound.
  • the area of the first contact surface 14 is equal to the area of the second contact surface 24 , that is, the area of the fusion surface of the first chip 10 is consistent with the area of the fusion surface of the second chip 20 .
  • the first conductor group 131 and the second conductor group 132 occupy all of the first contact surface 14
  • the third conductor group 231 and the fourth conductor group 232 occupy all of the second contact surface 24
  • the first conductor The area occupied by the group 131 on the first contact surface 14 is equal to the area occupied by the third conductor group 231 on the second contact surface 24, and the area occupied by the second conductor group 132 on the first contact surface 14 is equal to the area occupied by the fourth conductor group 232.
  • the area of the two contact surfaces 24 ensures that the first conductor group 131 is directly opposite to the third conductor group 231 , and the second conductor group 132 is directly opposite to the fourth conductor group 232 .
  • the area of the first contact surface 14 is equal to the area of the second contact surface 24, the first conductor group 131 and the second conductor group 132 occupy part of the first contact surface 14, and the third conductor group 231
  • the first conductor group 131 is directly opposite to the third conductor group 231
  • the second conductor group 132 is directly opposite to the fourth conductor group 232.
  • other conductors included in the first conductive contact pad 13 are directly opposite to other conductors included in the second conductive contact pad 23 .
  • the area of the first contact surface 14 is not equal to the area of the second contact surface 24 , that is, the area of the fusion surface of the first chip 10 is not consistent with the area of the fusion surface of the second chip 20 .
  • the area of the first contact surface 14 is smaller than that of the second contact surface 24 , a part of the second contact surface 24 will be opposite to the first substrate 11 .
  • the area of the first contact surface 14 is larger than the area of the second contact surface 24 , the part of the first contact surface 14 will be opposite to the second substrate 21 .
  • the first conductor group 131 and the second contact surface can occupy all of the first contact surface 14, and the third conductor group 231 and the fourth conductor group 232 can also occupy all of the second contact surface 24.
  • the body group 131 is directly opposite to the third conductor group 231, all the second conductor groups 132 are directly opposite to the fourth conductor group 232, and the third conductor group 231 and the fourth conductor group of the second conductive contact pad 23 Other parts of at least one of the conductor groups 232 may directly correspond to the first substrate 11 .
  • the area of the first contact surface 14 is greater than the area of the second contact surface 24 , reference can also be made to this embodiment, and details will not be described here.
  • the circumferential outer edge of the first contact surface 14 includes at least one of a straight line and a curved line
  • the circumferential outer edge of the second contact surface 24 includes at least one of a straight line and a curved line.
  • the shape of the first contact surface 14 and the shape of the second contact surface 24 can be completely the same or different, and the shape of the first contact surface 14 and the shape of the second contact surface 24 can be circular, oval, rectangular, etc. A variety of shapes, not limited here.
  • the first contact surface 14 is equal to the area of the second contact surface 24, the first conductor group 131 and the second conductor group 132 occupy the entire first contact surface 14, and the third conductor group 231 and the fourth conductor group 232 occupy all of the second contact surface 24, it can be explained that the shape of the first contact surface 14 is exactly the same as that of the second contact surface 24, and the first contact surface 14 and the second contact surface 24 completely coincident.
  • the volume of the first conductive contact pad 13 occupied by the first conductive body group 131 is greater than the volume occupied by the second conductive body group 132 of the first conductive contact pad 13; the third conductive body group 231 occupies the second conductive contact pad
  • the volume of the second conductive contact pad 23 is larger than the volume of the second conductive contact pad 23 occupied by the fourth conductive body group 232 . That is, the proportion of the conductive material with a low melting point in the first conductive contact pad 13 and the second conductive contact pad 23 is relatively low.
  • one end of the first conductive wire 12 is connected to the first conductor group 131 ; one end of the second conductive wire 22 is connected to the third conductor group 231 . That is, the side of the first conductive contact pad 13 away from the first conductive connection 12 includes the second conductor group 132, and the side of the second conductive contact pad 23 far away from the second conductive connection 22 includes the fourth conductor. Group 232.
  • first conductive wire 12 is connected to the first conductor group 131, and one end of the second conductive wire 22 is connected to the third conductor group 231. It can be further understood that the first Before the chip 10 and the second chip 20 are bonded, one end of the first conductive wire 12 is connected to the first conductor group 131, and one end of the second conductive wire 22 is connected to the third conductor group 231, and After the bonding structure is formed between the first conductive contact pad 13 and the second conductive contact pad 23, there may be a possibility of fusion between the conductive materials, but the above structural relationship can also be judged from the material configuration.
  • the second conductor group 132 includes a plurality of first sub-connection segments 1321, and a part of the first conductor group 131 is sandwiched between adjacent first sub-connection segments 1321, which can be understood as A gap is formed on a side of the conductor group 131 away from the first conductive connection 12 , so as to fill the first sub-connection section 1321 .
  • the fourth conductor group 232 includes a plurality of second sub-connection segments 2321, and a part of the third conductor group 231 is sandwiched between adjacent second sub-connection segments 2321, which can be understood as A gap is formed on the side of the three-conductor group 231 away from the second conductive connection 22 , so as to fill the second sub-connection section 2321 .
  • the area of the first contact surface 14 is equal to the area of the second contact surface 24, and the first conductor group 131 and the second conductor group 132 occupy all of the first contact surface 14, the third The conductor group 231 and the fourth conductor group 232 occupy the entire second contact surface 24, and the area occupied by the first conductor group 131 on the first contact surface 14 is smaller than the area occupied by the second conductor group 132 on the first contact surface 14 , the area occupied by the third conductor group 231 on the second contact surface 24 is smaller than the area occupied by the fourth conductor group 232 on the second contact surface 24, so as to ensure that the first conductor group 131 is directly opposite to the third conductor group 231, The second conductor group 132 is directly opposite to the fourth conductor group 232 .
  • the second conductor group 132 includes a plurality of first sub-connection sections 1321
  • the fourth conductor group 232 includes a plurality of second sub-connection sections 2321 .
  • the area of the first contact surface 14 is equal to the area of the second contact surface 24, and the first conductor group 131 and the second conductor group 132 occupy all of the first contact surface 14, and the third conductor group 231 and the fourth conductor group 232 occupy the entire second contact surface 24, and the area occupied by the first conductor group 131 is smaller than the area occupied by the second conductor group 132 on the first contact surface 14, and the third The area occupied by the conductor group 231 on the second contact surface 24 is smaller than the area occupied by the fourth conductor group 232 on the second contact surface 24, so as to ensure that the first conductor group 131 is directly opposite to the third conductor group 231, and the second conductor group 231 is directly opposite to the third conductor group 231.
  • the body group 132 is directly opposite the fourth electrical conductor group 232 .
  • a part of the first conductor group 131 is clamped in the two first sub-connection sections 1321
  • a part of the third conductor group 231 is clamped in the two second sub-connection sections 2321 .
  • the materials of the first conductor group 131 and the third conductor group 231 may be the same, the first conductor group 131 includes at least one of copper and tungsten, and the third conductor group 231 includes copper and tungsten. at least one of tungsten.
  • the materials of the first conductor group 131 and the third conductor group 231 are inconsistent, but the melting points of the two are substantially the same.
  • the materials of the second conductor group 132 and the fourth conductor group 232 can be consistent, the first conductor group 131 includes at least one of copper and tungsten, and the second conductor group 132 includes bismuth, At least one of cadmium, tin, lead, dysprosium and indium.
  • the materials of the second conductor group 132 and the fourth conductor group 232 are inconsistent, but the melting points of the two are substantially the same.
  • first conductor group 131 and the third conductor group 231 may only include a single material, for example, the first conductor group 131 and the third conductor group 231 may both be copper. Alternatively, the first conductor group 131 and the third conductor group 231 may also be alloys, such as copper-tungsten alloy.
  • the second set of electrical conductors 132 and the fourth set of electrical conductors 232 may only include a single material, for example, the second set of electrical conductors 132 and the fourth set of electrical conductors 232 may both be tin. Alternatively, the second conductor group 132 and the fourth conductor group 232 may be alloys, such as bismuth tin, bismuth lead, tin indium and the like.
  • the first set of electrical conductors 131 and the third set of electrical conductors 231 may be copper, while the second set of electrical conductors 132 and the fourth set of electrical conductors 232 may be tin. Due to the compounding effect of the low-melting-point metal tin and the thermal expansion effect of the metal copper, the micro-recesses on the copper surface can be smoothly fused with the low-melting-point metal tin layer. At low temperature fusion (such as the first temperature), the upper and lower layers of tin (Sn) are directly opposite, and copper (Cu) is directly opposite. During the fusion process, tin fuses with the adjacent copper to form Cu5Sn6 metal compound (IMC).
  • IMC Cu5Sn6 metal compound
  • the same materials of the upper and lower layers are relatively designed to form metal compounds to improve the bonding strength, and provide stacked chips (especially the alignment accuracy of the upper and lower layers) with resistance to stacked chip slippage caused by external force or movement, which is beneficial for future use.
  • the upper and lower first conductive contact pads 13 and second conductive contact pads 23 that are annealed at a higher temperature (such as the second temperature) are bonded to improve product yield.
  • the semiconductor structure of the present disclosure can make the upper and lower layers of the low-melting-point metal/alloy bonded at low temperature first, and also have high-strength bonding between high-melting-point metals (such as copper) and high-melting-point metals (such as copper).
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, please refer to FIG. 5 , the method for manufacturing a semiconductor structure includes:
  • the first chip 10 includes a first substrate 11, a first conductive connection 12, and a first conductive contact pad 13, the first conductive contact pad 13 is connected to the first conductive connection 12, the first A conductive contact pad 13 includes a first conductor group 131 and a second conductor group 132, the melting point of the first conductor group 131 is higher than the melting point of the second conductor group 132;
  • the second chip 20 includes a second substrate 21, a second conductive connection 22, and a second conductive contact pad 23, the second conductive contact pad 23 is connected to the second conductive connection 22, the second The second conductive contact pad 23 includes a third conductor group 231 and a fourth conductor group 232, the melting point of the third conductor group 231 is greater than the melting point of the fourth conductor group 232;
  • one end of the first conductive contact pad 13 facing the second conductive contact pad 23 is the first contact surface 14, and one end of the second conductive contact pad 23 facing the first contact surface 14 is the second contact surface 24, and the first conductor group
  • the area occupied by the first contact surface 14 by 131 is smaller than the area occupied by the second conductor group 132, and the area occupied by the third conductor group 231 is smaller than that occupied by the second contact surface 24 by the fourth conductor group 232.
  • the first conductive wire 12 of the first chip 10 is connected to the first conductive contact pad 13, and the second conductive wire 22 of the second chip 20 is connected to the second conductive contact pad 23,
  • the first conductive contact pad 13 includes a first conductive body group 131 and a second conductive body group 132
  • the second conductive contact pad 23 includes a third conductive body group 231 and a fourth conductive body group 232 .
  • the first conductor group 131 is directly opposite to the third conductor group 231
  • the second conductor group 132 is directly opposite to the fourth conductor group 232
  • the melting point of the first conductor group 131 is higher than that of the second conductor group 132.
  • the melting point of the third conductor group 231 is greater than the melting point of the fourth conductor group 232, so the second conductor group 132 and the fourth conductor group 232 can be melted and connected at the first temperature, that is, the first The pre-connection of the conductive contact pad 13 and the second conductive contact pad 23, and then the pre-connected first chip 10 and the second chip 20 are transferred to the second temperature annealing condition for bonding, so as to realize the first conductive contact pad 13 and the second chip 20.
  • connecting the first chip 10 and the second chip 20 includes: melting the second conductor group 132 and the fourth conductor group 232 at a first temperature, so that the first chip 10 and the second chip 20 are connected; Wherein, the first temperature is lower than the melting points of the first conductor group 131 and the third conductor group 231, that is, at the first temperature, the second conductor group 132 and the fourth conductor group 232 melt, while the first conductor group 131 and the third conductive body group 231 are not melted, at this time, the conductive materials of the first conductive contact pad 13 and the second conductive contact pad 23 can respectively infiltrate and fuse with each other at the interface, thereby forming a pre-bonded structure.
  • connecting the first chip 10 and the second chip 20 further includes: bonding the connected first chip 10 and the second chip 20 under the second temperature annealing condition, so that the first conductive contact pad 13 and the second conductive contact pad 23 are melted to form a bonding structure; wherein, the first temperature is lower than the second temperature.
  • the first conductive contact pad 13 and the second conductive contact pad 23 form a pre-bonded structure at the first temperature, so that they can be bonded when moving to the second temperature environment, which can avoid the occurrence of the first chip 10 and the second chip 20. Relative slip, thereby improving the yield rate of the semiconductor structure.
  • first chip 10 and the second chip 20 under the annealing condition at the second temperature are not limited, and reference may be made to the bonding method in the related art, which is highlighted here. Before performing bonding under certain conditions, the first chip 10 and the second chip 20 have been pre-connected.
  • the second conductor group 132 is formed on the first conductor group 131 by electroplating or printing; the fourth conductor group 232 is formed on the third conductor group 231 by electroplating or printing.
  • a method for fabricating a semiconductor structure is used to form the above-mentioned semiconductor structure.
  • the materials and structures of the first chip 10 and the second chip 20 involved in the manufacturing method of the semiconductor structure reference may be made to the specific description of the semiconductor structure above, and details are not repeated here.

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Abstract

本公开涉及半导体技术领域，提出了一种半导体结构及半导体结构的制作方法。半导体结构包括第一芯片和第二芯片，第一芯片的第一导电连线连接第一导电接触垫，第二芯片的第二导电连线连接第二导电接触垫，且第一导电接触垫包括第一导电体组和第二导电体组，第二导电接触垫包括第三导电体组和第四导电体组。通过使得第一导电接触垫和第二导电接触垫的实现预连接，因此不会出现第一芯片和第二芯片相对移动的情况，从而保证后续第一芯片和第二芯片可靠对准，以此改善半导体结构的性能。

Description

半导体结构及半导体结构的制作方法
交叉引用
本公开要求于2021年07月01日提交的申请号为202110746011.4、名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
相关技术中，芯片之间的键合是通过芯片上的金属垫相互连接而实现。堆叠后的芯片在键合前需要进行转运，若有震动或外力影响，将造成堆叠芯片对准受到滑移影响，增加了工艺制作难度。
发明内容
本公开提供一种半导体结构及半导体结构的制作方法，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
第一芯片，第一芯片包括第一衬底、第一导电连线以及第一导电接触垫，第一导电接触垫与第一导电连线相连接，第一导电接触垫包括第一导电体组和第二导电体组，第一导电体组的熔点大于第二导电体组的熔点；
第二芯片，第二芯片包括第二衬底、第二导电连线以及第二导电接触垫，第二导电接触垫与第二导电连线相连接，第二导电接触垫包括第三导电体组和第四导电体组，第三导电体组的熔点大于第四导电体组的熔点，第一导电体组与第三导电体组直接相对，第二导电体组与第四导电体组直接相对，以在第一导电接触垫和第二导电接触垫之间形成键合结构；
其中，第一导电接触垫朝向第二导电接触垫的一端为第一接触面，第二导电接触垫朝向第一接触面的一端为第二接触面，第一导电体组占据第一接触面的面积小于第二导电体组占据第一接触面的面积，第三导电体组占据第二接触面的面积小于第四导电体组占据第二接触面的面积。
根据本公开的第二个方面，提供了一种半导体结构的制作方法，包括：
提供第一芯片，第一芯片包括第一衬底、第一导电连线以及第一导电接触垫，第一导电接触垫与第一导电连线相连接，第一导电接触垫包括第一导电体组和第二导电体组，第一导电体组的熔点大于第二导电体组的熔点；
提供第二芯片，第二芯片包括第二衬底、第二导电连线以及第二导电接触垫，第二导电接触垫与第二导电连线相连接，第二导电接触垫包括第三导电体组和第四导电体组，第三导电体组的熔点大于第四导电体组的熔点；
对准第一芯片和第二芯片，使得第一导电体组与第三导电体组直接相对，第二导电体组与第四导电体组直接相对；
连接第一芯片和第二芯片；
其中，第一导电接触垫朝向第二导电接触垫的一端为第一接触面，第二导电接触垫朝向第一接触面的一端为第二接触面，第一导电体组占据第一接触面的面积小于第二导电体组占据第一接触面的面积，第三导电体组占据第二接触面的面积小于第四导电体组占据第二接触面的面积。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的第一芯片和第二芯片分解结构示意图；
图2是根据一示例性实施方式示出的一种半导体结构的第一芯片和第二芯片局部连接结构示意图；
图3是根据一示例性实施方式示出的一种半导体结构的第一接触面和第一接触面的结构示意图；
图4是根据另一示例性实施方式示出的一种半导体结构的第一接触面和第一接触面的结构示意图；
图5是根据一示例性实施方式示出的一种半导体结构的制作方法的流程示意图。
附图标记说明如下：
10、第一芯片；11、第一衬底；12、第一导电连线；13、第一导电接触垫；131、第 一导电体组；132、第二导电体组；1321、第一子导电段；14、第一接触面；
20、第二芯片；21、第二衬底；22、第二导电连线；23、第二导电接触垫；231、第三导电体组；232、第四导电体组；2321、第二子导电段；24、第二接触面。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构、系统和步骤。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构，请参考图1和图2，半导体结构包括：第一芯片10，第一芯片10包括第一衬底11、第一导电连线12以及第一导电接触垫13，第一导电接触垫13与第一导电连线12相连接，第一导电接触垫13包括第一导电体组131和第二导电体组132，第一导电体组131的熔点大于第二导电体组132的熔点；第二芯片20，第二芯片20包括第二衬底21、第二导电连线22以及第二导电接触垫23，第二导电接触垫23与第二导电连线22相连接，第二导电接触垫23包括第三导电体组231和第四导电体组232，第三导电体组231的熔点大于第四导电体组232的熔点，第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对，以在第一导电接触垫13和第二导电接触垫23之间形成键合结构；其中，第一导电接触垫13朝向第二导电接触垫23的一端为第一接触面14，第二导电接触垫23朝向第一接触面14的一端为第二接触面24，第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积小于第四导电体组232占据第二接触面24的面积。
本公开一个实施例的半导体结构包括第一芯片10和第二芯片20，第一芯片10的第一导电连线12连接第一导电接触垫13，第二芯片20的第二导电连线22连接第二导电接触 垫23，且第一导电接触垫13包括第一导电体组131和第二导电体组132，第二导电接触垫23包括第三导电体组231和第四导电体组232。通过第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对，且第一导电体组131的熔点大于第二导电体组132的熔点，第三导电体组231的熔点大于第四导电体组232的熔点，因此可以在第一温度下使得第二导电体组132和第四导电体组232熔化并连接，即实现了第一导电接触垫13和第二导电接触垫23的预连接，然后将预连接的第一芯片10和第二芯片20转移至第二温度退火条件下进行键合，以实现第一导电接触垫13和第二导电接触垫23的可靠键合，由于转移前第一芯片10和第二芯片20已完成了预连接，因此不会出现第一芯片10和第二芯片20相对移动的情况，从而保证后续第一芯片10和第二芯片20可靠对准，以此改善半导体结构的性能。
需要说明的是，在第一温度下，第二导电体组132和第四导电体组232熔化，而第一导电体组131和第三导电体组231不熔化，此时，第二导电体组132和第四导电体组232可以实现连接，且第一导电接触垫13和第二导电接触垫23的各种金属材料相互渗透融合，如图2所示，因此形成了金属化合物，从而实现第一导电接触垫13和第二导电接触垫23的预连接。由于第一导电接触垫13和第二导电接触垫23完成了预连接，因此在后续转移第一芯片10和第二芯片20的过程中就不会出现第一芯片10和第二芯片20的相对滑移，以此保证第一芯片10和第二芯片20处于可靠对准的连接条件下，将第一芯片10和第二芯片20在第二温度退火条件下进行相互键合，因此实现了第一导电接触垫13和第二导电接触垫23的可靠键合，在第一导电接触垫13和第二导电接触垫23之间形成了可靠的键合结构。而相关技术中，需要将第一芯片10和第二芯片20直接放置于高温环境进行键合，在转移过程中对准受到滑移影响，因此影响半导体结构的性能，本实施例中的半导体结构可以改善相关技术中的对准问题，以提高半导体结构的性能。
第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对，实际上是说明第一芯片10和第二芯片20键合前的位置关系，在键合后，即在第一导电接触垫13和第二导电接触垫23之间形成键合结构时，并不一定存在上述位置关系，导电材料之间可能由于融合并不能确定相应的位置关系，但从材料配置上可以判断上述位置关系。
在一些实施例中，第一导电连线12和第一导电接触垫13均位于第一衬底11内，第二导电连线22和第二导电接触垫23均位于第二衬底21内。
其中，第一导电连线12和第一导电接触垫13可以部分位于第一衬底11内，第一导 电连线12和第一导电接触垫13也可以全部位于第一衬底11内。相应的，第二导电连线22和第二导电接触垫23可以部分位于第二衬底21内，也可以全部位于第二衬底21内。
在一些实施例中，第一导电接触垫13可以位于第一衬底11的表面。相应的，第二导电接触垫23可以位于第二衬底21的表面。
需要注意的是，在第一芯片10和第二芯片20键合后，第一衬底11和第二衬底21相键合。第一衬底11包括硅衬底和形成于硅衬底上方的绝缘层，第一导电连线12的部分位于绝缘层内，第一导电接触垫13形成于绝缘层内。相应的，第二衬底21包括硅衬底和形成于硅衬底上方的绝缘层，第二导电连线22的部分位于绝缘层内，第二导电接触垫23形成于绝缘层内。在第一芯片10和第二芯片20键合时，第一导电接触垫13和第二导电接触垫23相键合，而第一芯片10和第二芯片20的绝缘层相键合。
可选的，第一芯片10的绝缘层与第二导电体组132相邻设置，第二芯片20的绝缘层与第四导电体组232相邻设置，第二导电体组132的膨胀系数远小于第一导电体组131的膨胀系数，相应的，第四导电体组232的膨胀系数远小于第三导电体组231的膨胀系数，因此，在对第一导电接触垫13和第二导电接触垫23进行键合过程中，第二导电体组132和第四导电体组232的膨胀量会较低，因此不会过度挤压已经键合的第一芯片10的绝缘层和第二芯片20的绝缘层，从而避免了绝缘层之间形成裂缝的问题。而相关技术中，铜直接相邻绝缘层，在键合过程中容易将周边已经键合的绝缘层撑开而形成裂缝，而本实施例可以解决上述问题。
具体的，硅衬底可以由含硅材料形成。硅衬底可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
绝缘层可以包括二氧化硅(SiO2)、碳氧化硅(SiOC)、氮化硅(SiN)、碳氮化硅(SiCN)等相关集成电路绝缘材料。
在一个实施例中，第一导电连线12为第一硅通
孔；第二导电连线22为第二硅通孔。第一硅通孔和第二硅通孔通过第一导电接触垫13和第二导电接触垫23实现连接。
在一个实施例中，第二导电体组132的厚度小于1um，第四导电体组232的厚度小于1um。
结合图1所示，第一导电接触垫13朝向第二导电接触垫23的一端为第一接触面14，第二导电接触垫23朝向第一接触面14的一端为第二接触面24；其中，第一导电体组131和第二导电体组132分别占据部分的第一接触面14，第三导电体组231和第四导电体组 232分别占据部分的第二接触面24，且第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积小于第四导电体组232占据第二接触面24的面积。第一芯片10和第二芯片20键合时，第一接触面14和第二接触面24相对接，以此实现第一导电接触垫13和第二导电接触垫23的电连接。
需要说明的是，由于第一导电体组131、第二导电体组132、第三导电体组231以及第四导电体组232均为导电体，因此第一导电接触垫13和第二导电接触垫23之间可以形成一个较大面积的电连接接触面。而将第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积小于第四导电体组232占据第二接触面24的面积，即在第一温度下第二导电体组132和第四导电体组232熔化，从而可以形成一个较大的预连接面，以此保证后续的连接稳定性。
可选的，第一导电体组131和第二导电体组132占据部分的第一接触面14，即第一导电接触垫13还可以包括其他的导电体。相应的，第三导电体组231和第四导电体组232占据部分的第二接触面24，第二导电接触垫23还可以包括其他的导电体。第一导电接触垫13和第二导电接触垫23的其他导电体的熔点不作限定，本公开重点通过限定第一导电体组131和第二导电体组132，以及第二导电体组231和第四导电体组232的熔点关系来体现第一芯片10和第二芯片20在相对低的温度下可以实现预连接。
可选的，第一导电体组131和第二导电体组132占据全部的第一接触面14，即第一导电接触垫13可以仅包括第一导电体组131和第二导电体组132，或者第一导电接触垫13可以包括其他的导电体，但此导电体不位于第一导电接触垫13远离第一导电连线12的端部。相应的，第三导电体组231和第四导电体组232占据全部的第二接触面24，即第二导电接触垫23可以仅包括第三导电体组231和第四导电体组232，或者第二导电接触垫23可以包括其他的导电体，但此导电体不位于第二导电接触垫23远离第二导电连线22的端部。
在一个实施例中，第一导电体组131可以包括多种导电材料，即第一导电体组131可以由多个不同类型的导电材料组合而成，此处的多种类型的导电材料区别于一种金属化合物，即第一导电体组131可以包括多种单一的金属材料，或者多种金属化合物，或者单一金属材料和金属化合物。相应的，第二导电体组132、第三导电体组231以及第四导电体组232均可以参考本实施例，此处不作赘述。
在一个实施例中，第一导电体组131仅包括第一导电体，第二导电体组132仅包括第二导电体；第三导电体组231仅包括第三导电体，第四导电体组232仅包括第四导电体。即第一导电体组131、第二导电体组132、第三导电体组231以及第四导电体组232均是单一的金属材料或者金属化合物。
在一个实施例中，第一接触面14的面积等于第二接触面24的面积，即第一芯片10的融合面的面积和第二芯片20的融合面的面积相一致。第一导电体组131和第二导电体组132占据全部的第一接触面14，且第三导电体组231和第四导电体组232占据全部的第二接触面24时，第一导电体组131占据第一接触面14的面积等于第三导电体组231占据第二接触面24的面积，而第二导电体组132占据第一接触面14的面积等于第四导电体组232占据第二接触面24的面积，以此保证第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对。
可选的，在第一接触面14的面积等于第二接触面24的面积，第一导电体组131和第二导电体组132占据部分的第一接触面14，且第三导电体组231和第四导电体组232占据部分的第二接触面24时，可以保证第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对，而第一导电接触垫13包括的其他导电体与第二导电接触垫23包括的其他导电体直接相对。
在一个实施例中，第一接触面14的面积不等于第二接触面24的面积，即第一芯片10的融合面的面积和第二芯片20的融合面的面积不相一致。在第一接触面14的面积小于第二接触面24的面积时，第二接触面24的部分会与第一衬底11相对。相应的，在第一接触面14的面积大于第二接触面24的面积时，第一接触面14的部分会与第二衬底21相对。
需要说明的是，第一接触面14的面积不等于第二接触面24的面积时，例如，第一接触面14的面积小于第二接触面24的面积时，第一导电体组131和第二导电体组132可以占据全部的第一接触面14，而第三导电体组231和第四导电体组232也可以占据全部的第二接触面24，此时，只要保证全部的第一导电体组131与第三导电体组231直接相对，全部的第二导电体组132与第四导电体组232直接相对即可，而第二导电接触垫23的第三导电体组231和第四导电体组232中的至少之一的其他部分可以直接对应第一衬底11。相应的，对于第一接触面14的面积大于第二接触面24的面积时，也可以参考本实施例，此处不作赘述。
在一个实施例中，第一接触面14的周向外边缘包括直线和曲线中的至少之一，第二接触面24的周向外边缘包括直线和曲线中的至少之一。第一接触面14的形状和第二接触 面24的形状可以完全相同，也可以不相同，第一接触面14的形状和第二接触面24的形状可以是圆形、椭圆形、长方形等各种形状，此处不作限定。
需要说明的是，当第一接触面14的面积等于第二接触面24的面积，第一导电体组131和第二导电体组132占据全部的第一接触面14，且第三导电体组231和第四导电体组232占据全部的第二接触面24时，则可以说明第一接触面14的形状和第二接触面24的形状完全相同，且第一接触面14和第二接触面24完全重合。
在一个实施例中，第一导电体组131占据第一导电接触垫13的体积大于第二导电体组132占据第一导电接触垫13的体积；第三导电体组231占据第二导电接触垫23的体积大于第四导电体组232占据第二导电接触垫23的体积。即第一导电接触垫13和第二导电接触垫23的低熔点的导电材料占比相对较低。
在一个实施例中，第一导电连线12的一端均连接于第一导电体组131上；第二导电连线22的一端均连接于第三导电体组231上。即第一导电接触垫13远离第一导电连线12的一侧才包括有第二导电体组132，第二导电接触垫23远离第二导电连线22的一侧才包括有第四导电体组232。
需要注意的是，第一导电连线12的一端均连接于第一导电体组131上，第二导电连线22的一端均连接于第三导电体组231上，可以进一步理解为，第一芯片10和第二芯片20键合前，第一导电连线12的一端均连接于第一导电体组131上，第二导电连线22的一端均连接于第三导电体组231上，而在第一导电接触垫13和第二导电接触垫23之间形成键合结构后，可能存在导电材料之间融合的可能性，但从材料配置上也可以判断上述结构关系。
在一个实施例中，第二导电体组132包括多个第一子连接段1321，相邻第一子连接段1321之间夹持第一导电体组131的一部分，即可以理解为是在第一导电体组131远离第一导电连线12的一侧形成有空隙，以此填充第一子连接段1321。
在一个实施例中，第四导电体组232包括多个第二子连接段2321，相邻第二子连接段2321之间夹持第三导电体组231的一部分，即可以理解为是在第三导电体组231远离第二导电连线22的一侧形成有空隙，以此填充第二子连接段2321。
结合图1和图3所示，第一接触面14的面积等于第二接触面24的面积，且第一导电体组131和第二导电体组132占据全部的第一接触面14，第三导电体组231和第四导电体组232占据全部的第二接触面24，而第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积 小于第四导电体组232占据第二接触面24的面积，以此保证第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对。而第二导电体组132包括多个第一子连接段1321，第四导电体组232包括多个第二子连接段2321。
结合图4所示，第一接触面14的面积等于第二接触面24的面积，且第一导电体组131和第二导电体组132占据全部的第一接触面14，第三导电体组231和第四导电体组232占据全部的第二接触面24，而第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积小于第四导电体组232占据第二接触面24的面积，以此保证第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对。而第一导电体组131的一部分夹持于两个第一子连接段1321内，第三导电体组231的一部分夹持于两个第二子连接段2321内。
在一个实施例中，第一导电体组131和第三导电体组231的材料可以相一致，第一导电体组131包括铜和钨中的至少一种，第三导电体组231包括铜和钨中的至少一种。当然，在某些实施例中，不排除第一导电体组131和第三导电体组231的材料不相一致，但二者的熔点大致相同。
在一个实施例中，第二导电体组132和第四导电体组232的材料可以相一致，第一导电体组131包括铜和钨中的至少一种，第二导电体组132包括铋、镉、锡、铅、镝以及铟中的至少一种。当然，在某些实施例中，不排除第二导电体组132和第四导电体组232的材料不相一致，但二者的熔点大致相同。
需要说明的是，第一导电体组131和第三导电体组231可以仅包括单一材料，例如，第一导电体组131和第三导电体组231可以均是铜。或者，第一导电体组131和第三导电体组231也可以是合金，例如铜钨合金。第二导电体组132和第四导电体组232可以仅包括单一材料，例如，第二导电体组132和第四导电体组232可以均是锡。或者，第二导电体组132和第四导电体组232可以是合金，例如铋锡、铋铅、锡铟等。
在一个实施例中，第一导电体组131和第三导电体组231可以是铜，而第二导电体组132和第四导电体组232可以是锡。由于低熔点金属锡的化合效应以及金属铜的热膨胀效应，铜表面微内凹能顺利与低熔点金属锡层进行融合。在低温融合(如第一温度)时，上下层的锡(Sn)直接相对，铜(Cu)直接相对，在融合过程中锡与旁边的铜融合，形成Cu5Sn6金属化合物(IMC)。此上下层相同材质相对设计，可以形成金属化合物，以提高键合强度，并向堆叠后芯片(尤其上下层芯片对准精度)提供因外力或搬动造成堆叠芯 片滑移的抵抗力，利于之后进行较高温(如第二温度)退火的上下层第一导电接触垫13和第二导电接触垫23键合，提升产品成品率。
本公开的半导体结构可以使得低温融合的低熔点金属/合金上下层能先键合，同时也能兼具有高熔点金属(如铜)与高熔点金属(如铜)的高强度键合。
本公开的一个实施例还提供了一种半导体结构的制作方法，请参考图5，半导体结构的制作方法包括：
S101，提供第一芯片10，第一芯片10包括第一衬底11、第一导电连线12以及第一导电接触垫13，第一导电接触垫13与第一导电连线12相连接，第一导电接触垫13包括第一导电体组131和第二导电体组132，第一导电体组131的熔点大于第二导电体组132的熔点；
S103，提供第二芯片20，第二芯片20包括第二衬底21、第二导电连线22以及第二导电接触垫23，第二导电接触垫23与第二导电连线22相连接，第二导电接触垫23包括第三导电体组231和第四导电体组232，第三导电体组231的熔点大于第四导电体组232的熔点；
S105，对准第一芯片10和第二芯片20，使得第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对；
S107，连接第一芯片10和第二芯片20；
其中，第一导电接触垫13朝向第二导电接触垫23的一端为第一接触面14，第二导电接触垫23朝向第一接触面14的一端为第二接触面24，第一导电体组131占据第一接触面14的面积小于第二导电体组132占据第一接触面14的面积，第三导电体组231占据第二接触面24的面积小于第四导电体组232占据第二接触面24的面积。
本公开一个实施例的半导体结构的制作方法的第一芯片10的第一导电连线12连接第一导电接触垫13，第二芯片20的第二导电连线22连接第二导电接触垫23，且第一导电接触垫13包括第一导电体组131和第二导电体组132，第二导电接触垫23包括第三导电体组231和第四导电体组232。通过第一导电体组131与第三导电体组231直接相对，第二导电体组132与第四导电体组232直接相对，且第一导电体组131的熔点大于第二导电体组132的熔点，第三导电体组231的熔点大于第四导电体组232的熔点，因此可以在第一温度下使得第二导电体组132和第四导电体组232熔化并连接，即实现了第一导电接触垫13和第二导电接触垫23的预连接，然后将预连接的第一芯片10和第二芯片20转移至第二温度退火条件下进行键合，以实现第一导电接触垫13和第二导电接触垫23的可靠键 合，由于转移前第一芯片10和第二芯片20已完成了预连接，因此不会出现第一芯片10和第二芯片20相对移动的情况，从而保证后续第一芯片10和第二芯片20可靠对准，以此改善半导体结构的性能。
在一个实施例中，连接第一芯片10和第二芯片20包括：采用第一温度熔化第二导电体组132与第四导电体组232，以使得第一芯片10和第二芯片20连接；其中，第一温度小于第一导电体组131和第三导电体组231的熔点，即在第一温度下，第二导电体组132和第四导电体组232熔化，而第一导电体组131和第三导电体组231不熔化，此时，第一导电接触垫13和第二导电接触垫23的导电材料可以各自在交界面处相互渗透融合，以此形成预键合结构。
在一个实施例中，连接第一芯片10和第二芯片20还包括：将连接后的第一芯片10和第二芯片20在第二温度退火条件下进行键合，以使得第一导电接触垫13和第二导电接触垫23熔化后形成键合结构；其中，第一温度小于第二温度。第一导电接触垫13和第二导电接触垫23在第一温度下形成了预键合结构，从而在移动至第二温度环境下进行键合，可以避免第一芯片10和第二芯片20出现相对滑移，以此提高半导体结构的良品率。
需要说明的是，第一芯片10和第二芯片20在第二温度退火条件下进行键合的具体过程不作限定，可以参考相关技术中的键合方式，此处重点体现，在第二温度退火条件下进行键合之前，第一芯片10和第二芯片20已完成了预连接。
在一个实施例中，采用电镀方法或印刷方法在第一导电体组131上形成第二导电体组132；采用电镀方法或印刷方法在第三导电体组231上形成第四导电体组232。
需要说明的是，在一个实施例中，半导体结构的制作方法用于形成上述的半导体结构。对于半导体结构的制作方法中涉及的第一芯片10和第二芯片20的材料以及结构可以参考上述半导体结构的具体说明，此处不作赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种半导体结构，包括：
    第一芯片，所述第一芯片包括第一衬底、第一导电连线以及第一导电接触垫，所述第一导电接触垫与所述第一导电连线相连接，所述第一导电接触垫包括第一导电体组和第二导电体组，所述第一导电体组的熔点大于所述第二导电体组的熔点；
    第二芯片，所述第二芯片包括第二衬底、第二导电连线以及第二导电接触垫，所述第二导电接触垫与所述第二导电连线相连接，所述第二导电接触垫包括第三导电体组和第四导电体组，所述第三导电体组的熔点大于所述第四导电体组的熔点，所述第一导电体组与所述第三导电体组直接相对，所述第二导电体组与所述第四导电体组直接相对，以在所述第一导电接触垫和所述第二导电接触垫之间形成键合结构；
    其中，所述第一导电接触垫朝向所述第二导电接触垫的一端为第一接触面，所述第二导电接触垫朝向所述第一接触面的一端为第二接触面，所述第一导电体组占据所述第一接触面的面积小于所述第二导电体组占据所述第一接触面的面积，所述第三导电体组占据所述第二接触面的面积小于所述第四导电体组占据所述第二接触面的面积。
  2. 根据权利要求1所述的半导体结构，其中，所述第一导电体组和所述第二导电体组占据全部的所述第一接触面，所述第三导电体组和所述第四导电体组占据全部的所述第二接触面。
  3. 根据权利要求2所述的半导体结构，其中，所述第一导电体组仅包括第一导电体，所述第二导电体组仅包括第二导电体；
    所述第三导电体组仅包括第三导电体，所述第四导电体组仅包括第四导电体。
  4. 根据权利要求3所述的半导体结构，其中，所述第一接触面的面积等于所述第二接触面的面积；
    其中，所述第一导电体组占据所述第一接触面的面积等于所述第三导电体组占据所述第二接触面的面积。
  5. 根据权利要求3所述的半导体结构，其中，所述第一接触面的面积不等于所述第二接触面的面积。
  6. 根据权利要求2所述的半导体结构，其中，所述第一接触面的周向外边缘包括直线和曲线中的至少之一，所述第二接触面的周向外边缘包括直线和曲线中的至少之一。
  7. 根据权利要求1至6中任一项所述的半导体结构，其中，所述第一导电体组占据所 述第一导电接触垫的体积大于所述第二导电体组占据所述第一导电接触垫的体积；
    所述第三导电体组占据所述第二导电接触垫的体积大于所述第四导电体组占据所述第二导电接触垫的体积。
  8. 根据权利要求7所述的半导体结构，其中，所述第一导电连线的一端均连接于所述第一导电体组上；
    所述第二导电连线的一端均连接于所述第三导电体组上。
  9. 根据权利要求8所述的半导体结构，其中，所述第二导电体组包括多个第一子导电段，相邻所述第一子导电段之间夹持所述第一导电体组的一部分；
    和/或，所述第四导电体组包括多个第二子导电段，相邻所述第二子导电段之间夹持所述第三导电体组的一部分。
  10. 根据权利要求7所述的半导体结构，其中，所述第一导电体组包括铜和钨中的至少一种，所述第二导电体组包括铋、镉、锡、铅、镝以及铟中的至少一种；
    所述第三导电体组包括铜和钨中的至少一种，所述第四导电体组包括铋、镉、锡、铅、镝以及铟中的至少一种。
  11. 根据权利要求1所述的半导体结构，其中，所述第一导电连线为第一硅通孔；
    所述第二导电连线为第二硅通孔。
  12. 根据权利要求1所述的半导体结构，其中，所述第一导电连线和所述第一导电接触垫均位于所述第一衬底内。
  13. 根据权利要求1所述的半导体结构，其中，所述第二导电连线和所述第二导电接触垫均位于所述第二衬底内。
  14. 根据权利要求1所述的半导体结构，其中，所述第一导电体组和所述第三导电体组的材料相一致。
  15. 根据权利要求1所述的半导体结构，其中，所述第二导电体组和所述第四导电体组的材料相一致。
  16. 根据权利要求1所述的半导体结构，其特征在于，所述第二导电体组的厚度小于1um，所述第四导电体组的厚度小于1um。
  17. 一种半导体结构的制作方法，包括：
    提供第一芯片，所述第一芯片包括第一衬底、第一导电连线以及第一导电接触垫，所述第一导电接触垫与所述第一导电连线相连接，所述第一导电接触垫包括第一导电体组和第二导电体组，所述第一导电体组的熔点大于所述第二导电体组的熔点；
    提供第二芯片，所述第二芯片包括第二衬底、第二导电连线以及第二导电接触垫，所述第二导电接触垫与所述第二导电连线相连接，所述第二导电接触垫包括第三导电体组和第四导电体组，所述第三导电体组的熔点大于所述第四导电体组的熔点；
    对准所述第一芯片和所述第二芯片，使得所述第一导电体组与所述第三导电体组直接相对，所述第二导电体组与所述第四导电体组直接相对；
    连接所述第一芯片和所述第二芯片；
    其中，所述第一导电接触垫朝向所述第二导电接触垫的一端为第一接触面，所述第二导电接触垫朝向所述第一接触面的一端为第二接触面，所述第一导电体组占据所述第一接触面的面积小于所述第二导电体组占据所述第一接触面的面积，所述第三导电体组占据所述第二接触面的面积小于所述第四导电体组占据所述第二接触面的面积。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，连接所述第一芯片和所述第二芯片包括：
    采用第一温度熔化所述第二导电体组与所述第四导电体组，以使得所述第一芯片和所述第二芯片连接；
    其中，所述第一温度小于所述第一导电体组和所述第三导电体组的熔点。
  19. 根据权利要求18所述的半导体结构的制作方法，其中，连接所述第一芯片和所述第二芯片还包括：
    将连接后的所述第一芯片和所述第二芯片在第二温度退火条件下进行键合，以使得所述第一导电接触垫和所述第二导电接触垫之间形成键合结构；
    其中，所述第一温度小于所述第二温度。
  20. 根据权利要求17至19中任一项所述的半导体结构的制作方法，其中，采用电镀方法或印刷方法在所述第一导电体组上形成所述第二导电体组；
    采用电镀方法或印刷方法在所述第三导电体组上形成所述第四导电体组。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US20220375824A1 (en) * 2021-05-19 2022-11-24 Changxin Memory Technologies, Inc. Die, memory and method of manufacturing die

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160013160A1 (en) * 2014-07-11 2016-01-14 Samsung Electronics Co., Ltd. Wafer-to-wafer bonding structure
US20160197049A1 (en) * 2013-03-15 2016-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Bonding with Air-Gap Structure
CN106571334A (zh) * 2016-10-26 2017-04-19 上海集成电路研发中心有限公司 一种硅片间的混合键合方法
US20180269172A1 (en) * 2017-03-17 2018-09-20 Invensas Bonding Technologies, Inc. Multi-metal contact structure
CN111801793A (zh) * 2018-04-11 2020-10-20 伊文萨思粘合技术公司 低温结合结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794202B2 (en) * 2000-03-15 2004-09-21 Tessera, Inc. Assemblies for temporarily connecting microelectronic elements for testing and methods therefor
US20050003650A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Three-dimensional stacked substrate arrangements
CN109243974A (zh) * 2018-08-02 2019-01-18 中国电子科技集团公司第五十五研究所 一种减小晶圆键合对准偏差的方法
KR102661959B1 (ko) * 2018-09-20 2024-04-30 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
US11444039B2 (en) * 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same
US20230299029A1 (en) * 2022-03-16 2023-09-21 Adeia Semiconductor Bonding Technologies Inc. Expansion control for bonding

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160197049A1 (en) * 2013-03-15 2016-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Bonding with Air-Gap Structure
US20160013160A1 (en) * 2014-07-11 2016-01-14 Samsung Electronics Co., Ltd. Wafer-to-wafer bonding structure
CN106571334A (zh) * 2016-10-26 2017-04-19 上海集成电路研发中心有限公司 一种硅片间的混合键合方法
US20180269172A1 (en) * 2017-03-17 2018-09-20 Invensas Bonding Technologies, Inc. Multi-metal contact structure
CN111801793A (zh) * 2018-04-11 2020-10-20 伊文萨思粘合技术公司 低温结合结构

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