TW200733099A - Dynamic semiconductor memory with improved refresh mechanism - Google Patents
Dynamic semiconductor memory with improved refresh mechanismInfo
- Publication number
- TW200733099A TW200733099A TW095123712A TW95123712A TW200733099A TW 200733099 A TW200733099 A TW 200733099A TW 095123712 A TW095123712 A TW 095123712A TW 95123712 A TW95123712 A TW 95123712A TW 200733099 A TW200733099 A TW 200733099A
- Authority
- TW
- Taiwan
- Prior art keywords
- refresh
- address
- normal access
- dynamic semiconductor
- semiconductor memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77610906P | 2006-02-23 | 2006-02-23 | |
| US11/378,183 US7313047B2 (en) | 2006-02-23 | 2006-03-16 | Dynamic semiconductor memory with improved refresh mechanism |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200733099A true TW200733099A (en) | 2007-09-01 |
| TWI303422B TWI303422B (en) | 2008-11-21 |
Family
ID=38319969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095123712A TWI303422B (en) | 2006-02-23 | 2006-06-30 | Dynamic semiconductor memory with improved refresh mechanism |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US7313047B2 (zh) |
| JP (1) | JP5063041B2 (zh) |
| KR (1) | KR100810040B1 (zh) |
| CN (1) | CN100573709C (zh) |
| DE (1) | DE102006029703A1 (zh) |
| TW (1) | TWI303422B (zh) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7313047B2 (en) * | 2006-02-23 | 2007-12-25 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
| JP5045337B2 (ja) * | 2007-09-27 | 2012-10-10 | 富士通セミコンダクター株式会社 | 半導体メモリ、半導体メモリの動作方法およびシステム |
| KR100919810B1 (ko) * | 2008-03-18 | 2009-10-01 | 주식회사 하이닉스반도체 | 리프래쉬 제어 장치 |
| CN102037514A (zh) * | 2008-05-21 | 2011-04-27 | Nxp股份有限公司 | 包括重排网络的数据处理系统 |
| CN102037652A (zh) | 2008-05-21 | 2011-04-27 | Nxp股份有限公司 | 包括存储器组的数据处理系统和数据重排 |
| KR100919815B1 (ko) * | 2008-08-04 | 2009-10-01 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| US7755967B2 (en) * | 2008-09-29 | 2010-07-13 | Qimonda North America Corp. | Memory device refresh method and apparatus |
| KR100974225B1 (ko) * | 2008-12-23 | 2010-08-06 | 주식회사 하이닉스반도체 | 임피던스 조정 주기 설정회로 및 반도체 집적회로 |
| JP2010182350A (ja) * | 2009-02-03 | 2010-08-19 | Renesas Electronics Corp | 半導体記憶装置 |
| JP2011018427A (ja) * | 2009-07-10 | 2011-01-27 | Renesas Electronics Corp | 半導体記憶装置 |
| KR20110030779A (ko) * | 2009-09-18 | 2011-03-24 | 삼성전자주식회사 | 메모리 장치, 이를 구비하는 메모리 시스템 및 이의 제어 방법 |
| CN102024491B (zh) * | 2009-09-22 | 2013-07-24 | 无锡华润上华半导体有限公司 | 随机读写存储器及其控制方法 |
| US8310893B2 (en) * | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
| KR20110093086A (ko) * | 2010-02-11 | 2011-08-18 | 삼성전자주식회사 | 셀프 리프레쉬 동작 모드에서 내부 고 전원전압을 사용하는 반도체 메모리 장치 및 그에 따른 고 전원전압 인가방법 |
| JP5430484B2 (ja) * | 2010-04-15 | 2014-02-26 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置、及びその制御方法 |
| US8250298B2 (en) | 2010-05-27 | 2012-08-21 | International Business Machines Corporation | Mechanisms for reducing DRAM power consumption |
| US9053812B2 (en) | 2010-09-24 | 2015-06-09 | Intel Corporation | Fast exit from DRAM self-refresh |
| US9292426B2 (en) * | 2010-09-24 | 2016-03-22 | Intel Corporation | Fast exit from DRAM self-refresh |
| US9286965B2 (en) * | 2010-12-03 | 2016-03-15 | Rambus Inc. | Memory refresh method and devices |
| KR20130042236A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 메모리 시스템 |
| TWI456739B (zh) * | 2011-12-13 | 2014-10-11 | Nat Univ Tsing Hua | 三維記憶體晶片之控制結構 |
| KR101975029B1 (ko) | 2012-05-17 | 2019-08-23 | 삼성전자주식회사 | 리프레쉬 주기를 조절하는 반도체 메모리 장치, 메모리 시스템 및 그 동작방법 |
| KR102011796B1 (ko) * | 2012-08-30 | 2019-08-20 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
| KR102107470B1 (ko) * | 2013-02-07 | 2020-05-07 | 삼성전자주식회사 | 메모리 장치 및 메모리 장치의 리프레시 방법 |
| US9570146B1 (en) * | 2013-02-27 | 2017-02-14 | Rambus Inc. | Alternate access to DRAM data using cycle stealing |
| KR20140139848A (ko) | 2013-05-28 | 2014-12-08 | 에스케이하이닉스 주식회사 | 어드레스 검출회로, 이를 포함하는 메모리 시스템 및 어드레스 검출방법 |
| US8982654B2 (en) | 2013-07-05 | 2015-03-17 | Qualcomm Incorporated | DRAM sub-array level refresh |
| KR20150113364A (ko) * | 2014-03-28 | 2015-10-08 | 에스케이하이닉스 주식회사 | 반도체 메모리 및 그의 동작방법 |
| KR20160041329A (ko) | 2014-10-07 | 2016-04-18 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| KR20160045461A (ko) * | 2014-10-17 | 2016-04-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그의 구동방법 |
| KR20160063726A (ko) | 2014-11-27 | 2016-06-07 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
| KR20160074920A (ko) | 2014-12-19 | 2016-06-29 | 에스케이하이닉스 주식회사 | 메모리 장치 |
| US20170110178A1 (en) * | 2015-09-17 | 2017-04-20 | Intel Corporation | Hybrid refresh with hidden refreshes and external refreshes |
| US9875785B2 (en) * | 2015-10-01 | 2018-01-23 | Qualcomm Incorporated | Refresh timer synchronization between memory controller and memory |
| KR20170082199A (ko) | 2016-01-05 | 2017-07-14 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| US9928895B2 (en) * | 2016-02-03 | 2018-03-27 | Samsung Electronics Co., Ltd. | Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof |
| US9514800B1 (en) | 2016-03-26 | 2016-12-06 | Bo Liu | DRAM and self-refresh method |
| US10394719B2 (en) * | 2017-01-25 | 2019-08-27 | Samsung Electronics Co., Ltd. | Refresh aware replacement policy for volatile memory cache |
| CN106951276B (zh) * | 2017-02-09 | 2020-05-12 | 苏州精控能源科技有限公司 | 多控制器的软件升级及地址冲突检测方法、装置 |
| US10141042B1 (en) * | 2017-05-23 | 2018-11-27 | Micron Technology, Inc. | Method and apparatus for precharge and refresh control |
| EP3454337B1 (en) * | 2017-09-06 | 2019-09-11 | Tu Kaiserslautern | Using runtime reverse engineering to optimize dram refresh |
| TWI682402B (zh) * | 2017-09-11 | 2020-01-11 | 湯朝景 | 應用於動態隨機存取記憶體的主動更新方法以及電路 |
| TWI639920B (zh) | 2017-11-17 | 2018-11-01 | 財團法人工業技術研究院 | 記憶體控制器及其控制方法以及記憶體及其控制方法 |
| US10269442B1 (en) | 2017-12-28 | 2019-04-23 | Micron Technology, Inc. | Drift mitigation with embedded refresh |
| CN110556139B (zh) * | 2018-05-31 | 2021-06-18 | 联发科技股份有限公司 | 用以控制存储器的电路及相关的方法 |
| US10685696B2 (en) * | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
| WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
| US11069393B2 (en) | 2019-06-04 | 2021-07-20 | Micron Technology, Inc. | Apparatuses and methods for controlling steal rates |
| US11302377B2 (en) | 2019-10-16 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic targeted refresh steals |
| CN112712833A (zh) * | 2019-10-25 | 2021-04-27 | 长鑫存储技术(上海)有限公司 | 写操作电路、半导体存储器和写操作方法 |
| US11348631B2 (en) | 2020-08-19 | 2022-05-31 | Micron Technology, Inc. | Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed |
| US11934654B2 (en) * | 2020-12-08 | 2024-03-19 | Rambus Inc. | Memory device having hidden refresh |
| US11264079B1 (en) | 2020-12-18 | 2022-03-01 | Micron Technology, Inc. | Apparatuses and methods for row hammer based cache lockdown |
| US11670356B2 (en) | 2021-07-16 | 2023-06-06 | Micron Technology, Inc. | Apparatuses and methods for refresh address masking |
Family Cites Families (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132595A (en) | 1979-04-04 | 1980-10-15 | Nec Corp | Semiconductor circuit |
| JPS61269296A (ja) * | 1985-05-24 | 1986-11-28 | Hitachi Micro Comput Eng Ltd | 半導体メモリ装置 |
| JPH05347093A (ja) * | 1992-06-16 | 1993-12-27 | Seiko Instr Inc | Ｄｒａｍのリフレッシュ回路およびリフレッシュ方法 |
| JPH08129881A (ja) * | 1994-10-31 | 1996-05-21 | Ricoh Co Ltd | Ｓｄｒａｍ制御装置 |
| US5627791A (en) | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
| US5835401A (en) * | 1996-12-05 | 1998-11-10 | Cypress Semiconductor Corporation | Dram with hidden refresh |
| US6589407B1 (en) * | 1997-05-23 | 2003-07-08 | Applied Materials, Inc. | Aluminum deposition shield |
| US6005818A (en) * | 1998-01-20 | 1999-12-21 | Stmicroelectronics, Inc. | Dynamic random access memory device with a latching mechanism that permits hidden refresh operations |
| JP3490887B2 (ja) * | 1998-03-05 | 2004-01-26 | シャープ株式会社 | 同期型半導体記憶装置 |
| JPH11312386A (ja) * | 1998-03-30 | 1999-11-09 | Siemens Ag | Ｄｒａｍチップ |
| JPH11339469A (ja) * | 1998-05-26 | 1999-12-10 | Hitachi Ltd | 半導体記憶装置 |
| US6496437B2 (en) * | 1999-01-20 | 2002-12-17 | Monolithic Systems Technology, Inc. | Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory |
| US6356485B1 (en) * | 1999-02-13 | 2002-03-12 | Integrated Device Technology, Inc. | Merging write cycles by comparing at least a portion of the respective write cycle addresses |
| JP2000251467A (ja) * | 1999-03-02 | 2000-09-14 | Nec Ibaraki Ltd | メモリリフレッシュ制御装置およびその制御方法 |
| US6282606B1 (en) * | 1999-04-02 | 2001-08-28 | Silicon Aquarius, Inc. | Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods |
| JP2001023372A (ja) * | 1999-05-06 | 2001-01-26 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| TW430793B (en) * | 1999-05-20 | 2001-04-21 | Ind Tech Res Inst | Self-row identification hidden-type refresh-circuit and refresh method |
| JP2001118383A (ja) | 1999-10-20 | 2001-04-27 | Fujitsu Ltd | リフレッシュを自動で行うダイナミックメモリ回路 |
| US6195303B1 (en) * | 1999-10-25 | 2001-02-27 | Winbond Electronics Corporation | Clock-based transparent refresh mechanisms for DRAMS |
| JP4707244B2 (ja) * | 2000-03-30 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置および半導体装置 |
| JP2002008370A (ja) * | 2000-06-21 | 2002-01-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6445636B1 (en) | 2000-08-17 | 2002-09-03 | Micron Technology, Inc. | Method and system for hiding refreshes in a dynamic random access memory |
| US6941415B1 (en) * | 2000-08-21 | 2005-09-06 | Micron Technology, Inc. | DRAM with hidden refresh |
| WO2002019341A2 (en) | 2000-08-30 | 2002-03-07 | Micron Technology, Inc. | Semiconductor memory having dual port cell supporting hidden refresh |
| JP3705113B2 (ja) * | 2000-10-27 | 2005-10-12 | セイコーエプソン株式会社 | 半導体メモリ装置内のワード線の活性化 |
| JP4767401B2 (ja) * | 2000-10-30 | 2011-09-07 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置及びその製造方法 |
| US6430073B1 (en) | 2000-12-06 | 2002-08-06 | International Business Machines Corporation | Dram CAM cell with hidden refresh |
| JP4749538B2 (ja) * | 2000-12-11 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| KR100408402B1 (ko) * | 2001-03-27 | 2003-12-06 | 삼성전자주식회사 | 메모리셀 액세스 시간을 줄일 수 있는 반도체메모리장치의 리프레쉬 방법 |
| JP2004288226A (ja) * | 2001-03-30 | 2004-10-14 | Internatl Business Mach Corp <Ibm> | Ｄｒａｍ及びｄｒａｍのリフレッシュ方法 |
| US6529433B2 (en) * | 2001-04-03 | 2003-03-04 | Hynix Semiconductor, Inc. | Refresh mechanism in dynamic memories |
| JP2002304885A (ja) * | 2001-04-05 | 2002-10-18 | Fujitsu Ltd | 半導体集積回路 |
| KR100396894B1 (ko) * | 2001-06-27 | 2003-09-02 | 삼성전자주식회사 | 버스 효율을 향상시키는 메모리 시스템 및 반도체 메모리장치와 상기 반도체 메모리 장치의 리프레쉬 방법 |
| US6757784B2 (en) | 2001-09-28 | 2004-06-29 | Intel Corporation | Hiding refresh of memory and refresh-hidden memory |
| JP2003297080A (ja) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2003317472A (ja) * | 2002-04-17 | 2003-11-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6665224B1 (en) * | 2002-05-22 | 2003-12-16 | Infineon Technologies Ag | Partial refresh for synchronous dynamic random access memory (SDRAM) circuits |
| US6862238B1 (en) * | 2003-09-25 | 2005-03-01 | Infineon Technologies Ag | Memory system with reduced refresh current |
| US7042785B2 (en) * | 2003-12-19 | 2006-05-09 | Infineon Technologies, Ag | Method and apparatus for controlling refresh cycles of a plural cycle refresh scheme in a dynamic memory |
| US6859407B1 (en) | 2004-01-14 | 2005-02-22 | Infineon Technologies Ag | Memory with auto refresh to designated banks |
| US7088632B2 (en) * | 2004-05-26 | 2006-08-08 | Freescale Semiconductor, Inc. | Automatic hidden refresh in a dram and method therefor |
| US7313047B2 (en) | 2006-02-23 | 2007-12-25 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
-
2006
- 2006-03-16 US US11/378,183 patent/US7313047B2/en active Active
- 2006-06-28 DE DE102006029703A patent/DE102006029703A1/de not_active Withdrawn
- 2006-06-30 TW TW095123712A patent/TWI303422B/zh not_active IP Right Cessation
- 2006-06-30 JP JP2006182788A patent/JP5063041B2/ja not_active Expired - Fee Related
- 2006-07-03 KR KR1020060062197A patent/KR100810040B1/ko not_active IP Right Cessation
- 2006-07-21 CN CNB200610105992XA patent/CN100573709C/zh not_active Expired - Fee Related
-
2007
- 2007-11-14 US US11/985,580 patent/US7869297B2/en active Active
-
2010
- 2010-11-05 US US12/940,490 patent/US8072829B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7313047B2 (en) | 2007-12-25 |
| CN101026003A (zh) | 2007-08-29 |
| US20110051528A1 (en) | 2011-03-03 |
| US7869297B2 (en) | 2011-01-11 |
| CN100573709C (zh) | 2009-12-23 |
| JP2007226934A (ja) | 2007-09-06 |
| KR100810040B1 (ko) | 2008-03-06 |
| KR20070087477A (ko) | 2007-08-28 |
| JP5063041B2 (ja) | 2012-10-31 |
| TWI303422B (en) | 2008-11-21 |
| US8072829B2 (en) | 2011-12-06 |
| DE102006029703A1 (de) | 2007-08-30 |
| US20080137464A1 (en) | 2008-06-12 |
| US20070195627A1 (en) | 2007-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW200733099A (en) | Dynamic semiconductor memory with improved refresh mechanism | |
| CN111292789B (zh) | 半导体存储器件及其操作方法 | |
| TW200710651A (en) | Automatic detection of micro-tile enabled memory | |
| WO2010080342A3 (en) | Pseudo dual-ported sram | |
| WO2008055270A3 (en) | Writing to asymmetric memory | |
| GB2442162A (en) | Technique to write to a non-volatile memory | |
| TW200710661A (en) | Memory controller interface for micro-tiled memory access | |
| WO2009060459A3 (en) | Shared memory system for a tightly-coupled multiprocessor | |
| ATE373307T1 (de) | Simultaner mehrbank für flash-speicher | |
| ATE448548T1 (de) | Mehrspalten-adressierungsmodus-speichersystem mit einem integrierten schaltungsspeicherbaustein | |
| WO2007015773A3 (en) | Memory device and method having multiple address, data and command buses | |
| US8395950B2 (en) | Memory device having a clock skew generator | |
| TW200709216A (en) | Memory device and method having a data bypass path to allow rapid testing and calibration | |
| BRPI0608200A2 (pt) | leitura de registrador para memória volátil | |
| GB201015450D0 (en) | Memory link initialization | |
| CN102479543A (zh) | 验证半导体存储器器件的多周期自刷新操作及其测试 | |
| TW200636724A (en) | Temperature sensor instruction signal generator and semiconductor memory device having the same | |
| JP2016526749A5 (zh) | ||
| TW200518095A (en) | Dynamic random access memory with smart refresh scheduler | |
| US9842641B2 (en) | Semiconductor device and operating method thereof | |
| US8649238B2 (en) | Semiconductor memory device and method of controlling the same | |
| US8902685B2 (en) | Memory device and method for operating the same | |
| KR100920845B1 (ko) | 로우 어드레스 디코더 및 이를 포함하는 반도체 메모리장치 | |
| JP2002352576A (ja) | 半導体記憶装置 | |
| KR100752639B1 (ko) | 외부 리프레쉬 핀과 외부 리프레쉬 뱅크 어드레스 핀을갖는 메모리 장치 및 그 리프레쉬 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |