SG143987A1 - Method for enhancing electrode surface area in dram cell capacitors - Google Patents

Method for enhancing electrode surface area in dram cell capacitors

Info

Publication number
SG143987A1
SG143987A1 SG200607169-0A SG2006071690A SG143987A1 SG 143987 A1 SG143987 A1 SG 143987A1 SG 2006071690 A SG2006071690 A SG 2006071690A SG 143987 A1 SG143987 A1 SG 143987A1
Authority
SG
Singapore
Prior art keywords
forming
lower electrode
texturizing
depositing
layer
Prior art date
Application number
SG200607169-0A
Other languages
English (en)
Inventor
Donald L Yates
Garry A Mercaldi
James J Hofmann
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG143987A1 publication Critical patent/SG143987A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
SG200607169-0A 2002-01-16 2003-01-16 Method for enhancing electrode surface area in dram cell capacitors SG143987A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/050,390 US6794704B2 (en) 2002-01-16 2002-01-16 Method for enhancing electrode surface area in DRAM cell capacitors

Publications (1)

Publication Number Publication Date
SG143987A1 true SG143987A1 (en) 2008-07-29

Family

ID=21964982

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200607169-0A SG143987A1 (en) 2002-01-16 2003-01-16 Method for enhancing electrode surface area in dram cell capacitors

Country Status (11)

Country Link
US (4) US6794704B2 (fr)
EP (2) EP1610379A3 (fr)
JP (2) JP4423541B2 (fr)
KR (1) KR100701543B1 (fr)
CN (1) CN1643678B (fr)
AT (1) ATE430986T1 (fr)
AU (1) AU2003205203A1 (fr)
DE (1) DE60327508D1 (fr)
SG (1) SG143987A1 (fr)
TW (1) TW591705B (fr)
WO (1) WO2003063172A2 (fr)

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WO2015038340A1 (fr) * 2013-09-10 2015-03-19 Bandgap Engineering, Inc. Gravure au métal combinée à une gravure de régularisation
KR102160791B1 (ko) 2014-02-03 2020-09-29 삼성디스플레이 주식회사 블록 공중합체 및 이를 사용한 패턴 형성 방법
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Also Published As

Publication number Publication date
US20060292875A1 (en) 2006-12-28
EP1466361B1 (fr) 2009-05-06
JP2009060121A (ja) 2009-03-19
US6794704B2 (en) 2004-09-21
US7573121B2 (en) 2009-08-11
JP2005527103A (ja) 2005-09-08
WO2003063172A3 (fr) 2004-03-25
CN1643678B (zh) 2010-04-28
AU2003205203A1 (en) 2003-09-02
CN1643678A (zh) 2005-07-20
DE60327508D1 (de) 2009-06-18
EP1466361A2 (fr) 2004-10-13
EP1610379A3 (fr) 2007-03-07
US20070048955A1 (en) 2007-03-01
US7148555B2 (en) 2006-12-12
TW200307317A (en) 2003-12-01
US7642157B2 (en) 2010-01-05
JP4423541B2 (ja) 2010-03-03
KR100701543B1 (ko) 2007-03-30
TW591705B (en) 2004-06-11
EP1610379A2 (fr) 2005-12-28
WO2003063172A2 (fr) 2003-07-31
US20030203508A1 (en) 2003-10-30
ATE430986T1 (de) 2009-05-15
KR20040077736A (ko) 2004-09-06
US20030134436A1 (en) 2003-07-17

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