WO2009133510A1 - Procédé de fabrication d'un condensateur sur un nanofil et circuit intégré incluant un tel condensateur - Google Patents

Procédé de fabrication d'un condensateur sur un nanofil et circuit intégré incluant un tel condensateur Download PDF

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Publication number
WO2009133510A1
WO2009133510A1 PCT/IB2009/051694 IB2009051694W WO2009133510A1 WO 2009133510 A1 WO2009133510 A1 WO 2009133510A1 IB 2009051694 W IB2009051694 W IB 2009051694W WO 2009133510 A1 WO2009133510 A1 WO 2009133510A1
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WO
WIPO (PCT)
Prior art keywords
metal
layer
capacitor
insulator
stack
Prior art date
Application number
PCT/IB2009/051694
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English (en)
Inventor
Jozef T M. Van Beek
Erik P. A. M. Bakkers
Freddy Roozeboom
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO2009133510A1 publication Critical patent/WO2009133510A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure

Definitions

  • the present invention relates to a method of manufacturing a capacitor on a wafer, the method comprising forming a plurality of vertical structures each having a sub-micron thickness on the wafer.
  • the present invention further relates to an integrated circuit (IC) comprising a capacitor.
  • IC integrated circuit
  • nanostructures In order to increase the capacitance of the capacitive element of a semiconductor device, nanostructures have been used to form capacitive elements that are grown vertically on a horizontal substrate, i.e. perpendicularly to the substrate surface to increase the surface area of the electrode plates.
  • US2007/0082495 A1 discloses a method of forming a capacitor having vertical pillars of a conductive material by depositing nanocrystals over the conductive material and using the nanocrystals as a hard mask to form the pillars.
  • the pillars are subsequently covered by a dielectric layer and a further conductive layer to form the capacitor.
  • a drawback of this method is its complexity, which significantly increases the manufacturing cost of such a device.
  • US2006/0279905 A1 discloses a method of forming a capacitor wherein a first electrode is formed by vertically growing a plurality of nanofibers on a substrate, subsequently coating the nanofibers with a dielectric layer and subsequently coating the dielectric layer with a conductive material to form the opposite electrode of the capacitor.
  • US2006/0186451 A1 discloses a method of fabricating a memory element comprising a capacitor in which a first electrode of the capacitor is formed by growing a plurality of multi-walled carbon nanotubes in a vertical direction on a catalyst layer deposited over a silicon (Si) substrate.
  • the nanotubes are covered by a dielectric layer deposited by means of chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form thin dielectric layers, thereby increasing the capacitance of the capacitor.
  • the dielectric layer is subsequently covered by a second electrode layer to complete the capacitor.
  • nanofibers or multi-walled nanocrystals as a capacitor electrode can have a detrimental effect on the conductive properties of such an electrode.
  • the semiconductor properties of such nanostructures can lead to a substantial series resistance across the capacitor plates.
  • the nanostructures when such nanostructures are used as electrodes, the nanostructures must be formed on a conductive layer that is externally contactable in order to make the nanostructure electrode externally accessible. This limits the applicability of such capacitors.
  • the present invention seeks to provide an improved method of forming a capacitor on a wafer.
  • the present invention further seeks to provide an integrated circuit having at least one of such a capacitor on its substrate.
  • a method of manufacturing a capacitor on a wafer comprising forming a plurality of vertical structures each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal stack over the plurality of vertical structures.
  • Such a method provides a capacitor with a much higher capacitance than a planar, e.g. horizontal capacitor, due to the increased surface area provided by the vertical structures of a sub-micron thickness, i.e. vertical nanostructures, in which the electrodes are formed on the vertical nanostructures without requiring the nanostructures to act as the bottom electrode.
  • the inner metal layer of the MIM stack i.e. the metal layer covering the nanostructures lowers the series resistance of the capacitor plates compared to a capacitor plate formed by the nanostructure itself. This is particularly valid when the nanostructure dimension, e.g.
  • the diameter of a nanowire is of the same magnitude as the thickness of the first metal layer in order to get a high packing density of the wires and hence a high capacitance density.
  • the series resistance of a semi-conductor nanostructure will be much higher than the metal layer of the present invention.
  • the nanostructures may be formed by patterning a deposited layer such as a dielectric layer, for instance as disclosed in US2007/0082495 A1.
  • the vertical nanostructures are formed by depositing a catalyst layer over the wafer, patterning the catalyst layer, and growing a plurality of nanowires on the patterned catalyst layer. This is a more cost-effective way of forming such a capacitor.
  • a further advantage of using nanowires in the method of the present invention is that the steps are suitable for integration in a back-end integrated circuit (IC) manufacturing process, where temperatures in excess of 500 C are typically undesirable because such high temperatures can deteriorate deposited materials and dopant regions.
  • the nanowires, such as GaP, InAs, InP, GaAs, Si, or Ge nanowires can be grown at temperatures well below 500 C, in contrast to the deposition of nanotubes, which deposition step typically has to be performed at temperatures in excess of 500 C.
  • the step of growing the plurality of nanowires is executed at a temperature in a temperature range of 300-500 C. - A -
  • the step of growing the metal-insulator-metal stack is executed at a temperature not exceeding 400 C.
  • the various layers of the metal-insulator-metal stack are grown by means of ALD.
  • ALD has the advantage that very thin layers with very high step coverage can be deposited over non-planar surfaces, which makes this technique suitable for depositing the various layers over nanostructures such as nanowires.
  • the method of the present invention typically forms part of an IC manufacturing process.
  • the manufacturing of such an IC may be completed using any suitable process.
  • the method further comprises patterning the metal-insulator-metal stack, covering the patterned metal-insulator- metal stack covered vertical structures with an insulating layer; patterning the insulating layer to expose the respective metal layers of the metal-insulator-metal stack; depositing a conductive material over the patterned insulating layer; and patterning the conductive material to form individual connections with the respective metal layers of the patterned metal-insulator-metal stack to make the capacitor electrodes accessible.
  • the conductive material may be any suitable conductive metal.
  • the conductive material is a metal chosen from the group consisting of copper and aluminum because these metals are particularly suitable for integration in a CMOS process.
  • the wafer comprises a passivation layer covering a buried interconnect layer
  • the step of patterning the insulating layer further comprises patterning the insulating layer and the substrate to expose the buried layer
  • the step of patterning the conductive material to form individual connections comprises patterning the conductive material to form individual connections between the respective metal layers of the metal-insulator- metal stacks and the buried interconnect layer.
  • the buried interconnect layer may form a part of an IC formed in the wafer.
  • the capacitor is formed on top of the IC, which means that the whole area of the IC, excluding the area needed for the IC interconnects such as bond pads, can be utilized for the formation of one or more capacitors.
  • the capacitor By connecting the capacitor to the buried interconnect layer, the capacitor may for instance be used in an electrostatic discharge protection circuit of the IC, for instance by connecting it to a diode structure in the IC in the wafer.
  • IC comprising at least one capacitor formed on a layer of the IC, wherein the at least one capacitor comprises a stack of a first metal, an insulator and a second metal, said stack covering a plurality of vertical structures each having a sub- micron thickness.
  • the integrated circuit comprises a plurality of capacitors, each capacitor being arranged to act as a memory element. This provides a memory device having memory elements that can retain large amounts of charge, thus improving the charge retention time of the elements.
  • the IC layer carries at least one catalyst layer portion, and wherein each vertical structure comprises a nanowire formed on a respective catalyst layer portion, because such an IC can be manufactured relatively cheaply since the nanostructures do not have to be formed by patterning.
  • the IC of the present invention may be integrated in any suitable electronic device.
  • FIGs.1a-i schematically depict the steps of an embodiment of the method of the present invention
  • FIG. 2 shows a scanning electron microscope (SEM) image of nanowires grown on a SiO 2 layer
  • FIG. 3 shows another scanning electron microscope (SEM) image of nanowires grown on a SiO 2 layer
  • FIG. 4 shows a scanning electron microscope (SEM) image of nanowires grown on a patterned catalyst layer
  • FIG. 5 depicts the impact of the length of the nanowire on the capacitance of the formed capacitor.
  • a wafer comprising a device layer 100, an interconnect layer 110 and a passivation layer 120 is provided.
  • the device layer 100 may include a plurality of transistors formed on the wafer substrate and the interconnect layer
  • the 110 may comprise one or more metal layers for interconnecting the devices in the device layer 110.
  • the layers 100 and 110 may comprise an integrated circuit formed in the wafer.
  • the wafer may be a silicon wafer or another suitable material for forming an IC.
  • the passivation layer 120 typically comprises a dielectric material such as SO 2 or Si 3 N 4 , or any other suitable dielectric material such as a high-k dielectric.
  • the passivation layer 120 has the function of electrically insulating the interconnect layer 110.
  • a catalyst layer 130 is deposited over the passivation layer.
  • This catalyst layer 130 is intended to facilitate the growth of a nanostructure such as a nanowire or a nanotube thereon.
  • Any suitable catalyst material may be used for the catalyst layer 130.
  • the catalyst material is chosen from the group of noble metals, because such metals have excellent catalytic properties, and in particular gold (Au).
  • the catalyst layer 130 may be grown using any suitable deposition, e.g. by evaporation or sputtering, and can be kept relatively thin, e.g. less than 10 nm.
  • the catalyst layer 130 is patterned into catalyst regions 135.
  • the patterning may be done using any suitable patterning techniques including wet etching and dry etching.
  • the catalyst regions 135 may have any suitable shape, e.g. circular shapes, square shapes, rectangular shapes and so on.
  • the spacing between the catalyst regions is chosen such that the nanostructures grown thereon are sufficiently far apart to allow the nanostructures to be covered by a metal-insulator-metal stack. In an embodiment, the distance between the catalyst regions 135 is chosen from a range of 50-500 nm.
  • nanostructures 140 e.g. nanowires or nanotubes
  • FIG. 2-4 demonstrate that such nanostructures 140 can be effectively grown on such a passivation layer 120.
  • the SEM image of FIG. 2 shows nanowires 220 that are directly grown on a Si ⁇ 2 layer with a random orientation and position.
  • FIG. 3 shows a SEM image of nanowires 320 that are epitaxially grown on a SiO 2 layer, thus giving a defined orientation but a random position.
  • the nanowires 320 have an increasing thickness going from panel (a) to panel (c).
  • the scale bars in FIG. 3 define 1 micron.
  • FIG. 4 shows a SEM image of nanowires 140 epitaxially grown on patterned catalyst regions 135. It can be seen that a well-controlled distribution and orientation of nanowires 140 is obtained.
  • the nanostructures 140 may be grown at temperatures that are compatible with the back-end processes for forming a CMOS IC in the wafer, thereby avoiding damage to the IC during the growth of the nanostructures 140.
  • the nanostructures 140 are grown at a temperature from the range of 300-500 C. Since the technique of growing such nanowires is well-known to the skilled person, this will not be explained in detail for reasons of brevity only.
  • the nanostructures 140 may be grown from any suitable material.
  • the nanostructures 140 are nanowires grown from a material selected from the group consisting of GaP, InAs, InP, GaAs, Si, Ge, because these materials allow formation of the nanowires at temperatures below 500 C, e.g. 420 C.
  • the nanostructures 140 typically have a sub-micron thickness in the nanometer domain, e.g. 10-50 nm.
  • the phrase 'thickness' is intended to describe the horizontal dimension of the nanostructures 140 such as the diameter of nanotubes or nanowires.
  • the nanostructures may be grown to any suitable height. In an embodiment, the nanostructures 140 are grown to a height in the range of 1 -10 micron.
  • a metal-insulator-metal (MIM) stack 150 is grown over the passivated layer 120, thereby covering the nanostructures 140.
  • the layers of the MIM stack 150 are grown by means of sequential ALD steps, because ALD grown layers have good uniformity in their thickness.
  • the first metal layer 152 may be a TiN layer grown to a thickness of 20 nm, after which the insulator layer 154, e.g. an AI 2 O 3 layer, is grown to a thickness of 10 nm.
  • the MIM stack 150 is completed by subsequently growing the second metal layer 156, which may be a TiN layer, to a thickness of 20 nm.
  • the capacitor having an overall thickness of 50 nm, with the first metal layer 152 being the first plate of the capacitor and the second metal layer 156 being the second plate of the capacitor.
  • the capacitor is wrapped around the nanostructures 140 rather than the nanostructures 140 forming a part of one of the capacitor plates.
  • the insulator layer 154 which acts as the dielectric layer between the plates of the capacitor, may be kept as thin as possible to maximize the capacitance of the capacitor. It should be appreciated that the above thicknesses of the respective layers of the MIM stack 150 are given by way of non-limiting example only and that other thicknesses are equally feasible.
  • the ALD process steps are performed at temperatures not exceeding 400 C. This also makes the ALD process steps compatible with the back-end process of the manufacturing of a CMOS IC. It will be appreciated that the MIM stack 150 may be grown using any suitable layer deposition technique such as chemical vapor deposition (CVD), plasma-enhanced CVD or physical vapor, or sputter, deposition (PVD).
  • CVD chemical vapor deposition
  • PVD sputter, deposition
  • the nanostructures 140 do not have to be grown in the aforementioned manner.
  • the approach described in US2007/0082495 A1 may also be used to form nanostructures 140 in the form of nanopillars by means of patterning, after which the MIM stack 150 may be deposited over such nanostructures.
  • the manufacturing process of an IC carrying the MIM capacitor 150 may be completed in any suitable manner.
  • the MIM stack 150 may be patterned such that the first metal layer 152 and the second metal layer 156 may be individually connected, as shown in regions 158.
  • the patterning of the MIM stack 150 may be performed using any suitable patterning process such as a wet etch or a dry etch.
  • a dielectric layer 160 is deposited over the patterned MIM stack 150.
  • This layer may be formed of any suitable dielectric material.
  • the dielectric material is polyimide.
  • the deposition may be achieved using any suitable technique.
  • the polyimide layer may be spin-coated over the patterned MIM stack 150.
  • the dielectric layer 160 is used to protect the MIM stack 150 from further processing, as well as to improve the structural integrity of the stack.
  • the dielectric layer 160 is subsequently patterned as shown in FIG. 1 h.
  • a trench 162 is formed to provide access to the first metal layer 152, and a trench 164 is formed to provide access to the second metal layer 156.
  • further trenches 166 and 168 may be formed to provide access to the appropriate sections of the buried interconnect layer 110.
  • the interconnect layer 110 is depicted as a continuous layer, the interconnect layer 110 typically comprises a plurality of patterned conductive structures, with the trenches 166 and 168 providing access to respective conductive structures in the buried interconnect layer 120.
  • a conductive material is subsequently deposited over the patterned dielectric layer 160 and subsequently patterned into conductive structures 170 such that the respective electrodes of the MIM capacitor 150 can be controlled through the conductive structures 170.
  • the material used for forming the conductive structures is Cu or Al, because these metals are compatible with a conventional CMOS process. Consequently, a MIM capacitor 150 is obtained that is formed on top of an
  • left panel which depicts the surface area of such a capacitor compared to a planar capacitor covering the same area of the passivation layer 120 as a function of wire diameter (shown in units of 10 nm) and length (three wire lengths of 1 micron, 5 micron and 9 micron respectively are shown), an increase in effective surface area in excess of a factor 50 can be achieved.
  • the predicted capacitance density per square millimeter of these MIM capacitors 150 is depicted in the right panel of FIG. 5. It can be seen that densities in well in excess of 0.5 * 10 "6 Farad/mm 2 can be achieved by the MIM capacitor 150.
  • an aggregate capacitance in the microfarad range can be obtained.
  • This for instance allows for the integration of on-chip high-value capacitors that can be used as decoupling capacitors, or that can be used in power management applications such as DC-DC conversion stages when combined with e.g. planar inductors and field-effect-transistor based switches.
  • the ability to utilize substantially the whole top surface area of the IC, except area regions required for forming interconnects such as bond pads makes it possible to integrate capacitors that previously had to be provided off- chip.
  • the present invention is not limited to growing a MIM capacitor 150 on top of an IC.
  • the MIM capacitor 150 may for instance also be formed in the transistor layer 100 without departing from the teachings of the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un procédé de fabrication d'un condensateur sur une tranche, et sur un circuit intégré (CI) incluant un tel condensateur. Le procédé comprend la formation d'une pluralité de structures verticales (140) présentant chacune une épaisseur inférieure au micron sur la tranche ; et le développement d'un empilement métal-isolant-métal (MIM) (150) sur la pluralité de structures verticales (140). Dans un mode de réalisation préféré, le procédé comprend en outre le dépôt d'une couche de catalyseur (130) sur la tranche ; et la formation des motifs de la couche de catalyseur, et l'étape de formation de la pluralité de structures verticales (140) comprend le développement d'une pluralité de nanofils sur la couche de catalyseur à motifs. En conséquence, on obtient un condensateur formé par l'empilement MIM (150), qui possède une densité de capacité très élevée et peut être formé sur le dessus d'un CI dans le processus final d'un processus de fabrication de CI.
PCT/IB2009/051694 2008-04-29 2009-04-24 Procédé de fabrication d'un condensateur sur un nanofil et circuit intégré incluant un tel condensateur WO2009133510A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08103766 2008-04-29
EP08103766.5 2008-04-29

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104981894A (zh) * 2012-12-13 2015-10-14 加州理工学院 制造三维高表面积电极
CN112018096A (zh) * 2020-07-31 2020-12-01 复旦大学 一种用于能量缓冲的纳米电容三维集成系统及其制备方法
CN112151538A (zh) * 2020-09-10 2020-12-29 复旦大学 一种纳米电容三维集成结构及其制造方法
CN112151537A (zh) * 2020-09-10 2020-12-29 复旦大学 一种高能量密度纳米电容三维集成结构及其制备方法

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US20030100189A1 (en) * 2001-11-28 2003-05-29 Chun-Tao Lee Method for increasing the capacity of an integrated circuit device
US20060292875A1 (en) * 2002-01-16 2006-12-28 Micron Technology, Inc. Method for enhancing electrode surface area in DRAM cell capacitors
DE102006009721A1 (de) * 2006-03-02 2007-09-06 Infineon Technologies Ag Nanowire-Speicherzelle
US20080003768A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Capacitor of a memory device and method for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030100189A1 (en) * 2001-11-28 2003-05-29 Chun-Tao Lee Method for increasing the capacity of an integrated circuit device
US20060292875A1 (en) * 2002-01-16 2006-12-28 Micron Technology, Inc. Method for enhancing electrode surface area in DRAM cell capacitors
DE102006009721A1 (de) * 2006-03-02 2007-09-06 Infineon Technologies Ag Nanowire-Speicherzelle
US20080003768A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Capacitor of a memory device and method for forming the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104981894A (zh) * 2012-12-13 2015-10-14 加州理工学院 制造三维高表面积电极
CN112018096A (zh) * 2020-07-31 2020-12-01 复旦大学 一种用于能量缓冲的纳米电容三维集成系统及其制备方法
CN112018096B (zh) * 2020-07-31 2022-05-24 复旦大学 一种用于能量缓冲的纳米电容三维集成系统及其制备方法
CN112151538A (zh) * 2020-09-10 2020-12-29 复旦大学 一种纳米电容三维集成结构及其制造方法
CN112151537A (zh) * 2020-09-10 2020-12-29 复旦大学 一种高能量密度纳米电容三维集成结构及其制备方法
CN112151538B (zh) * 2020-09-10 2022-04-29 复旦大学 一种纳米电容三维集成结构及其制造方法

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