-"部屮--',-'".''札，-'"〈1-;/1於合：^^卬,'',?': A7 B7 五、發明説明（I ) 發明背景 本發明像廣泛地有關於積體電路，並且更持別地是有 關於使用於形成積體電路用電容器的方法。 如所熟知之技藝，使用電容器之一種形式的積體電路 為動態隨機存取記億體（DRAM)胞元。該胞元包括有一用 以儲存電Μ或不儲存電Μ以代表邏輯1或邏輯0的電容 器，以及用電晶體以定址電容器。亦為所熟知之技藝是 ，隨著整合密度的增加，胞元中所使用的電晶體及電容 器二者所能使用的空間係不斷地被減少。然而，儲存在 電容器中的電荷量應儘可能地大，以確保優質的資料保 留時間。電容器可藉由減少二導電電極（亦即導電板）之 間的介質厚度、增加介質之介電常數及/或增加電極表 面積而增加。介質厚度減少量偽為相對應之漏電流增加 所限制，亦邸，將電子直接穿過介質降低保留時間。増 加介電常數則需要改變介電材料，而該方法卻不易與其 flfeDRAM製程中所需的製程相容。 有關增加電容器電極表面積方面，已有若干値技術被 提出；然而其卻需要眾多的額外製程步驟，其中部份製 程係不與其他所需的加工步驟相容。一個已被提出的技 術像於1 9 9 5年2月所發行的π I E E E T r a n s a c t i ο n s ο η Electron Devices" , v o1 . 42, No· 2第 295-300頁中-" 部 屮-',-' ". '' Zha,-'"<1-; / 1Yuhe: ^^ 卬,' ',?': A7 B7 V. Description of the Invention (I) BACKGROUND OF THE INVENTION The present invention relates generally to integrated circuits, and more particularly to a method for forming a capacitor for integrated circuits. As is well known in the art, a form of integrated circuit using a capacitor is a dynamic random access memory (DRAM) cell. The cell includes a capacitor used to store or not to represent a logic one or a logic zero, and a transistor to address the capacitor. It is also a well-known technique that, as the integration density increases, the space available for both the transistors and capacitors used in the cell is continuously reduced. However, the amount of charge stored in the capacitor should be as large as possible to ensure good data retention time. Capacitors can be increased by reducing the thickness of the dielectric between two conductive electrodes (ie, conductive plates), increasing the dielectric constant of the dielectric, and / or increasing the electrode surface area. The decrease in the thickness of the medium is pseudo-limited by the corresponding increase in leakage current. Therefore, passing electrons directly through the medium reduces the retention time.増 Adding a dielectric constant requires changing the dielectric material, but this method is not easily compatible with the process required in its flfeDRAM process. With regard to increasing the surface area of the capacitor electrode, several rhenium technologies have been proposed; however, they require numerous additional process steps, some of which are not compatible with other required process steps. A proposed technology image, π I E E E T r a n s a c t i ο n s ο η Electron Devices ", v o1. 42, No. 2 issued in February 1995, pp. 295-300
Watanabe等人所撰之標題為"An Advanced Technique for Fabricating Henispherical-Grained (HSG)Silicon Storage Electrodes"的文章内做説明。該篇論文說明 本紙张尺度述;家標牟（CNS ) Λ4规格（210X 297公# ) n I— i In - - - 1 - - 1 - n -I 士^_ I 1 -I -- —»- I ^lv I - I - -I- tt^i —II -^n (誚先閱讀背面之注意事項再楨艿本頁) A7 B7 五、發明説明（> ) 以一平坦表面非晶質矽形成DRAM電容器板並隨後將其改 變為具有不平坦表面半圓形晶粒矽（Si)的電容器板。該 方法包括有藉由低壓化學氣相沈積並接著以原始氣化物 移除極髙真空退火以形成平坦非晶質矽板（亦即電極）。 該退火製程將形成覆蓋於所有形式之儲存電極之整値表 面的HSG-Si,其覆蓋範圍亦包括有先前已被乾式蝕刻的 側壁表面。另一技術俗於U.S. Patent. No. 5324769中 說明。該專利俗説明藉由形成多晶矽圖案於半導體基板 上的方式以形成不平坦結構導體。具有針孔的絶線膜係 被形成於多晶圖案的表面。該多晶矽圖案隨後被以蝕刻 穿過針孔。接下來，該絶緣膜被移除。又另一技術係於 1996年 9 月所發行的”Japanese Journal of Applied Physics", vol. 35(1996)Part2， No. 9B第 L-1215-1218 頁中Matsuo等人所撰之標題為”Growth of Polycrystalline Silicon Grain"的文章内做説明。該篇文章說明圓頂形 晶粒的形成。一非晶質矽膜（a-Si)係以垂直式LPCVD沈積 於被形成於矽基板上之氣化層之上。a-Si膜的沈積後，接 著在原位置做以與沈積相同溫度執行的退火。 發明概要 根據本發明，提供一種方法以形成電容器用介質。該 方法包括有提供一半導體；形成一不均勻層於半導體表 面；將熱及壓力施加於半導體與不均勻層上以於半導體 表面産生坑洞；形成一層第二介電層於具有坑洞之半導 體表面以提供電容器用介質。 本紙张尺度述州十闺國家標率（CNS ) Λ4规格（210X297公釐） --------------1T-----^ (誚先閱讀背面之注意事項再填寫本頁) 五、發明説明（4 A7 B7 體 與 極積應 之。 晶電導一面連 法及表 生變 熱。 電面效 洞用方 單的半供表氣 方熱體 産-洞 加面 器表害 坑器上 有體晶提洞電 之加導 以坑 體表 容的有 有容面 具晶單份坑並 工體半 壓之 導體 電多之 具電表。供電雜部之方 加導在 加中 半導 成更成 其供洞方提至摻體體上 體半生 與面 將半 形之形 器提坑上被合一導導質 導將産 熱表 在於 於應洞 容儂之質元耦之半半介 半、將 加體 傜積 用對坑。電導體介胞一中雜於於 種體及 體導 層沈 可相常積一半導該AM及體摻置置 一導以 導半。質前 多有通面供雜半於DR以主該設設 供半， 半在行介之 更具，表提摻於置一體於。質極 提供洞 將生執一洞 有搔此之，該置設，晶成面介電 ，提坑 ，産中，'坑 具電因極性。設傜性電形表一二 性：生 性將備性之 將器。電特體俗極特一有洞。第 特有産 待及設持面 質容容器一導質電一成括坑極之 一驟面 一以的一表 介電電容另半介二另形包有電用 另步表 另洞般另體 ,得之電之晶一第之中器具一器 之的體。之坑一之導 法使器加明單。之明體容份第容。明括導圓明之於明半 方，容增發雜極用發主電部之電體發包半變發面傺發生 該積電以本摻電器本該該該用一晶本法在洞本表驟本産 由面加用據之一容據。。，器。電據方以坑據體步據以 藉表增被根面第電根體器份容方至根該壓之根導的根壓 的以偽 表一一 主容部電上接 。加面 半圓 加 ------------I裳------訂------線 (誚先閱讀背面之注意事項再頊寫本頁) 本紙張尺度適川十囚國家標率（CNS ) Λ4規格（210X 297公釐） A7 B7 溫度傜高 五、發明説明（4 根據本發明之另一待性，將半導體加熱與加壓以産生 半導體表面之坑洞的步驟包括有將具有介質層於其上的 半導體施加第一道退火的步驟，而其中將産生在半導體 表面中之坑洞變圓的步驟包括有將半導體施加第二道退 火的步驟。 根據本發明之另一特性，第一道退火的步驟包括有將 半導體施加第一溫度及第一壓力的步驟，而第二道退火 包括有將半導體施加第二溫度的步驟， 於第一溫度。 根據本發明之另一特性俗為：（A)第一壓力係高於第 二壓力；或（B)第二溫度傺高於第一溫度以及第一壓力 偽高於第二S力；或第二溫度傺高於第一溫度以及第二 壓力俗等於第一壓力。 圖式簡單說明 本發明之其他特性以及本發明本身將由下列詳細説明 並配合附画而變得更清楚，其中： 第1Α-1Ε圖偽圖示有關根據本發明之溝渠-電容DRAM胞 元在製造中之各階段的横截面圖示； 第2 _偽圖示習知技術中所發表之蝕刻速率與溫度間 相互關偽的曲線； 第3圖偽圖示習知技術中所發表之在二種不同溫度下 蝕刻在矽上之二氣化矽的效應之一糸列的圖示； 第4A及4B圆僳圖示製造根據本發明之第1A-1E圖的 DRAM用之一對順序退火步驟中所使用的溫度及壓力剖面 本紙张尺度4州屮1¾¾家標率（CNS ) Λ4規格（210X 297公釐） --------1^------、1T-----線 (誚先閱讀背面之注意事項再填ftT本頁) 部 中 ά il 卑 义;J )ί 消 t: η 卬 1? A7 B7 五、發明説明（ ) 1 I 圖； 1 1 第5A至 5D圖俗 圖 示 有 關 根 據 本 發 明 之 第 1 A至 1 E圖之 1 I DRAM胞元用 .電 容 器 在 製 造 中 之 各 階 段 的 横 截 面 圖 示 ； 1 | 第6A及 6B_偽 圖 示 製 造 根 據 本 發 明 之 第 1 A至 1 E圖 的 先 閱 1 I 讀 1 | DRAM用之 一 對 順 序 退 火 步 驟 中 所 使 用 的 溫 度 及 壓 力 横截 背 δ 1 I 之 1 面園。以 及 注 I 意 1 第7A至 7D圖偽 圖 示 有 關 根 據 本 發 明 之 叠 積 - 電 容 器 事 項 1 再 DRAM胞元在製造 中 之 各 階 段 的 横 截 面 圖 示 第 7 B圖傜為 % 1 本 裝 第7 A圖之放 大 部 份 9 該 放 大 部 份 俗 於 第 7 AB 中 所 圈 起並 頁 1 標記為7 B至 7 B 〇 1 1 細節說明 1 1 本發明 像 有 關 於 積 體 電 路 (1C)用 電 容 器 之 形 成 〇 該1C 1 1 為包括例 如 動 態 隨 機 存 取 記 憶 SUtt 體 (DRAM)或同步 DRAM (SDRAM) 1 丁 1 之隨機存 取 記 憶 體 (RAM ) 〇 其他之諸如特殊應用IC(ASIC) 1 | 或合併式DRAM -邏輯電路（嵌埋式DRAM)等1C亦為可使用。 1 1 典型地 是 > 若 干 個 I C平 行 形 成 於 晶 圓 上 〇 加 工 eis» 兀 成後 1 ,晶圓被 切 割 以 將 I c分成艟别晶Η 〇 該 晶 片 隨 後 被 包裝 線 I 為使用於 諸 如 電 m 糸 統 、 蜂 式 電 話 \ 値 人 數 位 肋 理 1 1 (PDAs)及 其 他 電 子 産 品 等 消 費 者 産 品 之 最 終 産 品 0 1 | 參考第 1 圖 > 提 供 一 諸 如 矽 晶 圓 之 基 板 的 一 部 份 之横 1 | 截面圖。 其 他 諸 如 砷 化 鎵 - 鍺 或 其 他 半 導 體 材 料 之 基板 1 1 傺為可用 〇 例 如 j 該 基 板 可 用 具 有 預 定 導 電 度 的 摻 植雜 1 I 質來做微 量 或 大 量 摻 雜 以 得 到 所 欲 之 電 性 〇 如 所 示 9 * 1 1 嵌埋之離 子 植 入 層 1 2而在 位 7 於 與 矽 基 板 1 〇上表面 14距離 1 1 1 1 1 1 本紙張尺度通州t囤國家標芈（CNS ) Λ4規格（210X 297公釐） A7 B7 經濟部中央標準局負工消費合作社印¾ 五、發明説明（ b ) 1 1 1 . 5微米深度處， 在此磷係被形成於其中C 在此之嵌埋摻 1 1 雜 層 1 2 之 摻 雜 濃 度具 有 大 約1〇12至1〇14每 平方公分的劑 1 1 量 〇 一 層 約 為 1 0 0埃厚的二氣妙襯墊_層1 3'倭妓I成1„趁 請 1 先 1 矽 基 板 u之 上 表 面1 4上 方 β如所示，一層 1000-5000埃 閱 讀 1 I 厚 的 氛 化 矽 及 / 或二 氧 化 矽層之介質層16設置於二氣化 η 面 1 I 之 1 矽 襯 墊 層 1 3之 ± .表..面 上 方 〇 ‘兔 1 事 1 接 著 9 如 第 1 A _所 示 9 一所形成之窗口 18傜使用傳統 項 1 式 光 石 板 印 刷 術 (亦即， -硬式」r ios或B S G 蔓3，未_示） 填 寫 本 i 及 化 學 蝕 刻 (亦卽，反應離子蝕刻RIE)技術而形成於氮 頁 1 I 化 矽 層 1 6 中 〇 被 開窗 口 之 氪化矽層16及硬 式罩幕用作使.. 1 1 用Λ 統 式 蝕 刻 技 術將 溝 渠 2 0蝕刻於矽基板 10之上表面14 1 1 的 下 面 部 份 的 罩 幕。 在 此 ，溝渠2 G之深度 係為從矽基板 1 訂 10 上 表 面 14 算 起 8徹 米 的 層级，而^溝渠2 0 之寬度股§ 1 0 _ 1 0 -0 .2 5撤米的層级。 …......—— ...W. 具有100-1000埃厚度之被沈積 1 I 二 氧 化 矽 的 一 介 質環 2 1 (第1B圖）傺使用任 何二步驟溝渠 1 | 蝕 刻 製 程 形 成 於 溝渠 2 0 之 上面部份周圍。 1 1 其 次 > 一 不 平 坦介 質 層 22形成於溝渠20 .............. 的表面上，如 ，咏 | 第 1C 圖 所 示 〇 此 亭之 介 質 層2 2僳為熱成長 至大約10-30 1 1 埃 厚 度 的 二 氣 化 矽。 該 m 二氣化矽層2 2將 可為成長於潔 1 1 大 氣 中 的 原 始氧彳b矽 、例如熱二氣化 矽、TE0S或氮 1 I 化 物 〇 應 注 意 的 是介 質 層 2 2在厚度及/或 組成以及局部 1 1 缺 陷 方 面 具 有 各 種變 化 (亦即不均勻度）。 因此，如第1C 1 1 圖 所 示 介 質 層 22係為 不 平 坦，亦即具有山 峰及山谷。應 1 I 注 /S·· 的 是 層 2 2 中 的不 均 勻 度可為其他諸如 低能摻雜等缺 1 1 8 _ 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4«L格（210X 297公犮） A7 B7 五、發明説明（7 ) 陷所提供造成。 簡短地參考第2圖，曲線30， 30a及30b傜將砂及二氣 化矽的蝕刻速率的圖視為溫度的函數；曲線30偽圖示在 大約7 (5 0拖耳的壓力下矽的蝕刻速率，曲線3 0 a傜圖示在 大約100拖耳的壓力下二氧化矽的蝕刻速率，而曲線30b 傜圖示在大約760拖耳的壓力下二氣化矽的蝕刻速率。 曲線30、30a及3Qb俗為氫所包阐之典型。應注意的是在 為壓力P之函數的臨界溫度T c ( P )以上時，為氫所包圍 之二氧化矽（亦卽曲線3 Q a，3 0 b )的蝕刻速率傜低於矽的 蝕刻速率；不論是單晶矽，多晶矽或非晶質矽皆然。在 7G0拖耳下之蝕刻速率及溫度間的關偽係發表於1995年 9 月所發行的"Journal of the Electrochemical Society", vol. 142，No. 9 中 Habuka 等人所撰之標題 為"Roughness of Silicon Surface Heated in Hydrogen Ambient” Electrodes"的文章内。 在二氣化矽層22(第1C圖）中之不均勻度（亦即，厚度 ,低能摻雜或其他缺陷）將導致二氣化矽穿孔點的發生 ，而其他部位卻仍為二氣化矽所覆蓋。因此參考發表於 Habuka等人所撰之標題為"Roughness of Silicon Surface Heated in Hydrogen Ambient"Electrodes"的文章之第 3圖，二氣化矽層22傜_示置於矽層10的上方。第3圖 的左邊圖示在高於臨界溫度T c ( P )之溫度的蝕刻，而第 3圖的右邊則圖示在低於臨界溫度Tc(P)之溫度的蝕刻 。應注意的是在高於臨界溫度T c ( P )之溫度時，二氣化 本紙張尺度讳州'丨’囤國家標率（CNS ) Λ4規格（210 X297公釐） --------'—装------17-----:-線 (誚先閱讀背面之注意事項再功巧本頁) ΑΊ Β7 經漓部中央標準局員工消費合作社印製 五、發明説明（ ) 1 I 矽 層 2 2將 被 快 速 移 除 9 而 於 薄 層 22被 移 除 後 産 生 相 當 平 1 1 坦 的 矽 1 0 表 面 〇 然 而 當 蝕 刻 在 低 於 臨 界 溫 度 Tc (F )之溫 1 1 度 時 i 坑 洞 2 5將 被 形 成 於 矽 層 1 C 中 〇 因 此 i 在 低 於 矽 之 請 1 先 1 蝕 刻 速 率 遠 大 於 二 氣 化 矽 之 蝕 刻 速 率 的 某 臨 界 溫 度 T c (P) 閱 讀 1 之 溫 度 時 矽 較 二 氧 化 矽 高 的 蝕 刻 速 率 將 導 致 坑 洞 25形 背 1 I 之 1 成 於 矽 1 0 中 〇 由 第 2 圖 之 曲 線 i 應 注 意 的 是 在 大 氣 壓 f专' 1 事 1 力 下 之 臨 界 溫 度 大 約 為 1 0 0 o°c 0 於 大 氣 壓 下 * 在 大 於 臨 項 再 1 界 溫 度 T c ( P )之溫度時， 蝕刻速率的差異為微小的且二 填 寫 本 \ 裝 氧 化 矽 膜 將 被 快 速 移 除 〇 第 2 圖 係 圖 示 在 例 如 大 約 1 0 0 頁 '—. 1 I 拖 耳 下 » 二 氣 化 矽 在 氫 中 的 蝕 刻 速 率 對 溫 度 的 依 存 度 較 1 1 不 明 顯 9 而 在 較 低 溫 的 蝕 刻 速 率 則 與 具 徹 小 溫 度 依 存 度 1 1 之 矽 在 氫 中 的 蝕 刻 速 率 較 為 接 近 〇 因 此 J 在 較 低 壓 時 i 1 訂 臨 界 溫 度 T c ( P )將較高壓時為低。 1 因 此 9 參 考 第 1C 圖 » 在 二 氧 化 矽 之 介 質 層 22成 長 於 矽 1 I 1 0上 方 後 9 該 結 構 將 被 置 入 未 圖 示 之 腔 室 或 爐 管 中 〇 一 1 I 値 二 階 段 退 火 步 驟 於 隨 後 被 執 行 〇 在 第 一 m 階 段 中 9 二 1 1 氧 化 矽 層 2 2 之 不 均 勻 度 (亦即， 例如 山 峰 及 山 谷 低 能 踩 I 摻 雜 或 缺 陷 )將變為形成於溝渠2 0側壁及底部的坑洞2 5 1 (第3 圖） 而 在 第 二 道 退 火 中 i 該 坑 洞 2 5之 尖 銳 的 邊 緣 1 1 將 被 變 圓 為 坑 洞 2 5 1 〇 首先應注意地是， 坑洞2 5之形成 1 1 及 變 圓 將 可 於 上 逑 之 氫 氣 包 圍 中 > 或 在 例 如 其 他 諸 如 氬 1 1 氣 N 氣 氣 及 氮 氣 等 鈍 氣 之 無 氧 周 圍 環 境 9 或 超 高 真 空 退 1 1 火 中 産 生 〇 亦 應 注 地 是 ) 二 道 退 火 在 同 一 腔 室 中 執 行 1 I 9 亦 即 同 一 位 置 的 狀 態 下 f 而 所 産 生 的 結 構 則 圖 示 於 第 1 1 -1 0- 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) Λ4%格（210X2W公兑） A7 B7 經濟部中央標準局負工消f合作社印製 五、發明説明（ 9 ) 1 I 1 D 圖 中 〇 1 1 因 此 > 也 參 考 第 5 A -5 D圖， 在不平坦的二氣化矽層2 2 1 1 形 成 後 > 該 結 構 將 被 置 入 腔 室 做 退 火處 理 〇 在 第 一 道 退 請 1 先 1 火 步 驟 中 (第5 B圖）， 該 腔 室 俗 處 於 如第 4 A 圖 之 左 邊 所 示 閱 讀 1 之 相 當 低 的 第 一 溫 度 T1 (亦即較臨界溫度T C ( P)為 低 )， 以 η 1 I 之 1 形 成 第 3 画 中 所 説 明 以 及 再 次 於 第 5Β僵 中 所 示 之 坑 涧 2 5 事 1 0 在 下 —* 道 退 火 的 過 程 中 該 溫 度 在原 位 置 被 升 至 如 第 項 再 4 A _ 右 邊 所 示 之 溫 度 T 2 ， 以 將 坑 洞 2 5之 尖 銳 邊 緣 變 圓 而 填 寫 本 裝 形 成 如 第 5C 圖 所 示 之 變 圓 的 坑 洞 2 5 '，並且亦將移除任何 頁 1 I 殘 留 的 二 氧 化 矽 層 2 2 〇 若 僅 能 完 成 殘留 二 氧 化 矽 之 部 分 1 1 移 除 則 諸 如 稀 釋 或 緩 衝 的 氫 氟 酸 之濕 式 蝕 刻 步 驟 將 可 1 1 被 使 用 〇 第 4 B 圖 偽 圖 示 二 道 序 列 退 火步 驟 〇 坑 洞 2 5將 藉 1 -ί — 由 第 二 道 退 火 步 驟 中 之 砂 原 子 表 面 遷移 變 圓 為 坑 洞 2 5 1 〇 1 m 注 意 的 是 ί 二 步 驟 退 火 可 於 二 退火 步 驟 溫 度 維 持 固 1 I 定 而 在 第 二 道 退 火 步 驟 中 之 腔 室 壓 力減 少 的 情 形 下 執 行 1 I 9 如 第 6 A及 6B 圖 所 示 〇 應 注 τήΰ. 的 是 ，在 第 一 道 退 火 步 驟 1 t 中 9 於 第 一 個 壓 力 P 1 時 9 該 溫 度 Τ 1僳低 於 在 第 一 痼 壓 力 線 P 1 時 之 臨 界 溫 度 T c (P )， 而ί- Ε第二 二道退火步驟中， 其中 1 t 壓 力 為 P 2 9 該 溫 度 T2偽 高 於 在 壓 力 Ρ 2時 之 臨 界 溫 度 1 1 T c (P )〇 而如第6 Β圖所示， 溫度在二個退步驟皆- -定； 1 I 在 第 一 道 退 火 步 驟 中 該 結 構 係 位 於 臨界 壓 力 之 上 9 而 在 1 1 第 二 道 退 火 步 驟 中 該 結 構 傷 位 於 臨 界壓 力 之 下 〇 1 1 在 一 實 施 例 中 9 第 一 道 退 火 (亦即坑洞2 5之形成（第 5B 1 1 -1 1 - 1 1 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4ML梠（210X 297公筇） 經滴部中央標準局員工消費合作社印製 A7 B7 五、發明説明（一） 圖））偽在大約850 °C的溫度T1、大約20拖耳的壓力P1以 及氫氣流量為2標準升/分鐘的速率下執行約1Q-6Q分鐘 。該第二道退火傜在原位置以下列加工執行（亦即，坑 洞25變圓為坑洞25'且二氣化矽層22被移除）：在大約 95〇-100(TC的溫度T2、大約1拖耳的壓力P2以及氫氣_^ 量為2標準升/分鐘的速率下。此處之坑洞深度傜典型 地為數至十奈米。 其次，如第1D及5C圖所示，在坑洞25變圓為坑洞25‘ 後，砷或磷將擴散進入被坑洞化之溝渠側壁及底部以形 成摻雜區域27。該摻雜區域27將提供電容器35之電極或 電極板。此處的摻雜區域2 7偽以提昇腔室中之溫度至大 約lOOfTC的階级而使用砷或磷氣體形成。其將可在第二 道退火後在原位置被執行，或可於分離的設備中執行。 摻雜亦可被執行於以其他諸如離子植入電漿摻雜（PLAD) 或電漿浸没離子植入（PII)等方法之分離的設備中。 其次，電容器35之介質層32像被形成。在此，該結構 將被置入溫度大約800°C-100(TC之具有氨氣（NH3 )大約 6拖耳的壓力下的腔室中約30分鐘·，然後以低壓化學 氣相沈積（LPCVD)使氮化物在大約700 °C於SiH2 Cl2 (DCS) 及NH3中形成；且隨後在大約900°C的溫度於大約760拖耳 壓力之水氣中維持10分鐘以形成熱成長氣化物（亦即氤 化物之再氧化）。 因此，第一電極摻雜區域27以及介質層32(第5D圖）的 二步驟退火將可於後序執行於相同的腔室或一整合的設 -12- 本紙張尺度適用中國國家標準（CNS ) Λ4规枋（210Χ297公筇） --------裝------訂------ 球 (請先閱讀背面之注意事項再填寫本頁) 經漪部中央標準局貝工消f合作社印製 A7 B7 五、發明説明（〇 ) 備中。應注意地是，介質層32具有順著矽10表面中變圓 化的坑洞2 5 ’的不規則表面。因此，在二氧化矽層2 2外 表面之表面區域偽較僅將二氣化矽層22沈積於第1B圖中 的溝渠2 0所得的表面區域為大。 該結構隨後以任何傳統的方式加工而形成DRAM胞元40 ，諸如第1E圖所示。因此，電容器3 &將包括有位於介質 層32上方之摻雜非晶質或摻雜多晶矽37以形成電容器35 之第二電極。應注意地是，多晶矽或非晶質矽沈積將可 以在原位置執行。然而所有這些製程將可在不背離本發 明之範醻下於分離設備中離開原位置被執行。應注意地 是，第二電極37之表面積已為矽10表面中之坑洞25'所 增加。DRAM4Q包含具有一為閘極通道49所隔離之源極及 汲極區域44, 46之電晶體42。閘極通道49具有置於其上方 的一閘極氧化物4 8及一摻雜多晶矽或多晶矽-矽化鎢閘 極電極5L應注意地是，汲極區域46偽被電連接至摻雜 多晶矽37而將汲極區域電連接至電容器35之第二電極。 現參考第7A-7D圖，一墨積電容器DRAM胞元80偽画示 於第7D圖中。一電晶體82傺以任何傳統的方式形成，其 具有一摻雜多晶矽層84於熱成長氧化物層88上方以及一 導體86於摻雜多晶矽層84上方，以提供電晶體82用閘極 電極。該電晶體82具有如所示之源極及汲極區域。如所 示，在完成電晶體82的形成後，該裝置將以任何傳統的 方式以介質層9Q保護之。其次，叠積電容器83之下面導 體92俗被形成以與源極區域接觸。下面導體92傜為經摻 本紙張尺度適用中國國家標準（CNS ) Λ4現枋（210X 297公荩） ---^---^---------ΪΤ------ ^ ("先閱讀背而之注意事項再填寫本頁) 經滴部中央標準局員工消費合作社印製 A7 B7 五、發明説明（p ) 雜的矽。 如第7A_所示之結構随後以上述之第1B-1E圖的二階段 退火製程加工。因此，一未表示於圖上之不平坦介質層 將形成於矽導體92表面上方。在未表示於圖上之二氣化 矽介質層成長於矽導體92上方後，該結構將被置入腔室 或爐管中，其中該步驟並未表示於圖上。上述之二階段 退火步驟偽於隨後被執行〇在第一階段中，二氣化矽層 的不均勻度（亦即，例如山峰及山谷、低能摻雜或缺陷 將轉變為形成於導體92(亦即，叠積電容器83之底部）之 周圍舆頂端之上方的坑洞25(第7Β圖），而在第二階段退 火中，坑洞25之尖鋭邊緣將變圓。 其次，一介質層94將被置於加工過的矽導體92上方， 而導體96(亦即，電容器83之頂端電極）則被形成於介質 層94上方（第7C圖）。應注意地是，電容器83之導體92與 9 6以及電容器介質層94之表面區域傺大於第7Α圖中之未 被坑洞化的矽導體92所産生的表面區域。因此，電容器 83之電容量將被增加。 雖然本發明已被特別地掲示並參考不同的實施例做說 明，惟本發明可於不違背其有關之範轉下而為改良及改 變偽為熟習本技藝之人士所明瞭的。因此，本發明之範 醻應不以參考上述説明來決定，而應以參考所附之申請 專利範圍以及其所有相當的範畴而決定之。 -14- 本紙張尺度適用中國國家標準（CNS ) Λ4規梠（210Χ297公筇） --------,_私衣------1Τ------^ (請先閱讀背面之注意事項4填寫本頁) A7 B7 五、發明説明（d ) 參考符號説明 10.....基板 1 2.....被嵌埋之離子植入層 1 3.....襯墊層 14.....上表面 16.....介質層 1 8.....窗口 20.....溝渠 2 1.....介質環 2 2,3 2 , 9 0,9 4 .....介質層 2 5,2 5'.....坑洞 2 7.....摻雜區域 3 0 , 3 0 a , 3 0 b......曲線 35.......電容器 3 7.......第二電楝 40,80. . . .DRAM 胞元 42,82....電晶體 44.......源極區域 46.......汲極區域 48.......闊極氣化物 4 9.......閘極通道 50.......閘極電極 83 .......«積電容器 84 .......摻雜多晶矽層 8 6,9 2,9 6 .....導體 88.......熱成長氣化層 -----1^.- 本紙张尺度適川屮1¾國家標率（CNS ) Λ4規格（2】0Χ297公犮） --------”—装------訂-----.V線 (誚先閱讀背面之注意事項再硪寫本頁)Watanabe and others wrote an article entitled "An Advanced Technique for Fabricating Henispherical-Grained (HSG) Silicon Storage Electrodes". This paper explains the specifications of this paper; family standard (CNS) Λ4 specification (210X 297 public #) n I— i In---1--1-n -I ^ _ I 1 -I-— » -I ^ lv I-I--I- tt ^ i —II-^ n (诮 Read the precautions on the back first and then 桢 艿 this page) A7 B7 V. Description of the invention (>) Amorphous with a flat surface Silicon forms a DRAM capacitor board and then changes it to a capacitor board with a semi-circular grain of silicon (Si) with an uneven surface. The method includes forming a flat amorphous silicon plate (ie, an electrode) by low-pressure chemical vapor deposition followed by removing the electrode with the original vapor and vacuum annealing. This annealing process will form HSG-Si covering the entire surface of all types of storage electrodes, and its coverage also includes the sidewall surface that has been previously dry-etched. Another technique is described in U.S. Patent. No. 5324769. The patent discloses that a polycrystalline silicon pattern is formed on a semiconductor substrate to form an uneven structure conductor. A pinhole film is formed on the surface of the polycrystalline pattern. The polycrystalline silicon pattern is then etched through the pinhole. Next, the insulating film is removed. Yet another technique was published in September 1996 by "Japanese Journal of Applied Physics", vol. 35 (1996) Part 2, No. 9B, pages L-1215-1218 by Matsuo et al. And entitled "Growth of Polycrystalline Silicon Grain ". This article describes the formation of dome-shaped grains. An amorphous silicon film (a-Si) is deposited on a vaporized layer formed on a silicon substrate by vertical LPCVD. After the deposition of the a-Si film, annealing is performed in situ at the same temperature as the deposition. SUMMARY OF THE INVENTION According to the present invention, a method is provided for forming a capacitor dielectric. The method includes providing a semiconductor; forming an uneven layer on a semiconductor surface; applying heat and pressure to the semiconductor and the uneven layer to generate a cavity on the semiconductor surface; and forming a second dielectric layer on the semiconductor having the cavity Surface to provide capacitor dielectric. The standard of this paper is the national standard rate (CNS) of the ten boudoirs in China. Λ4 specification (210X297 mm) -------------- 1T ----- ^ (诮 Please read the precautions on the back before (Fill in this page) V. Description of the invention (4 A7 B7 body and polar product should be compatible. Crystal conductance side connection method and surface heating become hot. Electric surface effect hole is used for semi-supply surface gas side heating body production-hole surfacer. The surface pit device has a bulk crystal to raise the electricity of the hole. The surface of the pit body contains a mask with a single crystal pit, and the body has half the voltage of the conductor. The meter has a large amount of electricity. The middle semiconductor is more suitable for the hole to be lifted to the upper body of the mixed body. The half-shaped shape is lifted on the pit. The guide is used to guide the heat generation. The half and half of the half will be used to add the accumulation of the body to the opposite pit. One of the electrical conductors is mixed with the seed body and the body's conductive layer, and the half of the AM and the body can be mixed to place a guide to guide the half. There are many general sources for hybrids, half for DR, and the other for the design, and half more in the line, and the presentation is integrated into the integration. The quality provides the hole, and there is nothing to do. ,crystal Dielectric formation, pit-lifting, and production, 'pits have polarity due to electrical properties. Designing electrical and electronic forms: nature and nature will prepare equipment. Electricity is very special and has unique holes. And a surface-capacity container, a conductive capacitor, a pit electrode, a surface, a capacitor, a surface, a dielectric, a half, a dielectric, a package, and a battery. Among the crystals, the body of the instrument and the device. The method of the pit one is added to the device. The body of the body is included. The enlightenment is guided to the half of the Ming. The electric body of the Ministry of Electricity has a semi-transformed hair surface. When the electricity is accumulated, the electric device should be used in a hole-shaped table in a hole-shaped table. According to the method, according to the pit, the electric pressure of the root surface of the root surface of the root surface of the root surface is increased to the root pressure of the root surface, and the main volume is electrically connected by a pseudo table. ------------ I Sang ------ Order ------ Line (诮 Read the notes on the back before writing this page) This paper is suitable for ten prisoners in Sichuan Standard rate (CNS) Λ4 specifications (210X 297 mm) A7 B7 Description (4 According to another aspect of the present invention, the step of heating and pressurizing a semiconductor to create a cavity on the semiconductor surface includes a step of applying a first annealing step to a semiconductor having a dielectric layer thereon, and wherein The step of rounding the pits in the semiconductor surface includes the step of applying a second annealing to the semiconductor. According to another characteristic of the present invention, the step of the first annealing includes applying the semiconductor with a first temperature and a first pressure The second annealing step includes a step of applying a semiconductor to a second temperature at the first temperature. According to another characteristic of the present invention: (A) the first pressure is higher than the second pressure; or (B ) The second temperature 傺 is higher than the first temperature and the first pressure is pseudo higher than the second S force; or the second temperature 傺 is higher than the first temperature and the second pressure is equal to the first pressure. The drawings briefly explain the other characteristics of the present invention and the present invention itself will be made clearer by the following detailed description and accompanying drawings, wherein: Figures 1A-1E are pseudo-illustrations of the trench-capacitor DRAM cell according to the present invention during manufacture. Cross-section diagrams of each stage in Figure 2; Pseudo-Illustration Curves Published in the Conventional Techniques of Pseudo-Illustration Techniques; Figure 3 Pseudo-Illustration Curves Published in the Conventional Techniques Schematic diagram of one of the effects of two vaporized silicon etched on silicon at different temperatures; Circles 4A and 4B are diagrams of a pair of sequential annealing steps used to make a DRAM according to Figures 1A-1E of the present invention. Temperature and pressure profile used This paper has a size of 4 states 家 1¾¾ house standard rate (CNS) Λ4 specification (210X 297 mm) -------- 1 ^ ------, 1T ----- Line (read the notes on the back first and then fill in the ftT page) in the middle of the page; il meaning; J) 消 t: η 卬 1? A7 B7 V. Description of the invention () 1 I Figure; 1 1 Sections 5A to 5D The diagram is related to the 1 I DRAM cell according to the 1A to 1E diagrams according to the present invention. Cross-section diagram of each stage of the device during manufacture; 1 | 6A and 6B_ Pseudo diagram manufacture according to the first reading of 1A to 1E of the present invention 1 I Read 1 | One pair of sequential annealing for DRAM The temperatures and pressures used in the steps cross δ 1 I 1 planes. And note I Note 1 Figures 7A to 7D are pseudo-illustrations related to the superposition of capacitors according to the present invention-Capacitor Matter 1 Cross-section diagrams of the various stages of DRAM cells during manufacturing Figure 7B Figure 傜 is% 1 7 A enlarged part of the picture 9 The enlarged part is conventionally circled in the 7th AB and the page 1 is labeled 7 B to 7 B 〇1 1 Detailed description 1 1 The present invention is related to the integrated circuit (1C) Formation of the capacitor. The 1C 1 1 is a random access memory (RAM) including, for example, a dynamic random access memory (SUTT) body or a synchronous DRAM (SDRAM). 1 Others such as a special application IC (ASIC) 1 Or 1C such as integrated DRAM-logic circuit (embedded DRAM) is also available. 1 1 is typically > Several ICs are formed in parallel on the wafer. 0 After processing eis », the wafer is diced to divide I c into wafers. This wafer is then used by packaging lines I for applications such as Electrical and electronic systems, cellular telephones, digital consumer products 1 1 (PDAs) and other consumer electronics and other end products 0 1 | Refer to Figure 1 > Provide a part of a substrate such as a silicon wafer份 之 横 1 | Sectional view. Other substrates, such as gallium arsenide-germanium or other semiconductor materials, are available. For example, the substrate can be doped with a doped impurity 1 I with a predetermined conductivity to do a small amount or a large amount of doping to obtain the desired electrical properties. As shown in the figure 9 * 1 1 Embedded ion implantation layer 1 2 and in position 7 at a distance of 14 from the top surface of the silicon substrate 1 1 1 1 1 1 1 Paper size Tongzhou National Standard (CNS) Λ4 specifications (210X 297mm) A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Ⅴ. Description of the invention (b) At a depth of 1 1 1.5 micrometers, the phosphorus system is formed in which C is embedded and doped. The doping concentration of 1 1 doped layer 1 2 has a dosage of about 1012 to 1014 per square centimeter of the agent 1 1. A layer of a bi-gas liner with a thickness of about 10 0 angstroms_layer 1 3 ′ I become 1 „Please take 1 first 1 above the silicon substrate u 1 above 4 4 β as shown, a layer of 1000-5000 angstroms is read 1 I a dielectric layer 16 of thick silicon dioxide and / or silicon dioxide layer is arranged on the second Gasification η surface 1 I 1 Silicon liner layer 1 3 ±. Table: Above the surface 0 'Rabbit 1 Matter 1 Next 9 As shown in Section 1 A _ 9 One formed window 18 傜 Use traditional item 1 light lithography (also That is, -Hard type "ios or BSG 3, not shown) Fill in this i and chemical etching (also, reactive ion etching RIE) technology to form on the nitrogen page 1 silicon layer 16 and open the window The tritiated silicon layer 16 and the hard mask are used as a mask to etch the trenches 20 to the lower part of the upper surface 14 1 1 of the silicon substrate 10 using a Λ system etching technique. Here, the depth of the trench 2 G is a level of 8 centimeters from the silicon substrate 1 to the top surface 14 and the width of the trench 2 0 is § 1 0 _ 1 0 -0.2 .5 5 meters. Hierarchy. … ......—— ... W. A dielectric ring with a thickness of 100-1000 Angstroms of deposited 1 I silicon dioxide 2 1 (Figure 1B) 傺 using any two-step trench 1 | Etching process to form Around the upper part of the trench 20. 1 1 Next> An uneven dielectric layer 22 is formed on the surface of the trench 20......., As shown in Figure 1C. The dielectric layer 2 of this pavilion 2 2 Rhenium is a silicon dioxide that thermally grows to a thickness of about 10-30 1 1 Angstroms. The m 2 gasified silicon layer 2 2 will be the original oxygen silicon grown in the atmosphere 1 1, such as thermal silicon dioxide, TE0S or nitrogen 1 I compounds. It should be noted that the dielectric layer 2 2 is thick in thickness. There are various variations (i.e., unevenness) in the composition and / or composition and local 1 1 defects. Therefore, as shown in Fig. 1C 1 1, the dielectric layer 22 is uneven, that is, it has peaks and valleys. What should be 1 I Note / S ·· is that the unevenness in layer 2 2 can be other defects such as low energy doping 1 1 8 _ 1 1 1 1 This paper size applies Chinese National Standard (CNS) A4 «L Grid ( 210X 297 Gong) A7 B7 V. Description of Invention (7) Caused by traps. Referring briefly to Figure 2, curves 30, 30a, and 30b consider the graphs of the etch rates of sand and silicon dioxide as a function of temperature; curve 30 pseudo-graphs the silicon at a pressure of about 7 (50 torr). Etching rate, curve 30a 傜 shows the etching rate of silicon dioxide at a pressure of about 100 torr, and curve 30b 傜 shows the etching rate of silicon dioxide at a pressure of about 760 torr. Curve 30, 30a and 3Qb are typical examples of hydrogen. It should be noted that when the critical temperature T c (P) is a function of pressure P, the silicon dioxide surrounded by hydrogen (also the curve 3 Q a, 3 The etching rate of 0 b) is lower than the etching rate of silicon; whether it is single crystal silicon, polycrystalline silicon or amorphous silicon. The relationship between the etching rate and temperature under 7G0 drag was published in September 1995 Published in the article entitled "Roughness of Silicon Surface Heated in Hydrogen Ambient" Electrodes "by Habuka et al. In" Journal of the Electrochemical Society ", vol. 142, No. 9 The non-uniformity (ie, thickness, Can be doped or other defects) will lead to the formation of piercing points of silicon dioxide, while other parts are still covered by silicon dioxide. Therefore, reference is published in Habuka et al. Entitled "Roughness of Silicon Surface Heated" In Hydrogen Ambient " Electrodes " article 3, the two gasified silicon layer 22 傜 is shown above the silicon layer 10. The left side of the figure 3 is shown at a temperature higher than the critical temperature T c (P). Etching, and the right side of Fig. 3 illustrates etching at a temperature lower than the critical temperature Tc (P). It should be noted that at temperatures higher than the critical temperature Tc (P), the size of the two-gasification paper is tabulated State '丨' national standard rate (CNS) Λ4 specification (210 X297 mm) --------'-- installation ------ 17 -----:-line (诮 read the back first Note on this page) Α 功 Β7 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the People's Republic of China. 5. Description of the invention () 1 I The silicon layer 2 2 will be removed quickly 9 and the thin layer 22 is removed Quite flat 1 1 tan silicon 1 0 surface. However, when etched below the critical temperature Tc (F) When the temperature is 11 degrees, i pits 25 will be formed in the silicon layer 1 C. Therefore, i is lower than silicon please 1 first 1 the etching rate is much greater than the critical rate of the silicon dioxide vaporization rate T c (P) The etch rate of silicon is higher than that of silicon dioxide at a reading temperature of 1 will result in a pit with a 25-shaped back 1 I of 1 is formed in silicon 10 0 From the curve i of Figure 2 It should be noted that at atmospheric pressure The critical temperature under f1 is about 1 0 0 o ° c 0 at atmospheric pressure * When the temperature is higher than the temperature T c (P), the difference between the etching rates is slight and two Fill in this \ The silicon oxide film will be quickly removed. Figure 2 is a diagram showing, for example, about 100 pages' —. 1 I under the ear »The dependence of the etching rate of silicon dioxide on hydrogen on temperature Less obvious than 1 1 and 9 at lower temperatures The etch rate of silicon in hydrogen with a dependence of 1 1 is closer to 〇. Therefore, at a lower pressure of J, the boundary temperature T c (P) of i 1 will be lower at a higher pressure. 1 Therefore 9 refer to Figure 1C »After the dielectric layer 22 of silicon dioxide grows above silicon 1 I 1 0 9 The structure will be placed in a chamber or furnace tube (not shown) 〇 1 I 値 Second stage annealing Steps are then performed. In the first m phase, the non-uniformity of the 9 2 1 1 silicon oxide layer 2 2 (ie, low-energy step I doping or defects in the peaks and valleys) will become formed on the trench 20 side walls. And the bottom hole 2 5 1 (Figure 3), and in the second annealing i, the sharp edge 1 1 of the hole 25 will be rounded into a hole 2 5 1 〇 The first thing to note is that the pit The formation of the hole 2 5 1 1 and rounding will be possible in the enclosing hydrogen environment> or in other oxygen-free surroundings 9 such as argon 1 1 gas N gas and nitrogen 9 or ultra-high vacuum exit 1 1 is generated in the fire 0 should also be noted) two annealing steps are performed in the same chamber 1 I 9 that is the state of the same position f The structure of the health is shown in Section 1 1 -1 0- 1 1 1 1 This paper size is applicable to the Chinese National Standard (CNS) Λ 4% grid (210X2W official conversion) A7 B7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (9) 1 I 1 D in the figure 〇 1 1 Therefore > Also refer to Figure 5 A-5 D, after the formation of the uneven silicon dioxide layer 2 2 1 1 > The structure will be Place it in the chamber for annealing. In the first retreat, the first 1 fire step (Figure 5B), the chamber is at a relatively low first temperature as shown in the left of Figure 4A, reading 1. T1 (that is, lower than the critical temperature TC (P)), with η 1 I 1 to form the pit illustrated in the third picture and again shown in the 5B frame 2 5 things 1 0 down— * In the process, the temperature is raised to the original position as shown in item 4A_ on the right. Degree T 2 to fill out the rounded sharp edge of pot hole 2 5 to form a round pot hole 2 5 ′ as shown in Figure 5C, and also remove any residual silicon dioxide from page 1 I Layer 2 2 〇 If only the residual silicon dioxide part 1 1 can be removed, a wet etching step such as diluted or buffered hydrofluoric acid will be used 1 1 Figure 4B is a schematic illustration of a two-step annealing sequence Step 0 pit 2 5 will be borrowed 1-ί — from the surface of sand atom migration in the second annealing step to round to pit 2 5 1 〇1 m Note that ί two-step annealing can be maintained at the temperature of the second annealing step 1 I is determined to be performed when the chamber pressure in the second annealing step is reduced. 1 I 9 is shown in Figures 6 A and 6B. It should be noted that τήΰ. In the first annealing step 1 t 9 At the first pressure P 1, the temperature T 1 is lower than the threshold at the first pressure line P 1. Temperature T c (P), and in the second and second annealing steps of ί-Ε, where 1 t pressure is P 2 9, the temperature T 2 is pseudo higher than the critical temperature 1 1 T c (P) at the pressure P 2. As shown in Fig. 6B, the temperature is constant in both retreat steps; 1 I the structure is above the critical pressure 9 in the first annealing step and the structure is damaged in the 1 1 second annealing step Below the critical pressure 0 1 1 In an embodiment 9 the first annealing (that is, the formation of pits 2 5 (the 5B 1 1 -1 1-1 1 1 1 1 1 This paper size applies to Chinese national standards ( CNS) A4ML 梠 （210X 297 筇） Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Labor A7 B7 V. Description of the Invention (1) Figure)) P1 at a temperature of about 850 ° C T1 and a pressure of about 20 ear And the hydrogen flow rate is performed at a rate of 2 standard liters / minute for about 1Q-6Q minutes. The second annealing step is performed in the original position in the following process (that is, the pit 25 is rounded to a pit 25 'and the silicon dioxide layer 22 is removed): at a temperature of about 95-100 ° C (temperature T2 of TC, At a pressure of about 1 torr and hydrogen at a rate of 2 standard liters / minute. The pit depth here is typically several to ten nanometers. Second, as shown in Figures 1D and 5C, After the hole 25 is rounded into a pit 25 ', arsenic or phosphorus will diffuse into the side walls and bottom of the ditched trench to form a doped region 27. This doped region 27 will provide the electrode or electrode plate of the capacitor 35. Here The doped region 2 7 is formed by using arsenic or phosphorus gas to raise the temperature in the chamber to a level of about 100 fTC. It can be performed in situ after the second annealing or in a separate device. Doping can also be performed in a separate device using other methods such as ion implantation plasma doping (PLAD) or plasma immersion ion implantation (PII). Second, the dielectric layer 32 of the capacitor 35 is formed like Here, the structure will be placed at a temperature of about 800 ° C-100 (TC with ammonia (NH3) about 6 In a chamber under ear pressure for approximately 30 minutes, then low pressure chemical vapor deposition (LPCVD) was used to form nitrides at approximately 700 ° C in SiH2Cl2 (DCS) and NH3; and subsequently at approximately 900 ° C. The temperature is maintained in water gas at a pressure of about 760 ohms for 10 minutes to form a thermally grown gas (ie, reoxidation of the halide). Therefore, the first electrode doped region 27 and the second layer of the dielectric layer 32 (Figure 5D) Step annealing can be performed in the same chamber or an integrated device in the subsequent sequence. -12- This paper size applies Chinese National Standards (CNS) Λ4 Regulations (210 × 297). ---- Order ------ Ball (Please read the notes on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Standards and Industry Co., Ltd. Printed by A7 B7 Fifth, the description of the invention (〇) In preparation. Should be It is noted that the dielectric layer 32 has an irregular surface that follows the rounded pits 2 5 ′ in the surface of the silicon 10. Therefore, the surface area of the outer surface of the silicon dioxide layer 2 2 is pseudo The surface area of layer 22 deposited on trench 20 in Figure 1B is large. The structure is then shaped in any conventional manner. DRAM cell 40, such as shown in Figure 1E. Therefore, capacitor 3 & will include doped amorphous or polycrystalline silicon 37 over dielectric layer 32 to form the second electrode of capacitor 35. It should be noted that Polycrystalline silicon or amorphous silicon deposition can be performed in situ. However, all these processes can be performed without leaving the original position in the separation device without departing from the scope of the present invention. It should be noted that the surface area of the second electrode 37 It has been added to the pits 25 'in the surface of the silicon 10. The DRAM 4Q includes a transistor 42 having a source and a drain region 44, 46 isolated by a gate channel 49. The gate channel 49 has a gate oxide 48 and a doped polycrystalline silicon or polycrystalline silicon-tungsten silicide gate electrode 5L placed above it. It should be noted that the drain region 46 is pseudo-electrically connected to the doped polycrystalline silicon 37 and The drain region is electrically connected to the second electrode of the capacitor 35. Referring now to Figs. 7A-7D, a pseudo plot of an ink product capacitor DRAM cell 80 is shown in Fig. 7D. A transistor 82A is formed in any conventional manner and has a doped polycrystalline silicon layer 84 over the thermally grown oxide layer 88 and a conductor 86 over the doped polycrystalline silicon layer 84 to provide a gate electrode for the transistor 82. The transistor 82 has a source and a drain region as shown. As shown, after the formation of the transistor 82 is completed, the device will be protected by the dielectric layer 9Q in any conventional manner. Secondly, the lower conductor 92 of the stacked capacitor 83 is formed to be in contact with the source region. The following conductor 92 傜 is the standard of China National Standard (CNS) Λ4 (210X 297 cm) after being mixed with this paper. --- ^ --- ^ --------- ΪΤ ------ ^ (" Read the back notice first and then fill out this page) A7 B7 printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Education 5. Description of Invention (p) Miscellaneous silicon. The structure shown in Fig. 7A_ is then processed by the two-step annealing process of Fig. 1B-1E described above. Therefore, an uneven dielectric layer not shown in the figure will be formed over the surface of the silicon conductor 92. After the second gasified silicon dielectric layer not shown in the figure is grown over the silicon conductor 92, the structure will be placed in a chamber or furnace tube, which step is not shown in the figure. The two-stage annealing step described above is performed subsequently. In the first stage, the non-uniformity of the two-gasified silicon layer (ie, for example, peaks and valleys, low-energy doping or defects will be transformed into the conductor 92 (also That is, the pits 25 (Fig. 7B) above the top of the surroundings of the stacked capacitor 83), and in the second-stage annealing, the sharp edges of the pits 25 will be rounded. Second, a dielectric layer 94 will Is placed over the processed silicon conductor 92, and a conductor 96 (ie, the top electrode of the capacitor 83) is formed over the dielectric layer 94 (FIG. 7C). It should be noted that the conductors 92 and 9 of the capacitor 83 6 and the surface area of the capacitor dielectric layer 94 is larger than the surface area generated by the unpitted silicon conductor 92 in FIG. 7A. Therefore, the capacitance of the capacitor 83 will be increased. Although the present invention has been specifically illustrated And the description is made with reference to different embodiments, but the present invention can be understood and improved by those skilled in the art without altering the relevant norms. Therefore, the scope of the present invention should not refer to the above. Description to decide, It should be determined by referring to the scope of the attached patent application and all equivalent scopes. -14- This paper size applies the Chinese National Standard (CNS) Λ4 Regulations (210 × 297 Gong) --------, _ 私 衣 ------ 1Τ ------ ^ (Please read the note on the back 4 to complete this page) A7 B7 V. Description of the invention (d) Reference symbol description 10 ..... Substrate 1 2 ..... embedded ion implantation layer 1 3 ..... liner layer 14 ..... upper surface 16 ..... dielectric layer 1 8 ..... window 20. .... ditch 2 1 ..... dielectric ring 2 2,3 2, 9 0,9 4 ..... dielectric layer 2 5,2 5 '..... pit 2 7 ... .. doped regions 3 0, 3 0 a, 3 0 b ... curve 35 ....... capacitor 3 7 ....... second voltage 40, 80 ... .DRAM cell 42, 82 .... Transistor 44 .... Source region 46 .... Drain region 48 .... Wide electrode gas 4 9. ...... Gate channel 50 ....... Gate electrode 83 ....... `` Production capacitor 84 ....... Doped polycrystalline silicon layer 8 6,9 2,9 6 ..... Conductor 88 ....... Thermal growth gasification layer ----- 1 ^ .- This paper is suitable for Sichuan 屮 1¾ National Standard (CNS) Λ4 Specification (2) 0 × 297 犮) -------- "— install ------ order -----. V line (诮 read first (Read the notes on the back and rewrite this page)