4Λ29 6 5 A7 埋膂郎智慧財產曷員工消費合作社印製 6114tWffd〇C/°°8_B7_ 五、發明說明（I ) 本發明是有關於一種半導體元件電容器（Capacitor)的 製造方法及結構，且特別是有關於一種動態隨機存取記憶 體（Dynamic Random Access Memory，DRAM)之電容器的製 造方法及結構。 積體電路記憶元件通常包括有電容器，而將這些電容 器充電成不同的狀態來表示所儲存的資料。例如動態隨機 存取記憶體（DRAMs)，一般由陣列式的記憶胞(Memory Cell) 所組成，其中每個記憶胞包含一個連接在一轉移場效電晶 體（FET)之源極/汲極區的電荷儲存電容，而在電荷儲存電 容的電極上提供有一個或另兩個不同的電荷位階來代表記 憶胞上1或0的邏輯訊號。 因此，電容器是動態隨機存取記憶體之記憶胞用以f諸 存訊號的心臟部位，如果電容器所儲存的電荷愈多，訊號 的儲存量也愈大，且讀出放大器在讀取資料時受雜訊的影 響，例如：（X粒子所產生的軟錯記（Soft Errors)，會大大的 降低。 動態隨機存取記憶體的電荷儲存電容器是由被介電層 所隔離的下電極（Lower Electrode)與上電極（Upper Electrode)所組成，而電極的材料往往是經摻雜後的複晶 矽。電荷儲存電容的下電極通常與轉移場效電晶體之源極 /汲極區相接觸，形成一個具有較低表面的複晶矽結構。 通常下電極有一部份會延伸到一絕緣層上’而此絕緣層乃 是形成在轉移場效電晶體其他部份的上方以及部份鄰接 DRAM的上方。雖然電容的下電極有可能是一平坦表面，____I 本紙張尺度適用+困Β家標準（CNS>A4规格（210 X 297公釐） --------------裝--- (請先閲讀背面之注$項再填寫本頁) •'5. -線· 442965 61 1 4twff.doc/008 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（y) 但是更普遍的是具有較複雜形狀的表面。 而爲增進儲存電容器的儲存電量，除了使用具有較高 介電常數的介電質，或控制介電材料沈積的厚度與品質 外，另外就是增加電容器儲存電極的表面積。而在記憶單 元逐漸縮小的情況下，如何在DRAM逐漸縮減的基底表 面積中增加電容器儲存電極的表面積，是目前在製程中， 較常面臨的問題。 請參照第1圖，其所繪示的爲習知一種動態隨機存取 記憶體疊層式（Stack Method)電容結構製造方法的剖面示 意圖。首先，提供一半導體基底100，其上已形成有一金 氧半電晶體（MOS)102，包括一閘極104、一源極/汲極區 106。在半導體基底1〇〇上有一場氧化層1〇7與一導電層 108。然後，沈積一絕緣層π〇。再在指定的源極/汲極區 106上’蝕刻絕緣層11〇而形成一接觸窗口。接著依序在 接觸窗口上’形成一下電極層120、一介電層130和一上 電極層140，構成一疊層式電容150的結構。介電層130 可爲氮化矽/二氧化矽層(NO)或是二氧化矽層/氮化矽/二氧 化矽層（ΟΝΟ)。而下電極層no和上電極層〗40可爲多晶 矽層’且下電極層120爲起伏的表面結構，其目的用以增 加電容150的表面積。最後，再形成一金屬接觸窗〗60以 及絕緣保護層（未顯示）等後續製程，以完成動態隨機存取 記憶體的結構。 上述疊層式電容結構是一種目前常用於動態隨機存取 記憶體中的電容結構，其方法是改進電容的表面形態 先 閲 讀 意 事 項 再 填 寫 本 頁 I I 訂 線 本紙張尺4舶中國國家镖準（CNS>A4蜒格（210 x 297公釐） 五、發明說明（々） <請先聞讀背面之注意事項再填窝本頁> (Morphology)，製造出各種凹凸不平的表面。雖然可以增 加電容器的表面積以提高電容量，但是其缺點在於增加的 程度有限，不足以應用於更小尺寸的元件。 而其他用來增進電容器下電極表面積的方式，包括製 作各種具有不平坦表面的結構，以提供較大的下電極表面 積，例如形成冠狀（Crown)、柱狀、鰭狀（Fin)、樹枝狀或 凹槽（Cavity)等結構，甚至再於上述結構上再形成一半球 顆粒複晶矽層（HSG-SO。但通常這些複雜的電容器之結構 難以製造，且大大地增加製程之複雜度。 本發明提出一種動態隨機存取記憶體之電容結構及其 製造方法，可以大大增加電容器的表面積，有效提高電容 量，以適用於更小尺寸的元件，如64Mb容量或以上之動 態隨機存取記憶體。 本發明的目的，就是在提供一種能提高電容器電荷儲 存的靜電容量且較好製造的電容器。 本發明之動態隨機存取記憶體之製造方法，係提供一 半導體基底，其上已形成有一金氧半電晶體，接著在半導 體基底上沉積一絕緣層。然後於絕緣層上，旋塗一層三基 本單位異量分子共聚物。定義該三基本單位異量分子共聚 物層之圖案，然後，低溫回火此三基本單位異量分子共聚 物層，再暴露此三基本單位異量分子共聚物層於紫外線及 含臭氧之環境中，使此三基本單位異量分子共聚物層轉化 成爲一交叉連續具複雜起伏三度中空結構之下電極層。之 後，在下電極層上沈積一介電層，接著，在介電層上沈積 5 本紙張尺度適用中困國家標準（CNS)A4规格（210 X 297公釐） A7 4429 6 5 6114tWffd〇C/〇QS_B7_ 五、發明說明（9 ) 一上電極層。然後蝕刻定義整個電容的圖案。 根據本發明之目的，提出一種下電極結構，其使用一 形成交叉連續具三度中空孔洞結構之材料，此材料不但有 高度規律性，而且爲具高複雜度之三度中空結構；此結構 之精密度及複雜度均非一般微影製程所能製造的·而此交 錯複雜中空多孔結構之材料也爲下電極層提供了極大之表 面積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖所繪示的爲習知一種動態隨機存取記憶體疊層 式（Stack Method)電容結構之製造方法的剖面示意圖。 第2圖是爲一較佳實施例中三基本單位異量分子共聚 物混和物結構之示意圖。 第3A圖至第3D圖所繪示的爲依照本發明一較佳實 施例之一種動態隨機存取記憶體疊層式電容結構製造方法 的剖面示意圖。 圖式之標記說明： 100,300:半導體基底 102,302:金氧半電晶體 1 04,304:蘭極 1 06,3 06:源極/汲極區 107,307:場氧化層 6 本紙張尺度適用中困Η家標準<CNS)A4规格（210 X 297公釐） {請先閲讀背面之注意事項再填寫本頁) 裝 ----^"1!訂--— — — — —--線. A7 B7 五、 I Utwff.doc/008 發明說明（& ) 108,308:導電層 1 10,310:絕緣層 3 12:三基本單位異量分子共聚物層 120,320:下電極餍 130.330·介電層 140.340:上電極層 150,350:電容 160,360:金屬接觸窗 實施例 爲了在DRAM逐漸縮減的基底表面積中，大大增加 電容器儲存電極的表面積，本發明採用一種交叉連續 (Bicontinuous)之材料’作爲下電極之材料。而較佳實施例 戶斤示’乃爲使用該交叉連續材料中之一種，但本發明所使 用之材料並不只限定於較佳實施例中所示之材料。 本發明之一較佳實施例使用，一種交叉連續 (Bicontinuous)具複雜起伏三度中空結構(Nanoporous)之陶 瓷材料，作爲下電極之材料。此陶瓷材料之製備乃使用三 基本單位異量分子共聚物（Triblock Copolymer)做起始原 料’即AiBA2，其中A爲聚異戊乙烯(p〇ly(isoprene)，以 下簡稱PI)，而B爲聚五甲基雙甲硅烷基苯乙烯 (Poly(pentamethyldisilylstyrene)，以下簡稱 P(PMDSS)) 〇 ΑιΒΑ2之組成爲24/100/26，A】BA2係以P(PMDSS)爲基 質，在P(PMDSS)基質中形成互相交錯纏繞之PI雙螺旋網 路結構（Double Gyroid Morphology)，PI所佔之體積比例爲 本紙張尺度適用中曲8家標準（CNS)A4規格（210 X 297公釐） 請 先 閲 讀 背 意 事 項 再 填 > 頁 訂 經濟部智慧財產局貝μ消费合作钍印製 6 5 A7 6 1 14twff.d〇c/008 ____B7__ 五、發明說明（l ) 33%左右。請參考第2圖，爲八#八2共聚物結構之示意圖， 此共聚物簡稱爲【P(PMDSS)-DG】。對【P(PMDSS)-DG】 共聚物再經一低溫回火之步驟，以氧化去除爲碳氫化合物 之PI基本單位，且使含矽之P(PMDSS)基本單位轉化成矽 氧碳陶瓷。如此一來，P(PMDSS)基質中形成之PI雙螺旋 網路結構會被移除，而其在P(PMDSS)基質中所佔之空間 會變成連續扭曲之三度孔洞構造；同時P(PMDSS)基質轉 化爲矽氧碳陶瓷，故形成交叉連續具複雜起伏三度中空結 構之陶瓷材料。此機制已揭露在科學期刊（Science)，Vol 286，第 1716-9 頁。 因此形成之陶瓷材料不但有高度規律性，而且爲具高 複雜度之三度中空結構；此結構之精密度及複雜度均非一 般微影製程所能製造的，而此複雜之中空多孔結構也爲下 電極提供了極大之表面積，以適用於更小尺寸之元件，如 64Mb容量或以上之DRAM。 請參照第3A圖至第3D圖，其繪示依照本發明一較 隹實施例的動態隨機存取記憶體疊層式電容之製造步驟的 剖面示意圖。 首先，請參照第3A圖，提供一半導體基底300，其 上已形成有一金氧半電晶體302，包括一閘極304與一源 極/汲極區306。且在半導體基底300上有一場氧化層307 與一導電層308。 接著例如以原砂酸四乙酯（Tetra-Ethyl-Ortho-Silicate ; TEOS)爲反應氣體，在半導體基底300上沉積一 84Λ29 6 5 A7 Printed by Intellectual Property Co., Ltd. 6114tWffd0C / °° 8_B7_ printed by employee consumer cooperatives V. Description of the invention (I) The present invention relates to a method and structure for manufacturing a semiconductor capacitor (Capacitor), and in particular A manufacturing method and structure of a capacitor for a dynamic random access memory (Dynamic Random Access Memory, DRAM). Integrated circuit memory elements usually include capacitors, and these capacitors are charged into different states to represent stored data. For example, dynamic random access memories (DRAMs) are generally composed of array-type memory cells, where each memory cell includes a source / drain region connected to a transfer field-effect transistor (FET). Charge storage capacitors, and one or two different charge levels are provided on the electrodes of the charge storage capacitors to represent 1 or 0 logic signals on the memory cells. Therefore, the capacitor is the heart part of the memory cell of the dynamic random access memory used to store the signals. If the capacitor stores more electric charge, the signal storage capacity also increases, and the sense amplifier is affected when reading data. The influence of noise, such as: (Soft Errors generated by X particles, will be greatly reduced. The charge storage capacitor of the dynamic random access memory is a lower electrode isolated by a dielectric layer (Lower Electrode) ) And the upper electrode (Upper Electrode), and the material of the electrode is often doped polycrystalline silicon. The lower electrode of the charge storage capacitor is usually in contact with the source / drain region of the field-effect transistor. A polycrystalline silicon structure with a lower surface. Usually a part of the lower electrode extends onto an insulating layer, and this insulating layer is formed over other parts of the FET and adjacent to the DRAM. .Although the lower electrode of the capacitor may be a flat surface, __I This paper size is applicable to the standard of the standard B (CNS > A4 (210 X 297 mm)) --- (Please read the back first Please fill in this page if you want to pay $.) • '5. -Line · 442965 61 1 4twff.doc / 008 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (y) Complex shaped surfaces. In order to increase the storage capacity of storage capacitors, in addition to using a dielectric with a higher dielectric constant, or controlling the thickness and quality of the dielectric material deposition, it is also increasing the surface area of the capacitor storage electrodes. When the memory unit is gradually shrinking, how to increase the surface area of the capacitor storage electrode in the gradually decreasing substrate surface area of the DRAM is a problem that is often faced in the current manufacturing process. Please refer to FIG. 1, which shows the conventional knowledge. A cross-sectional schematic diagram of a manufacturing method of a dynamic random access memory stacked method capacitor structure. First, a semiconductor substrate 100 is provided, and a gold-oxygen semiconductor (MOS) 102 has been formed thereon, including a gate 104 A source / drain region 106. There is a field oxide layer 107 and a conductive layer 108 on the semiconductor substrate 100. Then, an insulating layer π is deposited. A contact window is formed by 'etching the insulating layer 110 on the source / drain region 106. Then, a lower electrode layer 120, a dielectric layer 130, and an upper electrode layer 140 are sequentially formed on the contact window to form a stack. Structure of the capacitor 150. The dielectric layer 130 may be a silicon nitride / silicon dioxide (NO) layer or a silicon dioxide layer / silicon nitride / silicon dioxide layer (NO). The lower electrode layer no and the upper electrode The layer 40 can be a polycrystalline silicon layer and the lower electrode layer 120 has an undulating surface structure, the purpose of which is to increase the surface area of the capacitor 150. Finally, a metal contact window 60 and an insulation protection layer (not shown) are formed in subsequent processes. To complete the structure of dynamic random access memory. The above-mentioned stacked capacitor structure is a capacitor structure commonly used in dynamic random access memory. The method is to improve the surface morphology of the capacitor. Read the notice first and then fill out this page II. (CNS > A4 Grid (210 x 297 mm) 5. Description of the Invention (々) < Please read the notes on the back before filling in this page > (Morphology) to create various uneven surfaces. Although The surface area of the capacitor can be increased to increase the capacitance, but the disadvantage is that the increase is limited and it is not enough to apply to smaller components. Other methods to increase the surface area of the lower electrode of the capacitor include various structures with uneven surfaces. In order to provide a large surface area of the lower electrode, for example, a crown, a column, a fin, a dendrite or a cavity are formed, and even a hemispherical particle complex is formed on the above structure. Silicon layer (HSG-SO. However, these complex capacitor structures are usually difficult to manufacture and greatly increase the complexity of the process. The present invention proposes a The capacitance structure of the dynamic random access memory and its manufacturing method can greatly increase the surface area of the capacitor and effectively increase the capacitance, so that it is suitable for smaller size components, such as a dynamic random access memory with a capacity of 64Mb or more. The purpose of the invention is to provide a capacitor which can improve the electrostatic capacity of the capacitor's charge storage and is better manufactured. The manufacturing method of the dynamic random access memory of the present invention is to provide a semiconductor substrate on which a gold-oxygen semi-electricity has been formed. Crystal, and then deposit an insulating layer on the semiconductor substrate. Then spin-coat a three basic unit isomer molecule copolymer on the insulating layer. Define the pattern of the three basic unit isomer molecule copolymer layer, and then temper this at low temperature Three basic unit heterogeneous molecular copolymer layer, and then expose the three basic unit heterogeneous molecular copolymer layer to ultraviolet and ozone-containing environment, so that the three basic unit heterogeneous molecular copolymer layer is transformed into a continuous and complex undulation The electrode layer below the three-degree hollow structure. Then, a dielectric layer is deposited on the lower electrode layer, and then Deposit 5 paper layers on the dielectric layer. Applicable to the national standard (CNS) A4 specification (210 X 297 mm) A7 4429 6 5 6114tWffd0C / 〇QS_B7_ 5. Description of the invention (9) An electrode layer. Then Etching defines the pattern of the entire capacitor. According to the purpose of the present invention, a lower electrode structure is proposed, which uses a material that forms a cross-continuous three-dimensional hollow hole structure. This material is not only highly regular, but also highly complex. Hollow structure; the precision and complexity of this structure are not made by ordinary lithographic processes. And the material of this staggered complex hollow porous structure also provides a great surface area for the lower electrode layer. Other objects, features, and advantages can be more clearly understood. The following is a detailed description of a preferred embodiment and the accompanying drawings. The brief description of the drawings is as follows: A schematic cross-sectional view of a manufacturing method of a dynamic random access memory stacked method capacitor structure. Fig. 2 is a schematic diagram showing the structure of the three basic unit heterogeneous molecular copolymer blend in a preferred embodiment. 3A to 3D are schematic cross-sectional views illustrating a method for manufacturing a dynamic random access memory stacked capacitor structure according to a preferred embodiment of the present invention. Description of drawing symbols: 100,300: semiconductor substrate 102,302: metal-oxide semiconductor transistor 1 04,304: blue electrode 1 06,3 06: source / drain region 107,307: field oxide layer 6 This paper is applicable to the standard of the family ’s standards < CNS) A4 specification (210 X 297 mm) {Please read the precautions on the back before filling out this page) Install ---- ^ " 1! Order --- — — — —-Line. A7 B7 Five & I Utwff.doc / 008 Description of the invention 108,308: conductive layer 1 10,310: insulating layer 3 12: three basic unit isomer molecular copolymer layer 120,320: lower electrode 餍 130.330 · dielectric layer 140.340: upper electrode layer 150,350 : Capacitors 160, 360: Examples of metal contact windows In order to greatly increase the surface area of the capacitor storage electrode in the gradually reduced surface area of the DRAM substrate, the present invention uses a cross-continuous (Bicontinuous) material as the material of the lower electrode. In the preferred embodiment, the household materials are used as one of the cross-continuous materials, but the materials used in the present invention are not limited to those shown in the preferred embodiments. A preferred embodiment of the present invention uses a cross-continuous ceramic material with complex undulating three-degree hollow structure (Nanoporous) as the material of the lower electrode. This ceramic material is prepared by using three basic units of Triblock Copolymer as the starting material, namely AiBA2, where A is polyisoprene (poly (isoprene), hereinafter referred to as PI), and B is Poly (pentamethyldisilylstyrene) (hereinafter referred to as P (PMDSS)) 〇ΑιΒΑ2 composition is 24/100/26, A] BA2 is based on P (PMDSS) as the matrix, in P (PMDSS ) Double Gyroid Morphology is formed in the matrix. The proportion of volume occupied by PI is based on the paper size. Applicable to 8 Chinese Standards (CNS) A4 specifications (210 X 297 mm). Read the remarks and fill in the page. Page of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative Printing 6 5 A7 6 1 14twff.d〇c / 008 ____B7__ 5. Description of the invention (l) 33%. Please refer to Figure 2 for a schematic diagram of the structure of the eight #eight 2 copolymer, which is referred to as [P (PMDSS) -DG] for short. [P (PMDSS) -DG] copolymer was subjected to a low-temperature tempering step to remove the PI basic unit of hydrocarbons by oxidation, and convert the basic unit of P (PMDSS) containing silicon into silicon-carbon ceramics. In this way, the PI double helix network structure formed in the P (PMDSS) matrix will be removed, and the space it occupies in the P (PMDSS) matrix will become a continuously distorted three-degree hole structure; meanwhile, P (PMDSS ) The matrix is converted into silicon-oxycarbon ceramics, so a cross-continuous ceramic material with complex undulating three-degree hollow structure is formed. This mechanism has been disclosed in Science, Vol 286, pp. 1716-9. Therefore, the ceramic material formed is not only highly regular, but also a three-dimensional hollow structure with high complexity; the precision and complexity of this structure are not made by ordinary lithographic processes, and this complex hollow porous structure is also Provides a large surface area for the lower electrode, which is suitable for smaller size components, such as DRAM with a capacity of 64Mb or more. Please refer to FIG. 3A to FIG. 3D, which are schematic cross-sectional views showing the manufacturing steps of a dynamic random access memory multilayer capacitor according to a comparative embodiment of the present invention. First, referring to FIG. 3A, a semiconductor substrate 300 is provided, on which a metal-oxide semiconductor 302 has been formed, including a gate electrode 304 and a source / drain region 306. And there is a field oxide layer 307 and a conductive layer 308 on the semiconductor substrate 300. Then, for example, using tetraethyl ortho-ortho-stearate (Tetra-Ethyl-Ortho-Silicate; TEOS) as a reactive gas, a semiconductor substrate 300 is deposited on the substrate 8.
參紙張尺度4用中B B家標準（CNS)A4 ΛΙ袼（210 X 297公釐) J 丨丨— — — — — 丨_ 丨丨- — _ _ h ί 訂-------JW. (锖先W讀背面之注意事項再填寫本頁) A7 B7 442965 61 14twff.doc/008 五、發明說明（7 ) 絕緣層310，較佳的是二氧化矽層’而絕緣層3〗0的厚度 約在3000埃到約6000埃之間。 然後，請參照第3B圖’再在指定的源極/汲極區306 上，蝕刻絕緣層310而形成一接觸窗口。接著於絕緣層31〇 上，旋塗一層三基本單位異量分子共聚物【p(pmdss)-dg】 層312，並塡滿該接觸窗口。較佳的是以4000rpm左右之 轉速旋轉塗佈【P(PMDSS)-DG】溶液，此【P(PMDSS)-DG】 溶液中含4〜6%重量百分比之【P(PMDSS)-DG】混和物溶 於溶劑甲苯中。 接著，請參照第3C圖，定義三基本單位異量分子共 聚物【P(PMDSS)-DG】層312之圖案，之後，低溫回火此 【P(PMDSS)_DG】層312兩天，回火溫度在100°C至150 °C之間，較適爲120°C，再暴露此【P(PMDSS)-DG】層312 於254nm波長之紫外線及含2%臭氧之環境中至少1小 時，使此【P(PMDSS)-DG】層312中之PI被移除，而P(PMDSS) 所含之矽轉化爲矽氧碳。經此反應，此【P(PMDSS)-DG】 層312乃轉化成爲一交叉連續具複雜起伏三度中空結構之 陶瓷材料層，也就是下電極層320，而下電極層320的厚 度約在2000埃到約5000埃之間。 在暴露於紫外線及臭氧之步驟之後，【P(PMDSS)-DG】 層312中的PI雙螺旋網路結構會被移除，而其在P(PMDSS) 基質中所佔之空間會變成連續扭曲之三度孔洞構造；同時 P(PMDSS)基質中之矽轉化爲化性及結構皆穩定之矽氧碳 陶瓷，故形成交叉連續具三度中空孔洞結構之陶瓷材料。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝— (請先閲讀背面之注意事項再填寫本頁) 訂- .線· 硬齊邠智慧犲4¾員工消费合阼；^¾ 4429 6 5 6 114twff,doc/()08 B7 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（3 ) 此孔洞之大小約在200埃至620埃之間，孔洞之大小可經 由混和物比例之調整或分子量之變化來控制。 因此形成之陶瓷材料不但有高度規律性，而且爲胃胃 複雜度之三度中空結構；此結構之精密度及複雜度均 般微影製程所能製造的，而此交錯複雜中空多孔結構之材· 料也爲下電極層320提供了極大之表面積。 之後，請參照第3D圖，在下電極層320上沈積一介 電層330，例如氧化矽/氮化矽/氧化矽層(ΟΝΟ)，其形成方 法爲先加熱長成一層氧化矽層，接著形成一層氮化矽層’ 然後進行熱氧化的步驟，在氮化矽層上形成一層氧化矽 層。介電層330的厚度小於下電極層320，一般不超過300 埃左右。接著，在介電層330上沈積一上電極層340，例 如摻雜的多晶矽層，其形成方法爲化學氣相沈積法，並摻 雜有離子，以增加導電度。上電極層340的厚度約在1000 埃到約3000埃之間。然後蝕刻定義整個電容350的圖案。 於是下電極層320、介電層330和上電極層340彤成動態 隨機存取記憶體疊層式電容350的結構。 接著，形成絕緣保護層（未顯示）等後續製程，以完成 動態隨機存取記憶體的結構。 本發明提出一種下電極結構，其使用一形成交叉連續 具三度中空孔洞結構之材料，此材料不但有高度規律性， 而且爲具高複雜度之三度中空結構；此結構之精密度及複 雜度均非一般微影製程所能製造的，而此交錯複雜中空多 孔結構之材料也爲下電極層提供了極大之表面積。 本紙诋尺Jχ遘fflIPB國冢標早<CNS)A4規格（2Wχ297公¾) (請先閱讀背面之注意事項再填寫本頁) ----h- 訂---------線. 4429 6 5 A7 6 1 14twff.doc/008 ___B7_ 五、發明說明（1 ) 綜上所述，本發明所提出此種動態隨機存取記憶體電 容之製造方法，具有以下的好處： (1)使用一形成交叉連續具三度中空孔洞結構之材 料，爲下電極層提供了極大之表面積，而使儲存於電容器 內的電荷數量增加。 (2)本發明之電容結構的製程比一般習知中具各種複 雜表面之電容結構的製程簡單，可減少許多步驟以降低製 造的成本以及花費的時間。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先Μ讀背面之注意事項再填寫本頁) 裝 訂---------線r^- 經齊部智慧財產笱貝二消費合泎达印货 本紙張尺度適用中Η Β家襍準（CNS>A4规格（210 X 297公« )Refer to the paper standard 4 in the BB family standard (CNS) A4 ΛΙ 袼 (210 X 297 mm) J 丨 丨 — — — — — 丨 _ 丨 丨-— _ _ h ί Order ------- JW. (锖 Please read the notes on the back before filling this page) A7 B7 442965 61 14twff.doc / 008 V. Description of the invention (7) Insulation layer 310, preferably silicon dioxide layer, and insulation layer 3] 0 The thickness is between about 3000 Angstroms and about 6000 Angstroms. Then, referring to FIG. 3B ', the insulating layer 310 is etched on the designated source / drain region 306 to form a contact window. Next, a layer of three basic unit isomer molecular copolymers [p (pmdss) -dg] layer 312 is spin-coated on the insulating layer 31 and fills the contact window. Preferably, the [P (PMDSS) -DG] solution is spin-coated at a rotation speed of about 4000 rpm, and the [P (PMDSS) -DG] solution contains 4 to 6% by weight of the [P (PMDSS) -DG] blend. The material was dissolved in toluene. Next, referring to Figure 3C, define the pattern of the three basic unit heterogeneous molecular copolymer [P (PMDSS) -DG] layer 312, and then temper this [P (PMDSS) _DG] layer 312 for two days at low temperature, and then temper it. The temperature is between 100 ° C and 150 ° C, which is more suitable for 120 ° C, and then the [P (PMDSS) -DG] layer 312 is exposed to ultraviolet light with a wavelength of 254nm and an environment containing 2% ozone for at least 1 hour, so that The PI in the [P (PMDSS) -DG] layer 312 is removed, and the silicon contained in P (PMDSS) is converted to silicon oxygen carbon. After this reaction, the [P (PMDSS) -DG] layer 312 is transformed into a cross-continuous ceramic material layer with complex undulating three-degree hollow structure, that is, the lower electrode layer 320, and the thickness of the lower electrode layer 320 is about 2000 Angstroms to about 5000 Angstroms. After exposure to UV and ozone, the PI double helix network structure in the [P (PMDSS) -DG] layer 312 will be removed, and the space it occupies in the P (PMDSS) matrix will become continuously distorted Third-degree pore structure; At the same time, the silicon in the P (PMDSS) matrix is transformed into silicon-oxycarbon ceramics with stable chemical properties and structure, so it forms a cross-continuous ceramic material with a third-degree hollow pore structure. 9 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -------------- Packing— (Please read the precautions on the back before filling this page) Order -. Line · Hard and Smart, 4¾ Employee Consumption Combination; ^ ¾ 4429 6 5 6 114twff, doc / () 08 B7 A7 Printed by the Employee Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (3) The size is about 200 Angstroms to 620 Angstroms. The size of the pores can be controlled by adjusting the mixture ratio or changing the molecular weight. Therefore, the ceramic material formed is not only highly regular, but also has a three-dimensional hollow structure of stomach and stomach complexity; the precision and complexity of this structure can be manufactured by the lithographic process, and this material with staggered complex hollow porous structures The material also provides a great surface area for the lower electrode layer 320. After that, referring to FIG. 3D, a dielectric layer 330, such as a silicon oxide / silicon nitride / silicon oxide layer (NO), is deposited on the lower electrode layer 320. The method for forming the dielectric layer 330 is to first heat and grow a silicon oxide layer, and then form A silicon nitride layer 'followed by a thermal oxidation step to form a silicon oxide layer on the silicon nitride layer. The thickness of the dielectric layer 330 is smaller than that of the lower electrode layer 320, and generally does not exceed about 300 angstroms. Next, an upper electrode layer 340, such as a doped polycrystalline silicon layer, is deposited on the dielectric layer 330 by a chemical vapor deposition method and doped with ions to increase conductivity. The thickness of the upper electrode layer 340 is between about 1000 angstroms and about 3,000 angstroms. The pattern defining the entire capacitor 350 is then etched. Thus, the lower electrode layer 320, the dielectric layer 330, and the upper electrode layer 340 have a structure of a dynamic random access memory stacked capacitor 350. Then, a subsequent process such as an insulating protection layer (not shown) is formed to complete the structure of the dynamic random access memory. The present invention proposes a lower electrode structure using a material that forms a cross-continuous three-dimensional hollow hole structure. This material not only has a high degree of regularity, but also a three-dimensional hollow structure with high complexity; the precision and complexity of this structure The degree is not what ordinary lithographic process can make, and this material with staggered complex hollow porous structure also provides a great surface area for the lower electrode layer. This paper ruler Jχ 遘 fflIPB Kunizuka Standard < CNS) A4 specification (2Wx297 male ¾) (Please read the precautions on the back before filling this page) ---- h- Order --------- Line. 4429 6 5 A7 6 1 14twff.doc / 008 _B7_ V. Description of the invention (1) In summary, the method for manufacturing a dynamic random access memory capacitor proposed by the present invention has the following advantages: (1 ) The use of a material forming a cross-continuous three-dimensional hollow hole structure provides a great surface area for the lower electrode layer and increases the amount of charge stored in the capacitor. (2) The manufacturing process of the capacitor structure of the present invention is simpler than that of conventional capacitor structures with various complex surfaces, and many steps can be reduced to reduce manufacturing cost and time. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page) Binding --------- line r ^-Jingji Intellectual Property 笱 Beijing Second Consumption 泎 Up to Printed Paper Size Applicable Standard (CNS > A4 size (210 X 297 male «)