SG11201901194SA - Wafer-level package with enhanced performance - Google Patents

Wafer-level package with enhanced performance

Info

Publication number
SG11201901194SA
SG11201901194SA SG11201901194SA SG11201901194SA SG11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA SG 11201901194S A SG11201901194S A SG 11201901194SA
Authority
SG
Singapore
Prior art keywords
die
thinned
wafer
mold compound
international
Prior art date
Application number
SG11201901194SA
Other languages
English (en)
Inventor
Julio Costa
Jan Vandemeer
Jonathan Hammond
Merrill Hatcher
Jon Chadwick
Original Assignee
Qorvo Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qorvo Us Inc filed Critical Qorvo Us Inc
Publication of SG11201901194SA publication Critical patent/SG11201901194SA/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Micromachines (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
SG11201901194SA 2016-08-12 2017-08-14 Wafer-level package with enhanced performance SG11201901194SA (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662374332P 2016-08-12 2016-08-12
US201662374439P 2016-08-12 2016-08-12
US201662374318P 2016-08-12 2016-08-12
PCT/US2017/046758 WO2018031995A1 (en) 2016-08-12 2017-08-14 Wafer-level package with enhanced performance

Publications (1)

Publication Number Publication Date
SG11201901194SA true SG11201901194SA (en) 2019-03-28

Family

ID=59684109

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201901194SA SG11201901194SA (en) 2016-08-12 2017-08-14 Wafer-level package with enhanced performance

Country Status (6)

Country Link
US (2) US10109550B2 (ja)
EP (1) EP3497717A1 (ja)
JP (2) JP7037544B2 (ja)
CN (2) CN116884928A (ja)
SG (1) SG11201901194SA (ja)
WO (1) WO2018031995A1 (ja)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
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