CN109844938B - 具有增强性能的晶片级封装 - Google Patents
具有增强性能的晶片级封装 Download PDFInfo
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- CN109844938B CN109844938B CN201780063121.2A CN201780063121A CN109844938B CN 109844938 B CN109844938 B CN 109844938B CN 201780063121 A CN201780063121 A CN 201780063121A CN 109844938 B CN109844938 B CN 109844938B
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- 150000001875 compounds Chemical class 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 64
- 229910052710 silicon Inorganic materials 0.000 claims description 64
- 239000010703 silicon Substances 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 3
- 239000003365 glass fiber Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000012858 packaging process Methods 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 169
- 230000008569 process Effects 0.000 description 42
- UDQTXCHQKHIQMH-KYGLGHNPSA-N (3ar,5s,6s,7r,7ar)-5-(difluoromethyl)-2-(ethylamino)-5,6,7,7a-tetrahydro-3ah-pyrano[3,2-d][1,3]thiazole-6,7-diol Chemical compound S1C(NCC)=N[C@H]2[C@@H]1O[C@H](C(F)F)[C@@H](O)[C@@H]2O UDQTXCHQKHIQMH-KYGLGHNPSA-N 0.000 description 25
- 229940125936 compound 42 Drugs 0.000 description 25
- STPKWKPURVSAJF-LJEWAXOPSA-N (4r,5r)-5-[4-[[4-(1-aza-4-azoniabicyclo[2.2.2]octan-4-ylmethyl)phenyl]methoxy]phenyl]-3,3-dibutyl-7-(dimethylamino)-1,1-dioxo-4,5-dihydro-2h-1$l^{6}-benzothiepin-4-ol Chemical compound O[C@H]1C(CCCC)(CCCC)CS(=O)(=O)C2=CC=C(N(C)C)C=C2[C@H]1C(C=C1)=CC=C1OCC(C=C1)=CC=C1C[N+]1(CC2)CCN2CC1 STPKWKPURVSAJF-LJEWAXOPSA-N 0.000 description 24
- 239000012790 adhesive layer Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 16
- 238000000465 moulding Methods 0.000 description 14
- 239000002243 precursor Substances 0.000 description 12
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000748 compression moulding Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- OIPILFWXSMYKGL-UHFFFAOYSA-N acetylcholine Chemical compound CC(=O)OCC[N+](C)(C)C OIPILFWXSMYKGL-UHFFFAOYSA-N 0.000 description 3
- 229960004373 acetylcholine Drugs 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19011—Structure including integrated passive components
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
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Abstract
本公开涉及一种用于增强晶片级封装的热性能和电气性能的封装工艺。具有增强性能的所述晶片级封装包括具有第一装置层(20)的第一薄化裸片(14)、多层再分布结构(52)、第一模化合物(42)以及第二模化合物(74)。所述多层再分布结构包括在所述多层再分布结构的底部表面上的多个封装触点,和将所述第一装置层连接到所述封装触点的再分布互连件。所述第一模化合物驻留在所述多层再分布结构上方并且围绕所述第一薄化裸片,并且延伸超出所述第一薄化裸片的顶部表面以限定在所述第一模化合物内并且在所述第一薄化裸片上方的空腔(66)。所述第二模化合物填充所述空腔,并且与所述第一薄化裸片的所述顶部表面接触。
Description
相关申请
本申请要求2016年8月12日提交的临时专利申请序号62/374,318、2016年8月12日提交的临时专利申请序号62/374,332和2016年8月12日提交的临时专利申请序号62/374,439的权益,所述临时专利申请的公开内容特此以全文引用的方式并入本文中。
技术领域
本公开涉及一种封装工艺,并且更特别地,涉及一种用于提供具有增强的热性能和电气性能的晶片级封装的封装工艺。
背景技术
蜂窝装置和无线装置的广泛利用推动射频(RF)技术的快速发展。制造RF装置所在的衬底在实现RF技术中的高水平性能中起到重要作用。在常规硅衬底上制造RF装置可以从硅材料的低成本、大容量晶片生产、稳固的半导体设计工具以及稳固的半导体制造技术受益。
不管将常规硅衬底用于RF装置制造的益处如何,业内熟知的是,常规硅衬底对于RF装置可以具有两个不良性质:谐波失真和低电阻率值。谐波失真是在建造在硅衬底上方的RF装置中实现高水平线性度的关键障碍。另外,硅衬底中所遇到的低电阻率可以使微机电系统(MEMS)或其他无源部件在高频率下的品质因数(Q)降级。
此外,高速和高性能晶体管被更密集地集成在RF装置中。因此,RF装置产生的热的量将由于集成在RF装置中的大量晶体管、通过晶体管的大量电力和晶体管的高操作速度而显著地增加。因此,需要以达成更好散热的配置来封装RF装置。
晶片级扇出(WLFO)封装技术和嵌入式晶片级球栅阵列(EWLB)技术目前吸引了便携式RF应用中的大部分注意力。WLFO和EWLB技术被设计成在不增大封装大小的情况下提供高密度输入/输出端口。晶片上的I/O垫大小仍然很小,从而将裸片大小保持最小。这种能力允许在单个晶片内密集地封装RF装置。
为了适应RF装置的增加发热,为了减少RF装置的有害谐波失真,并且为了利用WLFO/EWLB封装技术的优点,本公开的目标因此是提供具有增强性能的改进封装设计。此外,还需要在不增大封装大小的情况下增强RF装置的性能。
发明内容
本公开涉及一种用于提供具有增强的热性能和电气性能的晶片级封装的封装工艺。根据示例性工艺,提供具有第一裸片和第一模化合物的模晶片。在本文中,所述第一裸片包括第一装置层、在所述第一装置层上方的第一介电层和在所述第一介电层上方的第一硅衬底。所述第一装置层包括在所述第一装置层的底部表面处的许多第一裸片触点。所述第一裸片的顶部表面是所述第一硅衬底的顶部表面,并且所述第一裸片的底部表面是所述第一装置层的所述底部表面。所述第一模化合物包封所述第一裸片的侧面和所述顶部表面,使得所述第一装置层的所述底部表面暴露。接下来,在所述模晶片下面形成多层再分布结构。所述多层再分布结构包括在所述多层再分布结构的底部表面上的许多封装触点,和将所述封装触点连接到所述第一裸片触点中的特定第一裸片触点的再分布互连件。每个封装触点是分开的并且被连续气隙包围,所述连续气隙在所述第一裸片下面延伸。所述再分布互连件与所述第一裸片触点之间的连接不含焊料。然后,形成具有平面化的底部表面的介电层以填充所述连续气隙。在所述介电层形成之后,使所述第一模化合物变薄,以暴露所述第一硅衬底的所述顶部表面。接下来,大体上移除所述第一裸片的所述第一硅衬底,以提供第一薄化裸片并且形成在所述第一模化合物内并且在所述第一薄化裸片上方的空腔。所述第一薄化裸片的顶部表面在所述空腔的底部处暴露。最后,涂覆第二模化合物,以大体上填充所述空腔并且直接接触所述第一薄化裸片的所述顶部表面。
在所述示例性工艺的一个实施方案中,所述第一裸片提供微机电系统(MEMS)部件。
在所述示例性工艺的一个实施方案中,所述第一裸片由绝缘体上硅(SOI)结构形成。所述第一裸片的所述第一装置层由所述SOI结构的硅外延层形成,所述第一裸片的所述第一介电层是所述SOI结构的埋入氧化物层,并且所述第一裸片的所述第一硅衬底是所述SOI结构的硅衬底。
在所述示例性工艺的一个实施方案中,所述模晶片还包括第二完整裸片,所述第二完整裸片包括第二装置层和在所述第二装置层上方的第二硅衬底。在本文中,所述第二裸片的顶部表面是所述第二硅衬底的顶部表面,并且所述第二裸片的底部表面是所述第二装置层的底部表面。所述第一裸片比所述第二裸片高。所述第一模化合物包封所述第二裸片的侧面和所述顶部表面,使得所述第二装置层的底部表面暴露。
在所述示例性工艺的一个实施方案中,所述第一裸片提供MEMS部件,并且所述第二完整裸片提供控制所述MEMS部件的互补金属氧化物半导体(CMOS)控制器。
在所述示例性工艺的一个实施方案中,所述第二模化合物具有大于2W/m·K的热导率。
在所述示例性工艺的一个实施方案中,所述第二模化合物具有大于1E6欧姆-厘米的电阻率。
在所述示例性工艺的一个实施方案中,所述第一模化合物与所述第二模化合物由相同材料形成。
在所述示例性工艺的一个实施方案中,所述第一模化合物与所述第二模化合物由不同材料形成。
在所述示例性工艺的一个实施方案中,在所述空腔的所述底部处暴露的所述第一薄化裸片的所述顶部表面是所述第一介电层的顶部表面。
在所述示例性工艺的一个实施方案中,所述多层再分布结构不含玻璃纤维。
根据另一实施方案,所述示例性工艺还包括在涂覆所述第二模化合物之前,经由粘合材料将所述介电层的所述底部表面附接到刚性载体,和在涂覆所述第二模化合物之后,从所述介电层脱离所述刚性载体。
在所述示例性工艺的一个实施方案中,所述介电层包封每个封装触点,并且所述示例性工艺还包括在涂覆所述第二模化合物之后移除所述介电层,以暴露所述封装触点。
在所述示例性工艺的一个实施方案中,所述介电层包封每个封装触点的侧面,并且所述介电层的所述底部表面与每个封装触点的底部表面处于同一个平面中。所述示例性工艺还包括在涂覆所述第二模化合物之后,直接在每个封装触点的底部表面上方形成凸块。可选地,所述示例性工艺还包括在涂覆所述第二模化合物之后移除所述介电层的至少一部分,使得每个封装触点的侧面的至少多个部分暴露。
在所述示例性工艺的一个实施方案中,所述介电层包封每个封装触点的侧面,并且垂直地延伸超出每个封装触点的底部表面。在本文中,所述介电层在至少70%的所述第一裸片下面延伸。所述示例性工艺还包括形成许多外部触点。每个外部触点经由所述介电层与对应的封装触点接触,并且在所述介电层下面延伸。
在所述示例性工艺的一个实施方案中,通过在载体上方涂覆粘合层来提供所述模晶片。接下来,将所述第一裸片附接到所述粘合层,使得所述第一装置层的所述底部表面处的所述第一裸片触点被所述粘合层覆盖。然后,在所述粘合层上方涂覆所述第一模化合物,以包封所述第一裸片。最后,移除所述载体和所述粘合层,以暴露所述第一装置层的所述底部表面。
所属领域的技术人员在结合随附图式阅读优选实施方案的以下详细描述之后会了解本公开的范围并且了解本公开的额外方面。
附图说明
并入本说明书中并且形成本说明书的一部分的随附图式图示了本公开的几个方面,并且与描述一起用于解释本公开的原理。
图1至图8图示根据本公开的一个实施方案的用于提供前体封装的示例性步骤。
图9提供图示用于从图8中示出的前体封装提供具有增强性能的晶片级封装的示例性工艺的流程图。
图10A至图20图示与图9的过程相关联的步骤。
将理解,为说明清楚起见,图1至图20可以不按比例绘制。
具体实施方式
下文所陈述的实施方案表示使所属领域的技术人员能够实践所述实施方案的必要信息,并且说明实践所述实施方案的最佳模式。在阅读根据随附图式的以下描述之后,所属领域的技术人员将理解本公开的概念,并且将认识到本文中未特别说明的这些概念的应用。应当理解,这些概念和应用在本公开和随附权利要求的范围内。
将理解,尽管在本文中可以使用术语第一、第二等来描述各种元件,但是这些元件不应受这些术语限制。这些术语仅用于区分一个元件与另一个元件。举例来说,在不背离本公开的范围的情况下,第一元件可以被称为第二元件,类似地,第二元件可以被称为第一元件。如本文中所使用,术语“和/或”包括相关联的列出项目中的一个或多个中的任一者和全部组合。
将理解,当例如层、区域或衬底的元件被称为“在另一元件上”或延伸“到另一元件上”时,所述元件能够直接在另一元件上或直接延伸到另一元件上,或也可以存在介入元件。相比而言,当元件被称为“直接在另一元件上”或“直接延伸到另一元件上”时,不存在介入元件。同样地,将理解,当例如层、区域或衬底的元件被称为“在另一元件上方”或“在另一元件上方”延伸时,所述元件能够直接在另一元件上方或直接在另一元件上方延伸,或也可以存在介入元件。相比而言,当元件被称为“直接在另一元件上方”或“直接在另一元件上方”延伸时,不存在介入元件。还将理解,当元件被称为“连接”或“耦合”到另一元件时,所述元件能够直接连接或耦合到另一元件,或可以存在介入元件。相比而言,当元件被称为“直接连接”或“直接耦合”到另一元件时,不存在介入元件。
在本文中可以使用例如“在……下方”或“在……之上”或“上部”或“下部”或“水平”或“垂直”的相对术语来描述如诸图所示的一个元件、层或区域与另一元件、层或区域的关系。将理解,这些术语和上文讨论的术语意图涵盖除了诸图中所描绘的定向以外的装置的不同定向。
本文中所使用的术语仅用于描述特定实施方案的目的,而不是意图作为对本公开的限制。如本文中所使用,单数形式“一”和“所述”意图也包括复数形式,除非上下文另有明确指示。还将理解,术语“包括”在于本文中使用时规定一定特征、整体、步骤、操作、元件和/或部件的存在,但是不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群的存在或添加。
除非另外规定,否则本文中所使用的所有术语(包括技术术语和科学术语)的意义与本公开所属的领域的普通技术人员通常所理解的意义相同。还将理解,本文中所使用的术语应被解译为具有与所述术语在本说明书和相关领域的背景中的意义一致的意义,而不是从理想化或过于正式的意义上解译,除非本文中明确地如此规定。
本公开涉及一种用于提供具有增强的热性能和电气性能的晶片级封装的封装工艺。图1至图8图示根据本公开的一个实施方案的用于提供前体封装的示例性步骤。尽管所述示例性步骤是顺序地说明,但是所述示例性步骤未必是依序的。一些步骤可以用不同于所呈现的次序的次序进行。此外,在本公开的范围内的工艺可以包括比图1至图8所示的步骤少或多的步骤。
最初,在载体12的顶部表面上涂覆粘合层10,如图1所示。然后,将绝缘体上硅(SOI)裸片14、微机电系统(MEMS)裸片16和互补金属氧化物半导体(CMOS)控制器裸片18附接到粘合层10,如图2所示。在不同应用中,可以有更少或更多的裸片附接到粘合层10。举例来说,在一些应用中,仅SOI裸片14可以附接到粘合层10;在一些应用中,仅MEMS裸片16和CMOS控制器裸片18可以附接到粘合层10,而在一些应用中,除了MEMS裸片/SOI裸片之外,薄化的集成式无源装置裸片(未示出)也可以附接到粘合层10。
SOI裸片14包括第一装置层20、在第一装置层20的顶部表面上方的第一介电层22和在第一介电层22上方的第一硅衬底24。因而,第一装置层20的底部表面是SOI裸片14的底部表面,并且第一硅衬底24的背面是SOI裸片14的顶部表面。第一装置层20包括在第一装置层20的底部表面处的许多第一裸片触点26。在本文中,SOI裸片14由SOI结构形成,所述SOI结构是指包括硅衬底、硅外延层和夹在所述硅衬底与所述硅外延层之间的埋入氧化物层的结构。SOI裸片14的第一装置层20是通过在所述SOI结构的所述硅外延层中或上集成电子部件(未示出)来形成。SOI裸片14的第一介电层22是所述SOI结构的所述埋入氧化物层。SOI裸片14的第一硅衬底24是所述SOI结构的所述硅衬底。第一装置层20具有介于0.1μm与50μm之间的厚度,并且第一介电层22具有介于10nm与2000nm之间的厚度。另外,分别地,SOI裸片14具有介于25μm与250μm之间或介于10μm与750μm之间的厚度,并且第一硅衬底24具有介于25μm与250μm之间或介于10μm与750μm之间的厚度。
MEMS裸片16包括第二装置层28、在第二装置层28的顶部表面上方的第二介电层30和在第二介电层30上方的第二硅衬底32。因而,第二装置层28的底部表面是MEMS裸片16的底部表面,并且第二硅衬底32的背面是MEMS裸片16的顶部表面。第二装置层28包括通常是开关的MEMS部件(未示出),和在第二装置层28的底部表面上的许多第二裸片触点34。过孔结构(未示出)可以用于将MEMS部件(未示出)连接到第二裸片触点34。第二装置层28具有介于0.5μm与100μm之间的厚度,并且可以由介电层与金属层(例如氧化硅、氮化硅、铝、钛、铜或类似物)的组合形成。第二介电层30具有介于10nm与10000nm之间的厚度,并且可以由氧化硅、氮化硅、氧化铝或氮化铝形成。另外,分别地,MEMS裸片16具有介于25μm与300μm之间或介于10μm与800μm之间的厚度,并且第二硅衬底32具有介于25μm与300μm之间或介于10μm与800μm之间的厚度。
CMOS控制器裸片18包括第三装置层36和在第三装置层36上方的第三硅衬底38。第三装置层36的底部表面是CMOS控制器裸片18的底部表面,并且第三硅衬底38的背面是CMOS控制器裸片18的顶部表面。第三装置层36可以包括控制薄化MEMS裸片14内的MEMS部件的CMOS控制器(未示出),和在第三装置层36的底部表面处的许多第三裸片许多第三裸片触点40。过孔结构(未示出)可以用于将CMOS控制器(未示出)连接到第三裸片触点40。第三装置层36具有介于0.1μm与50μm之间的厚度,并且可以由介电层与金属层(例如氧化硅、氮化硅、铝、钛、铜或类似物)的组合形成。另外,分别地,CMOS控制器裸片18具有介于25μm与250μm之间或介于10μm与750μm之间的厚度,并且第三硅衬底38具有介于25μm与250μm之间或介于10μm与750μm之间的厚度。在这个实施方案中,CMOS控制器裸片18可以比SOI裸片14及MEMS裸片16短。在不同应用中,CMOS控制器裸片18可以与SOI裸片14或MEMS裸片16具有相同高度,或CMOS控制器裸片18可以比SOI裸片14和MEMS裸片16高。
接下来,在粘合层10上方涂覆第一模化合物42,以包封SOI裸片14、MEMS裸片16和CMOS控制器裸片18,如图3所示。第一模化合物42可以是有机环氧树脂系统或类似材料,所述第一模化合物能够被用作保护SOI裸片14、MEMS裸片16和CMOS控制器裸片18免受例如氢氧化钾(KOH)、氢氧化钠(NaOH)和乙酰胆碱(ACH)的蚀刻化学品侵害的蚀刻剂屏障。可以通过各种程序来涂覆第一模化合物42,所述程序例如片状成型、包覆成型、压缩成型、传递成型、坝填充包封或丝网印刷包封。在典型的压缩成型中,用于涂覆第一模化合物42的成型压力介于100psi与1000psi之间。由于SOI裸片14、MEMS裸片16和CMOS控制器裸片18相对较厚,并且SOI裸片14、MEMS裸片16和CMOS控制器裸片18的底部表面是基本上平坦的,因此在这个成型步骤期间,SOI裸片14、MEMS裸片16或CMOS控制器裸片18可以不发生垂直变形。
然后使用固化工艺(未示出)以使第一模化合物42硬化。视被用作第一模化合物42的材料而定,固化温度介于100℃与320℃之间。然后移除粘合层10和载体12,以暴露第一装置层20的底部表面、第二装置层28的底部表面和第三装置层36的底部表面,如图4所示。可以通过加热粘合层10或将粘合层10曝露于紫外线或激光来提供粘合层10和载体12的移除。
参考图5至图8,根据本公开的一个实施方案提供一种再分布工艺。首先在SOI裸片14、MEMS裸片16和CMOS控制器裸片18下面形成第一介电图案44,如图5所示。因而,SOI裸片14的第一装置层20、MEMS裸片16的第二装置层28和CMOS控制器裸片18的第三装置层36与第一介电图案44接触。另外,在第一装置层20的底部表面处的第一裸片触点26、在第二装置层28的底部表面处的第二裸片触点34和在第三装置层36的底部表面处的第三裸片触点40经由第一介电图案44暴露。
接下来,形成许多再分布互连件46,如图6所示。出于说明目的,再分布互连件46包括五个第一再分布互连件46(1)和一个第二再分布互连件46(2)。在不同应用中,再分布互连件46可以包括更少或更多的第一再分布互连件46(1)/第二再分布互连件46(2)。每个第一再分布互连件46(1)经由第一介电图案44电耦合到第一、第二和第三裸片触点26、34和40中的对应裸片触点,并且在第一介电图案44下面延伸。第二再分布互连件46(2)被用于将一个第二裸片触点34连接到对应的第三裸片触点40,使得CMOS控制器裸片18内的CMOS控制器电连接薄化MEMS裸片16内的MEMS部件。第二再分布互连件46(2)也可以在第一介电图案44下面延伸。再分布互连件46与第一、第二和第三裸片触点26、34和40之间的连接不含焊料。
在第一介电图案44下面形成第二介电图案48,以部分地包封每个第一再分布互连件46(1),如图7所示。因而,每个第一再分布互连件46(1)的一部分通过第二介电图案48暴露。此外,第二介电图案48完全包封第二再分布互连件46(2)。因而,第二再分布互连件46(2)没有部分通过第二介电图案48暴露。在不同应用中,可以存在经由第二介电图案48电耦合到再分布互连件46的额外再分布互连件(未示出),和用于部分地包封所述额外再分布互连件中的每一个的在第二介电图案48下面形成的额外介电图案(未示出)。
最后,形成许多封装触点50,以使多层再分布结构52完整并且提供前体封装54,如图8所示。每个封装触点50在多层再分布结构52的底部表面上,并且经由第二介电图案48电耦合到对应第一再分布互连件46(1)的暴露部分。因此,第一再分布互连件46(1)将封装触点50连接到第一、第二和第三裸片触点26、34和40中的特定裸片触点。另外,封装触点50彼此分开并且在第二介电图案48下面延伸,使得同时地形成围绕每个封装触点50的连续气隙56。气隙56可以在SOI裸片14下面和/或在MEMS裸片16下面延伸。
多层再分布结构52可以不含玻璃纤维或不含玻璃。在本文中,玻璃纤维是指经过缠绕会变成较大分组的个别玻璃原丝。这些玻璃原丝接着可以被编织成织物。第一介电图案44和第二介电图案48可以由苯并环丁烯(BCB)、聚酰亚胺或其他介电材料形成。再分布互连件46可以由铜或其他合适的金属形成。封装触点50可以由铜、金、镍以及钯中的至少一种形成。多层再分布结构52具有介于2μm与300μm之间的厚度。
图9提供图示用于从图8所示的前体封装54提供具有增强性能的晶片级封装的示例性工艺的流程图。图10A至图20图示与图9的过程相关联的步骤。尽管所述流程图和所述相关联步骤是顺序地说明,但是所述流程图和所述相关联步骤未必是依序的。一些步骤可以用不同于所呈现的次序的次序进行。此外,在本公开的范围内的工艺可以包括比图9所示的步骤少或多的步骤。
首先,在多层再分布结构52的底部表面处形成第三介电层58,如图10A至图10D所示(步骤100)。在一些应用中,第三介电层58可以不残留在最终的晶片级封装中。因而,封装触点50不需要通过第三介电层58暴露,如图10A所示。第三介电层58完全填充包围每个封装触点50的气隙56,包封每个封装触点50,并且提供基本上平面化的底部表面。可以通过对电介质进行旋涂、层压、沉积或成型来形成第三介电层58以包封每个封装触点50,并且接着对第三介电层58进行抛光以实现基本上平面化的表面。
为了利于在稍后处理步骤中容易移除第三介电层58(更多细节在随后的讨论中),可以在多层再分布结构52与第三介电层58之间形成钝化层60,如图10B所示。钝化层60至少覆盖第二介电图案48的已暴露底部表面部分,以在第三介电层58的稍后移除期间保护第一和第二介电图案44和48。在一个实施方案中,可以在涂覆第三介电层58之前通过将蚀刻方式不同于第三介电层58的氮化硅、氮化铝或其他金属或介电膜沉积到气隙56内的第二介电图案48的已暴露底部表面部分来形成钝化层60。钝化层60未垂直地超出封装触点50,并且具有介于5nm与5000nm之间的厚度。在另一实施方案中,钝化层60可以是封装触点50的种子层,所述钝化层在封装触点50之前形成,并且与封装触点50可以由相同或不同材料形成(但是薄到不超过从第二介电图案48的底部表面突出的封装触点50的厚度的10分之一)。在本文中,钝化层60可以在第二介电图案48的整个底部表面上方延伸,并且可以夹在第二介电图案48与封装触点50之间(未示出)。
在一些应用中,第三介电层58的至少一部分可以残留在最终的晶片级封装中。因而,每个封装触点50需要通过第三介电层58暴露。在本文中,第三介电层58完全填充气隙56并且包封每个封装触点50的侧面,如图10C所示。第三介电层58的底部表面与每个封装触点50的底部表面处于同一个平面中。可以通过对电介质进行旋涂、层压、沉积或成型来形成第三介电层58以包封每个封装触点50,并且接着进行薄化步骤(例如化学机械平面化或蚀刻技术)以暴露每个封装触点50的底部表面。
另外,当气隙56在至少70%的SOI裸片14下面延伸和/或在至少70%的MEMS裸片16下面延伸时,第三介电层58可以包封每个封装触点50的侧面,完全填充气隙56,并且垂直地延伸超出每个封装触点50的底部表面,如图10D所示。由于第三介电层58可以垂直地延伸超出每个封装触点50的底部表面,因此许多独立的空气开口62在每个封装触点50正下方同时形成。每个封装触点50可以具有相同或不同的大小,并且可以具有相同或不同的形状,例如正方形、矩形、三角形以及圆形。因此,每个空气开口62可以具有相同或不同的大小,并且可以具有相同或不同的形状,例如正方形、矩形、三角形以及圆形。如果不存在位于SOI裸片14和MEMS裸片16正下方的封装触点50,则不会存在位于SOI裸片14和MEMS裸片16正下方的空气开口62。每个空气开口62具有介于25μm×25μm与400μm×400μm之间的大小,并且与气隙56相比要小得多。每个空气开口62的深度被减到最小以致于尽可能地接近零。在本文中,第三介电层58具有基本上平面化的底部表面,并且每个封装触点50通过第三介电层58暴露。可以通过对电介质进行旋涂、层压、沉积或成型来形成第三介电层58,并且可以接着进行抛光以实现基本上平面化的表面。对于图10A至图10D,第三介电层58可以由BCB、聚酰亚胺或其他介电材料(如UV敏感材料)形成。第三介电层58与第二介电图案48可以由相同或不同的材料形成。
在第三介电层58形成之后,使第一模化合物42变薄,以暴露SOI裸片14的第一硅衬底24和MEMS裸片16的第二硅衬底32,如图11所示(步骤102)。在本文中,图11是从图10A衍生,相同的薄化程序也可以应用于图10B至图10D(为简单起见未示出)。薄化程序可以用机械研磨工艺来进行。在本文中,CMOS控制器裸片18具有比MEMS裸片16和SOI裸片14两者低的高度,使得CMOS控制器裸片18的硅衬底38不被暴露,而是仍被第一模化合物42包封。
接下来,大体上移除第一硅衬底24和第二硅衬底32,以提供蚀刻后前体封装64,如图12所示(步骤104)。从SOI裸片14移除第一硅衬底24提供薄化SOI裸片14T,并且形成在第一模化合物42内并且在薄化SOI裸片14T上方的第一空腔66。从MEMS裸片16移除第二硅衬底32提供薄化MEMS裸片16T,并且形成在第一模化合物42内并且在薄化MEMS裸片16T上方的第二空腔68。在本文中,大体上移除硅衬底是指移除整个硅衬底的至少95%并且留下至多2μm硅衬底。在所需情况下,完全移除第一和第二硅衬底24和32,使得薄化SOI裸片14T的第一介电层22在第一空腔66的底部处暴露,并且薄化MEMS裸片16T的第二介电层30在第二空腔68的底部处暴露。
可以通过利用湿/干蚀刻剂化学品的蚀刻工艺来提供大体上移除第一和第二硅衬底24和32,所述蚀刻剂化学品可以是TMAH、KOH、ACH、NaOH或类似物。第一介电层22充当蚀刻终止层以保护薄化SOI裸片14T的第一装置层20,并且第二介电层30充当蚀刻终止层以保护薄化MEMS裸片16T的第二装置层28。第一模化合物42包封CMOS控制器裸片18并且保护CMOS控制器裸片18免受湿/干蚀刻剂化学品损害。在一些应用中,保护层(未示出)可以放置在第三介电层58的底部表面处,以保护第三介电层58和/或封装触点50免受蚀刻剂化学品损害(在封装触点50通过第三介电层58暴露的情况下,如图10C和10D所示)。在蚀刻工艺之前涂覆所述保护层,并且在蚀刻工艺之后移除所述保护层。此外,如果CMOS控制器裸片18的硅衬底38未被第一模化合物42包封(在一些应用中,如果CMOS控制器裸片18与SOI裸片14和MEMS裸片16具有相同高度,或比SOI裸片14和MEMS裸片16高,则CMOS控制器裸片18的硅衬底38会在薄化过程期间暴露),则可以在硅衬底38上方放置额外保护层(未示出),以保护CMOS控制器裸片18免受蚀刻剂化学品损害。在蚀刻工艺之前涂覆所述额外保护层,并且在蚀刻工艺之后移除所述额外保护层。
可以经由粘合材料72将蚀刻后前体封装64附接到刚性载体70,如图13所示(步骤106)。刚性载体70可以是光透射型的,并且由石英、熔融硅石或蓝宝石形成。粘合材料72可以是UV敏感胶带或膜。如果第三介电层58包封封装触点50或垂直地延伸超出每个封装触点50的底部表面(如图10A、图10B和图10D所示),则第三介电层58的平面化的底部表面与粘合材料72接触。如果第三介电层58的底部表面与每个封装触点50的底部表面处于同一个平面中(如图10C所示),则第三介电层58和封装触点50均与粘合材料72接触(未示出)。刚性载体70可以帮助辅助对蚀刻后前体封装64的机械支撑。在一些应用中,蚀刻后前体封装64不可附接到刚性载体70,并且刚性载体70不被用于随后的制造步骤中。
然后涂覆第二模化合物74,以基本上填充第一和第二空腔66和68,如图14所示(步骤108)。在本文中,大体上填充空腔是指填充整个空腔的至少75%。第二模化合物74直接驻留在在薄化SOI裸片14T的顶部表面和薄化MEMS裸片16T的顶部表面上方。如果没有第一硅衬底24留在第一空腔66中并且没有第二硅衬底32留在第二空腔68中,则第二模化合物74直接驻留在第一介电层22和第二介电层30上方。在一些情况下,第二模化合物74的一部分还可以驻留在第一模化合物42上方。通过第一模化合物42将第二模化合物74与CMOS控制器裸片18分开。CMOS控制器裸片18的顶部表面与第一模化合物42接触。
第二模化合物74具有大于2W/m·K或大于10W/m·K的热导率,并且具有大于1E6欧姆-厘米的电阻率。一般来说,第二模化合物74的热导率越高,薄化SOI裸片14T和薄化MEMS裸片16T的热性能越好。此外,第二模化合物74的高电阻率可以提高薄化MEMS裸片16T的MEMS部件(未示出)在高频率下的品质因数(Q),并且可以减少薄化SOI裸片14T中的损耗。
第二模化合物74可以由热塑性或热固性材料形成,所述材料例如PPS(聚苯硫醚)、掺杂了氮化硼或氧化铝热添加剂的包覆成型环氧物或类似材料。在一些应用中,蚀刻后前体封装64可以仅包括MEMS裸片16和CMOS控制器裸片18。第二模化合物74也可以由热导率小于2W/m·K的有机环氧树脂体系形成。第二模化合物74可以与第一模化合物42由相同或不同材料形成。然而,不同于第二模化合物74,第一模化合物42没有热导率或电阻率要求。在一些应用中,第一模化合物42和第二模化合物74均具有大于2W/m·K的热导率。在一些应用中,第一模化合物42具有小于2W/m·K的热导率,并且第二模化合物74具有大于2W/m·K的热导率。在一些应用中,第一模化合物42具有大于2W/m·K的热导率,并且第二模化合物74具有大于10W/m·K的热导率。
可以通过各种程序来涂覆第二模化合物74,所述程序例如片状成型、包覆成型、压缩成型、传递成型、坝填充包封以及丝网印刷包封。在第二模化合物74的成型过程期间,液化和成型压力在整个蚀刻后前体封装64上可能不均匀。薄化SOI裸片14T与直接在薄化的玻璃为主裸片14T下面的多层再分布结构52的第一部分的第一组合,和薄化MEMS裸片16T与直接在薄化MEMS裸片16T下面的多层再分布结构52的第二部分的第二组合可以比蚀刻后前体封装64的其他部分经历更大的成型压力。在典型的压缩成型中,如果第二模化合物74由高热导率材料(>=2W/m·K)形成,则用于涂覆第二模化合物74的成型压力和温度分别介于250psi与1000psi之间,和介于100℃与350℃之间。
请注意,薄化SOI裸片14T具有介于0.1μm与50μm之间的厚度,薄化MEMS裸片16T具有介于0.5μm与100μm之间的厚度,并且多层再分布结构52具有介于2μm与300μm之间的厚度。因而,薄化SOI裸片14T与多层再分布结构52的第一部分的第一组合,或薄化MEMS裸片16T与多层再分布结构52的第二部分的第二组合可以具有几μm薄的厚度。如果不存在填充气隙56、尤其是位于薄化SOI裸片14T正下方和/或位于薄化MEMS裸片16T正下方的气隙56的多个部分的第三介电层58,则所述第一组合的垂直变形和/或所述第二组合的垂直变形可以在成型步骤期间发生。在位于薄化SOI裸片14T正下方和/或位于薄化MEMS裸片16T正下方的气隙56的多个部分中没有额外支撑件的情况下,所述第一组合和所述第二组合不能承受高垂直成型压力。
在一个实施方案中,当第三介电层58完全填充气隙56,包封每个封装触点50,并且提供平面化的底部表面时(如图10A和图10B所示),在多层再分布结构52下不存在气隙。因而,与刚性载体70组合的第三介电层58可以为薄化SOI裸片14T和薄化MEMS裸片16T提供足够的机械支撑,从而承受高成型压力。薄化SOI裸片14T和薄化MEMS裸片16T的垂直变形可以减小到可接受的水平。
在另一实施方案中,当第三介电层58完全填充气隙56,包封每个封装触点50的侧面,并且具有与每个封装触点50的底部表面在同一个平面中的底部表面时(如图10C所示),在多层再分布结构52下不存在气隙。因而,与刚性载体70(未示出)组合的第三介电层58可以为薄化SOI裸片14T和薄化MEMS裸片16T提供足够的机械支撑,从而承受高成型压力。薄化SOI裸片14T和薄化MEMS裸片16T的垂直变形可以减小到可接受的水平。
另外,当第三介电层58完全填充气隙56,包封每个封装触点50的侧面,并且垂直地延伸超出每个封装触点50的底部表面时(如图10D所示),有许多空气开口62在每个封装触点50正下方形成。由于每个空气开口62与气隙56相比小得多,并且可以不位于薄化SOI裸片14T和薄化MEMS裸片16T正下方,因此空气开口62可以引起比未填充气隙56明显较少的薄化SOI裸片14T和薄化MEMS裸片16T的垂直变形。第三介电层58在至少70%的薄化SOI裸片14T下面延伸和/或在至少70%的薄化MEMS裸片16T下面延伸(因为气隙56在至少70%的薄化SOI裸片14T下面延伸和/或在至少70%的薄化MEMS裸片16T下面延伸,并且第三介电层58完全填充气隙56)。因而,与刚性载体70(未示出)组合的第三介电层58可以为薄化SOI裸片14T和薄化MEMS裸片16T提供足够的机械支撑,从而承受高成型压力。此外,可以存在位于第一模化合物42正下方和/或位于CMOS控制器裸片16正下方的一些空气开口62。由于第一模化合物42和CMOS控制器裸片16相对较厚,并且空气开口62具有相同大小(不超过400μm×400μm),因此第一模化合物42和/或CMOS控制器裸片16足够刚性以承受高成型压力。
接着进行固化工艺(未示出)以使第二模化合物74硬化(步骤110)。视被用作第二模化合物74的材料而定,固化温度介于100℃与320℃之间。然后对第二模化合物74的顶部表面进行平面化,如图15所示(步骤112)。如果第二模化合物74不覆盖第一模化合物42的顶部表面,则将第二模化合物74和/或第一模化合物42的顶部表面平面化成共平面的(未示出)。可以将机械研磨工艺用于平面化。
图16A至图16D(步骤114)图示在将刚性载体70脱离之后,第三介电层58暴露。图16A至图16D是分别从图10A至图10D衍生。如果刚性载体70是光透射型刚性载体并且粘合材料72是UV敏感膜或带,则将刚性载体70曝露到UV环境以实现脱离过程。
在脱离过程之后,封装触点50可以被第三介电层58完全包封(在图16A和图16B中示出)。为了完成具有增强性能的晶片级封装76,移除第三层58和钝化层60(如果存在),如图17所示(步骤116)。湿蚀刻可以用于从多层再分布结构52移除第三介电层58。如果第三介电层58与第二介电图案48之间不存在钝化层,则第三介电层58和第二介电图案48可以由具有不同蚀刻性质的不同材料形成。举例来说,第三介电层58和第二介电图案48由具有不同蚀刻性质的两种不同的聚酰亚胺材料形成。因而,可以实现在不攻击第二介电图案48的情况下选择性地蚀刻第三介电层58。如果钝化层60夹在第三介电层58与第二介电图案48之间,则第三介电层58和第二介电图案48可以由具有相同或不同蚀刻性质的材料形成。钝化层60是保护第二介电图案48的蚀刻终止层。湿或干蚀刻可以用于移除钝化层60。由于钝化层60和第二介电图案48是由具有不同蚀刻性质的不同材料形成,因此可以实现在不攻击第二介电图案48的情况下选择性地蚀刻钝化层60。另外,为了在蚀刻钝化层60时保护封装触点50,可以使用光刻技术。如果钝化层60是封装触点50的种子层,则可以不利用光刻技术来蚀刻钝化层60。封装触点50可能被攻击,但是由于钝化层60与从第二介电图案48的底部表面突出的每个封装触点50的一部分之间的大厚度差(大于10倍)而不会有明显变化。
在另一实施方案中,在脱离过程之后,每个封装触点50的底部表面可能暴露,并且与第三介电层58的底部表面在同一个平面中(在图16C中示出)。为了完成具有增强性能的晶片级封装76’,可以移除第三介电层58的至少一个部分,如图18所示(步骤116)。蚀刻技术可以用于移除第三介电层58的至少一个部分,以暴露每个封装触点50的侧面的至少多个部分。在本文中,第三介电层58和第二介电图案48可以由具有不同蚀刻性质的不同材料形成。此外,替代移除第三层58,可以直接在每个封装触点50的底部表面上方形成凸块78,以完成具有增强性能的晶片级封装76”,如图19所示(步骤116)。因此,每个凸块78电耦合到第一、第二和第三裸片触点26、34和40中的对应裸片触点。每个凸块78可以通过标准凸块化程序由例如锡或锡合金的焊料合金形成。
另外,在蚀刻工艺之后,每个封装触点50的底部表面可以通过第三介电层58暴露,所述第三介电层垂直地超出每个封装触点50的底部表面(在图16D中示出)。可以通过形成许多外部触点80来使晶片级封装76”’完整,如图20所示(步骤116)。每个外部触点80经由第三介电层58与对应的封装触点50接触,并且在第三介电层58下面延伸。因此,每个外部触点80电耦合到第一、第二和第三裸片触点26、34和40中的对应裸片触点。外部触点80可以由铜、镍、金、焊料以及其他可焊接金属中的至少一种形成。
最后,可以对晶片级封装76/76’/76”/76”’进行标记、切割,然后将晶片级封装单粒化成各个部件(步骤118)。
所属领域的技术人员将认识到对本公开的优选实施方案的改进和修改。所有这些改进和修改被视为在本文中公开的概念和随后的权利要求的范围内。
Claims (17)
1.一种制造晶片级封装的方法,所述方法包括:
提供具有第一裸片和第一模化合物的模晶片,其中:
·所述第一裸片包括第一装置层、在所述第一装置层上方的第一介电层和在所述第一介电层上方的第一硅衬底,其中所述第一装置层包括在所述第一装置层的底部表面处的多个第一裸片触点;
·所述第一裸片的顶部表面是所述第一硅衬底的顶部表面,并且所述第一裸片的底部表面是所述第一装置层的所述底部表面;并且
·所述第一模化合物包封所述第一裸片的侧面和所述顶部表面,其中所述第一装置层的所述底部表面暴露;
在所述模晶片下面形成多层再分布结构,其中:
·所述多层再分布结构包括第一介电图案、再分布互连件、第二介电图案以及多个封装触点;
·所述第一介电图案在所述第一裸片下面形成,并且所述多个第一裸片触点通过所述第一介电图案暴露;
·所述再分布互连件电联接到经由所述第一介电图案暴露的所述多个第一裸片触点,并且在所述第一介电图案下面延伸;
·所述第二介电图案在所述第一介电图案下面形成,以部分地包封每个再分布互连件;
·所述多个封装触点在所述多层再分布结构的底部表面上,其中所述再分布互连件将所述多个封装触点连接到所述多个第一裸片触点中的特定第一裸片触点;
·所述多个封装触点中的每一个是分开的并且被连续气隙包围,其中所述连续气隙在所述第一裸片下面延伸;并且
·所述再分布互连件与所述多个第一裸片触点之间的连接不含焊料;
形成支撑介电层,以填充所述连续气隙并且包封所述多个封装触点中的每一个,其中所述支撑介电层具有平面化的底部表面;
使所述第一模化合物变薄,以暴露所述第一硅衬底的所述顶部表面;
大体上移除所述第一裸片的所述第一硅衬底,以提供第一薄化裸片并且形成在所述第一模化合物内并且在所述第一薄化裸片上方的空腔,其中所述第一薄化裸片具有在所述空腔的底部处暴露的顶部表面;以及
涂覆第二模化合物,以大体上填充所述空腔并且直接接触所述第一薄化裸片的所述顶部表面。
2.如权利要求1所述的方法,其中所述第一裸片提供微机电系统(MEMS)部件。
3.如权利要求1所述的方法,其中所述第一裸片由绝缘体上硅(SOI)结构形成,其中所述第一裸片的所述第一装置层由所述SOI结构的硅外延层形成,所述第一裸片的所述第一介电层是所述SOI结构的埋入氧化物层,并且所述第一裸片的所述第一硅衬底是所述SOI结构的硅衬底。
4.如权利要求1所述的方法,其中所述模晶片还包括第二裸片,所述第二裸片包括第二装置层和在所述第二装置层上方的第二硅衬底,其中:
·所述第二裸片的顶部表面是所述第二硅衬底的顶部表面,并且所述第二裸片的底部表面是所述第二装置层的底部表面;
·所述第一裸片比所述第二裸片高;并且
·所述第一模化合物包封所述第二裸片的侧面和所述顶部表面,其中所述第二装置层的所述底部表面暴露。
5.如权利要求4所述的方法,其中所述第一裸片提供MEMS部件,并且所述第二裸片提供控制所述MEMS部件的互补金属氧化物半导体(CMOS)控制器。
6.如权利要求1所述的方法,其中所述第二模化合物具有大于2W/m·K的热导率。
7.如权利要求1所述的方法,其中所述第二模化合物具有大于1E6欧姆-厘米的电阻率。
8.如权利要求1所述的方法,其中所述第一模化合物与所述第二模化合物由相同材料形成。
9.如权利要求1所述的方法,其中所述第一模化合物与所述第二模化合物由不同材料形成。
10.如权利要求1所述的方法,其中在所述空腔的所述底部处暴露的所述第一薄化裸片的所述顶部表面是所述第一介电层的顶部表面。
11.如权利要求1所述的方法,其中所述多层再分布结构不含玻璃纤维。
12.如权利要求1所述的方法,所述方法还包括在涂覆所述第二模化合物之前,经由粘合材料将所述支撑介电层的所述平面化的底部表面附接到刚性载体。
13.如权利要求12所述的方法,所述方法还包括在涂覆所述第二模化合物之后,使所述刚性载体从所述支撑介电层脱离。
14.如权利要求1所述的方法,所述方法还包括在涂覆所述第二模化合物之后移除所述支撑介电层,以暴露所述多个封装触点。
15.一种制造晶片级封装的方法,所述方法包括:
提供具有第一裸片和第一模化合物的模晶片,其中:
·所述第一裸片包括第一装置层、在所述第一装置层上方的第一介电层和在所述第一介电层上方的第一硅衬底,其中所述第一装置层包括在所述第一装置层的底部表面处的多个第一裸片触点;
·所述第一裸片的顶部表面是所述第一硅衬底的顶部表面,并且所述第一裸片的底部表面是所述第一装置层的所述底部表面;并且
·所述第一模化合物包封所述第一裸片的侧面和所述顶部表面,其中所述第一装置层的所述底部表面暴露;
在所述模晶片下面形成多层再分布结构,其中:
·所述多层再分布结构包括第一介电图案、再分布互连件、第二介电图案以及多个封装触点;
·所述第一介电图案在所述第一裸片下面形成,并且所述多个第一裸片触点通过所述第一介电图案暴露;
·所述再分布互连件电联接到经由所述第一介电图案暴露的所述多个第一裸片触点,并且在所述第一介电图案下面延伸;
·所述第二介电图案在所述第一介电图案下面形成,以部分地包封每个再分布互连件;
·所述多个封装触点在所述多层再分布结构的底部表面上,其中所述再分布互连件将所述多个封装触点连接到所述多个第一裸片触点中的特定第一裸片触点;
·所述多个封装触点中的每一个是分开的并且被连续气隙包围,其中所述连续气隙在所述第一裸片下面延伸;并且
·所述再分布互连件与所述多个第一裸片触点之间的连接不含焊料;
形成支撑介电层,以填充所述连续气隙,其中:
·所述支撑介电层具有平面化的底部表面;
·所述支撑介电层包封所述多个封装触点中的每一个的侧面;并且
·所述支撑介电层的所述平面化的底部表面与所述多个封装触点中的每一个的底部表面处于同一个平面中;
使所述第一模化合物变薄,以暴露所述第一硅衬底的所述顶部表面;
大体上移除所述第一裸片的所述第一硅衬底,以提供第一薄化裸片并且形成在所述第一模化合物内并且在所述第一薄化裸片上方的空腔,其中所述第一薄化裸片具有在所述空腔的底部处暴露的顶部表面;
涂覆第二模化合物,以大体上填充所述空腔并且直接接触所述第一薄化裸片的所述顶部表面;以及
在涂覆所述第二模化合物之后移除所述支撑介电层的至少一部分,使得所述多个封装触点中的每一个的所述侧面的至少部分被暴露。
16.如权利要求1所述的方法,所述方法还包括在形成所述支撑介电层之前形成钝化层,所述钝化层至少覆盖在所述连续气隙内的所述第二介电图案的已暴露的底部表面部分,其中所述钝化层并不垂直地超出所述多个封装触点。
17.一种制造晶片级封装的方法,所述方法包括:
提供具有第一裸片和第一模化合物的模晶片,其中:
·所述第一裸片包括第一装置层、在所述第一装置层上方的第一介电层和在所述第一介电层上方的第一硅衬底,其中所述第一装置层包括在所述第一装置层的底部表面处的多个第一裸片触点;
·所述第一裸片的顶部表面是所述第一硅衬底的顶部表面,并且所述第一裸片的底部表面是所述第一装置层的所述底部表面;并且
·所述第一模化合物包封所述第一裸片的侧面和所述顶部表面,其中所述第一装置层的所述底部表面暴露;
在所述模晶片下面形成多层再分布结构,其中:
·所述多层再分布结构包括多个封装触点以及再分布互连件,所述多个封装触点在所述多层再分布结构的底部表面上,所述再分布互连件将所述多个封装触点连接到所述多个第一裸片触点中的特定第一裸片触点;
·所述多个封装触点中的每一个是分开的并且被连续气隙包围,其中所述连续气隙在所述第一裸片下面延伸;并且
·所述再分布互连件与所述多个第一裸片触点之间的连接不含焊料;
形成支撑介电层,以填充所述连续气隙,其中所述支撑介电层具有平面化的底部表面;
使所述第一模化合物变薄,以暴露所述第一硅衬底的所述顶部表面;
完全移除所述第一裸片的所述第一硅衬底,以提供第一薄化裸片并且形成在所述第一模化合物内并且在所述第一薄化裸片上方的空腔,其中在所述空腔的底部处暴露所述装置层的顶部表面;以及
涂覆第二模化合物,以大体上填充所述空腔并且直接接触所述第一薄化裸片的所述顶部表面。
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- 2017-08-14 CN CN201780063121.2A patent/CN109844938B/zh active Active
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- 2017-08-14 JP JP2019507768A patent/JP7037544B2/ja active Active
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Also Published As
Publication number | Publication date |
---|---|
JP2022071128A (ja) | 2022-05-13 |
US10804179B2 (en) | 2020-10-13 |
US20190057922A1 (en) | 2019-02-21 |
JP7265052B2 (ja) | 2023-04-25 |
EP3497717A1 (en) | 2019-06-19 |
WO2018031995A1 (en) | 2018-02-15 |
US10109550B2 (en) | 2018-10-23 |
JP2019525488A (ja) | 2019-09-05 |
JP7037544B2 (ja) | 2022-03-16 |
CN109844938A (zh) | 2019-06-04 |
SG11201901194SA (en) | 2019-03-28 |
CN116884928A (zh) | 2023-10-13 |
US20180047653A1 (en) | 2018-02-15 |
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