KR840000985A - 반도체 집적회로 및 그 제조방법 - Google Patents

반도체 집적회로 및 그 제조방법 Download PDF

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Publication number
KR840000985A
KR840000985A KR1019820002670A KR820002670A KR840000985A KR 840000985 A KR840000985 A KR 840000985A KR 1019820002670 A KR1019820002670 A KR 1019820002670A KR 820002670 A KR820002670 A KR 820002670A KR 840000985 A KR840000985 A KR 840000985A
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South Korea
Prior art keywords
unit cell
circuit
pattern
semiconductor integrated
bonding pads
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KR1019820002670A
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English (en)
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KR910000155B1 (ko
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요시가쯔(외 2) 다가하시
Original Assignee
미쓰다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼
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Publication of KR840000985A publication Critical patent/KR840000985A/ko
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Publication of KR910000155B1 publication Critical patent/KR910000155B1/ko

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

내용 없음

Description

반도체 집적회로 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 첫번째 엠보디먼트에 따른 CMOS형태의 논리적인 의레이아우트(layout)를 도식적으로 보여주는 평면도. 제2A도는 논리적인 IC를 위한 유니트 셀을 나타내는 평면도. 제3A도는셀을 나타내는 평면도. 제3B도는 제3A도에 나타난셀의 레이아우트에 첫째층을 이루는 알루미늄 배선이 적용된 경우의 평면도.

Claims (7)

  1. 반도체 서브스트레이트 위에는 다수의 유니트 셀이 형성되며 각 유니트 셀은 입력회로, 출력회로, 입력/출력회로중 적어도 하나의 회로기능을 제공할 수 있도록 미리 결정된 회로 소자들이 내부 연결될 수 있게 구성되어져 있고, 이때 각 유니트 셀과 관련되어 다수의 본딩패드가 구성되며, 입력, 출력 그리고 입력/출력회로중 최소한 두가지 선택된 기능을 각 유니트 셀에 제공하기 위한 배선 패턴은 각 유니트 셀로부터 선택된 두 회로기능을 추출해 내기 위해 최소한 두개의 본딩패드를 각 유니트 셀과 전기적으로 연결하기 위한 내부 결선을 포함하여서된 반도체 집적회로 장치.
  2. 각 유니트 셀에 제공되어진 두개의 본딩 패드중 하나는 유니트 셀의 입력회로에 신호를 공급하기 위해 채택되며, 다른 하나의 본딩 패드는 유니트 셀의 출력회로 부터 신호를 드라이브(drive)하기 위해 채택된 청구범위 1항 기재의 반도체 집적회로 장치.
  3. 각 본딩패드는 이전의 패드와의 접촉 상부와 내부에 도금되어진 상, 하의 도체막으로 구성된 청구범위 1항 기재의 반도체 집적회로 장치.
  4. 미리 결정된 소자 패턴 안에서 각 유니트 회로의 소자를 반도체 소브스트레이트 위에 구성하는 단계와, 미리 결정된 회로기능을 제공하기 위해 패턴 내의 각 유니트 셀의 최소한 회로소자를 내부 연결시키는 단계와, 미리 결정된 다양한 본딩패드 중에서 선택된 하나의 패턴에 따라 각 유니트를 위해 본딩패드를 구성하는 단계, 여기서 미리 결정된 다양한 본딩 패드는 앞에서 말한 최소한 두가지 회로기능을 각 유니트 셀에 제공할 수 있도록 적어도 두개의 분리된 본딩패드를 규정지을 수 있는 첫번째 패턴을 포함한 반도체 집적회로 장치를 제조하는 방법.
  5. 각 유니트 셀은 선택된 본딩패드 패턴에 따라 두개의 분리된 본딩패드와 연결되어지며, 각 유니트 셀은 입력, 출력의 두 회로기능을 제공하는 청구범위 4항 기재의 반도체 집적회로 장치를 제조하는 방법.
  6. 미리 결정된 본딩 패드 패턴은 첫번째 패턴에 의해서 규정된 두개의 본딩 패드가 형성돼 있는 반도체 서브 스트레이트 위의 두 영역 사이를 확장할 수 있도록 하나의 본딩패드를 제공하기 위한 두번째 패턴을 포함하는 청구범위 4항 기재의 반도체 집적회로 장치를 제조하는 방법.
  7. 각 유니트 셀의 각 회로소자는 폴리크리스탈린 실리콘막으로 형성된 게이트 전극을 가진 MOS장치이며, 각 유니트 셀의 선택되어진 회로소자들을 알루미늄 배선에 의해 내부 연결되어 있고, 각 본딩패드는 알루미늄으로 만들어진 청구범위 4항 기재의 반도체 집적회로 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8202670A 1981-06-22 1982-06-15 반도체 집적회로장치 및 그 제조방법 KR910000155B1 (ko)

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JP9535781A JPS57211248A (en) 1981-06-22 1981-06-22 Semiconductor integrated circuit device
JP56-95357 1981-06-22
JP56-095357 1981-06-22

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KR840000985A true KR840000985A (ko) 1984-03-26
KR910000155B1 KR910000155B1 (ko) 1991-01-21

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GB (1) GB2104284B (ko)
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IT (1) IT1152980B (ko)
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GB2104284B (en) 1985-06-19
DE3223276A1 (de) 1983-01-05
US4893168A (en) 1990-01-09
GB2104284A (en) 1983-03-02
JPS57211248A (en) 1982-12-25
FR2508255B1 (fr) 1987-12-24
IT8221971A0 (it) 1982-06-21
FR2508255A1 (fr) 1982-12-24
KR910000155B1 (ko) 1991-01-21
HK54686A (en) 1986-08-01
SG20786G (en) 1987-03-27
IT1152980B (it) 1987-01-14
JPH0440866B2 (ko) 1992-07-06

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